[PATCH] drm/exynos: use DIV_ROUND_CLOSEST to find the closest div
From: Chanho Park This patch uses DIV_ROUND_CLOSEST instead of DIV_ROUND_UP The DIV_ROUND_CLOSEST can be used to find the closest integer value when we divide some integers. Cc: Inki Dae Cc: Joonyoung Shim Cc: Seung-Woo Kim Signed-off-by: Chanho Park --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 4fb2952..da97f93 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -383,7 +383,7 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx, } /* Find the clock divider value that gets us closest to ideal_clk */ - clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); + clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk); return (clkdiv < 0x100) ? clkdiv : 0xff; } -- 2.5.0
[PATCH] drm/exynos: support exynos5422 mipi-dsi
Hi Emil,
On Wed, Feb 10, 2016 at 9:34 PM, Emil Velikov
wrote:
> Hi Chanho Park
>
> On 30 January 2016 at 14:11, Chanho Park wrote:
>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>
>> static struct of_device_id exynos_dsi_of_match[] = {
>
> If you feel extra gracious you can constify the array and all of it's
> entries, for good measure.
> Likely in another patch of course :-)
Andrzej already made the patch[1] as pointed out from you.
[1]: http://www.spinics.net/lists/dri-devel/msg100246.html
--
Best Regards,
Chanho Park
[PATCHv2] drm/exynos: add mic_bypass option for exynos542x fimd
From: Chanho Park
This patch adds a mic_bypass option to bypass the mic
from display out path. The mic(Mobile image compressor) compresses
RGB data from fimd and send the compressed data to the mipi dsi.
The bypass option can be founded from system register and the bit
of the option is 11.
Cc: Inki Dae
Cc: Joonyoung Shim
Cc: Seung-Woo Kim
Signed-off-by: Chanho Park
---
Change from v1:
- the option is only valid if lcdblk_mic_bypass_shift is
assigned
.../devicetree/bindings/display/exynos/samsung-fimd.txt | 2 ++
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 15 +++
2 files changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
index 27c3ce0..7f90c4a 100644
--- a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
@@ -45,6 +45,8 @@ Optional Properties:
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
- samsung,sysreg: handle to syscon used to control the system registers
+- samsung,mic-bypass: bypass mic(mobile image compressor) from display path.
+ This option is only available since exynos5420.
- i80-if-timings: timing configuration for lcd i80 interface support.
- cs-setup: clock cycles for the active period of address signal is enabled
until chip select is enabled.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 70194d0..1076b51 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -94,6 +94,7 @@ struct fimd_driver_data {
unsigned int lcdblk_offset;
unsigned int lcdblk_vt_shift;
unsigned int lcdblk_bypass_shift;
+ unsigned int lcdblk_mic_bypass_shift;
unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
@@ -140,6 +141,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = {
.lcdblk_offset = 0x214,
.lcdblk_vt_shift = 24,
.lcdblk_bypass_shift = 15,
+ .lcdblk_mic_bypass_shift = 11,
.has_shadowcon = 1,
.has_vidoutcon = 1,
.has_vtsel = 1,
@@ -162,6 +164,7 @@ struct fimd_context {
u32 i80ifcon;
booli80_if;
boolsuspended;
+ boolmic_bypass;
int pipe;
wait_queue_head_t wait_vsync_queue;
atomic_twait_vsync_event;
@@ -461,6 +464,14 @@ static void fimd_commit(struct exynos_drm_crtc *crtc)
return;
}
+ if (ctx->mic_bypass && ctx->sysreg && regmap_update_bits(ctx->sysreg,
+ driver_data->lcdblk_offset,
+ 0x1 << driver_data->lcdblk_mic_bypass_shift,
+ 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
+ DRM_ERROR("Failed to update sysreg for bypass mic.\n");
+ return;
+ }
+
/* setup horizontal and vertical display size. */
val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
VIDTCON2_HOZVAL(mode->hdisplay - 1) |
@@ -1014,6 +1025,10 @@ static int fimd_probe(struct platform_device *pdev)
if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
ctx->vidcon1 |= VIDCON1_INV_VCLK;
+ if (of_property_read_bool(dev->of_node, "samsung,mic-bypass") &&
+ ctx->driver_data->lcdblk_mic_bypass_shift)
+ ctx->mic_bypass = true;
+
i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
if (i80_if_timings) {
u32 val;
--
2.5.0
[PATCH 27/29] drm/amd/dal: Correctly interpret rotation as bit set
On Thu, Feb 11, 2016 at 7:20 PM, Harry Wentland
wrote:
> Signed-off-by: Harry Wentland
> Reviewed-by: Mykola Lysenko
> ---
> drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
> b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
> index 1cc9fd1054ab..da6c0116aa1a 100644
> --- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
> +++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
> @@ -366,16 +366,16 @@ static bool fill_rects_from_plane_state(
> surface->clip_rect = surface->dst_rect;
>
> switch (state->rotation) {
> - case DRM_ROTATE_0:
> + case BIT(DRM_ROTATE_0):
> surface->rotation = ROTATION_ANGLE_0;
> break;
> - case DRM_ROTATE_90:
> + case BIT(DRM_ROTATE_90):
> surface->rotation = ROTATION_ANGLE_90;
> break;
> - case DRM_ROTATE_180:
> + case BIT(DRM_ROTATE_180):
> surface->rotation = ROTATION_ANGLE_180;
> break;
> - case DRM_ROTATE_270:
> + case BIT(DRM_ROTATE_270):
> surface->rotation = ROTATION_ANGLE_270;
> break;
> default:
> --
> 2.1.4
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
One minor suggestion for the V2 of this patch-set, please squash
patches 27-29 into the previous patches (relevant to the code they
change). No point in reviewing code of earlier patches that is later
going to be changed by a patch in the same patch-set.
Thanks,
Oded
[PATCH] drm/exynos: add mic_bypass option for exynos542x fimd
Hi Inki,
On Thu, Feb 11, 2016 at 7:37 PM, Inki Dae wrote:
> Hi Chanho,
>
> 2016ë
01ì 30ì¼ 22:58ì Chanho Park ì´(ê°) ì´ ê¸:
>> From: Chanho Park
>>
>> This patch adds a mic_bypass option to bypass the mic
>> from display out path. The mic(Mobile image compressor) compresses
>> RGB data from fimd and send the compressed data to the mipi dsi.
>> The bypass option can be founded from system register and the bit
>> of the option is 11.
>>
>> Cc: Inki Dae
>> Cc: Joonyoung Shim
>> Cc: Seung-Woo Kim
>> Signed-off-by: Chanho Park
>> ---
>> .../devicetree/bindings/display/exynos/samsung-fimd.txt| 2 ++
>> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 14
>> ++
>> 2 files changed, 16 insertions(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
>> b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
>> index 27c3ce0..7f90c4a 100644
>> --- a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
>> +++ b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
>> @@ -45,6 +45,8 @@ Optional Properties:
>> Can be used in case timings cannot be provided otherwise
>> or to override timings provided by the panel.
>> - samsung,sysreg: handle to syscon used to control the system registers
>> +- samsung,mic-bypass: bypass mic(mobile image compressor) from display path.
>> + This option is only available since exynos5420.
>> - i80-if-timings: timing configuration for lcd i80 interface support.
>>- cs-setup: clock cycles for the active period of address signal is
>> enabled
>>until chip select is enabled.
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> index 70194d0..4fb2952 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> @@ -94,6 +94,7 @@ struct fimd_driver_data {
>> unsigned int lcdblk_offset;
>> unsigned int lcdblk_vt_shift;
>> unsigned int lcdblk_bypass_shift;
>> + unsigned int lcdblk_mic_bypass_shift;
>>
>> unsigned int has_shadowcon:1;
>> unsigned int has_clksel:1;
>> @@ -140,6 +141,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data
>> = {
>> .lcdblk_offset = 0x214,
>> .lcdblk_vt_shift = 24,
>> .lcdblk_bypass_shift = 15,
>> + .lcdblk_mic_bypass_shift = 11,
>> .has_shadowcon = 1,
>> .has_vidoutcon = 1,
>> .has_vtsel = 1,
>> @@ -162,6 +164,7 @@ struct fimd_context {
>> u32 i80ifcon;
>> booli80_if;
>> boolsuspended;
>> + boolmic_bypass;
>> int pipe;
>> wait_queue_head_t wait_vsync_queue;
>> atomic_twait_vsync_event;
>> @@ -461,6 +464,14 @@ static void fimd_commit(struct exynos_drm_crtc *crtc)
>> return;
>> }
>>
>> + if (ctx->mic_bypass && ctx->sysreg && regmap_update_bits(ctx->sysreg,
>> + driver_data->lcdblk_offset,
>> + 0x1 << driver_data->lcdblk_mic_bypass_shift,
>> + 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
>> + DRM_ERROR("Failed to update sysreg for bypass mic.\n");
>> + return;
>> + }
>
> It'd better to consider mic path also because mic bypass bit of lcdblk could
> be true by bootloader. In this case, fimd driver wouldn't do anything if
> mic_bypass property isn't declared but the mic_bypass bit of lcdblk register
> is still set to 1.
Actually, I wanted to set the bit on kernel side even though it's not
assigned from bootloader.
If the bootloader already set the bit, that means mic will be by-pass
and we don't care about it from kernel side.
The option is useful when I want to skip the mic on the kernel side.
>
> For this, I think you could check lcdblk_mic_pypass_shift to identify whether
> mic path is supported or not like below,
> if (ctx->lcdblk_mic_bypass_shift) {
It causes all exynos5 fimd driver skips the mic from display path.
How about below patch instead of this?
+ if (of_property_read_bool(dev->of_node, "samsung,mic-bypass") &&
+ ctx->driver_data->lcdblk_mic_bypass_shift)
+ ctx->mic_bypass = true;
Best Regards,
Chanho Park
> if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
> driver_data->lcdblk_offset,
> ctx->mic_bypass <<
> driver_data->lcdblk_mic_bypass_shift,
> ctx->mic_bypass <<
> driver_data->lcdblk_mic_bypass_shift)) {
> ...
> }
> }
>
> Thanks,
> Inki Dae
>
>> +
>> /* setup horizontal and vertical display size. */
>> val = VIDTCON2_LINEVAL(mode->v
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
On Thu, Feb 11, 2016 at 9:52 PM, Dave Airlie wrote: > On 12 February 2016 at 03:19, Harry Wentland > wrote: >> This set of patches enables the new DAL display driver for amdgpu on Carrizo >> Tonga, and Fiji ASICs. This driver will allow us going forward to bring >> display features on the open amdgpu driver (mostly) on par with the Catalyst >> driver. >> >> This driver adds support for >> - Atomic KMS API >> - MST >> - HDMI 2.0 >> - Better powerplay integration >> - Support of HW bandwidth formula on Carrizo >> - Better multi-display support and handling of co-functionality >> - Broader support of display dongles >> - Timing synchronization between DP and HDMI >> >> This patch series is based on Alex Deucher's drm-next-4.6-wip tree. >> > So the first minor criticism is this patch doesn't explain WHY. > > Why does the Linux kernel need 93k lines of code to run the displays > when whole drivers don't even come close. > > We've spent a lot of time ripping abstraction layers out of drivers (exynos > being the major one), what benefits does this major change bring to the > Linux kernel and the AMDGPU driver over and above a leaner, more focused > work. > > If were even to consider merging this it would be at a guess considered > staging level material which would require a TODO list of major cleanups. > > I do realise you've put a lot of work into this, but I think you are going to > get a lot of review pushback in the next few days and without knowing the > reasons this path was chosen it is going to be hard to take. Yeah agreed, we need to figure out the why/how first. Assembling a de-staging TODO is imo a second step. And the problem with that is that before we can do a full TODO we need to remove all the os and drm abstractions. I found delayed_work, timer, memory handling, pixel formats (in multiple copies), the i2c stuff Rob noticed and there's more I'm sure. With all that I just can't even see how the main DAL structures connect and how that would sensibly map to drm concepts. Which is most likely needed to make DAL properly atomic. So de-staging DAL (if we decided this is the right approach) would be multi-stage, with removal of the abstractions not needed first, then taking a 2nd look and figuring out how to untangle the actual concepts. Aside: If all this abstraction is to make dal run in userspace for testing or whatever - nouveau does this, we (Intel) want to do this too for unit-testing, so there's definitely room for sharing the tools. But the right approach imo is to just implement kernel services (like timers) in userspace. Another thing is that some of the features in here (hdmi 2.0, improved dongle support) really should be in shared helpers. If we have that hidden behind the dal abstraction it'll be pretty much impossible (with major work, which is unreasonable to ask of other people trying to get their own driver in) to extract&share it. And for sink handling having multiple copies of the same code just doesn't make sense. Anyway that's my quick thoughts from 2h of reading this. One wishlist: Some design overview or diagram how dal structures connect would be awesome as a reading aid. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
[PATCH 08/29] drm/amd/dal: I2C Aux Manager
On Thu, Feb 11, 2016 at 9:19 PM, Rob Clark wrote: > On Thu, Feb 11, 2016 at 12:19 PM, Harry Wentland > wrote: >> Implements low-level communication layer over I2C and Aux lines using >> GPIO handles. > > so without actually looking too closely at this rather large patch (in > a rather huge patchset).. I do wonder, why not i2c_adapter? Kernel > already has an implementation of that on top of gpio's.. Later down there also seems to be a reinvention of i2c over dp aux or something similar ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
[PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush
On Thu, Feb 11, 2016 at 07:19:45PM +0100, David Herrmann wrote: > Hi > > On Thu, Feb 11, 2016 at 7:08 PM, Ville Syrjälä > wrote: > > On Thu, Feb 11, 2016 at 03:54:38PM -0200, Tiago Vignatti wrote: > >> > >> Thanks for reviewing, David. Please take a look in my comments in-line. > >> > >> > >> On 02/09/2016 07:26 AM, David Herrmann wrote: > >> > > >> > On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti > >> > wrote: > >> >> From: Daniel Vetter > > > >> >> + > >> >> +#define DMA_BUF_SYNC_READ (1 << 0) > >> >> +#define DMA_BUF_SYNC_WRITE (2 << 0) > >> >> +#define DMA_BUF_SYNC_RW(DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE) > >> >> +#define DMA_BUF_SYNC_START (0 << 2) > >> >> +#define DMA_BUF_SYNC_END (1 << 2) > >> >> +#define DMA_BUF_SYNC_VALID_FLAGS_MASK \ > >> >> + (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END) > >> >> + > >> >> +#define DMA_BUF_BASE 'b' > >> >> +#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct > >> >> dma_buf_sync) > >> > > >> > Why _IOW? A read-only ioctl should be able to call DMA_BUF_SYNC_READ, > >> > right? > >> > >> yup. I've changed it to _IOWR now. > > > > AFAICS the ioctl only does copy_from_user() so _IOW seemed perfectly > > correct to me. > > AFAIK, the _IOC_DIR() arguments in ioctls specify the mode of the > operation, not the way the arguments are used. So if read(2) was an > ioctl, it would be annotated as _IOC_READ (even though it _writes_ > into the passed buffer). write(2) would be annotated as _IOC_WRITE > (even though it _reads_ the buffer). As such, they correspond to the > file-access mode, whether you opened it readable and/or writable. > > Anyway, turns out VFS does not verify those. As such, you can specify > whatever you want. I just checked with different existing ioctls > throughout the kernel (`git grep _IOC_DIR`), and they seem to match > what I describe. Not sure which ones you checked because I don't think I've ever seen that interpretation in the kernel. Though I suppose often it sort of matches, eg. when the ioctl just gets/sets some value. Any relationship to some hardware operation is mostly coincidental (well, except when the hardware really just does some kind of read/write operation). And for lost ioctls there is no hardware interaction whatsoever. As far as checking the file access mode goes, well lots of ioctls totally ignore it. About the direction you're right. _IOW means userspace writes to the kernel, and _IOR means userspace reads from the kernel. Which is exactly what the code did. Anyway ioctl-numbers.txt says this: _IOan ioctl with no parameters _IOW an ioctl with write parameters (copy_from_user) _IOR an ioctl with read parameters (copy_to_user) _IOWR an ioctl with both write and read parameters. so I win ;) -- Ville Syrjälä Intel OTC
[PATCH 01/10] drm/exynos: depend on ARCH_EXYNOS for DRM_EXYNOS
Hi Marek, For all patches, picked them up. Thanks, Inki Dae 2016ë 02ì 03ì¼ 21:42ì Marek Szyprowski ì´(ê°) ì´ ê¸: > From: Joonyoung Shim > > Because PLAT_SAMSUNG isn't include exynos SoCs for arm64, but > ARCH_EXYNOS can do it. And it also needs to add ARCH_S3C64XX instead of > PLAT_SAMSUNG. > > Signed-off-by: Joonyoung Shim > Signed-off-by: Marek Szyprowski > --- > drivers/gpu/drm/exynos/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig > index 83efca9..f17d392 100644 > --- a/drivers/gpu/drm/exynos/Kconfig > +++ b/drivers/gpu/drm/exynos/Kconfig > @@ -1,6 +1,6 @@ > config DRM_EXYNOS > tristate "DRM Support for Samsung SoC EXYNOS Series" > - depends on OF && DRM && (PLAT_SAMSUNG || ARCH_MULTIPLATFORM) > + depends on OF && DRM && (ARCH_S3C64XX || ARCH_EXYNOS || > ARCH_MULTIPLATFORM) > select DRM_KMS_HELPER > select DRM_KMS_FB_HELPER > select FB_CFB_FILLRECT >
[PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush
On Thu, Feb 11, 2016 at 03:54:38PM -0200, Tiago Vignatti wrote: > > Thanks for reviewing, David. Please take a look in my comments in-line. > > > On 02/09/2016 07:26 AM, David Herrmann wrote: > > > > On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti > > wrote: > >> From: Daniel Vetter > >> + > >> +#define DMA_BUF_SYNC_READ (1 << 0) > >> +#define DMA_BUF_SYNC_WRITE (2 << 0) > >> +#define DMA_BUF_SYNC_RW(DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE) > >> +#define DMA_BUF_SYNC_START (0 << 2) > >> +#define DMA_BUF_SYNC_END (1 << 2) > >> +#define DMA_BUF_SYNC_VALID_FLAGS_MASK \ > >> + (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END) > >> + > >> +#define DMA_BUF_BASE 'b' > >> +#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) > > > > Why _IOW? A read-only ioctl should be able to call DMA_BUF_SYNC_READ, right? > > yup. I've changed it to _IOWR now. AFAICS the ioctl only does copy_from_user() so _IOW seemed perfectly correct to me. -- Ville Syrjälä Intel OTC
[Bug 92936] Tonga powerplay isssues
https://bugs.freedesktop.org/show_bug.cgi?id=92936 --- Comment #18 from Andy Furniss --- (In reply to Alex Deucher from comment #17) > (In reply to Andy Furniss from comment #16) > > (In reply to Andy Furniss from comment #13) > > > (In reply to Alex Deucher from comment #12) > > > > Can you try my latest 4.6 wip branch? I fixed it in a more unified way. > > > > http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.6-wip > > > > > > This also fixes the memclk getting stuck and uvd corruption issues. > > > > It seems the changes got lost in the latest drm-next-4.6-wip update so I am > > back to stuck mclck. > > The fixes went into my drm-fixes branch (drm-fixes-4.5) which will go > upstream for 4.5. My drm-next-4.6-wip branch is just new features for 4.6. Ahh, OK. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/54e27d20/attachment.html>
[PATCH] drm/exynos: support exynos5422 mipi-dsi
Hi Chanho,
2016ë
01ì 30ì¼ 23:11ì Chanho Park ì´(ê°) ì´ ê¸:
> From: Chanho Park
>
> This patch supports mipi dsi for exynos5422. The dsi register
> offsets of the exynos5422 are similar with exynos5433. However,
> the values of the registers are quite different from the
> exynos5433. For example, the exynos5422 uses sw reset like
> previous chips.
Picked it up.
Thanks,
Inki Dae
>
> Cc: Inki Dae
> Cc: Joonyoung Shim
> Cc: Seung-Woo Kim
> Signed-off-by: Chanho Park
> ---
> .../bindings/display/exynos/exynos_dsim.txt| 1 +
> drivers/gpu/drm/exynos/exynos_drm_dsi.c| 31
> ++
> 2 files changed, 32 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> index 0e6f0c0..22756b3 100644
> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> @@ -6,6 +6,7 @@ Required properties:
> "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
> "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
> "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs
> */
> + "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
> "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
>- reg: physical base address and length of the registers set for the device
>- interrupts: should contain DSI interrupt
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index d84a498..3eff6bf 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -408,6 +408,24 @@ static unsigned int reg_values[] = {
> [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
> };
>
> +static unsigned int exynos5422_reg_values[] = {
> + [RESET_TYPE] = DSIM_SWRST,
> + [PLL_TIMER] = 500,
> + [STOP_STATE_CNT] = 0xf,
> + [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
> + [PHYCTRL_VREG_LP] = 0,
> + [PHYCTRL_SLEW_UP] = 0,
> + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
> + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
> + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
> + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
> + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
> + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
> + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
> + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
> + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
> +};
> +
> static unsigned int exynos5433_reg_values[] = {
> [RESET_TYPE] = DSIM_FUNCRST,
> [PLL_TIMER] = 22200,
> @@ -482,6 +500,17 @@ static struct exynos_dsi_driver_data
> exynos5433_dsi_driver_data = {
> .reg_values = exynos5433_reg_values,
> };
>
> +static struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
> + .reg_ofs = exynos5433_reg_ofs,
> + .plltmr_reg = 0xa0,
> + .has_clklane_stop = 1,
> + .num_clks = 2,
> + .max_freq = 1500,
> + .wait_for_reset = 1,
> + .num_bits_resol = 12,
> + .reg_values = exynos5422_reg_values,
> +};
> +
> static struct of_device_id exynos_dsi_of_match[] = {
> { .compatible = "samsung,exynos3250-mipi-dsi",
> .data = &exynos3_dsi_driver_data },
> @@ -491,6 +520,8 @@ static struct of_device_id exynos_dsi_of_match[] = {
> .data = &exynos4415_dsi_driver_data },
> { .compatible = "samsung,exynos5410-mipi-dsi",
> .data = &exynos5_dsi_driver_data },
> + { .compatible = "samsung,exynos5422-mipi-dsi",
> + .data = &exynos5422_dsi_driver_data },
> { .compatible = "samsung,exynos5433-mipi-dsi",
> .data = &exynos5433_dsi_driver_data },
> { }
>
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
pes.h -- 2.1.4 ___ dri-devel mailing list dri-devel at lists.freedesktop.org<mailto:dri-devel at lists.freedesktop.org> https://lists.freedesktop.org/mailman/listinfo/dri-devel -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/d7136311/attachment-0001.html>
[PATCH v9] dma-buf: Add ioctls to allow userspace to flush
From: Daniel Vetter
The userspace might need some sort of cache coherency management e.g. when CPU
and GPU domains are being accessed through dma-buf at the same time. To
circumvent this problem there are begin/end coherency markers, that forward
directly to existing dma-buf device drivers vfunc hooks. Userspace can make use
of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence would be
used like following:
- mmap dma-buf fd
- for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2. read/write
to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
want (with the new data being consumed by the GPU or say scanout device)
- munmap once you don't need the buffer any more
v2 (Tiago): Fix header file type names (u64 -> __u64)
v3 (Tiago): Add documentation. Use enum dma_buf_sync_flags to the begin/end
dma-buf functions. Check for overflows in start/length.
v4 (Tiago): use 2d regions for sync.
v5 (Tiago): forget about 2d regions (v4); use _IOW in DMA_BUF_IOCTL_SYNC and
remove range information from struct dma_buf_sync.
v6 (Tiago): use __u64 structured padded flags instead enum. Adjust
documentation about the recommendation on using sync ioctls.
v7 (Tiago): Alex' nit on flags definition and being even more wording in the
doc about sync usage.
v9 (Tiago): remove useless is_dma_buf_file check. Fix sync.flags conditionals
and its mask order check. Add include in dma-buf.h.
Cc: Ville Syrjälä
Cc: David Herrmann
Cc: Sumit Semwal
Reviewed-by: Stéphane Marchesin
Signed-off-by: Daniel Vetter
Signed-off-by: Tiago Vignatti
---
I left SYNC_START and SYNC_END exclusive, just how the logic was before. If we
see an useful use case, maybe like the way David said, to store two frames
next to each other in the same BO, we can patch up later fairly easily.
About the ioctl direction, just like Ville pointed, we're doing only
copy_from_user at the moment and seems that _IOW is all we need. So I also
didn't touch anything on that.
David, Ville PTAL. Thank you,
Tiago
Documentation/dma-buf-sharing.txt | 21 +-
drivers/dma-buf/dma-buf.c | 45 +++
include/uapi/linux/dma-buf.h | 40 ++
3 files changed, 105 insertions(+), 1 deletion(-)
create mode 100644 include/uapi/linux/dma-buf.h
diff --git a/Documentation/dma-buf-sharing.txt
b/Documentation/dma-buf-sharing.txt
index 4f4a84b..32ac32e 100644
--- a/Documentation/dma-buf-sharing.txt
+++ b/Documentation/dma-buf-sharing.txt
@@ -350,7 +350,26 @@ Being able to mmap an export dma-buf buffer object has 2
main use-cases:
handles, too). So it's beneficial to support this in a similar fashion on
dma-buf to have a good transition path for existing Android userspace.
- No special interfaces, userspace simply calls mmap on the dma-buf fd.
+ No special interfaces, userspace simply calls mmap on the dma-buf fd, making
+ sure that the cache synchronization ioctl (DMA_BUF_IOCTL_SYNC) is *always*
+ used when the access happens. This is discussed next paragraphs.
+
+ Some systems might need some sort of cache coherency management e.g. when
+ CPU and GPU domains are being accessed through dma-buf at the same time. To
+ circumvent this problem there are begin/end coherency markers, that forward
+ directly to existing dma-buf device drivers vfunc hooks. Userspace can make
+ use of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence
+ would be used like following:
+ - mmap dma-buf fd
+ - for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2. read/write
+ to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
+ want (with the new data being consumed by the GPU or say scanout device)
+ - munmap once you don't need the buffer any more
+
+Therefore, for correctness and optimal performance, systems with the memory
+cache shared by the GPU and CPU i.e. the "coherent" and also the
+"incoherent" are always required to use SYNC_START and SYNC_END before and
+after, respectively, when accessing the mapped address.
2. Supporting existing mmap interfaces in importers
diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
index b2ac13b..9810d1d 100644
--- a/drivers/dma-buf/dma-buf.c
+++ b/drivers/dma-buf/dma-buf.c
@@ -34,6 +34,8 @@
#include
#include
+#include
+
static inline int is_dma_buf_file(struct file *);
struct dma_buf_list {
@@ -251,11 +253,54 @@ out:
return events;
}
+static long dma_buf_ioctl(struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct dma_buf *dmabuf;
+ struct dma_buf_sync sync;
+ enum dma_data_direction direction;
+
+ dmabuf = file->private_data;
+
+ switch (cmd) {
+ case DMA_BUF_IOCTL_SYNC:
+ if (copy_from_user(&sync, (void __user *) arg, sizeof(sync)))
+ return -EFAULT;
+
+
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
bility_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/audio_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/audio_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/bios_parser_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dal_asic_id.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dal_register_logger.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dal_types.h > create mode 100644 > drivers/gpu/drm/amd/dal/include/dc_clock_generator_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dcs_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/ddc_service_types.h > create mode 100644 > drivers/gpu/drm/amd/dal/include/display_clock_interface.h > create mode 100644 > drivers/gpu/drm/amd/dal/include/display_path_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dmcu_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/dpcd_defs.h > create mode 100644 drivers/gpu/drm/amd/dal/include/encoder_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/fixed31_32.h > create mode 100644 drivers/gpu/drm/amd/dal/include/fixed32_32.h > create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_interface.h > create mode 100644 > drivers/gpu/drm/amd/dal/include/gpio_service_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/gpio_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/grph_csc_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_ctrl_defs.h > create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_defs.h > create mode 100644 drivers/gpu/drm/amd/dal/include/grph_object_id.h > create mode 100644 > drivers/gpu/drm/amd/dal/include/hw_sequencer_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/hw_sequencer_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/i2caux_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/irq_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/irq_service_interface.h > create mode 100644 > drivers/gpu/drm/amd/dal/include/link_service_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/link_service_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/logger_interface.h > create mode 100644 drivers/gpu/drm/amd/dal/include/logger_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/scaler_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/set_mode_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/signal_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/vector.h > create mode 100644 drivers/gpu/drm/amd/dal/include/video_csc_types.h > create mode 100644 drivers/gpu/drm/amd/dal/include/video_gamma_types.h > > -- > 2.1.4 > > ___ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel > -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/b9037908/attachment-0001.html>
[PATCH] drm/exynos: add mic_bypass option for exynos542x fimd
Hi Chanho,
2016ë
01ì 30ì¼ 22:58ì Chanho Park ì´(ê°) ì´ ê¸:
> From: Chanho Park
>
> This patch adds a mic_bypass option to bypass the mic
> from display out path. The mic(Mobile image compressor) compresses
> RGB data from fimd and send the compressed data to the mipi dsi.
> The bypass option can be founded from system register and the bit
> of the option is 11.
>
> Cc: Inki Dae
> Cc: Joonyoung Shim
> Cc: Seung-Woo Kim
> Signed-off-by: Chanho Park
> ---
> .../devicetree/bindings/display/exynos/samsung-fimd.txt| 2 ++
> drivers/gpu/drm/exynos/exynos_drm_fimd.c | 14
> ++
> 2 files changed, 16 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> index 27c3ce0..7f90c4a 100644
> --- a/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt
> @@ -45,6 +45,8 @@ Optional Properties:
> Can be used in case timings cannot be provided otherwise
> or to override timings provided by the panel.
> - samsung,sysreg: handle to syscon used to control the system registers
> +- samsung,mic-bypass: bypass mic(mobile image compressor) from display path.
> + This option is only available since exynos5420.
> - i80-if-timings: timing configuration for lcd i80 interface support.
>- cs-setup: clock cycles for the active period of address signal is enabled
>until chip select is enabled.
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> index 70194d0..4fb2952 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> @@ -94,6 +94,7 @@ struct fimd_driver_data {
> unsigned int lcdblk_offset;
> unsigned int lcdblk_vt_shift;
> unsigned int lcdblk_bypass_shift;
> + unsigned int lcdblk_mic_bypass_shift;
>
> unsigned int has_shadowcon:1;
> unsigned int has_clksel:1;
> @@ -140,6 +141,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data =
> {
> .lcdblk_offset = 0x214,
> .lcdblk_vt_shift = 24,
> .lcdblk_bypass_shift = 15,
> + .lcdblk_mic_bypass_shift = 11,
> .has_shadowcon = 1,
> .has_vidoutcon = 1,
> .has_vtsel = 1,
> @@ -162,6 +164,7 @@ struct fimd_context {
> u32 i80ifcon;
> booli80_if;
> boolsuspended;
> + boolmic_bypass;
> int pipe;
> wait_queue_head_t wait_vsync_queue;
> atomic_twait_vsync_event;
> @@ -461,6 +464,14 @@ static void fimd_commit(struct exynos_drm_crtc *crtc)
> return;
> }
>
> + if (ctx->mic_bypass && ctx->sysreg && regmap_update_bits(ctx->sysreg,
> + driver_data->lcdblk_offset,
> + 0x1 << driver_data->lcdblk_mic_bypass_shift,
> + 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
> + DRM_ERROR("Failed to update sysreg for bypass mic.\n");
> + return;
> + }
It'd better to consider mic path also because mic bypass bit of lcdblk could be
true by bootloader. In this case, fimd driver wouldn't do anything if
mic_bypass property isn't declared but the mic_bypass bit of lcdblk register is
still set to 1.
For this, I think you could check lcdblk_mic_pypass_shift to identify whether
mic path is supported or not like below,
if (ctx->lcdblk_mic_bypass_shift) {
if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
driver_data->lcdblk_offset,
ctx->mic_bypass <<
driver_data->lcdblk_mic_bypass_shift,
ctx->mic_bypass <<
driver_data->lcdblk_mic_bypass_shift)) {
...
}
}
Thanks,
Inki Dae
> +
> /* setup horizontal and vertical display size. */
> val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
> VIDTCON2_HOZVAL(mode->hdisplay - 1) |
> @@ -1014,6 +1025,9 @@ static int fimd_probe(struct platform_device *pdev)
> if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
> ctx->vidcon1 |= VIDCON1_INV_VCLK;
>
> + if (of_property_read_bool(dev->of_node, "samsung,mic-bypass"))
> + ctx->mic_bypass = true;
> +
> i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
> if (i80_if_timings) {
> u32 val;
>
[PATCH] radeon: Define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP for consistency and readability - libdrm
---
include/drm/radeon_drm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index cd31794..e57640a 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -1026,6 +1026,7 @@ struct drm_radeon_info {
#define SI_TILE_MODE_COLOR_2D_16BPP15
#define SI_TILE_MODE_COLOR_2D_32BPP16
#define SI_TILE_MODE_COLOR_2D_64BPP17
+#define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10
#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP11
#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP12
#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
--
2.7.1
[PATCH] radeon: Define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP for consistency and readability
---
drivers/gpu/drm/radeon/atombios_crtc.c | 2 +-
include/uapi/drm/radeon_drm.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 801dd60..c88f9fe 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1287,7 +1287,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
} else {
switch (target_fb->bits_per_pixel) {
case 8:
- index = 10;
+ index =
SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP;
break;
case 16:
index =
SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index ccb9bcd..407a092 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -1057,6 +1057,7 @@ struct drm_radeon_info {
#define SI_TILE_MODE_COLOR_2D_16BPP15
#define SI_TILE_MODE_COLOR_2D_32BPP16
#define SI_TILE_MODE_COLOR_2D_64BPP17
+#define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10
#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP11
#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP12
#define SI_TILE_MODE_DEPTH_STENCIL_1D 4
--
2.7.1
[PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush
Hi On Thu, Feb 11, 2016 at 7:08 PM, Ville Syrjälä wrote: > On Thu, Feb 11, 2016 at 03:54:38PM -0200, Tiago Vignatti wrote: >> >> Thanks for reviewing, David. Please take a look in my comments in-line. >> >> >> On 02/09/2016 07:26 AM, David Herrmann wrote: >> > >> > On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti >> > wrote: >> >> From: Daniel Vetter > >> >> + >> >> +#define DMA_BUF_SYNC_READ (1 << 0) >> >> +#define DMA_BUF_SYNC_WRITE (2 << 0) >> >> +#define DMA_BUF_SYNC_RW(DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE) >> >> +#define DMA_BUF_SYNC_START (0 << 2) >> >> +#define DMA_BUF_SYNC_END (1 << 2) >> >> +#define DMA_BUF_SYNC_VALID_FLAGS_MASK \ >> >> + (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END) >> >> + >> >> +#define DMA_BUF_BASE 'b' >> >> +#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct dma_buf_sync) >> > >> > Why _IOW? A read-only ioctl should be able to call DMA_BUF_SYNC_READ, >> > right? >> >> yup. I've changed it to _IOWR now. > > AFAICS the ioctl only does copy_from_user() so _IOW seemed perfectly > correct to me. AFAIK, the _IOC_DIR() arguments in ioctls specify the mode of the operation, not the way the arguments are used. So if read(2) was an ioctl, it would be annotated as _IOC_READ (even though it _writes_ into the passed buffer). write(2) would be annotated as _IOC_WRITE (even though it _reads_ the buffer). As such, they correspond to the file-access mode, whether you opened it readable and/or writable. Anyway, turns out VFS does not verify those. As such, you can specify whatever you want. I just checked with different existing ioctls throughout the kernel (`git grep _IOC_DIR`), and they seem to match what I describe. But I don't care much. I guess _IORW is fine either way. David
[PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush
Hi
On Thu, Feb 11, 2016 at 6:54 PM, Tiago Vignatti
wrote:
> On 02/09/2016 07:26 AM, David Herrmann wrote:
>>> +
>>> + switch (cmd) {
>>> + case DMA_BUF_IOCTL_SYNC:
>>> + if (copy_from_user(&sync, (void __user *) arg,
>>> sizeof(sync)))
>>> + return -EFAULT;
>>> +
>>> + if (sync.flags & DMA_BUF_SYNC_RW)
>>> + direction = DMA_BIDIRECTIONAL;
>>> + else if (sync.flags & DMA_BUF_SYNC_READ)
>>> + direction = DMA_FROM_DEVICE;
>>> + else if (sync.flags & DMA_BUF_SYNC_WRITE)
>>> + direction = DMA_TO_DEVICE;
>>> + else
>>> + return -EINVAL;
>>
>>
>> This looks bogus. It always ends up being "DMA_BIDIRECTIONAL" or
>> EINVAL. I recommend changing it to:
>>
>> switch (sync.flags & DMA_BUF_SYNC_RW) {
>> case DMA_BUF_SYNC_READ:
>> direction = DMA_FROM_DEVICE;
>> break;
>> case DMA_BUF_SYNC_WRITE:
>> direction = DMA_TO_DEVICE;
>> break;
>> case DMA_BUF_SYNC_READ:
>> direction = DMA_BIDIRECTIONAL;
>> break;
>> default:
>> return -EINVAL;
>> }
>
>
> hmm I can't really get what's wrong with my snip. Why bogus? Can you
> double-check actually your suggestion, cause that's wrong with _READ being
> repeated.
You did this:
if (sync.flags & DMA_BUF_SYNC_RW)
...but what you meant is this:
if ((sync.flags & DMA_BUF_SYNC_RW) == DMA_BUF_SYNC_RW)
Feel free to fix it with this simple change. I just thought a switch()
statement would be easier to read. And yes, I screwed up the third
'case' statement, which should read DMA_BUF_SYNC_RW rather than
DMA_BUF_SYNC_READ. Sorry for that.
>>> +
>>> + if (sync.flags & DMA_BUF_SYNC_END)
>>> + dma_buf_end_cpu_access(dmabuf, direction);
>>> + else
>>> + dma_buf_begin_cpu_access(dmabuf, direction);
>>
>>
>> Why are SYNC_START and SYNC_END exclusive? It feels very natural to me
>> to invoke both at the same time (especially if two objects are stored
>> in the same dma-buf).
>
>
> Can you open a bit and teach how two objects would be stored in the same
> dma-buf? I didn't care about this case and if we want that, we'd need also
> to change the sequence of accesses as described in the dma-buf-sharing.txt
> I'm proposing in this patch.
Just store two frames next to each other in the same BO. Create two
DRM-FBs with different offsets, covering one frame each. Now you can
just switch between the two FBs, backed by the same object.
I'm not saying that this is a good idea. I just wondered why the
START/END was exclusive, rather than inclusive. But.. I guess it is
cheap enough that someone can just call ioctl(END) followed by
ioctl(START).
>>> +
>>> +#define DMA_BUF_SYNC_READ (1 << 0)
>>> +#define DMA_BUF_SYNC_WRITE (2 << 0)
>>> +#define DMA_BUF_SYNC_RW(DMA_BUF_SYNC_READ | DMA_BUF_SYNC_WRITE)
>>> +#define DMA_BUF_SYNC_START (0 << 2)
>>> +#define DMA_BUF_SYNC_END (1 << 2)
>>> +#define DMA_BUF_SYNC_VALID_FLAGS_MASK \
>>> + (DMA_BUF_SYNC_RW | DMA_BUF_SYNC_END)
>>> +
>>> +#define DMA_BUF_BASE 'b'
>>> +#define DMA_BUF_IOCTL_SYNC _IOW(DMA_BUF_BASE, 0, struct
>>> dma_buf_sync)
>>
>>
>> Why _IOW? A read-only ioctl should be able to call DMA_BUF_SYNC_READ,
>> right?
>
>
> yup. I've changed it to _IOWR now.
Well, I'd have used _IOC_NONE, rather than READ/WRITE, but I just
checked and it seems vfs doesn't even enforce them. So... eh... I
don't care.
Thanks
David
[Bug 92936] Tonga powerplay isssues
https://bugs.freedesktop.org/show_bug.cgi?id=92936 --- Comment #17 from Alex Deucher --- (In reply to Andy Furniss from comment #16) > (In reply to Andy Furniss from comment #13) > > (In reply to Alex Deucher from comment #12) > > > Can you try my latest 4.6 wip branch? I fixed it in a more unified way. > > > http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.6-wip > > > > This also fixes the memclk getting stuck and uvd corruption issues. > > It seems the changes got lost in the latest drm-next-4.6-wip update so I am > back to stuck mclck. The fixes went into my drm-fixes branch (drm-fixes-4.5) which will go upstream for 4.5. My drm-next-4.6-wip branch is just new features for 4.6. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/35a7a673/attachment.html>
[Bug 92936] Tonga powerplay isssues
https://bugs.freedesktop.org/show_bug.cgi?id=92936 --- Comment #16 from Andy Furniss --- (In reply to Andy Furniss from comment #13) > (In reply to Alex Deucher from comment #12) > > Can you try my latest 4.6 wip branch? I fixed it in a more unified way. > > http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.6-wip > > This also fixes the memclk getting stuck and uvd corruption issues. It seems the changes got lost in the latest drm-next-4.6-wip update so I am back to stuck mclck. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/eee21fa0/attachment.html>
[PATCH v2 2/2] drm/i915/gen9: Add support for pipe background color (v2)
On Thu, Feb 11, 2016 at 08:05:26AM -0800, Matt Roper wrote:
> On Thu, Feb 11, 2016 at 12:00:50PM +0200, Ville Syrjälä wrote:
> > On Wed, Feb 10, 2016 at 06:32:59PM -0800, Matt Roper wrote:
> > > Gen9 platforms allow CRTC's to be programmed with a background/canvas
> > > color below the programmable planes. Let's expose this as a property to
> > > allow userspace to program a desired value.
> > >
> > > This patch is based on earlier work by Chandra Konduru; unfortunately
> > > the driver has evolved so much since his patches were written (in the
> > > pre-atomic era) that the functionality had to be pretty much completely
> > > rewritten for the new i915 atomic internals.
> > >
> > > v2:
> > > - Set initial background color (black) via proper helper function (Bob)
> > > - Fix debugfs output
> > > - General rebasing
> > >
> > > Cc: Chandra Konduru
> > > Cc: Bob Paauwe
> > > Cc: dri-devel at lists.freedesktop.org
> > > Signed-off-by: Matt Roper
> > > ---
> > > Documentation/DocBook/gpu.tmpl | 10 +++-
> > > drivers/gpu/drm/i915/i915_debugfs.c | 8 +++
> > > drivers/gpu/drm/i915/i915_reg.h | 9 +++
> > > drivers/gpu/drm/i915/intel_display.c | 46
> > >
> > > 4 files changed, 72 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/DocBook/gpu.tmpl
> > > b/Documentation/DocBook/gpu.tmpl
> > > index fe6b36a..9e003cd 100644
> > > --- a/Documentation/DocBook/gpu.tmpl
> > > +++ b/Documentation/DocBook/gpu.tmpl
> > > @@ -2092,7 +2092,7 @@ void intel_crt_init(struct drm_device *dev)
> > > TBD
> > >
> > >
> > > - i915
> > > + i915
> > > Generic
> > > "Broadcast RGB"
> > > ENUM
> > > @@ -2108,6 +2108,14 @@ void intel_crt_init(struct drm_device *dev)
> > > TBD
> > >
> > >
> > > + CRTC
> > > + âbackground_colorâ
> > > + RGBA
> > > +
> > > + CRTC
> > > + Background color of regions not covered by a
> > > plane
> > > +
> > > +
> > > SDVO-TV
> > > âmodeâ
> > > ENUM
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index ec0c2a05e..e7352fc 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -3104,6 +3104,14 @@ static int i915_display_info(struct seq_file *m,
> > > void *unused)
> > > intel_scaler_info(m, crtc);
> > > intel_plane_info(m, crtc);
> > > }
> > > + if (INTEL_INFO(dev)->gen >= 9 && pipe_config->base.active) {
> > > + struct drm_rgba background =
> > > pipe_config->base.background_color;
> > > +
> > > + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x
> > > b=%x\n",
> > > +DRM_RGBA_REDBITS(background, 10),
> > > +DRM_RGBA_GREENBITS(background, 10),
> > > +DRM_RGBA_BLUEBITS(background, 10));
> > > + }
> > >
> > > seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
> > > yesno(!crtc->cpu_fifo_underrun_disabled),
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 144586e..b0b014d 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7649,6 +7649,15 @@ enum skl_disp_power_wells {
> > > #define PIPE_CSC_POSTOFF_ME(pipe)_MMIO_PIPE(pipe,
> > > _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> > > #define PIPE_CSC_POSTOFF_LO(pipe)_MMIO_PIPE(pipe,
> > > _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
> > >
> > > +/* Skylake pipe bottom color */
> > > +#define _PIPE_BOTTOM_COLOR_A0x70034
> > > +#define _PIPE_BOTTOM_COLOR_B0x71034
> > > +#define _PIPE_BOTTOM_COLOR_C0x72034
> > > +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31)
> > > +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
> > > +#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
> > > +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _PIPE_BOTTOM_COLOR_A,
> > > _PIPE_BOTTOM_COLOR_B)
> > > +
> > > /* MIPI DSI registers */
> > >
> > > #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
> > > C only */
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 836bbdc..a616ac42 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3299,6 +3299,8 @@ static void intel_update_pipe_config(struct
> > > intel_crtc *crtc,
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > struct intel_crtc_state *pipe_config =
> > > to_intel_crtc_state(crtc->base.state);
> > > + struct drm_rgba background = pipe_config->base.background_color;
> > > + uint32_t val;
> > >
> > > /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> > > crtc->base.mode = crtc->base.state->mode;
> > > @@ -3335,6 +3337,26
[Bug 93998] Linux 4.5-rc2 ATI Radeon 3000 Graphics not rendering correctly
https://bugs.freedesktop.org/show_bug.cgi?id=93998 --- Comment #16 from SMF --- (In reply to SMF from comment #15) > (In reply to Michel D�nzer from comment #14) > > That's unfortunate, but doesn't change that it's probably not a driver bug > > and that you should get in touch with Dan Williams about it. > > Thanks just e-mailed him. Solution found see: https://bugzilla.kernel.org/show_bug.cgi?id=112211 For details. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/cce3b74c/attachment.html>
[Bug 93591] [TONGA] ARK Survival Evolved: corruption of main menu textures
https://bugs.freedesktop.org/show_bug.cgi?id=93591 --- Comment #2 from EoD --- This issue does also not affect my Barts on r600. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/d95c1581/attachment.html>
radeon_drm.h: missing TILE_MODE definition?
On Thu, 11 Feb 2016 at 10:30 Alex Deucher wrote: > On Thu, Feb 11, 2016 at 12:23 AM, Alexandre Demers > wrote: > > I was looking at /drivers/gpu/drm/radeon/atombios_crtc.c and at > radeon_drm.h > > (both under kernel and libdrm). I noticed that there seems to be a > missing > > TILE_MODE definition: under atombios_crtc, line 1289 > > (/drivers/gpu/drm/radeon/atombios_crtc.c#L1289), an unexplained value is > > being used (index = 10;) compared to the rest of the code around where > > defined variables are being used. > > > > Looking at the defined variables under radeon_drm.h, there is a missing > > value in the tile index. Index 10 is missing. If it was defined, it > could be > > used in place of the numerical value at line 1289 under atombios_crtc.c. > > According to the other names and usages, shouldn't there be a #define > > SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10? In fact, the equivalent of > > SI_TILE_MODE_COLORD_2D_8BPP is CIK_TILE_MODE_COLOR_2D under CIK; under > CIK, > > there is a variable defined for index 10, which is > > CIK_TILE_MODE_COLOR_2D_SCANOUT. Thus, I'd be inclined to think there > should > > really be a SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP variable defined. > > > > I've been searching in the SI 3D register documentation and I couldn't > find > > a tile index table to relate to. > > > > Lastly, based on how the other "X_2D_SCANOUT_YBPP" variables are covered > > under si_surface_sanity() (libdrm's radeon_surface.c), is it expected > that > > this index value (10) is not covered specifically. Should there be a > "case > > 1: *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP; break;" at line 1362, > > before "case 2: ..."? Would it make sense? > > > > I don't think it's a particularly useful case. In practice I doubt it > would ever be hit. I guess it's for 8bpp greyscale. The 3D engine > can't render to indexed color or 332 surfaces. If you aren't using > the 3D engine, there's not much point in using tiling to begin with. > > Alex > Thanks for the answer. At least, I'd like to add a "#define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10;" (if that variable name makes sense, I'm open to any other more meaningful name) just so we don't have a "index = 10" right there in the middle of the code while other cases use defined variables: it is mostly about consistency and readability of the code. Any objection? Your comment is more about if this case/index value should be covered under si_surface_sanity(). I'll trust you on the fact that it shouldn't be encountered. Cheers Alexandre Demers -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/4a793d92/attachment-0001.html>
[Bug 94091] Tonga unreal elemental segfault since radeonsi: put image, fmask, and sampler descriptors into one array
https://bugs.freedesktop.org/show_bug.cgi?id=94091 Andy Furniss changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #1 from Andy Furniss --- fixed in mesa https://cgit.freedesktop.org/mesa/mesa/commit/?id=1c8a1a8fed7a2ef61104040956b20613dc8b274d -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/3611817b/attachment.html>
[PATCH v2 2/2] drm/fsl-dcu: use flat regmap cache
On 2016-02-02 17:06, Stefan Agner wrote:
> Using flat regmap cache instead of RB-tree to avoid the following
> lockdep warning on driver load:
> [0.697285] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2755
> lockdep_trace_alloc+0x15c/0x160()
> [0.697449] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
>
> The RB-tree regmap cache needs to allocate new space on first
> writes. However, allocations in an atomic context (e.g. when a
> spinlock is held) are not allowed. The function regmap_write
> calls map->lock, which acquires a spinlock in the fast_io case.
> Since the FSL DCU driver uses MMIO, the regmap bus of type
> regmap_mmio is being used which has fast_io set to true.
>
> The MMIO space of the DCU driver is reasonable condense, hence
> using the much faster flat regmap cache is anyway the better
> choice.
As discussed with Thierry on IRC, using regmap cache often does not
really make sense in the context of display controllers. While trying to
use the suspend/resume, I realized that the current implementation in
the DCU driver has bugs and does not work (e.g. an explicit READREG is
missing, but even with that in place, restoring all registers and enable
the controller then seem not to work reliable). Using the new
suspend/resume helpers seem to work better...
Therefor I NACK my own patch here and vote for removing the regcache
entirely (and use the new DRM supsend/resume helpers to implement
suspend/resume)...
--
Stefan
>
> Signed-off-by: Stefan Agner
> Cc: Mark Brown
> ---
> Changes since v1:
> - Do not move drm_dev_alloc
>
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 18 +++---
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 6 --
> 2 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> index e01c813..9c21aad 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> @@ -36,11 +36,11 @@ static bool fsl_dcu_drm_is_volatile_reg(struct
> device *dev, unsigned int reg)
> return false;
> }
>
> -static const struct regmap_config fsl_dcu_regmap_config = {
> +static struct regmap_config fsl_dcu_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> .val_bits = 32,
> - .cache_type = REGCACHE_RBTREE,
> + .cache_type = REGCACHE_FLAT,
>
> .volatile_reg = fsl_dcu_drm_is_volatile_reg,
> };
> @@ -260,12 +260,14 @@ static const struct fsl_dcu_soc_data
> fsl_dcu_ls1021a_data = {
> .name = "ls1021a",
> .total_layer = 16,
> .max_layer = 4,
> + .max_register = LS1021A_DCU_MAX_REGISTER,
> };
>
> static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
> .name = "vf610",
> .total_layer = 64,
> .max_layer = 6,
> + .max_register = VF610_DCU_MAX_REGISTER,
> };
>
> static const struct of_device_id fsl_dcu_of_match[] = {
> @@ -331,6 +333,13 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
> return ret;
> }
>
> + id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
> + if (!id)
> + return -ENODEV;
> +
> + fsl_dev->soc = id->data;
> +
> + fsl_dcu_regmap_config.max_register = fsl_dev->soc->max_register;
> fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
> &fsl_dcu_regmap_config);
> if (IS_ERR(fsl_dev->regmap)) {
> @@ -338,11 +347,6 @@ static int fsl_dcu_drm_probe(struct platform_device
> *pdev)
> return PTR_ERR(fsl_dev->regmap);
> }
>
> - id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
> - if (!id)
> - return -ENODEV;
> - fsl_dev->soc = id->data;
> -
> drm = drm_dev_alloc(driver, dev);
> if (!drm)
> return -ENOMEM;
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
> index 2a724f3..7c296a0 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
> @@ -114,8 +114,6 @@
> #define DCU_UPDATE_MODE_MODE BIT(31)
> #define DCU_UPDATE_MODE_READREG BIT(30)
>
> -#define DCU_DCFB_MAX 0x300
> -
> #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40)
>
> #define DCU_LAYER_HEIGHT(x) ((x) << 16)
> @@ -155,6 +153,9 @@
> #define DCU_LAYER_POST_SKIP(x) ((x) << 16)
> #define DCU_LAYER_PRE_SKIP(x)(x)
>
> +#define VF610_DCU_MAX_REGISTER 0x11fc
> +#define LS1021A_DCU_MAX_REGISTER 0x5fc
> +
> #define FSL_DCU_RGB565 4
> #define FSL_DCU_RGB888 5
> #define FSL_DCU_ARGB 6
> @@ -175,6 +176,7 @@ struct fsl_dcu_soc_data {
> unsigned int total_layer;
> /*max layer number DCU supported*/
> unsigned int max_layer;
> + unsigned int max_register;
> };
>
> struct fsl_dcu_drm
[REGRESSION] i915: No HDMI output with 4.4
On Thu, Feb 11, 2016 at 01:16:53PM +0200, Oleksandr Natalenko wrote:
> Ville,
>
> here is another dmesg: [1]
>
> I've reconnected HDMI cable three times.
>
> Forgot to note, it is HDMI monitor plugged into machine's DVI with
> HDMI-DVI cable. I guess this should matter as well.
Shouldn't really matter. HDMI and DVI are identical at this level.
>
> [1] https://gist.github.com/7057ea8512b9aa7ee5bd
OK, so the hpd interrupt does happen, and yet the live status supposedly
claims that nothing is there. Port C live status definitely works here
on my IVB, so not sure what the deal is.
Can you grab intel-gpu-tools and run
intel_reg read 0xc4000 0xc4004 0xc4008 0xc400c 0xc4030
a couple of times after plugging the monitor in, and also run it when
nothing is plugged in.
Also you could try something like the following patch so we might
observe the live status with a bit more detail. Though the fact that it
doesn't seem to work for you even when the monitor was already plugged
in is somewhat troubling:
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1392,12 +1392,17 @@ intel_hdmi_detect(struct drm_connector *connector, bool
force)
intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
- for (try = 0; !live_status && try < 9; try++) {
- if (try)
- msleep(10);
- live_status = intel_digital_port_connected(dev_priv,
+ printk("port %c live status\n ",
port_name(hdmi_to_dig_port(intel_hdmi)->port));
+ for (try = 0; try < 250; try++) {
+ bool status = intel_digital_port_connected(dev_priv,
hdmi_to_dig_port(intel_hdmi));
+ live_status |= status;
+ printk("%c", status ? '#' : '_');
+ if (try % 50 == 49)
+ printk("\n ");
+ usleep_range(1000, 1000);
}
+ printk("\n");
if (!live_status)
DRM_DEBUG_KMS("Live status not up!");
--
2.4.10
Oh, and if you have another cable you can try, might be a good idea to
see if it behaves any better.
>
> 11.02.2016 11:26, Ville Syrjälä напиÑав:
> > On Thu, Feb 11, 2016 at 10:54:08AM +0200, Oleksandr Natalenko wrote:
> >> Daniel,
> >>
> >> I've already tried Ville's patch you've mentioned with no luck.
> >>
> >> Kindly find unpatched v4.5-rc3 dmesg with drm debug enabled here: [1]
> >>
> >> [1] https://gist.github.com/efb44b7c6bc325978b80
> >
> > That's an IVB. So no wonder my patch doesn't help.
> >
> > Can you grab another dmesg after disconnecting and reconnecting the
> > HDMI cable?
--
Ville Syrjälä
Intel OTC
[PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush
Thanks for reviewing, David. Please take a look in my comments in-line.
On 02/09/2016 07:26 AM, David Herrmann wrote:
>
> On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
> wrote:
>> From: Daniel Vetter
>>
>> The userspace might need some sort of cache coherency management e.g. when
>> CPU
>> and GPU domains are being accessed through dma-buf at the same time. To
>> circumvent this problem there are begin/end coherency markers, that forward
>> directly to existing dma-buf device drivers vfunc hooks. Userspace can make
>> use
>> of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence would be
>> used like following:
>> - mmap dma-buf fd
>> - for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2.
>> read/write
>> to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
>> want (with the new data being consumed by the GPU or say scanout
>> device)
>> - munmap once you don't need the buffer any more
>>
>> v2 (Tiago): Fix header file type names (u64 -> __u64)
>> v3 (Tiago): Add documentation. Use enum dma_buf_sync_flags to the begin/end
>> dma-buf functions. Check for overflows in start/length.
>> v4 (Tiago): use 2d regions for sync.
>> v5 (Tiago): forget about 2d regions (v4); use _IOW in DMA_BUF_IOCTL_SYNC and
>> remove range information from struct dma_buf_sync.
>> v6 (Tiago): use __u64 structured padded flags instead enum. Adjust
>> documentation about the recommendation on using sync ioctls.
>> v7 (Tiago): Alex' nit on flags definition and being even more wording in the
>> doc about sync usage.
>>
>> Cc: Sumit Semwal
>> Signed-off-by: Daniel Vetter
>> Signed-off-by: Tiago Vignatti
>> ---
>> Documentation/dma-buf-sharing.txt | 21 ++-
>> drivers/dma-buf/dma-buf.c | 43
>> +++
>> include/uapi/linux/dma-buf.h | 38 ++
>> 3 files changed, 101 insertions(+), 1 deletion(-)
>> create mode 100644 include/uapi/linux/dma-buf.h
>>
>> diff --git a/Documentation/dma-buf-sharing.txt
>> b/Documentation/dma-buf-sharing.txt
>> index 4f4a84b..32ac32e 100644
>> --- a/Documentation/dma-buf-sharing.txt
>> +++ b/Documentation/dma-buf-sharing.txt
>> @@ -350,7 +350,26 @@ Being able to mmap an export dma-buf buffer object has
>> 2 main use-cases:
>> handles, too). So it's beneficial to support this in a similar fashion
>> on
>> dma-buf to have a good transition path for existing Android userspace.
>>
>> - No special interfaces, userspace simply calls mmap on the dma-buf fd.
>> + No special interfaces, userspace simply calls mmap on the dma-buf fd,
>> making
>> + sure that the cache synchronization ioctl (DMA_BUF_IOCTL_SYNC) is
>> *always*
>> + used when the access happens. This is discussed next paragraphs.
>> +
>> + Some systems might need some sort of cache coherency management e.g. when
>> + CPU and GPU domains are being accessed through dma-buf at the same time.
>> To
>> + circumvent this problem there are begin/end coherency markers, that
>> forward
>> + directly to existing dma-buf device drivers vfunc hooks. Userspace can
>> make
>> + use of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence
>> + would be used like following:
>> + - mmap dma-buf fd
>> + - for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2.
>> read/write
>> + to mmap area 3. SYNC_END ioctl. This can be repeated as often as you
>> + want (with the new data being consumed by the GPU or say scanout
>> device)
>> + - munmap once you don't need the buffer any more
>> +
>> +Therefore, for correctness and optimal performance, systems with the
>> memory
>> +cache shared by the GPU and CPU i.e. the "coherent" and also the
>> +"incoherent" are always required to use SYNC_START and SYNC_END before
>> and
>> +after, respectively, when accessing the mapped address.
>>
>> 2. Supporting existing mmap interfaces in importers
>>
>> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
>> index b2ac13b..9a298bd 100644
>> --- a/drivers/dma-buf/dma-buf.c
>> +++ b/drivers/dma-buf/dma-buf.c
>> @@ -34,6 +34,8 @@
>> #include
>> #include
>>
>> +#include
>> +
>> static inline int is_dma_buf_file(struct file *);
>>
>> struct dma_buf_list {
>> @@ -251,11 +253,52 @@ out:
>> return events;
>> }
>>
>> +static long dma_buf_ioctl(struct file *file,
>> + unsigned int cmd, unsigned long arg)
>> +{
>> + struct dma_buf *dmabuf;
>> + struct dma_buf_sync sync;
>> + enum dma_data_direction direction;
>> +
>> + dmabuf = file->private_data;
>> +
>> + if (!is_dma_buf_file(file))
>> + return -EINVAL;
>
> Why? This can never happen, and you better not use dma_buf_ioctl()
> outside of dma_buf_fops..
> I guess it's simply copied from the other fop callbacks, but I don't
> see why. dma_buf_poll() doesn't do it, neither sh
[PATCH 08/29] drm/amd/dal: I2C Aux Manager
On Thu, Feb 11, 2016 at 12:19 PM, Harry Wentland wrote: > Implements low-level communication layer over I2C and Aux lines using > GPIO handles. so without actually looking too closely at this rather large patch (in a rather huge patchset).. I do wonder, why not i2c_adapter? Kernel already has an implementation of that on top of gpio's.. BR, -R > Signed-off-by: Harry Wentland > Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/dal/dc/i2caux/Makefile | 33 + > drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c | 567 > drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h | 119 +++ > .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 788 + > .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.h | 56 ++ > .../i2caux/dce110/i2c_generic_hw_engine_dce110.h | 25 + > .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c| 954 > + > .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h| 58 ++ > .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c| 172 > .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h| 43 + > .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 266 ++ > .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 39 + > .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c| 112 +++ > .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h| 33 + > drivers/gpu/drm/amd/dal/dc/i2caux/engine.h | 129 +++ > drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c| 67 ++ > drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c | 121 +++ > drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h | 113 +++ > .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c | 286 ++ > .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h | 77 ++ > drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c | 246 ++ > drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h | 80 ++ > drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c | 614 + > drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h | 81 ++ > drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 529 > drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 123 +++ > 26 files changed, 5731 insertions(+) > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/Makefile > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c > create mode 100644 > drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c > create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
[Bug 94091] Tonga unreal elemental segfault since radeonsi: put image, fmask, and sampler descriptors into one array
https://bugs.freedesktop.org/show_bug.cgi?id=94091 Bug ID: 94091 Summary: Tonga unreal elemental segfault since radeonsi: put image, fmask, and sampler descriptors into one array Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/radeonsi Assignee: dri-devel at lists.freedesktop.org Reporter: adf.lists at gmail.com QA Contact: dri-devel at lists.freedesktop.org Created attachment 121675 --> https://bugs.freedesktop.org/attachment.cgi?id=121675&action=edit gdb bt R9285 since mesa commit below Unreal ElementalDemo quits at start with a segfault. gdb from demo generated core attached commit 7aedbbacae6d3ec3d06735fff2eb662964773ad2 Author: Marek Olšák Date: Sat Feb 6 22:09:45 2016 +0100 radeonsi: put image, fmask, and sampler descriptors into one array The texture slot is expanded to 16 dwords containing 2 descriptors. Those can be: - Image and fmask, or - Image and sampler state By carefully choosing the locations, we can put all three into one slot, with the fmask and sampler state being mutually exclusive. This improves shaders in 2 ways: - 2 user SGPRs are unused, shaders can use them as temporary registers now - each pair of descriptors is always on the same cache line v2: cosmetic changes: add back v8i32, don't load a sampler state & fmask at the same time -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/1bdc7323/attachment.html>
[PATCH 3/6] drm: Fix drm_vblank_pre/post_modeset regression from Linux 4.4
On 02/08/2016 02:13 AM, Mario Kleiner wrote: > Changes to drm_update_vblank_count() in Linux 4.4 broke the > behaviour of the pre/post modeset functions as the new update > code doesn't deal with hw vblank counter resets inbetween calls > to drm_vblank_pre_modeset an drm_vblank_post_modeset, as it > should. > > This causes mistreatment of such hw counter resets as counter > wraparound, and thereby large forward jumps of the software > vblank counter which in turn cause vblank event dispatching > and vblank waits to fail/hang --> userspace clients hang. > > This symptom was reported on radeon-kms to cause a infinite > hang of KDE Plasma 5 shell's login procedure, preventing users > from logging in. > > Fix this by detecting when drm_update_vblank_count() is called > inside a pre->post modeset interval. If so, clamp valid vblank > increments to the safe values 0 and 1, pretty much restoring > the update behavior of the old update code of Linux 4.3 and > earlier. Also reset the last recorded hw vblank count at call > to drm_vblank_post_modeset() to be safe against hw that after > modesetting, dpms on etc. only fires its first vblank irq after > drm_vblank_post_modeset() was already called. > > Reported-by: Vlastimil Babka FWIW, I've applied the whole patchset to 4.4 and the kde5 login problem didn't occur. I can test the next version too. Thanks, Vlastimil
[PATCH v3 2/2] drm: remove drm_device_is_unplugged and related code
When a UDL monitor is unplugged, we need to still treat it as a fully
functional device which just happens to have its connector unplugged.
This allows user-space to properly deallocate fbs and dumb buffers
before closing the device.
This drops the "unplugged" flag hack, which puts the device in a
non-functional state after USB unplug and rejects most operations on
the device such as ioctls with error -ENODEV.
Signed-off-by: Haixia Shi
Reviewed-by: Stéphane Marchesin
Cc: David Herrmann
---
drivers/gpu/drm/drm_drv.c | 6 --
drivers/gpu/drm/drm_fops.c | 2 --
drivers/gpu/drm/drm_gem.c | 3 ---
drivers/gpu/drm/drm_ioctl.c | 3 ---
drivers/gpu/drm/drm_vm.c| 3 ---
drivers/gpu/drm/udl/udl_connector.c | 2 --
drivers/gpu/drm/udl/udl_fb.c| 6 --
include/drm/drmP.h | 14 --
8 files changed, 39 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 167c8d3..f93ee12 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -376,9 +376,6 @@ struct drm_minor *drm_minor_acquire(unsigned int minor_id)
if (!minor) {
return ERR_PTR(-ENODEV);
- } else if (drm_device_is_unplugged(minor->dev)) {
- drm_dev_unref(minor->dev);
- return ERR_PTR(-ENODEV);
}
return minor;
@@ -464,9 +461,6 @@ void drm_unplug_dev(struct drm_device *dev)
drm_minor_unregister(dev, DRM_MINOR_CONTROL);
mutex_lock(&drm_global_mutex);
-
- drm_device_set_unplugged(dev);
-
if (dev->open_count == 0) {
drm_put_dev(dev);
}
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 1ea8790..b4332d4 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -497,8 +497,6 @@ int drm_release(struct inode *inode, struct file *filp)
if (!--dev->open_count) {
retcode = drm_lastclose(dev);
- if (drm_device_is_unplugged(dev))
- drm_put_dev(dev);
}
mutex_unlock(&drm_global_mutex);
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 2e8c77e..c622e32 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -900,9 +900,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct
*vma)
struct drm_vma_offset_node *node;
int ret;
- if (drm_device_is_unplugged(dev))
- return -ENODEV;
-
drm_vma_offset_lock_lookup(dev->vma_offset_manager);
node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
vma->vm_pgoff,
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 8ce2a0c..f959074 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -695,9 +695,6 @@ long drm_ioctl(struct file *filp,
dev = file_priv->minor->dev;
- if (drm_device_is_unplugged(dev))
- return -ENODEV;
-
is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END;
if (is_driver_ioctl) {
diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
index f90bd5f..3a68be4 100644
--- a/drivers/gpu/drm/drm_vm.c
+++ b/drivers/gpu/drm/drm_vm.c
@@ -657,9 +657,6 @@ int drm_legacy_mmap(struct file *filp, struct
vm_area_struct *vma)
struct drm_device *dev = priv->minor->dev;
int ret;
- if (drm_device_is_unplugged(dev))
- return -ENODEV;
-
mutex_lock(&dev->struct_mutex);
ret = drm_mmap_locked(filp, vma);
mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/udl/udl_connector.c
b/drivers/gpu/drm/udl/udl_connector.c
index 4709b54..a6d5e21 100644
--- a/drivers/gpu/drm/udl/udl_connector.c
+++ b/drivers/gpu/drm/udl/udl_connector.c
@@ -96,8 +96,6 @@ static int udl_mode_valid(struct drm_connector *connector,
static enum drm_connector_status
udl_detect(struct drm_connector *connector, bool force)
{
- if (drm_device_is_unplugged(connector->dev))
- return connector_status_disconnected;
return connector_status_connected;
}
diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
index 200419d..29aca6c 100644
--- a/drivers/gpu/drm/udl/udl_fb.c
+++ b/drivers/gpu/drm/udl/udl_fb.c
@@ -321,12 +321,6 @@ static void udl_fb_imageblit(struct fb_info *info, const
struct fb_image *image)
static int udl_fb_open(struct fb_info *info, int user)
{
struct udl_fbdev *ufbdev = info->par;
- struct drm_device *dev = ufbdev->ufb.base.dev;
- struct udl_device *udl = dev->dev_private;
-
- /* If the USB device is gone, we don't accept new opens */
- if (drm_device_is_unplugged(udl->ddev))
- return -ENODEV;
ufbdev->fb_count++;
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index d7162cf..40c6099 100644
--- a/include/drm/drmP.h
+++ b/includ
[REGRESSION] i915: No HDMI output with 4.4
Ville, here is another dmesg: [1] I've reconnected HDMI cable three times. Forgot to note, it is HDMI monitor plugged into machine's DVI with HDMI-DVI cable. I guess this should matter as well. [1] https://gist.github.com/7057ea8512b9aa7ee5bd 11.02.2016 11:26, Ville Syrjälä напиÑав: > On Thu, Feb 11, 2016 at 10:54:08AM +0200, Oleksandr Natalenko wrote: >> Daniel, >> >> I've already tried Ville's patch you've mentioned with no luck. >> >> Kindly find unpatched v4.5-rc3 dmesg with drm debug enabled here: [1] >> >> [1] https://gist.github.com/efb44b7c6bc325978b80 > > That's an IVB. So no wonder my patch doesn't help. > > Can you grab another dmesg after disconnecting and reconnecting the > HDMI cable?
[PATCH v7 3/5] dma-buf: Add ioctls to allow userspace to flush
On Thu, Feb 11, 2016 at 12:54 PM, Tiago Vignatti
wrote:
>
> Thanks for reviewing, David. Please take a look in my comments in-line.
>
>
> On 02/09/2016 07:26 AM, David Herrmann wrote:
>>
>>
>> On Tue, Dec 22, 2015 at 10:36 PM, Tiago Vignatti
>> wrote:
>>>
>>> From: Daniel Vetter
>>>
>>> The userspace might need some sort of cache coherency management e.g.
>>> when CPU
>>> and GPU domains are being accessed through dma-buf at the same time. To
>>> circumvent this problem there are begin/end coherency markers, that
>>> forward
>>> directly to existing dma-buf device drivers vfunc hooks. Userspace can
>>> make use
>>> of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The sequence would
>>> be
>>> used like following:
>>> - mmap dma-buf fd
>>> - for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2.
>>> read/write
>>> to mmap area 3. SYNC_END ioctl. This can be repeated as often as
>>> you
>>> want (with the new data being consumed by the GPU or say scanout
>>> device)
>>> - munmap once you don't need the buffer any more
>>>
>>> v2 (Tiago): Fix header file type names (u64 -> __u64)
>>> v3 (Tiago): Add documentation. Use enum dma_buf_sync_flags to the
>>> begin/end
>>> dma-buf functions. Check for overflows in start/length.
>>> v4 (Tiago): use 2d regions for sync.
>>> v5 (Tiago): forget about 2d regions (v4); use _IOW in DMA_BUF_IOCTL_SYNC
>>> and
>>> remove range information from struct dma_buf_sync.
>>> v6 (Tiago): use __u64 structured padded flags instead enum. Adjust
>>> documentation about the recommendation on using sync ioctls.
>>> v7 (Tiago): Alex' nit on flags definition and being even more wording in
>>> the
>>> doc about sync usage.
>>>
>>> Cc: Sumit Semwal
>>> Signed-off-by: Daniel Vetter
>>> Signed-off-by: Tiago Vignatti
>>> ---
>>> Documentation/dma-buf-sharing.txt | 21 ++-
>>> drivers/dma-buf/dma-buf.c | 43
>>> +++
>>> include/uapi/linux/dma-buf.h | 38
>>> ++
>>> 3 files changed, 101 insertions(+), 1 deletion(-)
>>> create mode 100644 include/uapi/linux/dma-buf.h
>>>
>>> diff --git a/Documentation/dma-buf-sharing.txt
>>> b/Documentation/dma-buf-sharing.txt
>>> index 4f4a84b..32ac32e 100644
>>> --- a/Documentation/dma-buf-sharing.txt
>>> +++ b/Documentation/dma-buf-sharing.txt
>>> @@ -350,7 +350,26 @@ Being able to mmap an export dma-buf buffer object
>>> has 2 main use-cases:
>>> handles, too). So it's beneficial to support this in a similar
>>> fashion on
>>> dma-buf to have a good transition path for existing Android
>>> userspace.
>>>
>>> - No special interfaces, userspace simply calls mmap on the dma-buf fd.
>>> + No special interfaces, userspace simply calls mmap on the dma-buf fd,
>>> making
>>> + sure that the cache synchronization ioctl (DMA_BUF_IOCTL_SYNC) is
>>> *always*
>>> + used when the access happens. This is discussed next paragraphs.
>>> +
>>> + Some systems might need some sort of cache coherency management e.g.
>>> when
>>> + CPU and GPU domains are being accessed through dma-buf at the same
>>> time. To
>>> + circumvent this problem there are begin/end coherency markers, that
>>> forward
>>> + directly to existing dma-buf device drivers vfunc hooks. Userspace
>>> can make
>>> + use of those markers through the DMA_BUF_IOCTL_SYNC ioctl. The
>>> sequence
>>> + would be used like following:
>>> + - mmap dma-buf fd
>>> + - for each drawing/upload cycle in CPU 1. SYNC_START ioctl, 2.
>>> read/write
>>> + to mmap area 3. SYNC_END ioctl. This can be repeated as often as
>>> you
>>> + want (with the new data being consumed by the GPU or say scanout
>>> device)
>>> + - munmap once you don't need the buffer any more
>>> +
>>> +Therefore, for correctness and optimal performance, systems with the
>>> memory
>>> +cache shared by the GPU and CPU i.e. the "coherent" and also the
>>> +"incoherent" are always required to use SYNC_START and SYNC_END
>>> before and
>>> +after, respectively, when accessing the mapped address.
>>>
>>> 2. Supporting existing mmap interfaces in importers
>>>
>>> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
>>> index b2ac13b..9a298bd 100644
>>> --- a/drivers/dma-buf/dma-buf.c
>>> +++ b/drivers/dma-buf/dma-buf.c
>>> @@ -34,6 +34,8 @@
>>> #include
>>> #include
>>>
>>> +#include
>>> +
>>> static inline int is_dma_buf_file(struct file *);
>>>
>>> struct dma_buf_list {
>>> @@ -251,11 +253,52 @@ out:
>>> return events;
>>> }
>>>
>>> +static long dma_buf_ioctl(struct file *file,
>>> + unsigned int cmd, unsigned long arg)
>>> +{
>>> + struct dma_buf *dmabuf;
>>> + struct dma_buf_sync sync;
>>> + enum dma_data_direction direction;
>>> +
>>> + dmabuf = file->private_data;
>>> +
>>> + if (!is_dma_buf_file(file))
>>> + return -EINVAL;
>>
>>
>>
[PATCH 5/5] drm/exynos: remove incorrect ccflags from Makefile
Include directories are provided by core already, adding them in driver is redundand and causes warnings in cause of out-of-tree build. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/Makefile | 1 - drivers/gpu/drm/exynos/exynos_drm_rotator.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile index 6496532..968b31c 100644 --- a/drivers/gpu/drm/exynos/Makefile +++ b/drivers/gpu/drm/exynos/Makefile @@ -2,7 +2,6 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/exynos exynosdrm-y := exynos_drm_drv.o exynos_drm_crtc.o exynos_drm_fbdev.o \ exynos_drm_fb.o exynos_drm_gem.o exynos_drm_core.o \ exynos_drm_plane.o diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c index bea0f78..72c9511 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c +++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c @@ -20,7 +20,6 @@ #include #include #include "regs-rotator.h" -#include "exynos_drm.h" #include "exynos_drm_drv.h" #include "exynos_drm_ipp.h" -- 1.9.1
[PATCH 4/5] drm/exynos/decon: make irq handler static
The function is used only locally.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 98615e2..7223919 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -431,7 +431,7 @@ static void decon_disable(struct exynos_drm_crtc *crtc)
set_bit(BIT_SUSPENDED, &ctx->flags);
}
-void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
+static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
{
struct decon_context *ctx = crtc->ctx;
--
1.9.1
[PATCH 3/5] drm/exynos/hdmi: remove unused variable
The variable is unused for long time.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 9ec3ab1..c702efc 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1043,10 +1043,8 @@ static void hdmi_reg_infoframe(struct hdmi_context
*hdata,
{
u32 hdr_sum;
u8 chksum;
- u32 mod;
u8 ar;
- mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
if (hdata->dvi_mode) {
hdmi_reg_writeb(hdata, HDMI_VSI_CON,
HDMI_VSI_CON_DO_NOT_TRANSMIT);
--
1.9.1
[PATCH 2/5] drm/exynos/dsi: constify read only structures
All global variables are read only.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 54fcf00..34b1edd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -241,7 +241,7 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_VIDOUT_AVAILABLEBIT(3)
struct exynos_dsi_driver_data {
- unsigned int *reg_ofs;
+ const unsigned int *reg_ofs;
unsigned int plltmr_reg;
unsigned int has_freqband:1;
unsigned int has_clklane_stop:1;
@@ -249,7 +249,7 @@ struct exynos_dsi_driver_data {
unsigned int max_freq;
unsigned int wait_for_reset;
unsigned int num_bits_resol;
- unsigned int *reg_values;
+ const unsigned int *reg_values;
};
struct exynos_dsi {
@@ -330,7 +330,7 @@ static inline u32 exynos_dsi_read(struct exynos_dsi *dsi,
enum reg_idx idx)
return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
}
-static unsigned int exynos_reg_ofs[] = {
+static const unsigned int exynos_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x00,
[DSIM_SWRST_REG] = 0x04,
[DSIM_CLKCTRL_REG] = 0x08,
@@ -354,7 +354,7 @@ static unsigned int exynos_reg_ofs[] = {
[DSIM_PHYTIMING2_REG] = 0x6c,
};
-static unsigned int exynos5433_reg_ofs[] = {
+static const unsigned int exynos5433_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x04,
[DSIM_SWRST_REG] = 0x0C,
[DSIM_CLKCTRL_REG] = 0x10,
@@ -396,7 +396,7 @@ enum reg_value_idx {
PHYTIMING_HS_TRAIL
};
-static unsigned int reg_values[] = {
+static const unsigned int reg_values[] = {
[RESET_TYPE] = DSIM_SWRST,
[PLL_TIMER] = 500,
[STOP_STATE_CNT] = 0xf,
@@ -414,7 +414,7 @@ static unsigned int reg_values[] = {
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
};
-static unsigned int exynos5422_reg_values[] = {
+static const unsigned int exynos5422_reg_values[] = {
[RESET_TYPE] = DSIM_SWRST,
[PLL_TIMER] = 500,
[STOP_STATE_CNT] = 0xf,
@@ -432,7 +432,7 @@ static unsigned int exynos5422_reg_values[] = {
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
};
-static unsigned int exynos5433_reg_values[] = {
+static const unsigned int exynos5433_reg_values[] = {
[RESET_TYPE] = DSIM_FUNCRST,
[PLL_TIMER] = 22200,
[STOP_STATE_CNT] = 0xa,
@@ -450,7 +450,7 @@ static unsigned int exynos5433_reg_values[] = {
[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
};
-static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
+static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x50,
.has_freqband = 1,
@@ -462,7 +462,7 @@ static struct exynos_dsi_driver_data
exynos3_dsi_driver_data = {
.reg_values = reg_values,
};
-static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x50,
.has_freqband = 1,
@@ -474,7 +474,7 @@ static struct exynos_dsi_driver_data
exynos4_dsi_driver_data = {
.reg_values = reg_values,
};
-static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
+static const struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x58,
.has_clklane_stop = 1,
@@ -485,7 +485,7 @@ static struct exynos_dsi_driver_data
exynos4415_dsi_driver_data = {
.reg_values = reg_values,
};
-static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
.reg_ofs = exynos_reg_ofs,
.plltmr_reg = 0x58,
.num_clks = 2,
@@ -495,7 +495,7 @@ static struct exynos_dsi_driver_data
exynos5_dsi_driver_data = {
.reg_values = reg_values,
};
-static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
+static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
.reg_ofs = exynos5433_reg_ofs,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
@@ -506,7 +506,7 @@ static struct exynos_dsi_driver_data
exynos5433_dsi_driver_data = {
.reg_values = exynos5433_reg_values,
};
-static struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
+static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
.reg_ofs = exynos5433_reg_ofs,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
@@ -517,7 +517,7 @@ static struct exynos_dsi_driver_data
exynos5422_dsi_driver_data = {
.reg_values = exynos5422_reg_values,
};
-static struct of_device_id exynos_dsi_of_match[] = {
+static const struct of_device_id exynos_dsi_of_match[] = {
[PATCH 1/5] drm/exynos/dsi: replace registry access macros with functions
Functions are preferred over macros as more type-safe.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 108 +---
1 file changed, 57 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 3eff6bf..54fcf00 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -209,12 +209,6 @@
#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
-#define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \
- dsi->driver_data->reg_ofs[(reg_idx)])
-#define DSI_WRITE(dsi, reg_idx, val) writel((val), \
- REG_ADDR((dsi), (reg_idx)))
-#define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx)))
-
static char *clk_names[5] = { "bus_clk", "sclk_mipi",
"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
"sclk_rgb_vclk_to_dsim0" };
@@ -324,6 +318,18 @@ enum reg_idx {
DSIM_PHYTIMING2_REG,
NUM_REGS
};
+
+static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
+ u32 val)
+{
+ writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
+}
+
+static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
+{
+ return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
+}
+
static unsigned int exynos_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x00,
[DSIM_SWRST_REG] = 0x04,
@@ -546,10 +552,10 @@ static void exynos_dsi_wait_for_reset(struct exynos_dsi
*dsi)
static void exynos_dsi_reset(struct exynos_dsi *dsi)
{
- struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+ u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
reinit_completion(&dsi->completed);
- DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]);
+ exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
}
#ifndef MHZ
@@ -652,7 +658,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
reg |= DSIM_FREQ_BAND(band);
}
- DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg);
+ exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
timeout = 1000;
do {
@@ -660,7 +666,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi
*dsi,
dev_err(dsi->dev, "PLL failed to stabilize\n");
return 0;
}
- reg = DSI_READ(dsi, DSIM_STATUS_REG);
+ reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
} while ((reg & DSIM_PLL_STABLE) == 0);
return fout;
@@ -690,7 +696,7 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
hs_clk, byte_clk, esc_clk);
- reg = DSI_READ(dsi, DSIM_CLKCTRL_REG);
+ reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
| DSIM_BYTE_CLK_SRC_MASK);
@@ -700,7 +706,7 @@ static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
| DSIM_BYTE_CLK_SRC(0)
| DSIM_TX_REQUEST_HSCLK;
- DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg);
+ exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
return 0;
}
@@ -717,7 +723,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
/* B D-PHY: D-PHY Master & Slave Analog Block control */
reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
reg_values[PHYCTRL_SLEW_UP];
- DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg);
+ exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
/*
* T LPX: Transmitted length of any Low-Power state period
@@ -725,7 +731,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
* burst
*/
reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
- DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg);
+ exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
/*
* T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
@@ -745,7 +751,7 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
reg_values[PHYTIMING_CLK_POST] |
reg_values[PHYTIMING_CLK_TRAIL];
- DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg);
+ exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
/*
* T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
@@ -758,29 +764,29 @@ static void exynos_dsi_set_phy_ctrl(struct exynos_dsi
*dsi)
*/
reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
reg_values[PHYTIMING_HS_TR
[PATCH 0/5] Misc fixes/improvements for Exynos DRM
Hi Inki, This set of small fixes and improvements is based on exynos-drm-next, except patch 'drm/exynos/dsi: constify read only structures', which requires '[PATCH] drm/exynos: support exynos5422 mipi-dsi' which you have just picked up :) Regards Andrzej Andrzej Hajda (5): drm/exynos/dsi: replace registry access macros with functions drm/exynos/dsi: constify read only structures drm/exynos/hdmi: remove unused variable drm/exynos/decon: make irq handler static drm/exynos: remove incorrect ccflags from Makefile drivers/gpu/drm/exynos/Makefile | 1 - drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 138 ++ drivers/gpu/drm/exynos/exynos_drm_rotator.c | 1 - drivers/gpu/drm/exynos/exynos_hdmi.c | 2 - 5 files changed, 73 insertions(+), 71 deletions(-) -- 1.9.1
[PATCH] drm/exynos: fix incorrect cpu address for dma_mmap_attrs()
dma_mmap_attrs() should be called with cpu address returned by
dma_alloc_attrs(). Existing code however passed pages array base as cpu
address. This worked only by a pure luck on ARM architecture. This patch
fixes this issue.
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 2 +-
drivers/gpu/drm/exynos/exynos_drm_gem.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index f6118ba..8baabd8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -50,7 +50,7 @@ static int exynos_drm_fb_mmap(struct fb_info *info,
if (vm_size > exynos_gem->size)
return -EINVAL;
- ret = dma_mmap_attrs(helper->dev->dev, vma, exynos_gem->pages,
+ ret = dma_mmap_attrs(helper->dev->dev, vma, exynos_gem->cookie,
exynos_gem->dma_addr, exynos_gem->size,
&exynos_gem->dma_attrs);
if (ret < 0) {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c
b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 47d126a..26b5e4b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -335,7 +335,7 @@ static int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem
*exynos_gem,
if (vm_size > exynos_gem->size)
return -EINVAL;
- ret = dma_mmap_attrs(drm_dev->dev, vma, exynos_gem->pages,
+ ret = dma_mmap_attrs(drm_dev->dev, vma, exynos_gem->cookie,
exynos_gem->dma_addr, exynos_gem->size,
&exynos_gem->dma_attrs);
if (ret < 0) {
--
1.9.2
radeon_drm.h: missing TILE_MODE definition?
On Thu, Feb 11, 2016 at 11:55 AM, Alexandre Demers wrote: > > On Thu, 11 Feb 2016 at 10:30 Alex Deucher wrote: >> >> On Thu, Feb 11, 2016 at 12:23 AM, Alexandre Demers >> wrote: >> > I was looking at /drivers/gpu/drm/radeon/atombios_crtc.c and at >> > radeon_drm.h >> > (both under kernel and libdrm). I noticed that there seems to be a >> > missing >> > TILE_MODE definition: under atombios_crtc, line 1289 >> > (/drivers/gpu/drm/radeon/atombios_crtc.c#L1289), an unexplained value is >> > being used (index = 10;) compared to the rest of the code around where >> > defined variables are being used. >> > >> > Looking at the defined variables under radeon_drm.h, there is a missing >> > value in the tile index. Index 10 is missing. If it was defined, it >> > could be >> > used in place of the numerical value at line 1289 under atombios_crtc.c. >> > According to the other names and usages, shouldn't there be a #define >> > SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10? In fact, the equivalent of >> > SI_TILE_MODE_COLORD_2D_8BPP is CIK_TILE_MODE_COLOR_2D under CIK; under >> > CIK, >> > there is a variable defined for index 10, which is >> > CIK_TILE_MODE_COLOR_2D_SCANOUT. Thus, I'd be inclined to think there >> > should >> > really be a SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP variable defined. >> > >> > I've been searching in the SI 3D register documentation and I couldn't >> > find >> > a tile index table to relate to. >> > >> > Lastly, based on how the other "X_2D_SCANOUT_YBPP" variables are covered >> > under si_surface_sanity() (libdrm's radeon_surface.c), is it expected >> > that >> > this index value (10) is not covered specifically. Should there be a >> > "case >> > 1: *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP; break;" at line >> > 1362, >> > before "case 2: ..."? Would it make sense? >> > >> >> I don't think it's a particularly useful case. In practice I doubt it >> would ever be hit. I guess it's for 8bpp greyscale. The 3D engine >> can't render to indexed color or 332 surfaces. If you aren't using >> the 3D engine, there's not much point in using tiling to begin with. >> >> Alex > > > Thanks for the answer. > > At least, I'd like to add a "#define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP > 10;" (if that variable name makes sense, I'm open to any other more > meaningful name) just so we don't have a "index = 10" right there in the > middle of the code while other cases use defined variables: it is mostly > about consistency and readability of the code. Any objection? > Go ahead. Alex > Your comment is more about if this case/index value should be covered under > si_surface_sanity(). I'll trust you on the fact that it shouldn't be > encountered. > > Cheers > Alexandre Demers
[PATCH] drm/exynos/decon: fix disable clocks order
Decon requires that clocks should be disabled in reverse order. Otherwise
system hangs.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 1bf6a21..98615e2 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -582,9 +582,9 @@ out:
static int exynos5433_decon_suspend(struct device *dev)
{
struct decon_context *ctx = dev_get_drvdata(dev);
- int i;
+ int i = ARRAY_SIZE(decon_clks_name);
- for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++)
+ while (--i >= 0)
clk_disable_unprepare(ctx->clks[i]);
return 0;
--
1.9.1
[Intel-gfx] [PATCH v2 1/2] drm: Add infrastructure for CRTC background color property (v2)
Hi Matt, [auto build test WARNING on drm/drm-next] [also build test WARNING on v4.5-rc3 next-20160210] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Matt-Roper/CRTC-background-color-support-for-i915/20160211-103451 base: git://people.freedesktop.org/~airlied/linux.git drm-next reproduce: make htmldocs All warnings (new ones prefixed by >>): drivers/gpu/drm/i915/i915_irq.c:2659: warning: No description found for parameter 'wedged' drivers/gpu/drm/i915/i915_irq.c:2659: warning: No description found for parameter 'fmt' include/drm/drm_crtc.h:447: warning: No description found for parameter 'mode_blob' include/drm/drm_crtc.h:862: warning: No description found for parameter 'name' include/drm/drm_crtc.h:1320: warning: No description found for parameter 'tile_blob_ptr' include/drm/drm_crtc.h:1359: warning: No description found for parameter 'rotation' include/drm/drm_crtc.h:1621: warning: No description found for parameter 'name' include/drm/drm_crtc.h:1621: warning: No description found for parameter 'mutex' include/drm/drm_crtc.h:1621: warning: No description found for parameter 'helper_private' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tile_idr' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'delayed_event' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'edid_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'dpms_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'path_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tile_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'plane_type_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'rotation_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_x' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_y' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_w' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_src_h' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_x' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_y' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_w' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_h' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_fb_id' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_crtc_id' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_active' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'prop_mode_id' >> include/drm/drm_crtc.h:2231: warning: No description found for parameter >> 'prop_background_color' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'dvi_i_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'dvi_i_select_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_select_subconnector_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_mode_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_left_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_right_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_top_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_bottom_margin_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_brightness_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_contrast_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_flicker_reduction_property' include/drm/drm_crtc.h:2231: warning: No description found for parameter 'tv_overscan_property&
[PATCH 29/29] drm/amd/dal: Force bw programming for DCE 10 until we start calculate BW.
From: Andrey Grodzovsky
Signed-off-by: Andrey Grodzovsky
Acked-by: Jordan Lazare
Reviewed-by: Harry Wentland
---
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c| 28 --
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c| 3 ++-
2 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
index 82c5e155d91a..a1dbac487366 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -335,33 +335,6 @@ static void dal_dc_clock_gating_dce100_power_up(struct
dc_context *ctx, bool ena
}
}
-/**
- * Call display_engine_clock_dce80 to perform the Dclk programming.
- */
-static void set_display_clock(struct validate_context *context)
-{
- /* Program the display engine clock.
-* Check DFS bypass mode support or not. DFSbypass feature is only when
-* BIOS GPU info table reports support. */
-
- if (/*dal_adapter_service_is_dfs_bypass_enabled()*/ false) {
- /*TODO: set_display_clock_dfs_bypass(
- hws,
- path_set,
- context->res_ctx.pool.display_clock,
- context->res_ctx.min_clocks.min_dclk_khz);*/
- } else
- dal_display_clock_set_clock(context->res_ctx.pool.display_clock,
- 681000);
-
- /* TODO: When changing display engine clock, DMCU WaitLoop must be
-* reconfigured in order to maintain the same delays within DMCU
-* programming sequences. */
-
- /* TODO: Start GTC counter */
-}
-
-
static void set_displaymarks(
const struct dc *dc, struct validate_context *context)
{
@@ -381,7 +354,6 @@ bool dce100_hw_sequencer_construct(struct dc *dc)
dc->hwss.enable_fe_clock = dce100_enable_fe_clock;
dc->hwss.pipe_control_lock = dce100_pipe_control_lock;
dc->hwss.set_blender_mode = dce100_set_blender_mode;
- dc->hwss.set_display_clock = set_display_clock;
dc->hwss.set_displaymarks = set_displaymarks;
return true;
}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index e67ba81f1c85..783d47eba325 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -773,7 +773,8 @@ enum dc_status dce100_validate_bandwidth(
const struct dc *dc,
struct validate_context *context)
{
- /* TODO implement when needed */
+ /* TODO implement when needed but for now hardcode max value*/
+ context->bw_results.dispclk_khz = 681000;
return DC_OK;
}
--
2.1.4
[PATCH 28/29] drm/amd/dal: fix flip clean-up state
From: Mykola Lysenko
Get on par with buffer management changes made in base driver
Signed-off-by: Mykola Lysenko
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 10 --
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 17 +++--
2 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
index aeb7887356cd..0ceb505355e8 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -1329,7 +1329,7 @@ void amdgpu_dm_flip_cleanup(
} else
DRM_ERROR("failed to reserve buffer after flip\n");
- drm_gem_object_unreference_unlocked(&works->old_rbo->gem_base);
+ amdgpu_bo_unref(&works->old_rbo);
kfree(works->shared);
kfree(works);
}
@@ -1379,13 +1379,11 @@ static void dm_page_flip(struct amdgpu_device *adev,
target = acrtc->target;
/*
-* Received a page flip call after the display has been reset. Make sure
-* we return the buffers.
+* Received a page flip call after the display has been reset.
+* Just return in this case. Everything should be clean-up on reset.
*/
- if (!target) {
- amdgpu_dm_flip_cleanup(adev, acrtc);
+ if (!target)
return;
- }
addr.address.grph.addr.low_part = lower_32_bits(crtc_base);
addr.address.grph.addr.high_part = upper_32_bits(crtc_base);
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
index da6c0116aa1a..7643f751fcc6 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
@@ -1972,22 +1972,27 @@ static void manage_dm_interrupts(
struct amdgpu_crtc *acrtc,
bool enable)
{
+ /*
+* this is not correct translation but will work as soon as VBLANK
+* constant is the same as PFLIP
+*/
+ int irq_type =
+ amdgpu_crtc_idx_to_irq_type(
+ adev,
+ acrtc->crtc_id);
+
if (enable) {
drm_crtc_vblank_on(&acrtc->base);
amdgpu_irq_get(
adev,
&adev->pageflip_irq,
- amdgpu_crtc_idx_to_irq_type(
- adev,
- acrtc->crtc_id));
+ irq_type);
} else {
unsigned long flags;
amdgpu_irq_put(
adev,
&adev->pageflip_irq,
- amdgpu_crtc_idx_to_irq_type(
- adev,
- acrtc->crtc_id));
+ irq_type);
drm_crtc_vblank_off(&acrtc->base);
/*
--
2.1.4
[PATCH 27/29] drm/amd/dal: Correctly interpret rotation as bit set
Signed-off-by: Harry Wentland
Reviewed-by: Mykola Lysenko
---
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
index 1cc9fd1054ab..da6c0116aa1a 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
@@ -366,16 +366,16 @@ static bool fill_rects_from_plane_state(
surface->clip_rect = surface->dst_rect;
switch (state->rotation) {
- case DRM_ROTATE_0:
+ case BIT(DRM_ROTATE_0):
surface->rotation = ROTATION_ANGLE_0;
break;
- case DRM_ROTATE_90:
+ case BIT(DRM_ROTATE_90):
surface->rotation = ROTATION_ANGLE_90;
break;
- case DRM_ROTATE_180:
+ case BIT(DRM_ROTATE_180):
surface->rotation = ROTATION_ANGLE_180;
break;
- case DRM_ROTATE_270:
+ case BIT(DRM_ROTATE_270):
surface->rotation = ROTATION_ANGLE_270;
break;
default:
--
2.1.4
[PATCH 26/29] drm/amdgpu: Use dal driver for Carrizo, Tonga, and Fiji
Start to use dal by default on Carrizo, Tonga, and Fiji ASICs.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Kconfig | 3 +
drivers/gpu/drm/amd/amdgpu/Makefile| 17 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 69 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 20 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 54 ++-
drivers/gpu/drm/amd/amdgpu/vi.c| 250 +
9 files changed, 402 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig
b/drivers/gpu/drm/amd/amdgpu/Kconfig
index b30fcfa4b1f2..3a37e37bef28 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -15,3 +15,6 @@ config DRM_AMDGPU_USERPTR
help
This option selects CONFIG_MMU_NOTIFIER if it isn't already
selected to enabled full userptr support.
+
+source "drivers/gpu/drm/amd/dal/Kconfig"
+
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7fcdcedaadb..c434ee5c589f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -3,13 +3,19 @@
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
FULL_AMD_PATH=$(src)/..
+DAL_FOLDER_NAME=dal
+FULL_AMD_DAL_PATH = $(FULL_AMD_PATH)/$(DAL_FOLDER_NAME)
ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_PATH)/include \
-I$(FULL_AMD_PATH)/amdgpu \
-I$(FULL_AMD_PATH)/scheduler \
-I$(FULL_AMD_PATH)/powerplay/inc \
- -I$(FULL_AMD_PATH)/acp/include
+ -I$(FULL_AMD_PATH)/acp/include \
+ -I$(FULL_AMD_DAL_PATH) \
+ -I$(FULL_AMD_DAL_PATH)/include \
+ -I$(FULL_AMD_DAL_PATH)/dc \
+ -I$(FULL_AMD_DAL_PATH)/amdgpu_dm
amdgpu-y := amdgpu_drv.o
@@ -118,6 +124,15 @@ amdgpu-y += $(AMD_POWERPLAY_FILES)
endif
+ifneq ($(CONFIG_DRM_AMD_DAL),)
+
+RELATIVE_AMD_DAL_PATH = ../$(DAL_FOLDER_NAME)
+include $(FULL_AMD_DAL_PATH)/Makefile
+
+amdgpu-y += $(AMD_DAL_FILES)
+
+endif
+
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
CFLAGS_amdgpu_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 99e660fec190..d154b3473ae8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -54,6 +54,7 @@
#include "amdgpu_gds.h"
#include "amd_powerplay.h"
#include "amdgpu_acp.h"
+#include "amdgpu_dm.h"
#include "gpu_scheduler.h"
@@ -85,6 +86,7 @@ extern int amdgpu_vm_debug;
extern int amdgpu_sched_jobs;
extern int amdgpu_sched_hw_submission;
extern int amdgpu_powerplay;
+extern int amdgpu_dal;
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
#define AMDGPU_MAX_USEC_TIMEOUT10 /* 100 ms */
@@ -2017,6 +2019,7 @@ struct amdgpu_device {
/* display */
struct amdgpu_mode_info mode_info;
+ /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
struct work_struct hotplug_work;
struct amdgpu_irq_src crtc_irq;
struct amdgpu_irq_src pageflip_irq;
@@ -2064,6 +2067,9 @@ struct amdgpu_device {
/* GDS */
struct amdgpu_gds gds;
+ /* display related functionality */
+ struct amdgpu_display_manager dm;
+
const struct amdgpu_ip_block_version *ip_blocks;
int num_ip_blocks;
struct amdgpu_ip_block_status *ip_block_status;
@@ -2100,7 +2106,7 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg,
u32 v);
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
-
+bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
/*
* Cast helper
*/
@@ -2345,6 +2351,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_gds_switch(adev, r, v, d, w, a)
(adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
+#define amdgpu_has_dal_support(adev) (amdgpu_dal &&
amdgpu_device_has_dal_support(adev))
+
/* Common functions */
int amdgpu_gpu_reset(struct amdgpu_device *adev);
void amdgpu_pci_config_reset(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f0fb938457d9..3df6fe35ec63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1369,6 +1369,32 @@ static int amdgpu_resume(struct amdgpu_device *adev)
return 0;
}
+
+/**
+ * amdgpu_device_has_dal_support - check if dal is supported
+ *
+ * @adev: amdgpu_device_pointer
+ *
+ * Returns true for supported, false for not supported
+ */
+bool amdgpu_device_has_dal_support(struct amdgpu_dev
[PATCH 25/29] drm/amd/dal: Adding amdgpu_dm for dal
Implements DRM's atomic KMS interfaces using DC.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile | 17 +
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 1470 +++
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h | 168 ++
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 474
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 820 +++
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h | 122 +
.../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c| 480
.../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h| 36 +
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 457
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c| 2572
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h| 100 +
drivers/gpu/drm/amd/dal/dc/dm_services.h | 17 -
12 files changed, 6716 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
new file mode 100644
index ..0f365c65342e
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile for the 'dm' sub-component of DAL.
+# It provides the control and status of dm blocks.
+
+
+
+AMDGPUDM = amdgpu_dm_types.o amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o
+
+ifneq ($(CONFIG_DRM_AMD_DAL),)
+AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o
+endif
+
+subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc
+
+AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))
+
+AMD_DAL_FILES += $(AMDGPU_DM)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
new file mode 100644
index ..aeb7887356cd
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -0,0 +1,1470 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services_types.h"
+#include "dc.h"
+
+#include "vid.h"
+#include "amdgpu.h"
+#include "atom.h"
+#include "amdgpu_dm.h"
+#include "amdgpu_dm_types.h"
+
+#include "amd_shared.h"
+#include "amdgpu_dm_irq.h"
+#include "dm_helpers.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "dce/dce_11_0_enum.h"
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "oss/oss_3_0_d.h"
+#include "oss/oss_3_0_sh_mask.h"
+#include "gmc/gmc_8_1_d.h"
+#include "gmc/gmc_8_1_sh_mask.h"
+
+#include
+#include
+
+#include
+#include
+#include
+
+/* TODO: Remove when mc access work around is removed */
+static const u32 crtc_offsets[] =
+{
+ CRTC0_REGISTER_OFFSET,
+ CRTC1_REGISTER_OFFSET,
+ CRTC2_REGISTER_OFFSET,
+ CRTC3_REGISTER_OFFSET,
+ CRTC4_REGISTER_OFFSET,
+ CRTC5_REGISTER_OFFSET,
+ CRTC6_REGISTER_OFFSET
+};
+/* TODO: End of when Remove mc access work around is removed */
+
+/* Define variables here
+ * These values will be passed to DAL for feature enable purpose
+ * Disable ALL for HDMI light up
+ * TODO: follow up if need this mechanism*/
+struct dal_override_parameters display_param = {
+
[PATCH 24/29] drm/amd/dal: Add display core
Adds a logical representation of our hardware. Provides ability to - dc_validate_resources - validate a display configuration - dc_commit_targets - commit a display configuration - dc_commit_surfaces_to_target - update surfaces - dc_link_detect - detect displays at link - dc_resume - resume display HW - dc_interrupt_set/ack - set and ack interrupts - etc. Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/Makefile | 28 + drivers/gpu/drm/amd/dal/dc/core/dc.c | 932 +++ drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c | 56 + drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 1644 drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 1151 ++ drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 1728 + drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c| 201 +++ drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 1243 +++ drivers/gpu/drm/amd/dal/dc/core/dc_sink.c | 116 ++ drivers/gpu/drm/amd/dal/dc/core/dc_stream.c | 188 +++ drivers/gpu/drm/amd/dal/dc/core/dc_surface.c | 123 ++ drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 548 +++ 12 files changed, 7958 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_sink.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_stream.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_surface.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_target.c diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile new file mode 100644 index ..aed26eec81f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/Makefile @@ -0,0 +1,28 @@ +# +# Makefile for Display Core (dc) component. +# + +DC_LIBS = adapter asic_capability audio basics bios calcs \ +gpio gpu i2caux irq virtual + +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 +DC_LIBS += dce110 +endif + +ifdef CONFIG_DRM_AMD_DAL_DCE10_0 +DC_LIBS += dce100 +endif + +AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS))) + +include $(AMD_DC) + +DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_target.o dc_sink.o dc_stream.o \ +dc_hw_sequencer.o dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o + +AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE)) + +AMD_DAL_FILES += $(AMD_DISPLAY_CORE) + + + diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c new file mode 100644 index ..0b8f158c0ec2 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c @@ -0,0 +1,932 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#include "dm_services.h" + +#include "dc.h" + +#include "core_status.h" +#include "core_types.h" +#include "hw_sequencer.h" + +#include "resource.h" + +#include "adapter_service_interface.h" +#include "clock_source.h" +#include "dc_bios_types.h" + +#include "bandwidth_calcs.h" +#include "include/irq_service_interface.h" +#include "transform.h" +#include "timing_generator.h" +#include "virtual/virtual_link_encoder.h" + +#include "link_hwss.h" +#include "link_encoder.h" + +#include "dc_link_ddc.h" + +/*** + * Private structures + **/ + +struct dc
[PATCH 23/29] drm/amd/dal: Add empty encoder programming for virtual HW
Adds empty encoder HW programming functions to support
enablement of virtual pipes (i.e. pipes without actual
display output).
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/virtual/Makefile| 9 ++
.../drm/amd/dal/dc/virtual/virtual_link_encoder.c | 133 +
.../drm/amd/dal/dc/virtual/virtual_link_encoder.h | 35 ++
.../amd/dal/dc/virtual/virtual_stream_encoder.c| 124 +++
.../amd/dal/dc/virtual/virtual_stream_encoder.h| 39 ++
5 files changed, 340 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
b/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
new file mode 100644
index ..0e2cbc0bb532
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the virtual sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o
+
+AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL))
+
+AMD_DAL_FILES += $(AMD_DAL_VIRTUAL)
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
new file mode 100644
index ..ade443d79c02
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services_types.h"
+
+#include "virtual_link_encoder.h"
+
+#define VIRTUAL_MAX_PIXEL_CLK_IN_KHZ 60
+
+static bool virtual_link_encoder_validate_output_with_stream(
+ struct link_encoder *enc,
+ struct core_stream *stream) { return true; }
+
+static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
+
+static void virtual_link_encoder_setup(
+ struct link_encoder *enc,
+ enum signal_type signal) {}
+
+static void virtual_link_encoder_enable_tmds_output(
+ struct link_encoder *enc,
+ enum clock_source_id clock_source,
+ enum dc_color_depth color_depth,
+ bool hdmi,
+ bool dual_link,
+ uint32_t pixel_clock) {}
+
+static void virtual_link_encoder_enable_dp_output(
+ struct link_encoder *enc,
+ const struct link_settings *link_settings,
+ enum clock_source_id clock_source) {}
+
+static void virtual_link_encoder_enable_dp_mst_output(
+ struct link_encoder *enc,
+ const struct link_settings *link_settings,
+ enum clock_source_id clock_source) {}
+
+static void virtual_link_encoder_disable_output(
+ struct link_encoder *link_enc,
+ enum signal_type signal) {}
+
+static void virtual_link_encoder_dp_set_lane_settings(
+ struct link_encoder *enc,
+ const struct link_training_settings *link_settings) {}
+
+static void virtual_link_encoder_dp_set_phy_pattern(
+ struct link_encoder *enc,
+ const struct encoder_set_dp_phy_pattern_param *param) {}
+
+static void virtual_link_encoder_update_mst_stream_allocation_table(
+ struct link_encoder *enc,
+ const struct link_mst_stream_allocation_table *table) {}
+
+static void virtual_link_encoder_set_lcd_backlight_level(
+ struct link_encoder *enc,
+ uint32_t level) {}
+
+static void virtual_link_encoder_edp_backlight_control(
+ struct link_encoder *enc,
+ bool enable) {}
+
+static void virtual_link_encoder_edp_power_control(
+ struct link_encoder *enc,
+ bool power_up) {}
+
+static void vir
[PATCH 22/29] drm/amd/dal: Add Tonga/Fiji HW sequencer and resource
Enables HW programming on Tonga and Fiji (DCE 10) ASICs. This
mostly re-uses DCE 11 programming code with minor exceptions
and using DCE 10 register offsets.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce100/Makefile | 23 +
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c| 388 +++
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.h| 36 +
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c| 1134
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.h| 43 +
5 files changed, 1624 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
new file mode 100644
index ..656c38e1b0f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE100 = dce100_resource.o dce100_hw_sequencer.o
+
+AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
+
+AMD_DAL_FILES += $(AMD_DAL_DCE100)
+
+
+###
+# DCE 10x
+###
+ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
+TG_DCE100 = dce100_resource.o
+
+AMD_DAL_TG_DCE100 = $(addprefix \
+ $(AMDDALPATH)/dc/dce100/,$(TG_DCE100))
+
+AMD_DAL_FILES += $(AMD_DAL_TG_DCE100)
+endif
+
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
new file mode 100644
index ..82c5e155d91a
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -0,0 +1,388 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dc.h"
+#include "core_dc.h"
+#include "core_types.h"
+#include "hw_sequencer.h"
+#include "dce100_hw_sequencer.h"
+#include "dce110/dce110_hw_sequencer.h"
+
+/* include DCE10 register header files */
+#include "dce/dce_10_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+
+struct dce100_hw_seq_reg_offsets {
+ uint32_t blnd;
+ uint32_t crtc;
+};
+
+enum pipe_lock_control {
+ PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
+ PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
+ PIPE_LOCK_CONTROL_SCL = 1 << 2,
+ PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
+ PIPE_LOCK_CONTROL_MODE = 1 << 4
+};
+
+enum blender_mode {
+ BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ BLENDER_MODE_STEREO
+};
+
+static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
+{
+ .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+}
+};
+
+#define HW_REG_BLND(reg, id)\
+ (reg + reg_offsets[id].blnd)
+
+#define HW_REG_CRTC(reg, id)\
+ (reg + reg_offsets[id].crtc)
+
+
+/***
+ * Private definitions
+
**/
+/**
[PATCH 21/29] drm/amd/dal: Add Carrizo HW sequencer and resource
Adds dce110_resource and dce110_hw_sequencer files.
dce110_resource manages creation of HW resources, along with correct
ASIC register offset for each block.
dce110_hw_sequencers is responsible for programming HW sequences,
such as enable_stream, program_scaler, power_down_encoders, etc.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce110/Makefile | 15 +
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c| 1658
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h| 36 +
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c| 1238 +++
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.h| 46 +
5 files changed, 2993 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
new file mode 100644
index ..ae9d2de92da2
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
@@ -0,0 +1,15 @@
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
+dce110_ipp_gamma.o dce110_link_encoder.o dce110_opp.o \
+dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
+dce110_timing_generator.o dce110_transform.o dce110_transform_gamut.o \
+dce110_transform_scl.o dce110_transform_sclv.o dce110_opp_csc.o\
+dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
+dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o
+
+AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
+
+AMD_DAL_FILES += $(AMD_DAL_DCE110)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
new file mode 100644
index ..71fa7b1f8061
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -0,0 +1,1658 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dc.h"
+#include "dc_bios_types.h"
+#include "core_types.h"
+#include "core_status.h"
+#include "resource.h"
+#include "hw_sequencer.h"
+#include "dm_helpers.h"
+#include "dce110_hw_sequencer.h"
+
+#include "gpu/dce110/dc_clock_gating_dce110.h"
+
+#include "timing_generator.h"
+#include "mem_input.h"
+#include "opp.h"
+#include "ipp.h"
+#include "transform.h"
+#include "stream_encoder.h"
+#include "link_encoder.h"
+#include "clock_source.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+struct dce110_hw_seq_reg_offsets {
+ uint32_t dcfe;
+ uint32_t blnd;
+ uint32_t crtc;
+};
+
+enum pipe_lock_control {
+ PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
+ PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
+ PIPE_LOCK_CONTROL_SCL = 1 << 2,
+ PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
+ PIPE_LOCK_CONTROL_MODE = 1 << 4
+};
+
+enum blender_mode {
+ BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ BLENDER_MODE_STEREO
+};
+
+static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
+{
+ .dcfe = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
+ .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .dcfe = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL
[PATCH 20/29] drm/amd/dal: Add transform & scaler HW programming
Adds scaler, viewport, gamut remap, and pixel depth programming.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 91 +++
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 87 +++
.../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 851 +
.../amd/dal/dc/dce110/dce110_transform_bit_depth.h | 51 ++
.../drm/amd/dal/dc/dce110/dce110_transform_gamut.c | 296 +++
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 818
.../drm/amd/dal/dc/dce110/dce110_transform_sclv.c | 531 +
7 files changed, 2725 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
new file mode 100644
index ..2654a965065d
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dc_types.h"
+#include "core_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/fixed31_32.h"
+#include "include/logger_interface.h"
+
+#include "dce110_transform.h"
+
+#include "dce110_transform_bit_depth.h"
+
+static struct transform_funcs dce110_transform_funcs = {
+ .transform_power_up =
+ dce110_transform_power_up,
+ .transform_set_scaler =
+ dce110_transform_set_scaler,
+ .transform_set_scaler_bypass =
+ dce110_transform_set_scaler_bypass,
+ .transform_update_viewport =
+ dce110_transform_update_viewport,
+ .transform_set_scaler_filter =
+ dce110_transform_set_scaler_filter,
+ .transform_set_gamut_remap =
+ dce110_transform_set_gamut_remap,
+ .transform_set_pixel_storage_depth =
+ dce110_transform_set_pixel_storage_depth,
+ .transform_get_current_pixel_storage_depth =
+ dce110_transform_get_current_pixel_storage_depth
+};
+
+/*/
+/* Constructor, Destructor */
+/*/
+
+bool dce110_transform_construct(
+ struct dce110_transform *xfm110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dce110_transform_reg_offsets *reg_offsets)
+{
+ xfm110->base.ctx = ctx;
+
+ xfm110->base.inst = inst;
+ xfm110->base.funcs = &dce110_transform_funcs;
+
+ xfm110->offsets = *reg_offsets;
+
+ xfm110->lb_pixel_depth_supported =
+ LB_PIXEL_DEPTH_18BPP |
+ LB_PIXEL_DEPTH_24BPP |
+ LB_PIXEL_DEPTH_30BPP;
+
+ return true;
+}
+
+bool dce110_transform_power_up(struct transform *xfm)
+{
+ return dce110_transform_power_up_line_buffer(xfm);
+}
+
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
new file mode 100644
index ..117aca337f9d
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
@@ -0,0 +1,87 @@
+/* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted,
[PATCH 19/29] drm/amd/dal: Add output pixel processing HW programming
Adds programming for color space conversion (CSC),
regamma, and formatter.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c | 272 +++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h | 143 ++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c | 904 +++
.../drm/amd/dal/dc/dce110/dce110_opp_formatter.c | 610 +
.../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 2474
5 files changed, 4403 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
new file mode 100644
index ..acb405e7b2e7
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dce110_opp.h"
+
+#include "gamma_types.h"
+
+enum {
+ MAX_LUT_ENTRY = 256,
+ MAX_NUMBER_OF_ENTRIES = 256
+};
+
+static void build_evenly_distributed_points(
+ struct gamma_pixel *points,
+ uint32_t numberof_points,
+ struct fixed31_32 max_value,
+ struct fixed31_32 divider1,
+ struct fixed31_32 divider2,
+ struct fixed31_32 divider3)
+{
+ struct gamma_pixel *p = points;
+ struct gamma_pixel *p_last = p + numberof_points - 1;
+
+ uint32_t i = 0;
+
+ do {
+ struct fixed31_32 value = dal_fixed31_32_div_int(
+ dal_fixed31_32_mul_int(max_value, i),
+ numberof_points - 1);
+
+ p->r = value;
+ p->g = value;
+ p->b = value;
+
+ ++p;
+ ++i;
+ } while (i != numberof_points);
+
+ p->r = dal_fixed31_32_div(p_last->r, divider1);
+ p->g = dal_fixed31_32_div(p_last->g, divider1);
+ p->b = dal_fixed31_32_div(p_last->b, divider1);
+
+ ++p;
+
+ p->r = dal_fixed31_32_div(p_last->r, divider2);
+ p->g = dal_fixed31_32_div(p_last->g, divider2);
+ p->b = dal_fixed31_32_div(p_last->b, divider2);
+
+ ++p;
+
+ p->r = dal_fixed31_32_div(p_last->r, divider3);
+ p->g = dal_fixed31_32_div(p_last->g, divider3);
+ p->b = dal_fixed31_32_div(p_last->b, divider3);
+}
+
+/*/
+/* Constructor, Destructor */
+/*/
+
+struct opp_funcs funcs = {
+ .opp_map_legacy_and_regamma_hw_to_x_user =
dce110_opp_map_legacy_and_regamma_hw_to_x_user,
+ .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
+ .opp_program_bit_depth_reduction =
dce110_opp_program_bit_depth_reduction,
+ .opp_program_clamping_and_pixel_encoding =
dce110_opp_program_clamping_and_pixel_encoding,
+ .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
+ .opp_set_csc_default = dce110_opp_set_csc_default,
+ .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
+ .opp_set_regamma = dce110_opp_set_regamma
+};
+
+bool dce110_opp_construct(struct dce110_opp *opp110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dce110_opp_reg_offsets *offsets)
+{
+
+ opp110->base.funcs = &funcs;
+
+ opp110->base.ctx = ctx;
+
+ opp110->base.inst = inst;
+
+ opp110->offs
[PATCH 18/29] drm/amd/dal: Add input pixel processing HW programming
Adds programming of cursor and input gamma.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c | 65 ++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h | 100 +++
.../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c | 256 ++
.../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c | 872 +
4 files changed, 1293 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
new file mode 100644
index ..6ab35272f979
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dce110_ipp.h"
+
+static struct ipp_funcs funcs = {
+ .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes,
+ .ipp_cursor_set_position = dce110_ipp_cursor_set_position,
+ .ipp_program_prescale = dce110_ipp_program_prescale,
+ .ipp_set_degamma = dce110_ipp_set_degamma,
+ .ipp_set_legacy_input_gamma_mode =
dce110_ipp_set_legacy_input_gamma_mode,
+ .ipp_set_legacy_input_gamma_ramp =
dce110_ipp_set_legacy_input_gamma_ramp,
+ .ipp_set_palette = dce110_ipp_set_palette,
+};
+
+bool dce110_ipp_construct(
+ struct dce110_ipp* ipp,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dce110_ipp_reg_offsets *offset)
+{
+ ipp->base.ctx = ctx;
+
+ ipp->base.inst = inst;
+
+ ipp->offsets = *offset;
+
+ ipp->base.funcs = &funcs;
+
+ return true;
+}
+
+void dce110_ipp_destroy(struct input_pixel_processor **ipp)
+{
+ dm_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
+ *ipp = NULL;
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
new file mode 100644
index ..709906face3f
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_IPP_DCE110_H__
+#define __DC_IPP_DCE110_H__
+
+#include "inc/ipp.h"
+
+
+struct gamma_parameters;
+struct dev_c_lut;
+
+#define TO_DCE110_IPP(input_pixel_processor)\
+ container_of(input_pixel_processor, struct dce110_ipp,
[PATCH 17/29] drm/amd/dal: Add framebuffer compression HW programming
Adds framebuffer compression programming. Currently unused.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 886 +
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h | 84 ++
2 files changed, 970 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
new file mode 100644
index ..285d54439f4c
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
@@ -0,0 +1,886 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "gmc/gmc_8_2_sh_mask.h"
+#include "gmc/gmc_8_2_d.h"
+
+#include "include/logger_interface.h"
+#include "include/adapter_service_interface.h"
+
+#include "dce110_compressor.h"
+
+#define DCP_REG(reg)\
+ (reg + cp110->offsets.dcp_offset)
+#define DMIF_REG(reg)\
+ (reg + cp110->offsets.dmif_offset)
+
+static const struct dce110_compressor_reg_offsets reg_offsets[] = {
+{
+ .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+ .dmif_offset =
+ (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
+ - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
+},
+{
+ .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+ .dmif_offset =
+ (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
+ - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
+},
+{
+ .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+ .dmif_offset =
+ (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
+ - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
+}
+};
+
+static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
+
+enum fbc_idle_force {
+ /* Bit 0 - Display registers updated */
+ FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x0001,
+
+ /* Bit 2 - FBC_GRPH_COMP_EN register updated */
+ FBC_IDLE_FORCE_GRPH_COMP_EN = 0x0002,
+ /* Bit 3 - FBC_SRC_SEL register updated */
+ FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x0004,
+ /* Bit 4 - FBC_MIN_COMPRESSION register updated */
+ FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x0008,
+ /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
+ FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x0010,
+ /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
+ FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x0020,
+ /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
+ FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x0040,
+
+ /* Bit 24 - Memory write to region 0 defined by MC registers. */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x0100,
+ /* Bit 25 - Memory write to region 1 defined by MC registers */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x0200,
+ /* Bit 26 - Memory write to region 2 defined by MC registers */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x0400,
+ /* Bit 27 - Memory write to region 3 defined by MC registers. */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x0800,
+
+ /* Bit 28 - Memory write from any client other than MCIF */
+ FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x1000,
+ /* Bit 29 - CG statics screen signal is inactive */
+ FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x2000,
+};
+
+static uint32_t lpt_size_alignment(struct dce110_compressor *cp110)
+{
+ /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
+ return cp110->base.raw_size * cp110->base.banks_num *
+ cp110->base.dram_channels_num;
+}
+
+static uint32_t lpt
[PATCH 16/29] drm/amd/dal: Add surface HW programming
Adds watermark, DMIF, and surface programming.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 965 +
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 117 +++
2 files changed, 1082 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
new file mode 100644
index ..3a928e63e647
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -0,0 +1,965 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+/* TODO: this needs to be looked at, used by Stella's workaround*/
+#include "gmc/gmc_8_2_d.h"
+#include "gmc/gmc_8_2_sh_mask.h"
+
+#include "include/logger_interface.h"
+#include "adapter_service_interface.h"
+#include "inc/bandwidth_calcs.h"
+
+#include "dce110_mem_input.h"
+
+#define MAX_WATERMARK 0x
+#define SAFE_NBP_MARK 0x7FFF
+
+#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
+#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
+#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
+
+static void set_flip_control(
+ struct dce110_mem_input *mem_input110,
+ bool immediate)
+{
+ uint32_t value = 0;
+
+ value = dm_read_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_FLIP_CONTROL));
+ set_reg_field_value(value, 0,
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
+ set_reg_field_value(value, 0,
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_H_RETRACE_EN);
+ if (immediate == true)
+ set_reg_field_value(value, 1,
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
+
+ dm_write_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_FLIP_CONTROL),
+ value);
+}
+
+static void program_sec_addr(
+ struct dce110_mem_input *mem_input110,
+ PHYSICAL_ADDRESS_LOC address)
+{
+ uint32_t value = 0;
+ uint32_t temp = 0;
+ /*high register MUST be programmed first*/
+ temp = address.high_part &
+GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
+
+ set_reg_field_value(value, temp,
+ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
+ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
+
+ dm_write_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH),
+ value);
+
+ temp = 0;
+ value = 0;
+ temp = address.low_part >>
+ GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
+
+ set_reg_field_value(value, temp,
+ GRPH_SECONDARY_SURFACE_ADDRESS,
+ GRPH_SECONDARY_SURFACE_ADDRESS);
+
+ dm_write_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS),
+ value);
+}
+
+static void program_pri_addr(
+ struct dce110_mem_input *mem_input110,
+ PHYSICAL_ADDRESS_LOC address)
+{
+ uint32_t value = 0;
+ uint32_t temp = 0;
+
+ /*high register MUST be programmed first*/
+ temp = address.high_part &
+GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
+
+ set_reg_field_value(value, temp,
+ GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
+ GRPH_PRIMARY_SURFACE_ADDR
[PATCH 15/29] drm/amd/dal: Add timing generator HW programming
Adds ability to validate and program timings, enable, disable, and blank
CRTCs, and get CRTC status information.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../amd/dal/dc/dce110/dce110_timing_generator.c| 1864
.../amd/dal/dc/dce110/dce110_timing_generator.h| 234 +++
2 files changed, 2098 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
new file mode 100644
index ..6e6a7a5cac6a
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
@@ -0,0 +1,1864 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dc_types.h"
+#include "dc_bios_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/adapter_service_interface.h"
+#include "include/logger_interface.h"
+#include "dce110_timing_generator.h"
+
+#include "../inc/timing_generator.h"
+
+enum black_color_format {
+ BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
+ BLACK_COLOR_FORMAT_RGB_LIMITED,
+ BLACK_COLOR_FORMAT_YUV_TV,
+ BLACK_COLOR_FORMAT_YUV_CV,
+ BLACK_COLOR_FORMAT_YUV_SUPER_AA,
+
+ BLACK_COLOR_FORMAT_COUNT
+};
+
+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
+
+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
+
+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
+
+
+/***
+ * GSL Sync related values */
+
+/* In VSync mode, after 4 units of time, master pipe will generate
+ * flip_ready signal */
+#define VFLIP_READY_DELAY 4
+/* In HSync mode, after 2 units of time, master pipe will generate
+ * flip_ready signal */
+#define HFLIP_READY_DELAY 2
+/* 6 lines delay between forcing flip and checking all pipes ready */
+#define HFLIP_CHECK_DELAY 6
+/* 3 lines before end of frame */
+#define FLIP_READY_BACK_LOOKUP 3
+
+/* Trigger Source Select - ASIC-dependant, actual values for the
+ * register programming */
+enum trigger_source_select {
+ TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0,
+ TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1,
+ TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2,
+ TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3,
+ TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4,
+ TRIGGER_SOURCE_SELECT_GENERICF = 5,
+ TRIGGER_SOURCE_SELECT_GENERICE = 6,
+ TRIGGER_SOURCE_SELECT_VSYNCA = 7,
+ TRIGGER_SOURCE_SELECT_HSYNCA = 8,
+ TRIGGER_SOURCE_SELECT_VSYNCB = 9,
+ TRIGGER_SOURCE_SELECT_HSYNCB = 10,
+ TRIGGER_SOURCE_SELECT_HPD1 = 11,
+ TRIGGER_SOURCE_SELECT_HPD2 = 12,
+ TRIGGER_SOURCE_SELECT_GENERICD = 13,
+ TRIGGER_SOURCE_SELECT_GENERICC = 14,
+ TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15,
+ TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16,
+ TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17,
+ TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18,
+ TRIGGER_SOURCE_SELECT_BLONY = 19,
+ TRIGGER_SOURCE_SELECT_GENERICA = 20,
+ TRIGGER_SOURCE_SELECT_GENERICB = 21,
+ TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22,
+ TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23
+};
+
+/* Trigger Source Select - ASIC-dependant, actual values for the
+ * register programming */
+enum trigger_polarity_select {
+ TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0,
+ TRIGGER_POLARITY_SELECT_CRTC = 1,
+ TRIGGER_POLARITY_SELECT_GENERICA = 2,
+ TRIGGER_POLARITY_S
[PATCH 14/29] drm/amd/dal: Add clock source HW programming
Adds pixel clock programming and functionality to
power down clock sources.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../drm/amd/dal/dc/dce110/dce110_clock_source.c| 1162
.../drm/amd/dal/dc/dce110/dce110_clock_source.h| 64 ++
2 files changed, 1226 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
new file mode 100644
index ..e1bac1f77b79
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
@@ -0,0 +1,1162 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dc_types.h"
+#include "core_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/logger_interface.h"
+
+#include "dce110_clock_source.h"
+
+#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
+#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
+#define MAX_PLL_CALC_ERROR 0x
+
+static const struct spread_spectrum_data *get_ss_data_entry(
+ struct dce110_clk_src *clk_src,
+ enum signal_type signal,
+ uint32_t pix_clk_khz)
+{
+
+ uint32_t entrys_num;
+ uint32_t i;
+ struct spread_spectrum_data *ss_parm = NULL;
+ struct spread_spectrum_data *ret = NULL;
+
+ switch (signal) {
+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
+ case SIGNAL_TYPE_DVI_DUAL_LINK:
+ ss_parm = clk_src->dvi_ss_params;
+ entrys_num = clk_src->dvi_ss_params_cnt;
+ break;
+
+ case SIGNAL_TYPE_HDMI_TYPE_A:
+ ss_parm = clk_src->hdmi_ss_params;
+ entrys_num = clk_src->hdmi_ss_params_cnt;
+ break;
+
+ case SIGNAL_TYPE_DISPLAY_PORT:
+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
+ case SIGNAL_TYPE_EDP:
+ ss_parm = clk_src->dp_ss_params;
+ entrys_num = clk_src->dp_ss_params_cnt;
+ break;
+
+ default:
+ ss_parm = NULL;
+ entrys_num = 0;
+ break;
+ }
+
+ if (ss_parm == NULL)
+ return ret;
+
+ for (i = 0; i < entrys_num; ++i, ++ss_parm) {
+ if (ss_parm->freq_range_khz >= pix_clk_khz) {
+ ret = ss_parm;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+* Function: calculate_fb_and_fractional_fb_divider
+*
+* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
+*
+*PARAMETERS:
+* targetPixelClock Desired frequency in 10 KHz
+* ref_divider Reference divider (already known)
+* postDivider Post Divider (already known)
+* feedback_divider_param Pointer where to store
+* calculated feedback divider value
+* fract_feedback_divider_param Pointer where to store
+* calculated fract feedback divider value
+*
+*RETURNS:
+* It fills the locations pointed by feedback_divider_param
+* and fract_feedback_divider_param
+* It returns - true if feedback divider not 0
+* - false should never happen)
+*/
+static bool calculate_fb_and_fractional_fb_divider(
+ struct calc_pll_clock_source *calc_pll_cs,
+ uint32_t target_pix_clk_khz,
+ uint32_t ref_divider,
+ uint32_t post_divider,
+ uint32_t *feedback_divider_param,
+ uint32_t *fract_feedback_divider_param)
+{
+ uint64_t feedbac
[PATCH 13/29] drm/amd/dal: Add encoder HW programming
Responsible for programming back-end of display path, such as DIG,
UNIPHY, DP, DAC, and DVO.
Supports:
- DisplayPort (single stream)
- HDMI
- DVI
- eDP
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../drm/amd/dal/dc/dce110/dce110_link_encoder.c| 1927
.../drm/amd/dal/dc/dce110/dce110_link_encoder.h| 156 ++
.../drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 1123
.../drm/amd/dal/dc/dce110/dce110_stream_encoder.h | 122 ++
4 files changed, 3328 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
new file mode 100644
index ..f714215c0dd5
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
@@ -0,0 +1,1927 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "core_types.h"
+#include "link_encoder.h"
+#include "stream_encoder.h"
+#include "dce110_link_encoder.h"
+
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "dce/dce_11_0_enum.h"
+
+#define LINK_REG(reg)\
+ (enc110->link_regs->reg)
+
+#define AUX_REG(reg)\
+ (enc110->aux_regs->reg)
+
+#define BL_REG(reg)\
+ (enc110->bl_regs->reg)
+
+/* For current ASICs pixel clock - 600MHz */
+#define MAX_ENCODER_CLK 60
+
+#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 60
+
+#define DEFAULT_AUX_MAX_DATA_SIZE 16
+#define AUX_MAX_DEFER_WRITE_RETRY 20
+/*
+ * @brief
+ * Trigger Source Select
+ * ASIC-dependent, actual values for register programming
+ */
+#define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
+
+/* all values are in milliseconds */
+/* For eDP, after power-up/power/down,
+ * 300/500 msec max. delay from LCDVCC to black video generation */
+#define PANEL_POWER_UP_TIMEOUT 300
+#define PANEL_POWER_DOWN_TIMEOUT 500
+#define HPD_CHECK_INTERVAL 10
+
+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
+#define TMDS_MIN_PIXEL_CLOCK 25000
+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
+#define TMDS_MAX_PIXEL_CLOCK 165000
+/* For current ASICs pixel clock - 600MHz */
+#define MAX_ENCODER_CLOCK 60
+
+enum {
+ DP_MST_UPDATE_MAX_RETRY = 50
+};
+
+#define DIG_REG(reg)\
+ (reg + enc110->offsets.dig)
+
+#define DP_REG(reg)\
+ (reg + enc110->offsets.dp)
+
+static struct link_encoder_funcs dce110_lnk_enc_funcs = {
+ .validate_output_with_stream =
+ dce110_link_encoder_validate_output_with_stream,
+ .hw_init = dce110_link_encoder_hw_init,
+ .setup = dce110_link_encoder_setup,
+ .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
+ .enable_dp_output = dce110_link_encoder_enable_dp_output,
+ .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
+ .disable_output = dce110_link_encoder_disable_output,
+ .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
+ .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
+ .update_mst_stream_allocation_table =
+ dce110_link_encoder_update_mst_stream_allocation_table,
+ .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
+
[PATCH 12/29] drm/amd/dal: Bandwidth calculations
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/calcs/Makefile | 10 +
drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 3941
drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c| 300 ++
drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c | 1992 ++
drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h | 74 +
5 files changed, 6317 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
new file mode 100644
index ..7f1916b79b88
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the 'calcs' sub-component of DAL.
+# It calculates Bandwidth and Watermarks values for HW programming
+#
+
+BW_CALCS = bandwidth_calcs.o bw_fixed.o scaler_filter.o
+
+AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
+
+AMD_DAL_FILES += $(AMD_DAL_BW_CALCS)
diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
new file mode 100644
index ..8faabbc12fd3
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
@@ -0,0 +1,3941 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "bandwidth_calcs.h"
+
+/***
+ * Private Functions
+
**/
+
+static void calculate_bandwidth(
+ const struct bw_calcs_dceip *dceip,
+ const struct bw_calcs_vbios *vbios,
+ const struct bw_calcs_mode_data_internal *mode_data,
+ struct bw_calcs_results *results)
+
+{
+ const int32_t pixels_per_chunk = 512;
+ const int32_t max_chunks_non_fbc_mode = 16;
+ const int32_t high = 2;
+ const int32_t mid = 1;
+ const int32_t low = 0;
+
+ int32_t i, j, k;
+ struct bw_fixed yclk[3];
+ struct bw_fixed sclk[3];
+ bool d0_underlay_enable;
+ bool d1_underlay_enable;
+ enum bw_defines sclk_message;
+ enum bw_defines yclk_message;
+ enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
+ enum bw_defines tiling_mode[maximum_number_of_surfaces];
+ enum bw_defines stereo_mode[maximum_number_of_surfaces];
+ enum bw_defines surface_type[maximum_number_of_surfaces];
+ enum bw_defines voltage;
+ enum bw_defines pipe_check;
+ enum bw_defines hsr_check;
+ enum bw_defines vsr_check;
+ enum bw_defines lb_size_check;
+ enum bw_defines fbc_check;
+ enum bw_defines rotation_check;
+ enum bw_defines mode_check;
+
+ yclk[low] = vbios->low_yclk;
+ yclk[mid] = vbios->high_yclk;
+ yclk[high] = vbios->high_yclk;
+ sclk[low] = vbios->low_sclk;
+ sclk[mid] = vbios->mid_sclk;
+ sclk[high] = vbios->high_sclk;
+ /* surface assignment:*/
+ /* 0: d0 underlay or underlay luma*/
+ /* 1: d0 underlay chroma*/
+ /* 2: d1 underlay or underlay luma*/
+ /* 3: d1 underlay chroma*/
+ /* 4: d0 graphics*/
+ /* 5: d1 graphics*/
+ /* 6: d2 graphics*/
+ /* 7: d3 graphics, same mode as d2*/
+ /* 8: d4 graphics, same mode as d2*/
+ /* 9: d5 graphics, same mode as d2*/
+ /* ...*/
+ /* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
+ /* maximum_number_of_surfaces-1: d1 display_write_back420 c
[PATCH 11/29] drm/amd/dal: Audio
Responsible for programming the audio encoder in the display path.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/audio/Makefile | 22 +
drivers/gpu/drm/amd/dal/dc/audio/audio.h | 195 ++
drivers/gpu/drm/amd/dal/dc/audio/audio_base.c | 470 +
.../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c | 453 +
.../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h | 42 +
.../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 1930
.../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h | 47 +
drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c| 771
drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h| 285 +++
9 files changed, 4215 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile
b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
new file mode 100644
index ..0999372cecf0
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for the 'audio' sub-component of DAL.
+# It provides the control and status of HW adapter resources,
+# that are global for the ASIC and sharable between pipes.
+
+AUDIO = audio_base.o hw_ctx_audio.o
+
+AMD_DAL_AUDIO = $(addprefix $(AMDDALPATH)/dc/audio/,$(AUDIO))
+
+AMD_DAL_FILES += $(AMD_DAL_AUDIO)
+
+
+###
+# DCE 11x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+AUDIO_DCE11 = audio_dce110.o hw_ctx_audio_dce110.o
+
+AMD_DAL_AUDIO_DCE11 = $(addprefix
$(AMDDALPATH)/dc/audio/dce110/,$(AUDIO_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio.h
b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
new file mode 100644
index ..ad2dc18ef37b
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_AUDIO_H__
+#define __DAL_AUDIO_H__
+
+#include "include/audio_interface.h"
+#include "hw_ctx_audio.h"
+#include "include/link_service_types.h"
+
+/* only for hook functions */
+/**
+ *which will be overwritten by derived audio object.
+ *audio hw context object is independent object
+ */
+
+struct audio;
+
+struct audio_funcs {
+ /*
+*get_object_id
+*get_object_type
+*enumerate_input_signals
+*enumerate_output_signals
+*is_input_signal_supported
+*is_output_signal_supported
+*set_object_properties
+*get_object_properties
+*/
+
+ void (*destroy)(struct audio **audio);
+ /*power_up
+*power_down
+*release_hw_base
+*/
+
+ /* setup audio */
+ enum audio_result (*setup)(
+ struct audio *audio,
+ struct audio_output *output,
+ struct audio_info *info);
+
+ enum audio_result (*enable_output)(
+ struct audio *audio,
+ enum engine_id engine_id,
+ enum signal_type signal);
+
+ enum audio_result (*disable_output)(
+ struct audio *audio,
+ enum engine_id engine_id,
[PATCH 10/29] drm/amd/dal: GPU
Encapsulates programming for HW blocks which are shared between display
paths, such as clock sources.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/gpu/Makefile| 22 +
.../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c| 92 ++
.../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h| 63 ++
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 90 ++
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h | 33 +
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 968 +
.../amd/dal/dc/gpu/dce110/display_clock_dce110.h | 53 ++
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c | 205 +
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h | 82 ++
drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c | 127 +++
drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h | 63 ++
11 files changed, 1798 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
new file mode 100644
index ..b481a6d5c6bb
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for the 'gpu' sub-component of DAL.
+# It provides the control and status of HW adapter resources,
+# that are global for the ASIC and sharable between pipes.
+
+GPU = dc_clock_generator.o display_clock.o divider_range.o
+
+AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
+
+AMD_DAL_FILES += $(AMD_DAL_GPU)
+
+
+###
+# DCE 110 family
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+GPU_DCE110 = display_clock_dce110.o dc_clock_gating_dce110.o
+
+AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
+
+AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
new file mode 100644
index ..b3b0f99933f7
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "dc_clock_generator.h"
+
+void dal_dc_clock_generator_destroy(struct dc_clock_generator **dc)
+{
+ if (dc == NULL || *dc == NULL) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ (*dc)->funcs->destroy(dc);
+
+ *dc = NULL;
+}
+
+void dal_dc_clock_generator_set_display_pipe_mapping(
+ struct dc_clock_generator *dc_clk_gen,
+ struct dccg_mapping_params *params)
+{
+ dc_clk_gen->funcs->set_display_pipe_mapping(dc_clk_gen, params);
+}
+
+bool dal_dc_clock_generator_get_dp_ref_clk_ds_params(
+ struct dc_clock_generator *dc_clk_gen,
+ struct dccg_dp_ref_clk_ds_params *params)
+{
+ return dc_clk_gen->funcs->get_dp_ref_clk_ds_params(dc_clk_gen, params);
+}
+
+bool dal_dc_clock_generator_enable_gtc_counter(
+ struct dc_clock_generator *dc_clk_gen,
+ uint3
[PATCH 09/29] drm/amd/dal: IRQ Service
Interface to set and ack DCE interrupts.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/irq/Makefile| 21 ++
.../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c | 389 +
.../drm/amd/dal/dc/irq/dce110/irq_service_dce110.h | 34 ++
drivers/gpu/drm/amd/dal/dc/irq/irq_service.c | 177 ++
drivers/gpu/drm/amd/dal/dc/irq/irq_service.h | 85 +
5 files changed, 706 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.h
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/Makefile
b/drivers/gpu/drm/amd/dal/dc/irq/Makefile
new file mode 100644
index ..f1c5faf94b83
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/irq/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile for the 'audio' sub-component of DAL.
+# It provides the control and status of HW adapter resources,
+# that are global for the ASIC and sharable between pipes.
+
+IRQ = irq_service.o
+
+AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
+
+AMD_DAL_FILES += $(AMD_DAL_IRQ)
+
+###
+# DCE 11x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+IRQ_DCE11 = irq_service_dce110.o
+
+AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_IRQ_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
new file mode 100644
index ..4085b6f6e7fd
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce110.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ DC_HPD_INT_STATUS,
+ DC_HPD_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+ set_reg_field_value(
+ value,
+ current_status ? 0 : 1,
+ DC_HPD_INT_CONTROL,
+ DC_HPD_INT_POLARITY);
+
+ dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+ return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+ .set = NULL,
+ .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+#define hpd_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+ .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
+ .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
+ .enable_value = {\
+ DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
+ ~DC
[PATCH 08/29] drm/amd/dal: I2C Aux Manager
Implements low-level communication layer over I2C and Aux lines using GPIO handles. Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/i2caux/Makefile | 33 + drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c | 567 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h | 119 +++ .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 788 + .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.h | 56 ++ .../i2caux/dce110/i2c_generic_hw_engine_dce110.h | 25 + .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c| 954 + .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h| 58 ++ .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c| 172 .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h| 43 + .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 266 ++ .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 39 + .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c| 112 +++ .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h| 33 + drivers/gpu/drm/amd/dal/dc/i2caux/engine.h | 129 +++ drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c| 67 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c | 121 +++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h | 113 +++ .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c | 286 ++ .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h | 77 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c | 246 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h | 80 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c | 614 + drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h | 81 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 529 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 123 +++ 26 files changed, 5731 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile new file mode 100644 index ..390d83d649f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile @@ -0,0 +1,33 @@ +# +# Makefile for the 'i2c' sub-component of DAL. +# It provides the control and status of HW i2c engine of the adapter. + +I2CAUX = aux_engine.o engine_base.o i2caux.o i2c_engine.o \ +i2c_generic_hw_engine.o i2c_hw_engine.o i2c_sw_engine.o + +AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX)) + +AMD_DAL_FILES += $(AMD_DAL_I2CAUX) + + +### +# DCE 11x family +### +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 +I2CAUX_DCE110 = i2caux_dce110.o i2c_sw_engine_dce110.o i2c_hw_engine_dce110.o \ + aux_engine_dce110.o + +AMD_DAL_I2CAUX_DCE110 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce110/,$(I2CAUX_DCE110)) + +AMD_DAL_FILES += $(AMD_DAL_I2CAUX_DCE110) +endif + +### +# Diagnostics on FPGA +##
[PATCH 07/29] drm/amd/dal: BIOS Parser
Wrapper to access Video BIOS command and data tables Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/bios/Makefile | 26 + drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 5029 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h | 84 + .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c | 198 + .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h | 108 + drivers/gpu/drm/amd/dal/dc/bios/command_table.c| 2730 +++ drivers/gpu/drm/amd/dal/dc/bios/command_table.h| 117 + .../gpu/drm/amd/dal/dc/bios/command_table_helper.c | 285 ++ .../gpu/drm/amd/dal/dc/bios/command_table_helper.h | 90 + .../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 484 ++ .../dal/dc/bios/dce110/bios_parser_helper_dce110.h | 34 + .../dc/bios/dce110/command_table_helper_dce110.c | 366 ++ .../dc/bios/dce110/command_table_helper_dce110.h | 34 + 13 files changed, 9585 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile new file mode 100644 index ..ddfe457e3a8b --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile @@ -0,0 +1,26 @@ +# +# Makefile for the 'bios' sub-component of DAL. +# It provides the parsing and executing controls for atom bios image. + +BIOS = bios_parser.o bios_parser_helper.o command_table.o command_table_helper.o + +AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) + +AMD_DAL_FILES += $(AMD_DAL_BIOS) + +ifndef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT +AMD_DAL_FILES := $(filter-out $(AMDDALPATH)/dc/bios/bios_parser_helper.o,$(AMD_DAL_FILES)) +endif + + +### +# DCE 11x +### +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 + +ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT +AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/bios_parser_helper_dce110.o +endif + +AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o +endif diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c new file mode 100644 index ..4ce5f9fcf907 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c @@ -0,0 +1,5029 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "atom.h" + +#include "dc_bios_types.h" +#include "include/adapter_service_interface.h" +#include "include/grph_object_ctrl_defs.h" +#include "include/bios_parser_interface.h" +#include "include/i2caux_interface.h" +#include "include/logger_interface.h" + +#include "command_table.h" +#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT) +#include "bios_parser_helper.h" +#endif +#include "command_table_helper.h" +#include "bios_parser.h" +#include "bios_parser_interface.h"
[PATCH 06/29] drm/amd/dal: Adapter Service
Provides information about ASIC features and capabilities. Also provides access to ASIC resources such as VBIOS, GPIO and I2cAux Manager Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/adapter/Makefile| 24 + .../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 2089 .../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 71 + .../adapter/dce110/hw_ctx_adapter_service_dce110.c | 304 +++ .../adapter/dce110/hw_ctx_adapter_service_dce110.h | 40 + .../diagnostics/hw_ctx_adapter_service_diag.c | 133 ++ .../diagnostics/hw_ctx_adapter_service_diag.h | 33 + .../amd/dal/dc/adapter/hw_ctx_adapter_service.c| 164 ++ .../amd/dal/dc/adapter/hw_ctx_adapter_service.h| 86 + .../drm/amd/dal/dc/adapter/wireless_data_source.c | 208 ++ .../drm/amd/dal/dc/adapter/wireless_data_source.h | 80 + 11 files changed, 3232 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile new file mode 100644 index ..2c6ca7a513bd --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile @@ -0,0 +1,24 @@ +# +# Makefile for the 'adapter' sub-component of DAL. +# It provides the control and status of HW adapter. + +ADAPTER = adapter_service.o hw_ctx_adapter_service.o wireless_data_source.o + +AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER)) + +AMD_DAL_FILES += $(AMD_DAL_ADAPTER) + + +### +# DCE 11x +### + +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 +AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce110/hw_ctx_adapter_service_dce110.o +endif + +### +# FPGA Diagnositcs +### + +AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.o diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c new file mode 100644 index ..dd2f931fe9a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c @@ -0,0 +1,2089 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "dc_bios_types.h" + +#include "include/adapter_service_interface.h" +#include "include/i2caux_interface.h" +#include "include/asic_capability_types.h" +#include "include/gpio_service_interface.h" +#include "include/asic_capability_interface.h" +#include "include/logger_interface.h" + +#include "adapter_service.h" + +#include "hw_ctx_adapter_service.h" +#include "wireless_data_source.h" + +#include "atom.h" + +#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) +#include "dce110/hw_ctx_adapter_service_dce110.h" +#endif + +#include "diagnostics/hw_ctx_adapter
[PATCH 05/29] drm/amd/dal: GPIO (General Purpose IO)
Manages all DCE GPIO pins. The pins are represented as generic IO handles as well as handles dedicated for certain functions, such as DDC, HPD, and DVO. Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/gpio/Makefile | 32 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c | 882 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h | 46 ++ .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c | 81 ++ .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h | 32 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c | 366 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h | 47 ++ .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c | 400 ++ .../amd/dal/dc/gpio/dce110/hw_translate_dce110.h | 34 + drivers/gpu/drm/amd/dal/dc/gpio/ddc.c | 290 +++ drivers/gpu/drm/amd/dal/dc/gpio/ddc.h | 45 ++ .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c | 97 +++ .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h | 34 + .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c | 65 ++ .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.h | 32 + .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c | 101 +++ .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h | 35 + .../dal/dc/gpio/diagnostics/hw_translate_diag.c| 41 + .../dal/dc/gpio/diagnostics/hw_translate_diag.h| 34 + drivers/gpu/drm/amd/dal/dc/gpio/gpio.h | 48 ++ drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c| 279 +++ drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c | 386 + drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h | 57 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c | 104 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h | 60 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c | 93 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h | 71 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c | 407 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h | 129 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c | 92 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h | 47 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c | 85 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h | 79 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c | 87 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h | 45 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c | 77 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h | 50 ++ drivers/gpu/drm/amd/dal/dc/gpio/irq.c | 180 + drivers/gpu/drm/amd/dal/dc/gpio/irq.h | 42 + 39 files changed, 5112 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c create mode 100644 drivers/gpu
[PATCH 04/29] drm/amd/dal: Asic Capabilities
Add a generic way to manage display HW capabilities
for different ASICs and implement it for Carrizo.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/asic_capability/Makefile| 35
.../amd/dal/dc/asic_capability/asic_capability.c | 190 +
.../dc/asic_capability/carrizo_asic_capability.c | 147
.../dc/asic_capability/carrizo_asic_capability.h | 36
.../dal/dc/asic_capability/tonga_asic_capability.c | 146
.../dal/dc/asic_capability/tonga_asic_capability.h | 36
6 files changed, 590 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
new file mode 100644
index ..8491b38ae726
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
@@ -0,0 +1,35 @@
+#
+# Makefile for the 'asic_capability' sub-component of DAL.
+#
+
+ASIC_CAPABILITY = asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
+
+###
+# DCE 10x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE10_0
+ASIC_CAPABILITY_DCE10 = tonga_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE10 = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE10))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE10)
+endif
+
+
+###
+# DCE 11x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+ASIC_CAPABILITY_DCE11 = carrizo_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE11 = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
new file mode 100644
index ..7a905f532040
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "include/asic_capability_interface.h"
+#include "include/asic_capability_types.h"
+#include "include/dal_types.h"
+#include "include/dal_asic_id.h"
+
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+#include "tonga_asic_capability.h"
+#endif
+
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#include "carrizo_asic_capability.h"
+#endif
+
+/*
+ * Initializes asic_capability instance.
+ */
+static bool construct(
+ struct asic_capability *cap,
+ struct hw_asic_id *init,
+ struct dc_context *ctx)
+{
+ bool asic_supported = false;
+
+ cap->ctx = ctx;
+ dm_memset(cap->data, 0, sizeof(cap->data));
+
+ /* ASIC data */
+ cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
+ cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
+ cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
+ cap->runtime_flags = init->runtime_flags;
+ cap->data[ASIC_DATA_REVISION
[PATCH 03/29] drm/amd/dal: Fixed point arithmetic
Arithmetic operations on real numbers represented
as fixed-point numbers.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/basics/Makefile | 2 +-
drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c | 692 +
drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c | 223
3 files changed, 916 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile
b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
index 6f382812fae3..93e23714e411 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
@@ -3,7 +3,7 @@
# It provides the general basic services required by other DAL
# subcomponents.
-BASICS = conversion.o grph_object_id.o logger.o register_logger.o
signal_types.o vector.o
+BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o logger.o
register_logger.o signal_types.o vector.o
AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
new file mode 100644
index ..9f93b3b20634
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/fixed31_32.h"
+
+static inline uint64_t abs_i64(
+ int64_t arg)
+{
+ if (arg > 0)
+ return (uint64_t)arg;
+ else
+ return (uint64_t)(-arg);
+}
+
+/*
+ * @brief
+ * result = dividend / divisor
+ * *remainder = dividend % divisor
+ */
+static inline uint64_t complete_integer_division_u64(
+ uint64_t dividend,
+ uint64_t divisor,
+ uint64_t *remainder)
+{
+ uint64_t result;
+
+ ASSERT(divisor);
+
+ result = div64_u64_rem(dividend, divisor, remainder);
+
+ return result;
+}
+
+#define BITS_PER_FRACTIONAL_PART \
+ 32
+
+#define FRACTIONAL_PART_MASK \
+ ((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
+
+#define GET_INTEGER_PART(x) \
+ ((x) >> BITS_PER_FRACTIONAL_PART)
+
+#define GET_FRACTIONAL_PART(x) \
+ (FRACTIONAL_PART_MASK & (x))
+
+struct fixed31_32 dal_fixed31_32_from_fraction(
+ int64_t numerator,
+ int64_t denominator)
+{
+ struct fixed31_32 res;
+
+ bool arg1_negative = numerator < 0;
+ bool arg2_negative = denominator < 0;
+
+ uint64_t arg1_value = arg1_negative ? -numerator : numerator;
+ uint64_t arg2_value = arg2_negative ? -denominator : denominator;
+
+ uint64_t remainder;
+
+ /* determine integer part */
+
+ uint64_t res_value = complete_integer_division_u64(
+ arg1_value, arg2_value, &remainder);
+
+ ASSERT(res_value <= LONG_MAX);
+
+ /* determine fractional part */
+ {
+ uint32_t i = BITS_PER_FRACTIONAL_PART;
+
+ do {
+ remainder <<= 1;
+
+ res_value <<= 1;
+
+ if (remainder >= arg2_value) {
+ res_value |= 1;
+ remainder -= arg2_value;
+ }
+ } while (--i != 0);
+ }
+
+ /* round up LSB */
+ {
+ uint64_t summand = (remainder << 1) >= arg2_value;
+
+ ASSERT(res_value <= LLONG_MAX - summand);
+
+ res_value += summand;
+ }
+
+ res.value = (int64_t)res_value;
+
+ if (arg1_negative ^ arg2_negative)
+ res.value = -res.value;
+
+ return res;
+}
+
+struct fixed31_32 dal_fixed31_32_from_int(
+ int64_t arg)
+{
+ struct fixed31_32 res;
+
+ ASSERT
[PATCH 02/29] drm/amd/dal: Add DAL Basic Types and Logger
Laying the groundwork for the AMD DAL display driver. This patch includes the basic services and defines basic types required by the display driver, such as: - ASIC register access - VBIOS access - Vector and flat_set data structures - Display signal types - ASIC versions and IDs - HW IDs - Logging functionality This patch adds Kconfig options to enable the DAL display driver. - DRM_AMD_DAL - DRM_AMD_DAL_VBIOS_PRESENT - DRM_AMD_DAL_DCE11_0 - DRM_AMD_DAL_DCE10_0 - DEBUG_KERNEL_DAL Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/Kconfig| 48 ++ drivers/gpu/drm/amd/dal/Makefile | 21 + drivers/gpu/drm/amd/dal/dc/basics/Makefile | 10 + drivers/gpu/drm/amd/dal/dc/basics/conversion.c | 224 + drivers/gpu/drm/amd/dal/dc/basics/conversion.h | 49 ++ drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c | 134 +++ drivers/gpu/drm/amd/dal/dc/basics/logger.c | 954 + drivers/gpu/drm/amd/dal/dc/basics/logger.h | 64 ++ .../gpu/drm/amd/dal/dc/basics/register_logger.c| 197 + drivers/gpu/drm/amd/dal/dc/basics/signal_types.c | 116 +++ drivers/gpu/drm/amd/dal/dc/basics/vector.c | 309 +++ 11 files changed, 2126 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/Kconfig create mode 100644 drivers/gpu/drm/amd/dal/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.h create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.h create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/register_logger.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/signal_types.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/vector.c diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig new file mode 100644 index ..2289c0b10dae --- /dev/null +++ b/drivers/gpu/drm/amd/dal/Kconfig @@ -0,0 +1,48 @@ +menu "Display Engine Configuration" + depends on DRM && (DRM_AMDSOC || DRM_AMDGPU) + +config DRM_AMD_DAL +bool "AMD DAL - Enable new display engine +help + Choose this option if you want to use the new display engine + support for AMD SOC. + + Will be deprecated when the DAL component becomes stable and + AMDSOC will fully switch to it. + +config DRM_AMD_DAL_VBIOS_PRESENT +bool "Video Bios available on board" +depends on DRM_AMD_DAL +help + This option is needed to allow a full range of feature +support when working on +x86 platforms and there is a VBIOS +present in the system + +config DRM_AMD_DAL_DCE11_0 +bool "Carrizo family" +depends on DRM_AMD_DAL +help + Choose this option +if you want to have +CZ family +for display engine + +config DRM_AMD_DAL_DCE10_0 +bool "VI family" +depends on DRM_AMD_DAL +help + Choose this option +if you want to have +VI family for display +engine. + +config DEBUG_KERNEL_DAL +bool "Enable kgdb break in DAL" +depends on DRM_AMD_DAL +help + Choose this option + if you want to hit + kdgb_break in assert. + +endmenu diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile new file mode 100644 index ..25ae4646c4d3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/Makefile @@ -0,0 +1,21 @@ +# +# Makefile for the DAL (Display Abstract Layer), which is a sub-component +# of the AMDGPU drm driver. +# It provides the HW control for display related functionalities. + +AMDDALPATH = $(RELATIVE_AMD_DAL_PATH) + +subdir-ccflags-y += -Werror + +subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include + +subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/ + +#TODO: remove when Timing Sync feature is complete +subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0 + +DAL_LIBS = amdgpu_dm dc + +AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/,$(DAL_LIBS))) + +include $(AMD_DAL) diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile b/drivers/gpu/drm/amd/dal/dc/basics/Makefile new file mode 100644 index ..6f382812fae3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the 'utils' sub-component of DAL. +# It provides the general basic services required by other DAL +# subcomponents. + +BASICS = conversion.o grph_object_id.o logger.o register_logger.o signal_types.o vector.o + +AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS)) + +AMD_DAL_FILES += $(AMD_DAL_BASICS) diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/b
[PATCH 01/29] drm/amd/dal: Add dal headers
Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dal_services.h | 266 ++ drivers/gpu/drm/amd/dal/dal_services_types.h | 62 ++ drivers/gpu/drm/amd/dal/dc/dc.h| 462 ++ drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 277 ++ drivers/gpu/drm/amd/dal/dc/dc_types.h | 936 + drivers/gpu/drm/amd/dal/dc/dm_helpers.h| 98 +++ drivers/gpu/drm/amd/dal/dc/dm_services.h | 485 +++ drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 167 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 510 +++ drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h | 64 ++ drivers/gpu/drm/amd/dal/dc/inc/clock_source.h | 176 drivers/gpu/drm/amd/dal/dc/inc/compressor.h| 140 +++ drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 54 ++ drivers/gpu/drm/amd/dal/dc/inc/core_status.h | 46 + drivers/gpu/drm/amd/dal/dc/inc/core_types.h| 357 drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h | 151 drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h| 56 ++ drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h | 118 +++ drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 126 +++ drivers/gpu/drm/amd/dal/dc/inc/ipp.h | 106 +++ drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h | 138 +++ drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 68 ++ drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 83 ++ drivers/gpu/drm/amd/dal/dc/inc/opp.h | 308 +++ drivers/gpu/drm/amd/dal/dc/inc/resource.h | 80 ++ drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h| 88 ++ drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h | 155 drivers/gpu/drm/amd/dal/dc/inc/transform.h | 217 + drivers/gpu/drm/amd/dal/dc/irq_types.h | 199 + .../amd/dal/include/adapter_service_interface.h| 632 ++ .../drm/amd/dal/include/adapter_service_types.h| 71 ++ .../amd/dal/include/asic_capability_interface.h| 58 ++ .../drm/amd/dal/include/asic_capability_types.h| 134 +++ drivers/gpu/drm/amd/dal/include/audio_interface.h | 184 drivers/gpu/drm/amd/dal/include/audio_types.h | 277 ++ .../drm/amd/dal/include/bios_parser_interface.h| 98 +++ .../gpu/drm/amd/dal/include/bios_parser_types.h| 327 +++ drivers/gpu/drm/amd/dal/include/dal_asic_id.h | 117 +++ .../gpu/drm/amd/dal/include/dal_register_logger.h | 43 + drivers/gpu/drm/amd/dal/include/dal_types.h| 305 +++ .../amd/dal/include/dc_clock_generator_interface.h | 77 ++ drivers/gpu/drm/amd/dal/include/dcs_types.h| 742 drivers/gpu/drm/amd/dal/include/ddc_interface.h| 74 ++ .../gpu/drm/amd/dal/include/ddc_service_types.h| 221 + .../drm/amd/dal/include/display_clock_interface.h | 186 .../drm/amd/dal/include/display_path_interface.h | 436 ++ drivers/gpu/drm/amd/dal/include/dmcu_interface.h | 87 ++ drivers/gpu/drm/amd/dal/include/dmcu_types.h | 199 + drivers/gpu/drm/amd/dal/include/dpcd_defs.h| 873 +++ .../gpu/drm/amd/dal/include/encoder_interface.h| 278 ++ drivers/gpu/drm/amd/dal/include/fixed31_32.h | 389 + drivers/gpu/drm/amd/dal/include/fixed32_32.h | 82 ++ drivers/gpu/drm/amd/dal/include/gpio_interface.h | 93 ++ .../drm/amd/dal/include/gpio_service_interface.h | 81 ++ drivers/gpu/drm/amd/dal/include/gpio_types.h | 341 drivers/gpu/drm/amd/dal/include/grph_csc_types.h | 98 +++ .../drm/amd/dal/include/grph_object_ctrl_defs.h| 593 + drivers/gpu/drm/amd/dal/include/grph_object_defs.h | 328 drivers/gpu/drm/amd/dal/include/grph_object_id.h | 277 ++ .../drm/amd/dal/include/hw_sequencer_interface.h | 388 + .../gpu/drm/amd/dal/include/hw_sequencer_types.h | 304 +++ drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 127 +++ drivers/gpu/drm/amd/dal/include/irq_interface.h| 53 ++ .../drm/amd/dal/include/irq_service_interface.h| 55 ++ .../drm/amd/dal/include/link_service_interface.h | 202 + .../gpu/drm/amd/dal/include/link_service_types.h | 427 ++ drivers/gpu/drm/amd/dal/include/logger_interface.h | 153 drivers/gpu/drm/amd/dal/include/logger_types.h | 356 drivers/gpu/drm/amd/dal/include/scaler_types.h | 196 + drivers/gpu/drm/amd/dal/include/set_mode_types.h | 142 drivers/gpu/drm/amd/dal/include/signal_types.h | 59 ++ drivers/gpu/drm/amd/dal/include/vector.h | 150 drivers/gpu/drm/amd/dal/include/video_csc_types.h | 135 +++ .../gpu/drm/amd/dal/include/video_gamma_types.h| 57 ++ 74 files changed, 16498 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dal_services.h create mode 100644 drivers/gpu/drm/amd/dal/dal_services_types.h create mode 100644 d
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
This set of patches enables the new DAL display driver for amdgpu on Carrizo Tonga, and Fiji ASICs. This driver will allow us going forward to bring display features on the open amdgpu driver (mostly) on par with the Catalyst driver. This driver adds support for - Atomic KMS API - MST - HDMI 2.0 - Better powerplay integration - Support of HW bandwidth formula on Carrizo - Better multi-display support and handling of co-functionality - Broader support of display dongles - Timing synchronization between DP and HDMI This patch series is based on Alex Deucher's drm-next-4.6-wip tree. Andrey Grodzovsky (1): drm/amd/dal: Force bw programming for DCE 10 until we start calculate BW. Harry Wentland (27): drm/amd/dal: Add dal headers drm/amd/dal: Add DAL Basic Types and Logger drm/amd/dal: Fixed point arithmetic drm/amd/dal: Asic Capabilities drm/amd/dal: GPIO (General Purpose IO) drm/amd/dal: Adapter Service drm/amd/dal: BIOS Parser drm/amd/dal: I2C Aux Manager drm/amd/dal: IRQ Service drm/amd/dal: GPU drm/amd/dal: Audio drm/amd/dal: Bandwidth calculations drm/amd/dal: Add encoder HW programming drm/amd/dal: Add clock source HW programming drm/amd/dal: Add timing generator HW programming drm/amd/dal: Add surface HW programming drm/amd/dal: Add framebuffer compression HW programming drm/amd/dal: Add input pixel processing HW programming drm/amd/dal: Add output pixel processing HW programming drm/amd/dal: Add transform & scaler HW programming drm/amd/dal: Add Carrizo HW sequencer and resource drm/amd/dal: Add Tonga/Fiji HW sequencer and resource drm/amd/dal: Add empty encoder programming for virtual HW drm/amd/dal: Add display core drm/amd/dal: Adding amdgpu_dm for dal drm/amdgpu: Use dal driver for Carrizo, Tonga, and Fiji drm/amd/dal: Correctly interpret rotation as bit set Mykola Lysenko (1): drm/amd/dal: fix flip clean-up state drivers/gpu/drm/amd/amdgpu/Kconfig |3 + drivers/gpu/drm/amd/amdgpu/Makefile| 17 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 69 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|4 + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c |5 - drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 54 +- drivers/gpu/drm/amd/amdgpu/vi.c| 250 + drivers/gpu/drm/amd/dal/Kconfig| 48 + drivers/gpu/drm/amd/dal/Makefile | 21 + drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile | 17 + drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 1468 ++ drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h | 168 + .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 474 ++ drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 820 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h | 122 + .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c| 480 ++ .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h| 36 + .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 457 ++ .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c| 2577 ++ .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h| 100 + drivers/gpu/drm/amd/dal/dal_services.h | 266 ++ drivers/gpu/drm/amd/dal/dal_services_types.h | 62 + drivers/gpu/drm/amd/dal/dc/Makefile| 28 + drivers/gpu/drm/amd/dal/dc/adapter/Makefile| 24 + .../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 2089 .../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 71 + .../adapter/dce110/hw_ctx_adapter_service_dce110.c | 304 ++ .../adapter/dce110/hw_ctx_adapter_service_dce110.h | 40 + .../diagnostics/hw_ctx_adapter_service_diag.c | 133 + .../diagnostics/hw_ctx_adapter_service_diag.h | 33 + .../amd/dal/dc/adapter/hw_ctx_adapter_service.c| 164 + .../amd/dal/dc/adapter/hw_ctx_adapter_service.h| 86 + .../drm/amd/dal/dc/adapter/wireless_data_source.c | 208 + .../drm/amd/dal/dc/adapter/wireless_data_source.h | 80 + .../gpu/drm/amd/dal/dc/asic_capability/Makefile| 35 + .../amd/dal/dc/asic_capability/asic_capability.c | 190 + .../dc/asic_capability/carrizo_asic_capability.c | 147 + .../dc/asic_capability/carrizo_asic_capability.h | 36 + .../dal/dc/asic_capability/tonga_asic_capability.c | 146 + .../dal/dc/asic_capability/tonga_asic_capability.h | 36 + drivers/gpu/drm/amd/dal/dc/audio/Makefile | 22 + drivers/gpu/drm/amd/dal/dc/audio/audio.h | 195 + drivers/gpu/drm/amd/dal/dc/audio/audio_base.c | 470 ++ .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c | 453 ++ .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h | 42 + .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 1930 .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h | 47 + drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_au
[PATCH v2 2/2] drm/i915/gen9: Add support for pipe background color (v2)
On Wed, Feb 10, 2016 at 06:32:59PM -0800, Matt Roper wrote:
> Gen9 platforms allow CRTC's to be programmed with a background/canvas
> color below the programmable planes. Let's expose this as a property to
> allow userspace to program a desired value.
>
> This patch is based on earlier work by Chandra Konduru; unfortunately
> the driver has evolved so much since his patches were written (in the
> pre-atomic era) that the functionality had to be pretty much completely
> rewritten for the new i915 atomic internals.
>
> v2:
> - Set initial background color (black) via proper helper function (Bob)
> - Fix debugfs output
> - General rebasing
>
> Cc: Chandra Konduru
> Cc: Bob Paauwe
> Cc: dri-devel at lists.freedesktop.org
> Signed-off-by: Matt Roper
> ---
> Documentation/DocBook/gpu.tmpl | 10 +++-
> drivers/gpu/drm/i915/i915_debugfs.c | 8 +++
> drivers/gpu/drm/i915/i915_reg.h | 9 +++
> drivers/gpu/drm/i915/intel_display.c | 46
>
> 4 files changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
> index fe6b36a..9e003cd 100644
> --- a/Documentation/DocBook/gpu.tmpl
> +++ b/Documentation/DocBook/gpu.tmpl
> @@ -2092,7 +2092,7 @@ void intel_crt_init(struct drm_device *dev)
> TBD
>
>
> - i915
> + i915
> Generic
> "Broadcast RGB"
> ENUM
> @@ -2108,6 +2108,14 @@ void intel_crt_init(struct drm_device *dev)
> TBD
>
>
> + CRTC
> + âbackground_colorâ
> + RGBA
> +
> + CRTC
> + Background color of regions not covered by a
> plane
> +
> +
> SDVO-TV
> âmodeâ
> ENUM
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ec0c2a05e..e7352fc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3104,6 +3104,14 @@ static int i915_display_info(struct seq_file *m, void
> *unused)
> intel_scaler_info(m, crtc);
> intel_plane_info(m, crtc);
> }
> + if (INTEL_INFO(dev)->gen >= 9 && pipe_config->base.active) {
> + struct drm_rgba background =
> pipe_config->base.background_color;
> +
> + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x
> b=%x\n",
> +DRM_RGBA_REDBITS(background, 10),
> +DRM_RGBA_GREENBITS(background, 10),
> +DRM_RGBA_BLUEBITS(background, 10));
> + }
>
> seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
> yesno(!crtc->cpu_fifo_underrun_disabled),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 144586e..b0b014d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7649,6 +7649,15 @@ enum skl_disp_power_wells {
> #define PIPE_CSC_POSTOFF_ME(pipe)_MMIO_PIPE(pipe,
> _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> #define PIPE_CSC_POSTOFF_LO(pipe)_MMIO_PIPE(pipe,
> _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>
> +/* Skylake pipe bottom color */
> +#define _PIPE_BOTTOM_COLOR_A0x70034
> +#define _PIPE_BOTTOM_COLOR_B0x71034
> +#define _PIPE_BOTTOM_COLOR_C0x72034
> +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31)
> +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
> +#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
> +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _PIPE_BOTTOM_COLOR_A,
> _PIPE_BOTTOM_COLOR_B)
> +
> /* MIPI DSI registers */
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
> C only */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 836bbdc..a616ac42 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3299,6 +3299,8 @@ static void intel_update_pipe_config(struct intel_crtc
> *crtc,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc->base.state);
> + struct drm_rgba background = pipe_config->base.background_color;
> + uint32_t val;
>
> /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> crtc->base.mode = crtc->base.state->mode;
> @@ -3335,6 +3337,26 @@ static void intel_update_pipe_config(struct intel_crtc
> *crtc,
> else if (old_crtc_state->pch_pfit.enabled)
> ironlake_pfit_disable(crtc, true);
> }
> +
> + if (INTEL_INFO(dev)->gen >= 9) {
> + /* BGR 16bpc ==> RGB 10bpc */
> + val = DRM_RGBA_REDBITS(background, 10) << 20
> + | DRM_RGBA_GREENBITS(background, 10) << 10
> + | DRM_RGBA_BLUEBITS(backgr
[PATCH] drm/msm: remove unused variable
On Thu, Feb 11, 2016 at 10:10:00AM +0100, Arnd Bergmann wrote:
> After the drm_device_is_unplugged() was removed, the 'dev' variable is now
> unused, and we get a warning for that:
>
> drivers/gpu/drm/msm/msm_fbdev.c: In function 'msm_fbdev_mmap':
> drivers/gpu/drm/msm/msm_fbdev.c:65:21: error: unused variable 'dev'
> [-Werror=unused-variable]
>
> This removes the variable as well.
>
> Signed-off-by: Arnd Bergmann
> Fixes: e9f8250f2f92 ("drm/msm: remove the drm_device_is_unplugged check")
Applied, thanks.
-Daniel
> ---
> drivers/gpu/drm/msm/msm_fbdev.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
> index e119c2979509..d9759bf3482e 100644
> --- a/drivers/gpu/drm/msm/msm_fbdev.c
> +++ b/drivers/gpu/drm/msm/msm_fbdev.c
> @@ -62,7 +62,6 @@ static int msm_fbdev_mmap(struct fb_info *info, struct
> vm_area_struct *vma)
> struct drm_fb_helper *helper = (struct drm_fb_helper *)info->par;
> struct msm_fbdev *fbdev = to_msm_fbdev(helper);
> struct drm_gem_object *drm_obj = fbdev->bo;
> - struct drm_device *dev = helper->dev;
> int ret = 0;
>
> ret = drm_gem_mmap_obj(drm_obj, drm_obj->size, vma);
> --
> 2.7.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[PATCH v2 2/2] drm: remove drm_device_is_unplugged checks in common drm code.
Hi On Thu, Feb 11, 2016 at 12:18 AM, Haixia Shi wrote: > When USB cable is disconnected, we mark udl device as unplugged so that > udl_detect reports connector status as disconnected, but still keep > the drm device alive until user-space closes it. > > Signed-off-by: Haixia Shi > Reviewed-by: Stéphane Marchesin I assume this is based on the discussion I had with Stephane on IRC. I'm fine with going this way and keeping the device fully alive, and just treat the device removal as a connector-unplug. However, you really must document all this in your commit message. Anyway, if you want to keep the device alive, then please change the code to entirely drop the "unplugged" flag and all related code. Then make sure you somehow reset "udl->udev" to NULL and make sure no code-path uses the usb-device after it was unplugged. I guess there should be appropriate locks already. This way, you end up with a fully functional UDL device, which just happens to have to connector plugged. But you *really* have to be careful that no-one touches the usb device, as the interface might be re-used by some other device any time (or in case the usb-core provides protection against this, please document it). Thanks David
[REGRESSION] i915: No HDMI output with 4.4
On Thu, Feb 11, 2016 at 10:54:08AM +0200, Oleksandr Natalenko wrote: > Daniel, > > I've already tried Ville's patch you've mentioned with no luck. > > Kindly find unpatched v4.5-rc3 dmesg with drm debug enabled here: [1] > > [1] https://gist.github.com/efb44b7c6bc325978b80 That's an IVB. So no wonder my patch doesn't help. Can you grab another dmesg after disconnecting and reconnecting the HDMI cable? > > 11.02.2016 10:21, Daniel Vetter wrote: > > Please boot with drm.debug=0xe and attach the dmesg. Also please test > > the > > patch later on in this thread: > > > > https://lkml.org/lkml/2016/2/9/587 > > > > Ville is working on a proper fix for this specific case. But could be > > that > > you're hitting yet another issue. -- Ville Syrjälä Intel OTC
[PATCH v2 2/2] drm: remove drm_device_is_unplugged checks in common drm code.
Well, in that case it would be even simpler. We don't even need the "unplugged" flag check in udl_detect because all connectors are already unplugged in udl_usb_disconnect (in drm_connector_unplug_all()). It is not necessary to check the flag in udl_fb_open() either, if the intention is to keep the device alive. As for code paths that uses udl->udev, I only see the following 3 places: (1) udl_parse_vendor_description and udl_alloc_urb_list: both are only called at udl_driver_load(), so not a problem (2) udl_usb_probe: won't happen after USB device is unplugged (3) udl_get_edid: only called from udl_get_modes, won't be an issue because connectors are already unplugged So, it seems that I *really* just need to drop the "unplugged" flag and update the commit message. On Thu, Feb 11, 2016 at 2:30 AM, David Herrmann wrote: > Hi > > On Thu, Feb 11, 2016 at 12:18 AM, Haixia Shi wrote: > > When USB cable is disconnected, we mark udl device as unplugged so that > > udl_detect reports connector status as disconnected, but still keep > > the drm device alive until user-space closes it. > > > > Signed-off-by: Haixia Shi > > Reviewed-by: Stéphane Marchesin > > I assume this is based on the discussion I had with Stephane on IRC. > I'm fine with going this way and keeping the device fully alive, and > just treat the device removal as a connector-unplug. However, you > really must document all this in your commit message. > > Anyway, if you want to keep the device alive, then please change the > code to entirely drop the "unplugged" flag and all related code. Then > make sure you somehow reset "udl->udev" to NULL and make sure no > code-path uses the usb-device after it was unplugged. I guess there > should be appropriate locks already. > > This way, you end up with a fully functional UDL device, which just > happens to have to connector plugged. But you *really* have to be > careful that no-one touches the usb device, as the interface might be > re-used by some other device any time (or in case the usb-core > provides protection against this, please document it). > > Thanks > David > -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/e9e0d932/attachment-0001.html>
[REGRESSION] i915: No HDMI output with 4.4
Daniel, I've already tried Ville's patch you've mentioned with no luck. Kindly find unpatched v4.5-rc3 dmesg with drm debug enabled here: [1] [1] https://gist.github.com/efb44b7c6bc325978b80 11.02.2016 10:21, Daniel Vetter wrote: > Please boot with drm.debug=0xe and attach the dmesg. Also please test > the > patch later on in this thread: > > https://lkml.org/lkml/2016/2/9/587 > > Ville is working on a proper fix for this specific case. But could be > that > you're hitting yet another issue.
radeon_drm.h: missing TILE_MODE definition?
On Thu, Feb 11, 2016 at 12:23 AM, Alexandre Demers wrote: > I was looking at /drivers/gpu/drm/radeon/atombios_crtc.c and at radeon_drm.h > (both under kernel and libdrm). I noticed that there seems to be a missing > TILE_MODE definition: under atombios_crtc, line 1289 > (/drivers/gpu/drm/radeon/atombios_crtc.c#L1289), an unexplained value is > being used (index = 10;) compared to the rest of the code around where > defined variables are being used. > > Looking at the defined variables under radeon_drm.h, there is a missing > value in the tile index. Index 10 is missing. If it was defined, it could be > used in place of the numerical value at line 1289 under atombios_crtc.c. > According to the other names and usages, shouldn't there be a #define > SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10? In fact, the equivalent of > SI_TILE_MODE_COLORD_2D_8BPP is CIK_TILE_MODE_COLOR_2D under CIK; under CIK, > there is a variable defined for index 10, which is > CIK_TILE_MODE_COLOR_2D_SCANOUT. Thus, I'd be inclined to think there should > really be a SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP variable defined. > > I've been searching in the SI 3D register documentation and I couldn't find > a tile index table to relate to. > > Lastly, based on how the other "X_2D_SCANOUT_YBPP" variables are covered > under si_surface_sanity() (libdrm's radeon_surface.c), is it expected that > this index value (10) is not covered specifically. Should there be a "case > 1: *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP; break;" at line 1362, > before "case 2: ..."? Would it make sense? > I don't think it's a particularly useful case. In practice I doubt it would ever be hit. I guess it's for 8bpp greyscale. The 3D engine can't render to indexed color or 332 surfaces. If you aren't using the 3D engine, there's not much point in using tiling to begin with. Alex
[PATCH] drm/msm: remove unused variable
After the drm_device_is_unplugged() was removed, the 'dev' variable is now
unused, and we get a warning for that:
drivers/gpu/drm/msm/msm_fbdev.c: In function 'msm_fbdev_mmap':
drivers/gpu/drm/msm/msm_fbdev.c:65:21: error: unused variable 'dev'
[-Werror=unused-variable]
This removes the variable as well.
Signed-off-by: Arnd Bergmann
Fixes: e9f8250f2f92 ("drm/msm: remove the drm_device_is_unplugged check")
---
drivers/gpu/drm/msm/msm_fbdev.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c
index e119c2979509..d9759bf3482e 100644
--- a/drivers/gpu/drm/msm/msm_fbdev.c
+++ b/drivers/gpu/drm/msm/msm_fbdev.c
@@ -62,7 +62,6 @@ static int msm_fbdev_mmap(struct fb_info *info, struct
vm_area_struct *vma)
struct drm_fb_helper *helper = (struct drm_fb_helper *)info->par;
struct msm_fbdev *fbdev = to_msm_fbdev(helper);
struct drm_gem_object *drm_obj = fbdev->bo;
- struct drm_device *dev = helper->dev;
int ret = 0;
ret = drm_gem_mmap_obj(drm_obj, drm_obj->size, vma);
--
2.7.0
[REGRESSION] i915: No HDMI output with 4.4
Daniel, I do confirm that this hacky patch: https://lkml.org/lkml/2016/1/19/637 works around my issue. I understand that this is improper fix, so let me know how could I debug my issue further. Thanks. 09.02.2016 12:11, Daniel Vetter wrote: > Can you please retest with latest -rc? There's been some bugs in the > HDMI > detection changes, which should be fixed now. > > If that doesn't help please try to bisect which exact change caused the > regression. > > Thanks, Daniel
[PATCH] drm/bridge: removed dummy mode_fixup function from dw-hdmi.
On Wed, Feb 10, 2016 at 04:10:39PM +, Carlos Palminha wrote:
> Other bridge drivers don't implement this optional function.
> Removed dummy code from dw-hdmi brigde driver.
>
> Signed-off-by: Carlos Palminha
Merged your three patches to remove dummy mode_fixup functions. I've also
squashed in a fixup for your encoder_funcs->mode_fixup patch. But that
part (i.e. drm_encoder and drm_crtc ->mode_fixup plus dummy func removal)
isn't complete yet. Are you still looking into that some more?
Thanks, Daniel
> ---
> drivers/gpu/drm/bridge/dw-hdmi.c | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c
> b/drivers/gpu/drm/bridge/dw-hdmi.c
> index b0aac473..9795b72 100644
> --- a/drivers/gpu/drm/bridge/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/dw-hdmi.c
> @@ -1391,13 +1391,6 @@ static void dw_hdmi_bridge_mode_set(struct drm_bridge
> *bridge,
> mutex_unlock(&hdmi->mutex);
> }
>
> -static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> -{
> - return true;
> -}
> -
> static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
> {
> struct dw_hdmi *hdmi = bridge->driver_private;
> @@ -1546,7 +1539,6 @@ static const struct drm_bridge_funcs
> dw_hdmi_bridge_funcs = {
> .pre_enable = dw_hdmi_bridge_nop,
> .post_disable = dw_hdmi_bridge_nop,
> .mode_set = dw_hdmi_bridge_mode_set,
> - .mode_fixup = dw_hdmi_bridge_mode_fixup,
> };
>
> static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
> --
> 2.5.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[REGRESSION] i915: No HDMI output with 4.4
On Thu, Feb 11, 2016 at 09:45:17AM +0200, Oleksandr Natalenko wrote: > Daniel, > > I do confirm that this hacky patch: > > https://lkml.org/lkml/2016/1/19/637 > > works around my issue. I understand that this is improper fix, so let me > know how could I debug my issue further. Please boot with drm.debug=0xe and attach the dmesg. Also please test the patch later on in this thread: https://lkml.org/lkml/2016/2/9/587 Ville is working on a proper fix for this specific case. But could be that you're hitting yet another issue. Thanks, Daniel > > Thanks. > > 09.02.2016 12:11, Daniel Vetter wrote: > >Can you please retest with latest -rc? There's been some bugs in the HDMI > >detection changes, which should be fixed now. > > > >If that doesn't help please try to bisect which exact change caused the > >regression. > > > >Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[PATCH v2 2/2] drm: remove drm_device_is_unplugged checks in common drm code.
On Wed, Feb 10, 2016 at 03:18:38PM -0800, Haixia Shi wrote:
> When USB cable is disconnected, we mark udl device as unplugged so that
> udl_detect reports connector status as disconnected, but still keep
> the drm device alive until user-space closes it.
>
> Signed-off-by: Haixia Shi
> Reviewed-by: Stéphane Marchesin
Please add more details capturing the discussion, i.e. why exactly this
was done. Also, has Stephane really re-reviewed this new version already?
And please Cc: everyone involved in the previous patch discussion, too.
Thanks, Daniel
> ---
> drivers/gpu/drm/drm_drv.c | 6 --
> drivers/gpu/drm/drm_fops.c | 2 --
> drivers/gpu/drm/drm_gem.c | 3 ---
> drivers/gpu/drm/drm_ioctl.c | 3 ---
> drivers/gpu/drm/drm_vm.c| 3 ---
> drivers/gpu/drm/udl/udl_connector.c | 2 +-
> drivers/gpu/drm/udl/udl_drv.c | 1 +
> drivers/gpu/drm/udl/udl_drv.h | 3 +++
> drivers/gpu/drm/udl/udl_fb.c| 2 +-
> drivers/gpu/drm/udl/udl_main.c | 15 +++
> include/drm/drmP.h | 14 --
> 11 files changed, 21 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
> index 167c8d3..f93ee12 100644
> --- a/drivers/gpu/drm/drm_drv.c
> +++ b/drivers/gpu/drm/drm_drv.c
> @@ -376,9 +376,6 @@ struct drm_minor *drm_minor_acquire(unsigned int minor_id)
>
> if (!minor) {
> return ERR_PTR(-ENODEV);
> - } else if (drm_device_is_unplugged(minor->dev)) {
> - drm_dev_unref(minor->dev);
> - return ERR_PTR(-ENODEV);
> }
>
> return minor;
> @@ -464,9 +461,6 @@ void drm_unplug_dev(struct drm_device *dev)
> drm_minor_unregister(dev, DRM_MINOR_CONTROL);
>
> mutex_lock(&drm_global_mutex);
> -
> - drm_device_set_unplugged(dev);
> -
> if (dev->open_count == 0) {
> drm_put_dev(dev);
> }
> diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
> index 1ea8790..b4332d4 100644
> --- a/drivers/gpu/drm/drm_fops.c
> +++ b/drivers/gpu/drm/drm_fops.c
> @@ -497,8 +497,6 @@ int drm_release(struct inode *inode, struct file *filp)
>
> if (!--dev->open_count) {
> retcode = drm_lastclose(dev);
> - if (drm_device_is_unplugged(dev))
> - drm_put_dev(dev);
> }
> mutex_unlock(&drm_global_mutex);
>
> diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> index 2e8c77e..c622e32 100644
> --- a/drivers/gpu/drm/drm_gem.c
> +++ b/drivers/gpu/drm/drm_gem.c
> @@ -900,9 +900,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct
> *vma)
> struct drm_vma_offset_node *node;
> int ret;
>
> - if (drm_device_is_unplugged(dev))
> - return -ENODEV;
> -
> drm_vma_offset_lock_lookup(dev->vma_offset_manager);
> node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager,
> vma->vm_pgoff,
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index 8ce2a0c..f959074 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -695,9 +695,6 @@ long drm_ioctl(struct file *filp,
>
> dev = file_priv->minor->dev;
>
> - if (drm_device_is_unplugged(dev))
> - return -ENODEV;
> -
> is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END;
>
> if (is_driver_ioctl) {
> diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c
> index f90bd5f..3a68be4 100644
> --- a/drivers/gpu/drm/drm_vm.c
> +++ b/drivers/gpu/drm/drm_vm.c
> @@ -657,9 +657,6 @@ int drm_legacy_mmap(struct file *filp, struct
> vm_area_struct *vma)
> struct drm_device *dev = priv->minor->dev;
> int ret;
>
> - if (drm_device_is_unplugged(dev))
> - return -ENODEV;
> -
> mutex_lock(&dev->struct_mutex);
> ret = drm_mmap_locked(filp, vma);
> mutex_unlock(&dev->struct_mutex);
> diff --git a/drivers/gpu/drm/udl/udl_connector.c
> b/drivers/gpu/drm/udl/udl_connector.c
> index 4709b54..b168f2c 100644
> --- a/drivers/gpu/drm/udl/udl_connector.c
> +++ b/drivers/gpu/drm/udl/udl_connector.c
> @@ -96,7 +96,7 @@ static int udl_mode_valid(struct drm_connector *connector,
> static enum drm_connector_status
> udl_detect(struct drm_connector *connector, bool force)
> {
> - if (drm_device_is_unplugged(connector->dev))
> + if (udl_device_is_unplugged(connector->dev))
> return connector_status_disconnected;
> return connector_status_connected;
> }
> diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c
> index d5728ec..3cbafe7 100644
> --- a/drivers/gpu/drm/udl/udl_drv.c
> +++ b/drivers/gpu/drm/udl/udl_drv.c
> @@ -97,6 +97,7 @@ static void udl_usb_disconnect(struct usb_interface
> *interface)
> drm_connector_unplug_all(dev);
> udl_fbdev_unplug(dev);
> udl_drop_usb(de
[PATCH 2/2] drm: make unplugged flag specific to udl driver
On Wed, Feb 10, 2016 at 02:02:46PM -0800, Stéphane Marchesin wrote: > On Wed, Feb 10, 2016 at 1:54 PM, David Herrmann > wrote: > > Hi > > > > On Wed, Feb 10, 2016 at 10:46 PM, Stéphane Marchesin > > wrote: > >> On Wed, Feb 10, 2016 at 1:38 PM, David Herrmann > >> wrote: > >>> Hi > >>> > >>> On Wed, Feb 10, 2016 at 9:39 PM, Haixia Shi wrote: > > > + if (udl_device_is_unplugged(dev) && > > + nr != DRM_IOCTL_NR(DRM_IOCTL_MODE_SETCRTC) && > > + nr != DRM_IOCTL_NR(DRM_IOCTL_MODE_RMFB) && > > + nr != DRM_IOCTL_NR(DRM_IOCTL_MODE_DESTROY_DUMB)) > > + return -ENODEV; > > > >Why? > > > >Just do: > > > >if (udl_device_is_unplugged(dev)) > >return -ENODEV; > > > >Why this complex logic here? > > Because there are legitimate ioctl calls after UDL is unplugged. See > crbug.com/583508 and crbug.com/583758 for some background. > > The userspace (Chrome in this case) has allocated FBs and Dumb buffers on > the drm device and needs to be given a chance to properly deallocate them > (via RMFB and DESTROY_DUMB). In addition, it needs to call SETCRTC with > fb_id = 0 to properly release the last refcount on the primary fb. > > I initially proposed adding an "UNPLUG_DISALLOW" flag to ioctls so that > we > can whitelist them on a case-by-case basis but that proposal got shot > down > as being unnecessary, but you can see my original patch at > https://chromium-review.googlesource.com/#/c/326160/ > >>> > >>> If a device is unplugged, you should consider all your resources to be > >>> destroyed. There is no reason to release them manually. User-space > >>> *must* be able to deal with asynchronous unplugs. > >> > >> So the problem if you do that is that things like a buffer's memory > >> pages can disappear from under you. How would you deal with that case? > >> User space certainly can't have a segfault handler catch that just in > >> case :) Yeah, dma-buf and fence lifetime is entirely unsolved. I agree that they /should/ keep being alive. Of course the actual data in it might be toast, but that's not any different from a gpu hang. At least i915 only gives you asynchronous signalling for "bad stuff happened" in that case, buffer access to corrupted data continues to work. And must do so, because X/compositors/clients would just die if we don't do that, and that's Not Good(tm). > > If you rip out hardware resources, then you better be able to deal > > with it. Sure, UDL is an exception as it doesn't have memory resources > > on the chip. But it sounds fishy to me, if you base your API on it. On > > a lot of other devices, the memory will simply not be there. So you > > cannot keep it around. > > The thing is, you are not unplugging a device here; you are unplugging > a USB monitor. As a proof that this is just a monitor, I can plug > another USB monitor with the same driver and pick up where I left off. > I guess I am saying that the concept of unplugging a device is not > applicable here (or to any driver that I know, for that matter). > > Other drivers already handle all this by, for example, failing page > flips if the monitor is gone. We basically want to do the same for > UDL; I don't think we need to invent a new level of unplug here. Just an aside: Imo failing pageflips is really bad behaviour of some kernel drivers (yes mst does it by force-disabling sinks). Imo userspace should ask for things to get disabled explicitly, much less potential for races. For mst I think the right solution is to send out the uevent, stope enumerating the port, but keep it internally alive until it's all gone. Something similar could make sense for uld. > > There are many ways to invalidate memory mappings. You either unmap > > the entire range (and user-space must deal with SIGBUS, which is > > completely feasible and a lot of code already does it), or you replace > > all with a zero page, or you duplicate all pages, ... IMO, user-space > > has to start dealing with hardware unplug properly and stop pretending > > it cannot happen. > > What you are suggesting is much more complicated than you claim, for > example if you destroy the dmabuf which is shared with another driver, > what happens? User space definitely can't deal with that. > > I think we should wait until we have unpluggable display hardware > before inventing really complex support for it. I agree that for now we probably should just have hacks for udl (and yeah fixing up mst to no longer just go poof is on my todo list somewhere), and leave the larger issue of drivers disappearing unfixed. Atm module unload is the only real user for that (except udl ofc), and that's a developer feature. Fixing all the dma-buf/fence/drm device lifetime issues properly is super hard I think. And tons of work. -Daniel -- Daniel Vetter Software Engineer, Intel C
[PATCH] drm/bridge: removed dummy mode_fixup function from dw-hdmi.
On 11-02-2016 08:22, Daniel Vetter wrote:
> On Wed, Feb 10, 2016 at 04:10:39PM +, Carlos Palminha wrote:
>> Other bridge drivers don't implement this optional function.
>> Removed dummy code from dw-hdmi brigde driver.
>>
>> Signed-off-by: Carlos Palminha
>
> Merged your three patches to remove dummy mode_fixup functions. I've also
> squashed in a fixup for your encoder_funcs->mode_fixup patch. But that
> part (i.e. drm_encoder and drm_crtc ->mode_fixup plus dummy func removal)
> isn't complete yet. Are you still looking into that some more?
>
nice! :)
I'm planning to start nuking the crtc ones in the following days...
thanks,
c.palminha
> Thanks, Daniel
>
>> ---
>> drivers/gpu/drm/bridge/dw-hdmi.c | 8
>> 1 file changed, 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c
>> b/drivers/gpu/drm/bridge/dw-hdmi.c
>> index b0aac473..9795b72 100644
>> --- a/drivers/gpu/drm/bridge/dw-hdmi.c
>> +++ b/drivers/gpu/drm/bridge/dw-hdmi.c
>> @@ -1391,13 +1391,6 @@ static void dw_hdmi_bridge_mode_set(struct drm_bridge
>> *bridge,
>> mutex_unlock(&hdmi->mutex);
>> }
>>
>> -static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
>> - const struct drm_display_mode *mode,
>> - struct drm_display_mode *adjusted_mode)
>> -{
>> -return true;
>> -}
>> -
>> static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
>> {
>> struct dw_hdmi *hdmi = bridge->driver_private;
>> @@ -1546,7 +1539,6 @@ static const struct drm_bridge_funcs
>> dw_hdmi_bridge_funcs = {
>> .pre_enable = dw_hdmi_bridge_nop,
>> .post_disable = dw_hdmi_bridge_nop,
>> .mode_set = dw_hdmi_bridge_mode_set,
>> -.mode_fixup = dw_hdmi_bridge_mode_fixup,
>> };
>>
>> static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
>> --
>> 2.5.0
>>
>
[PATCHv12 18/17] cec: check for RC_CORE support
If CONFIG_RC_CORE is not enabled, then remove the rc support, otherwise
the module won't link.
This will be folded into patch 07/17 for the final pull request.
Signed-off-by: Hans Verkuil
---
drivers/media/Kconfig | 2 --
drivers/media/cec.c | 16
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig
index 4f7fd52..ef8192e 100644
--- a/drivers/media/Kconfig
+++ b/drivers/media/Kconfig
@@ -82,8 +82,6 @@ config MEDIA_RC_SUPPORT
config MEDIA_CEC
tristate "CEC API (EXPERIMENTAL)"
- depends on MEDIA_RC_SUPPORT
- select RC_CORE
---help---
Enable the CEC API.
diff --git a/drivers/media/cec.c b/drivers/media/cec.c
index a14ac73..e9fa698 100644
--- a/drivers/media/cec.c
+++ b/drivers/media/cec.c
@@ -744,6 +744,7 @@ static int cec_receive_notify(struct cec_adapter *adap,
struct cec_msg *msg,
if (!(adap->capabilities & CEC_CAP_RC))
break;
+#if IS_ENABLED(CONFIG_RC_CORE)
switch (msg->msg[2]) {
/*
* Play function, this message can have variable length
@@ -773,12 +774,15 @@ static int cec_receive_notify(struct cec_adapter *adap,
struct cec_msg *msg,
rc_keydown(adap->rc, RC_TYPE_CEC, msg->msg[2], 0);
break;
}
+#endif
break;
case CEC_MSG_USER_CONTROL_RELEASED:
if (!(adap->capabilities & CEC_CAP_RC))
break;
+#if IS_ENABLED(CONFIG_RC_CORE)
rc_keyup(adap->rc);
+#endif
break;
/*
@@ -2059,6 +2063,7 @@ struct cec_adapter *cec_create_adapter(const struct
cec_adap_ops *ops,
if (!(caps & CEC_CAP_RC))
return adap;
+#if IS_ENABLED(CONFIG_RC_CORE)
/* Prepare the RC input device */
adap->rc = rc_allocate_device();
if (!adap->rc) {
@@ -2089,6 +2094,9 @@ struct cec_adapter *cec_create_adapter(const struct
cec_adap_ops *ops,
adap->rc->priv = adap;
adap->rc->map_name = RC_MAP_CEC;
adap->rc->timeout = MS_TO_NS(100);
+#else
+ adap->capabilities &= ~CEC_CAP_RC;
+#endif
return adap;
}
EXPORT_SYMBOL_GPL(cec_create_adapter);
@@ -2097,6 +2105,7 @@ int cec_register_adapter(struct cec_adapter *adap)
{
int res;
+#if IS_ENABLED(CONFIG_RC_CORE)
if (adap->capabilities & CEC_CAP_RC) {
res = rc_register_device(adap->rc);
@@ -2108,13 +2117,16 @@ int cec_register_adapter(struct cec_adapter *adap)
return res;
}
}
+#endif
res = cec_devnode_register(&adap->devnode, adap->owner);
+#if IS_ENABLED(CONFIG_RC_CORE)
if (res) {
/* Note: rc_unregister also calls rc_free */
rc_unregister_device(adap->rc);
adap->rc = NULL;
}
+#endif
return res;
}
EXPORT_SYMBOL_GPL(cec_register_adapter);
@@ -2123,9 +2135,11 @@ void cec_unregister_adapter(struct cec_adapter *adap)
{
if (IS_ERR_OR_NULL(adap))
return;
+#if IS_ENABLED(CONFIG_RC_CORE)
/* Note: rc_unregister also calls rc_free */
rc_unregister_device(adap->rc);
adap->rc = NULL;
+#endif
cec_devnode_unregister(&adap->devnode);
}
EXPORT_SYMBOL_GPL(cec_unregister_adapter);
@@ -2139,8 +2153,10 @@ void cec_delete_adapter(struct cec_adapter *adap)
kthread_stop(adap->kthread_config);
if (adap->is_enabled)
cec_enable(adap, false);
+#if IS_ENABLED(CONFIG_RC_CORE)
if (adap->rc)
rc_free_device(adap->rc);
+#endif
kfree(adap->name);
kfree(adap);
}
--
2.7.0
[PATCH v2 2/2] drm/i915/gen9: Add support for pipe background color (v2)
On Thu, Feb 11, 2016 at 12:00:50PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 10, 2016 at 06:32:59PM -0800, Matt Roper wrote:
> > Gen9 platforms allow CRTC's to be programmed with a background/canvas
> > color below the programmable planes. Let's expose this as a property to
> > allow userspace to program a desired value.
> >
> > This patch is based on earlier work by Chandra Konduru; unfortunately
> > the driver has evolved so much since his patches were written (in the
> > pre-atomic era) that the functionality had to be pretty much completely
> > rewritten for the new i915 atomic internals.
> >
> > v2:
> > - Set initial background color (black) via proper helper function (Bob)
> > - Fix debugfs output
> > - General rebasing
> >
> > Cc: Chandra Konduru
> > Cc: Bob Paauwe
> > Cc: dri-devel at lists.freedesktop.org
> > Signed-off-by: Matt Roper
> > ---
> > Documentation/DocBook/gpu.tmpl | 10 +++-
> > drivers/gpu/drm/i915/i915_debugfs.c | 8 +++
> > drivers/gpu/drm/i915/i915_reg.h | 9 +++
> > drivers/gpu/drm/i915/intel_display.c | 46
> >
> > 4 files changed, 72 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
> > index fe6b36a..9e003cd 100644
> > --- a/Documentation/DocBook/gpu.tmpl
> > +++ b/Documentation/DocBook/gpu.tmpl
> > @@ -2092,7 +2092,7 @@ void intel_crt_init(struct drm_device *dev)
> > TBD
> >
> >
> > - i915
> > + i915
> > Generic
> > "Broadcast RGB"
> > ENUM
> > @@ -2108,6 +2108,14 @@ void intel_crt_init(struct drm_device *dev)
> > TBD
> >
> >
> > + CRTC
> > + âbackground_colorâ
> > + RGBA
> > +
> > + CRTC
> > + Background color of regions not covered by a
> > plane
> > +
> > +
> > SDVO-TV
> > âmodeâ
> > ENUM
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index ec0c2a05e..e7352fc 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -3104,6 +3104,14 @@ static int i915_display_info(struct seq_file *m,
> > void *unused)
> > intel_scaler_info(m, crtc);
> > intel_plane_info(m, crtc);
> > }
> > + if (INTEL_INFO(dev)->gen >= 9 && pipe_config->base.active) {
> > + struct drm_rgba background =
> > pipe_config->base.background_color;
> > +
> > + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x
> > b=%x\n",
> > + DRM_RGBA_REDBITS(background, 10),
> > + DRM_RGBA_GREENBITS(background, 10),
> > + DRM_RGBA_BLUEBITS(background, 10));
> > + }
> >
> > seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
> >yesno(!crtc->cpu_fifo_underrun_disabled),
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 144586e..b0b014d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7649,6 +7649,15 @@ enum skl_disp_power_wells {
> > #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe,
> > _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> > #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe,
> > _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
> >
> > +/* Skylake pipe bottom color */
> > +#define _PIPE_BOTTOM_COLOR_A0x70034
> > +#define _PIPE_BOTTOM_COLOR_B0x71034
> > +#define _PIPE_BOTTOM_COLOR_C0x72034
> > +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31)
> > +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
> > +#define PIPE_BOTTOM_COLOR_MASK 0x3FFF
> > +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _PIPE_BOTTOM_COLOR_A,
> > _PIPE_BOTTOM_COLOR_B)
> > +
> > /* MIPI DSI registers */
> >
> > #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and
> > C only */
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 836bbdc..a616ac42 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3299,6 +3299,8 @@ static void intel_update_pipe_config(struct
> > intel_crtc *crtc,
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_crtc_state *pipe_config =
> > to_intel_crtc_state(crtc->base.state);
> > + struct drm_rgba background = pipe_config->base.background_color;
> > + uint32_t val;
> >
> > /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> > crtc->base.mode = crtc->base.state->mode;
> > @@ -3335,6 +3337,26 @@ static void intel_update_pipe_config(struct
> > intel_crtc *crtc,
> > else if (old_crtc_state->pch_pfit.enabled)
> > ironlake_pfit_disable(crtc, true);
> > }
> > +
> > + if (INTEL_INFO(dev)->gen
radeon_drm.h: missing TILE_MODE definition?
I was looking at /drivers/gpu/drm/radeon/atombios_crtc.c and at radeon_drm.h (both under kernel and libdrm). I noticed that there seems to be a missing TILE_MODE definition: under atombios_crtc, line 1289 (/drivers/gpu/drm/radeon/atombios_crtc.c#L1289), an unexplained value is being used (index = 10;) compared to the rest of the code around where defined variables are being used. Looking at the defined variables under radeon_drm.h, there is a missing value in the tile index. Index 10 is missing. If it was defined, it could be used in place of the numerical value at line 1289 under atombios_crtc.c. According to the other names and usages, shouldn't there be a #define SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP 10? In fact, the equivalent of SI_TILE_MODE_COLORD_2D_8BPP is CIK_TILE_MODE_COLOR_2D under CIK; under CIK, there is a variable defined for index 10, which is CIK_TILE_MODE_COLOR_2D_SCANOUT. Thus, I'd be inclined to think there should really be a SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP variable defined. I've been searching in the SI 3D register documentation and I couldn't find a tile index table to relate to. Lastly, based on how the other "X_2D_SCANOUT_YBPP" variables are covered under si_surface_sanity() (libdrm's radeon_surface.c), is it expected that this index value (10) is not covered specifically. Should there be a "case 1: *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_8BPP; break;" at line 1362, before "case 2: ..."? Would it make sense? Cheers, Alexandre Demers -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/0ea3f9e7/attachment.html>
[Bug 79504] LLVM error on fragment shader
https://bugs.freedesktop.org/show_bug.cgi?id=79504 Timothy Arceri changed: What|Removed |Added Assignee|idr at freedesktop.org |dri-devel at lists.freedesktop ||.org QA Contact|intel-3d-bugs at lists.freedes |dri-devel at lists.freedesktop |ktop.org|.org Component|glsl-compiler |Drivers/Gallium/radeonsi --- Comment #16 from Timothy Arceri --- Test program no longer hits any issues in the glsl compiler, and program runs on i965. The program says My First Triangle but has a couple of squares, I'm assuming that's just an issue with the program rather than Mesa. Reassigning to radeonsi for further testing. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/5bb6ea7b/attachment.html>
What can a "freezed" X server status be, and a HowTo to get some kernel crash dumps
sks queued] CPU 2 RUNQUEUE: 88023fd16c80 CURRENT: PID: 0 TASK: 880236271c00 COMMAND: "swapper/2" RT PRIO_ARRAY: 88023fd16e30 [no tasks queued] CFS RB_ROOT: 88023fd16d20 [no tasks queued] CPU 3 RUNQUEUE: 88023fd96c80 CURRENT: PID: 0 TASK: 880236273800 COMMAND: "swapper/3" RT PRIO_ARRAY: 88023fd96e30 [no tasks queued] CFS RB_ROOT: 88023fd96d20 [no tasks queued] -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/57e1117a/attachment-0001.html>
[Bug 35998] RS600: Texture alignment issues under Gnome Shell
https://bugs.freedesktop.org/show_bug.cgi?id=35998 --- Comment #35 from Andrew Randrianasulu --- Created attachment 121663 --> https://bugs.freedesktop.org/attachment.cgi?id=121663&action=edit dmesg as you can see this happens also on 32-bit kernel/32 bit userspace -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/f024bd90/attachment.html>
[Bug 35998] RS600: Texture alignment issues under Gnome Shell
https://bugs.freedesktop.org/show_bug.cgi?id=35998 --- Comment #34 from Andrew Randrianasulu --- Created attachment 121662 --> https://bugs.freedesktop.org/attachment.cgi?id=121662&action=edit chromium BSU also show this bug using r300g driver from OpenGL version string: 2.1 Mesa 11.1.0-devel (git-8ae8fec), on kernel 4.2.0. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/fac19a51/attachment.html>
[Bug 35998] RS600: Texture alignment issues under Gnome Shell
https://bugs.freedesktop.org/show_bug.cgi?id=35998 --- Comment #33 from Andrew Randrianasulu --- I also have affected system and wanted for ages to see it fixed (with or without my help). unfortunately, even if I still can try and load old linux distro where last working fglrx (proprietary driver) was working - I have no idea what to do next - even mmiotrace format apparently changed from 2.6.29 kernel era, and here i fear some more tracing will be needed (and tools for userspace tracing also appear to bitrot or not even properly support this GPU). i tried to appear on #radeon but everyone was busy there (I think this situation will continue more or less due to new bug flow, new hardware, new features, other users and developers also wanting various levels of help). may be setting special 'hackday' for this or other specific bugs will help? if you like the idea - please reply (I tend to read dri-devel and mesa-dev ML). Thanks in advance! -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160211/6d1ff47c/attachment.html>
