RFC: group maintainership for misc drm trees
On Tue, Feb 16, 2016 at 11:44:52AM +1000, Dave Airlie wrote: > On 15 February 2016 at 20:06, Daniel Vetter wrote: > > Hi all, > > > > I've already chatted with some of you in private, here's the entire idea > > with a > > bit more thought. My motiviation for group maintainership of drm-misc was > > that I > > got a bit a guilty feeling the last few vacations/conferences when folks > > pinged > > about reviewed/tested pretty patches not landing. But also just increasing > > the > > bus factor and sharing the load better is good. And finally a shared misc > > drm > > tree would allow fringe drivers to get faster into Dave's drm-next by > > piggy-packing on top of the one pull request train. And it would also > > reduce a > > bit tree proliferation (at one point we had > > drm-misc/-bridge/-panel/-trivial and > > may more even). And at least everyone I chatted with seems to like the idea > > in > > principle. > > > > But what's still open is how to do it exactly. One big change with group > > maintainership is that you can't rebase a tree anymore. And right now I > > need to > > rebase drm-misc fairly often to throw out bad apples again. I think solving > > that > > is the important bit to make a shared drm-misc work. A few ideas: > > This is kinda what I don't like. I don't want a tree that can't rebase > out bad stuff > coming to me that often. If we are being too over eager in merging > stuff the answer > is to merge less not try and merge more. If we have a tree where things > are thrown until they stick I'm not sure the history will ever be nice > to pull from. > > I'd rather consider a staging tree where everything from patchwork can > get thrown > into, CIed, but that we cherry-pick fixes things to go back to me from the > what > works category. I fully agree on your concern that drm-misc could become a mess - that's why I think everything bigger than e.g. 2 patches or touching drivers needs to soak first in a topic branch. We could still get it into drm-misc with cherry-picks to avoid too many merges. The other part where I often had to squash in fixups is build fail on arm. But I fixed myself with some decent cross-compile toolchain, so I'm positive that won't happen any more. I think a good idea would be that I test-drive this process a bit without adding more maintainers, i.e. - no more rebases for drm-misc - topic branches for everything big - dutifully testing arm before pushing I'll do that over the next few weeks, then we can see how bad it would look and whether we need more to avoid bad history. > I'm finding with i915 for example there is a massive latency in the pipeline > now > waiting for fixes, and the pipeline to the end of drm-intel-next is > very long and > hard to figure out what fixes should be pulled back, and how much of the > driver has been rewritten between the -next and the -fixes pulls. > > > - I think CI is super-important. We're starting to finally roll that out for > > real for i915, and it's catching an awful lot of stuff already. Not yet > > ready > > for prime-time on public mailing lists, and for misc we probably can't > > test > > every patch before they land like we do for i915. But CI should have veto > > power before a pull request goes to Dave imo. > > > > For non-i915 Daniel Stone and others are working on ARM CI using the > > generic > > igt testcases for kms. And I'm open to merging driver-specific tests into > > igt > > too, if it makes sense, and e.g. Eric has already pushed some vc4 tests. > > > > - Stuff needs to at least compile cleanly before pushing. I've been really > > bad > > at that wrt arm drivers with my own drm-misc, but turns out it's fairly > > easy > > to get this right: > > http://blog.ffwll.ch/2016/02/arm-kernel-cross-compiling.html > > > > - Bad apples need to be kicked out with reverts, not rebases. I think that's > > fine for simple patches, and hence those can go directly to drm-misc. But > > a > > bunch of subsystem-wide refactorings go in through mis trees, and for > > those > > constantly mass-reverting until it's all solid is silly. And ime you need > > some > > soak time in a shared tree to iron out bugs with those kind of > > endeavours. We > > can address that with ad-hoc&short-lived topic branches which are then > > again > > owned by a single maintainer, but automatically pulled into an integration > > tree. After some soaking time to give CI systems time to crunch through > > those > > topic branches can then be merged into the main drm-misc and removed. > > I think integration trees are probably the way forward, but I > understand they come > with a massive overhead for constant merging, I like the idea of topic > branches until > it becomes my turn to spaghetti merge 3-4 features at once. At that > point I still > fallback to the slow things down, pick one feature merge it, back the > others off, > and I think this is something we should do more off, the pile
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
Hi Daniel, we've considered making cursor a plane but haven't done so (yet) because cursor is sort of a unique concept in our HW and doesn't map well to planes. Will take the time to look at the other mappings a bit more closely. Cheers, Harry On 2016-02-14 09:01 AM, Daniel Vetter wrote: > top-level post since I can't reply to the diagram directly. So from > very cursor reading-around in the code I think you have a few > mismatches in how you map drm concepts to dal structures: > > - cursor is just a drm_plane - step 0 of atomic support is universale > plane support, and you didn't do that in this patch series. Same holds > for video overlay support (which seems implemented but not exposed). > > - drm_plane should probably match to both surface + target structs, > since how a plane is composited in the screen rect is a plane state > > - stream should probably map to crtc > > - for cases where you need 2 streams for 1 crtc or 2 surfaces for 1 > plane internally remap them with some aux pointer. But imo still base > them on drm core structures (since in most cases you can expose them > all). You probably need a full remapping table to make this work, but > the state itself should still all be in extensions of core drm_*_state > structs > > - drm_encoder probably matches to dc_link, but not sure. drm_encoder > is mostly just a convenience thing really, you can ignore it > > - dc_sink seems to be the drm_connector, or well mostly. Here it gets > really unclear due to the massive amount of private code for > screen/sink handling that dal has. > > Cheers, Daniel > > > On Sat, Feb 13, 2016 at 1:05 AM, Wentland, Harry > wrote: >> Hi Dave, Daniel, others, >> >> The goal with DAL is to provide a unified, full featured display stack to >> service all of our Linux offerings. This driver will have to support our >> full feature set beyond what's supported by amdgpu, e.g. >>- synchronzied timings across different displays >>- freesync >>- solid support of 6 displays in any configuration (HDMI, DVI, DP, DP >> MST, etc) >>- solid support of 4k at 60 timings on APUs >>- power features, such as >> - clock-accurate bandwidth formulas >> - improved interaction with powerplay to maximize power savings >> - Improved audio and other infoframe related features >> - Improved stability with powerplay since display hw is involved in the SMC >> hw interactions and improper programming sequences can lead to GPU hangs, >> etc. >> >> The current amdgpu display stack grew somewhat organically and as such is >> not well suited to handling all of the hardware dependencies involved >> especially in areas like audio. The drm abstractions used by the old code >> map less and less well to new hw pipelines. Atomic helps, but if we are >> going to convert, it seemed like a good time to start fresh. >> >> Our DC (Display Core in dc.h, etc.) is the framework to allow us to well >> represent current and future HW architectures. These don't always map >> one-to-one to DRM interfaces. For one we can't make the assumption that >> surfaces map one-to-one to pipes. >> >> The DAL internal abstractions were used since they match the abstractions >> used by our drivers for other OSes, pre and post silicon validation tools >> and HW team programming models. Keeping it as close to that as possible >> makes it easier to debug and validate and provides the most likely change of >> success in complex display configurations. >> >> Please see the attached DC.png for an overview of the DAL design. >> >> For an atomic sequence you might want to look at >> - enable/disable displays or change display config -> dc_commit_targets >> (in dc/core/dc.c, called from amdgpu_dm_atomic_commit in >> amdgpu_dm/amdgpu_dm_types.c) >> >> - commit planes-> >> dc_commit_surfaces_to_targets >> (in dc/core/dc_target.c, called from dm_dc_surface_commit in >> amdgpu_dm/amdgpu_dm_types.c) >> >> - validate -> dc_validate_resources >> (in dc/core/dc.c, called from amdgpu_dm_atomic_check in >> amdgpu_dm/amdgpu_dm_types.c) >> >> >> There's still a bunch of legacy stuff in these patches that's on our list of >> things to refactor. Some of that is >> - dc/adapter >> - dc/asic_capability >> - dc/audio >> - dc/bios >> - dc/gpio >> >> We should be able to cut the size of this code to about 1/3 of what it is >> now. >> >> As for the LOC we have about >> 22k for HW programming >> 30k legacy stuff >> 6k dc/calcs - autogenerated from formulas provided by HW team >> 15k includes >> 6k amdgpu_dm >> 8k dc/core >> >> About 14k of those are blank lines (we have a habit of leaving lots of blank >> space) and 16k are comments. >> >> Cheers, >> Harry >> >> >> From: Daniel Vetter on behalf of Daniel Vetter >> >> Sent: Friday, February 12, 2016 12:34 AM >> To: Dave Airlie >> Cc: Wentland, Harry; dri-devel >> Subje
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
Hi Jerome, some of the kernel API is abstracted to allow testing of this driver in user space for pre- and post-silicon validation. An alternative that we've considered is implementing the kernel functions in user space. That's definitely an option. We're definitely open to push things into drm and help develop common functionality, such as MST and others. The DC abstraction is necessary, however, to handle current and future hardware requirements agnostically. Cheers, Harry On 2016-02-14 06:22 AM, Jerome Glisse wrote: > On Sat, Feb 13, 2016 at 12:05:48AM +, Wentland, Harry wrote: >> Hi Dave, Daniel, others, > [...] > >> There's still a bunch of legacy stuff in these patches that's on our list of >> things to refactor. Some of that is >> - dc/adapter >> - dc/asic_capability >> - dc/audio >> - dc/bios >> - dc/gpio >> >> We should be able to cut the size of this code to about 1/3 of what it is >> now. >> >> As for the LOC we have about >> 22k for HW programming >> 30k legacy stuff >> 6k dc/calcs - autogenerated from formulas provided by HW team >> 15k includes >> 6k amdgpu_dm >> 8k dc/core >> >> About 14k of those are blank lines (we have a habit of leaving lots of blank >> space) and 16k are comments. > Cleaning up that is not enough, abstracting kernel API like kmalloc or i2c, > or similar, is a no go. If the current drm infrastructure does not suit your > need then you need to work on improving it to suit your need. You can not > redevelop a whole drm layer inside your code and expect to upstream it. > > Linux device driver are about sharing infrastructure and trying to expose > it through common API to userspace. > > So i strongly suggest that you start thinking on how to change the drm API > to suit your need and to start discussions about those changes. If you need > them then they will likely be usefull to others down the road. > > Cheers, > Jérôme
[PATCH 00/29] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
Hi Rob, thanks for the heads-up for this. We're definitely interested in contributing to proposed new frameworks. I'm not sure we want to tightly couple userspace with hardware, though. Your proposal seems to assume that user mode is responsible for knowing how many planes any given configuration needs, or iterating through failures until a successful solution is found. First this is quite sub-optimal and would be hard to get right without duplicating most of kernel driver resource management in user mode. Second this doesn't solve the problem with fbcon or other solutions when there is no user-mode component. Cheers, Harry On 2016-02-14 08:32 AM, Rob Clark wrote: > On Fri, Feb 12, 2016 at 7:05 PM, Wentland, Harry > wrote: >> The current amdgpu display stack grew somewhat organically and as such is >> not well suited to handling all of the hardware dependencies involved >> especially in areas like audio. The drm abstractions used by the old code >> map less and less well to new hw pipelines. Atomic helps, but if we are >> going to convert, it seemed like a good time to start fresh. >> >> Our DC (Display Core in dc.h, etc.) is the framework to allow us to well >> represent current and future HW architectures. These don't always map >> one-to-one to DRM interfaces. For one we can't make the assumption that >> surfaces map one-to-one to pipes. > So, this sounds a bit vaguely like some things that I have discussed > from drm/msm.. where you might end up using multiple planes to scan > out a single surface, or multiplex a single plane between multiple > surfaces (or combinations thereof).. > > I think what we'll end up doing is virtualizing planes so we advertise > to userspace more planes than actually exist, and at atomic update > time, dynamically assign pipes to planes, and reject things if > userspace asks for too many planes.. although this is getting into an > area where it helps to assume that there is a userspace component > which is familiar with your hw, which is true for android (and I think > some day wayland compositors will have to grow similar capability for > driver specific userspace plugin to make decisions about how to assign > planes). > > Not sure if a similar approach would help you to fit better into the > kms/atomic framework? > > BR, > -R
[PATCH 08/29] drm/amd/dal: I2C Aux Manager
Hi Rob, that's a good point. We'll see if we can use DRM and existing amdgpu code for i2c/aux and rip this one out. Cheers, Harry On 2016-02-11 03:19 PM, Rob Clark wrote: > On Thu, Feb 11, 2016 at 12:19 PM, Harry Wentland > wrote: >> Implements low-level communication layer over I2C and Aux lines using >> GPIO handles. > so without actually looking too closely at this rather large patch (in > a rather huge patchset).. I do wonder, why not i2c_adapter? Kernel > already has an implementation of that on top of gpio's.. > > BR, > -R > >> Signed-off-by: Harry Wentland >> Reviewed-by: Alex Deucher >> --- >> drivers/gpu/drm/amd/dal/dc/i2caux/Makefile | 33 + >> drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c | 567 >> drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h | 119 +++ >> .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 788 + >> .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.h | 56 ++ >> .../i2caux/dce110/i2c_generic_hw_engine_dce110.h | 25 + >> .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c| 954 >> + >> .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h| 58 ++ >> .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c| 172 >> .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h| 43 + >> .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 266 ++ >> .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 39 + >> .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c| 112 +++ >> .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h| 33 + >> drivers/gpu/drm/amd/dal/dc/i2caux/engine.h | 129 +++ >> drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c| 67 ++ >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c | 121 +++ >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h | 113 +++ >> .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c | 286 ++ >> .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h | 77 ++ >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c | 246 ++ >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h | 80 ++ >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c | 614 + >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h | 81 ++ >> drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 529 >> drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 123 +++ >> 26 files changed, 5731 insertions(+) >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/Makefile >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine.h >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c >> create mode 100644 >> drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c >> create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h
userptr support in drm drivers
On Tue, Feb 16, 2016 at 09:33:51PM +0100, Christian König wrote: > At least for Radeon and Amdgpu the current situation is actually what we > want. > > >However I still find it confusing > >that full userptr support is under #if defined(CONFIG_MMU_NOTIFIER), > >and not under #if defined(CONFIG_RADEON_USERPTR), resp. #if > >defined(CONFIG_AMDGPU_USERPTR). It means that full userptr support may > >be included even if these options are disabled. > Which is perfectly fine. Userptr support should be enabled when MMU_NOTIFIER > is available. > > How this becomes available is a different story. You can explicitly enable > it which then pulls in the MMU_NOTIFIER dependency or you just enable it > when you have the notfier anyway because of some other dependency. > > That we have two options doing the same is just a matter of branching of > amdgpu from radeon and not cleaning up the configuration options. So feel > free to cleaning this up and write a patch which makes pulling in > MMU_NOTIFIER as a general DRM option. Yeah I like that flow. Jean, if you want to bring i915 into alignment with radone by adding a I915_USERPTR option that selects MMU_NOTIFIER (probably default y since vulkan needs this), then I very much want will merge it. Distro kernels pretty much all select MMU_NOTIFIER already for unrelated reasons, but it's good to be less suprising for everyone who builds their own custom kernel. Thanks, Daniel > > Regards, > Christian. > > Am 16.02.2016 um 20:58 schrieb Jean Delvare: > >Hi all, > > > >While checking the openSUSE kernel configuration, I noticed a couple > >oddities regarding userptr support in the i915, radeon and amdgpu drm > >drivers. I'll like to discuss the current situation and come up with an > >agreement on how this could be cleaned up. > > > >Firstly, i915. This driver has userptr code under #if > >defined(CONFIG_MMU_NOTIFIER), however it neither selects this option nor > >depends on it. Given that CONFIG_MMU_NOTIFIER is not a user-visible > >option (it can only be selected by other kernel configuration options), > >it means that you get full userptr support or not depending on other > >unrelated kernel options. This isn't good. > > > >Secondly, radeon and amdgpu. They are slightly better in that they have > >Kconfig options selecting CONFIG_MMU_NOTIFIER (DRM_RADEON_USERPTR and > >DRM_AMDGPU_USERPTR respectively.) However I still find it confusing > >that full userptr support is under #if defined(CONFIG_MMU_NOTIFIER), > >and not under #if defined(CONFIG_RADEON_USERPTR), resp. #if > >defined(CONFIG_AMDGPU_USERPTR). It means that full userptr support may > >be included even if these options are disabled. > > > >I am not too familiar with MMU and this userptr stuff, but from where I > >stand, only two approaches make sense: > > > >* Either there is a good reason why people may want to disable full > > userptr support. In this case options CONFIG_RADEON_USERPTR and > > CONFIG_AMDGPU_USERPTR should really enable the code in question, it > > should not be built without these options. And a similar option > > should be introduced for the i915 driver to the same effect. Or > > alternatively a single option for the whole DRM subsystem may make > > more sense, as I doubt anyone would want to enable support in one > > driver and disable it in another. > > > >* Or there is no specific reason why people would want to disable full > > userptr support, in which case options CONFIG_RADEON_USERPTR and > > CONFIG_AMDGPU_USERPTR should be removed and all 3 drivers should > > unconditionally select CONFIG_MMU_NOTIFIER. > > > >If the sole purpose of these these settings is for development or > >debugging purposes, I'd go for option 1 with a run-time option to > >disable full userptr (drm.userptr=ro or some such.) > > > >As a general rule, fewer configuration options is better. > > > >Once a decision is made, I volunteer to write the patches. > > > >Thanks, > > ___ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
userptr support in drm drivers
At least for Radeon and Amdgpu the current situation is actually what we want. > However I still find it confusing > that full userptr support is under #if defined(CONFIG_MMU_NOTIFIER), > and not under #if defined(CONFIG_RADEON_USERPTR), resp. #if > defined(CONFIG_AMDGPU_USERPTR). It means that full userptr support may > be included even if these options are disabled. Which is perfectly fine. Userptr support should be enabled when MMU_NOTIFIER is available. How this becomes available is a different story. You can explicitly enable it which then pulls in the MMU_NOTIFIER dependency or you just enable it when you have the notfier anyway because of some other dependency. That we have two options doing the same is just a matter of branching of amdgpu from radeon and not cleaning up the configuration options. So feel free to cleaning this up and write a patch which makes pulling in MMU_NOTIFIER as a general DRM option. Regards, Christian. Am 16.02.2016 um 20:58 schrieb Jean Delvare: > Hi all, > > While checking the openSUSE kernel configuration, I noticed a couple > oddities regarding userptr support in the i915, radeon and amdgpu drm > drivers. I'll like to discuss the current situation and come up with an > agreement on how this could be cleaned up. > > Firstly, i915. This driver has userptr code under #if > defined(CONFIG_MMU_NOTIFIER), however it neither selects this option nor > depends on it. Given that CONFIG_MMU_NOTIFIER is not a user-visible > option (it can only be selected by other kernel configuration options), > it means that you get full userptr support or not depending on other > unrelated kernel options. This isn't good. > > Secondly, radeon and amdgpu. They are slightly better in that they have > Kconfig options selecting CONFIG_MMU_NOTIFIER (DRM_RADEON_USERPTR and > DRM_AMDGPU_USERPTR respectively.) However I still find it confusing > that full userptr support is under #if defined(CONFIG_MMU_NOTIFIER), > and not under #if defined(CONFIG_RADEON_USERPTR), resp. #if > defined(CONFIG_AMDGPU_USERPTR). It means that full userptr support may > be included even if these options are disabled. > > I am not too familiar with MMU and this userptr stuff, but from where I > stand, only two approaches make sense: > > * Either there is a good reason why people may want to disable full >userptr support. In this case options CONFIG_RADEON_USERPTR and >CONFIG_AMDGPU_USERPTR should really enable the code in question, it >should not be built without these options. And a similar option >should be introduced for the i915 driver to the same effect. Or >alternatively a single option for the whole DRM subsystem may make >more sense, as I doubt anyone would want to enable support in one >driver and disable it in another. > > * Or there is no specific reason why people would want to disable full >userptr support, in which case options CONFIG_RADEON_USERPTR and >CONFIG_AMDGPU_USERPTR should be removed and all 3 drivers should >unconditionally select CONFIG_MMU_NOTIFIER. > > If the sole purpose of these these settings is for development or > debugging purposes, I'd go for option 1 with a run-time option to > disable full userptr (drm.userptr=ro or some such.) > > As a general rule, fewer configuration options is better. > > Once a decision is made, I volunteer to write the patches. > > Thanks,
userptr support in drm drivers
Hi all, While checking the openSUSE kernel configuration, I noticed a couple oddities regarding userptr support in the i915, radeon and amdgpu drm drivers. I'll like to discuss the current situation and come up with an agreement on how this could be cleaned up. Firstly, i915. This driver has userptr code under #if defined(CONFIG_MMU_NOTIFIER), however it neither selects this option nor depends on it. Given that CONFIG_MMU_NOTIFIER is not a user-visible option (it can only be selected by other kernel configuration options), it means that you get full userptr support or not depending on other unrelated kernel options. This isn't good. Secondly, radeon and amdgpu. They are slightly better in that they have Kconfig options selecting CONFIG_MMU_NOTIFIER (DRM_RADEON_USERPTR and DRM_AMDGPU_USERPTR respectively.) However I still find it confusing that full userptr support is under #if defined(CONFIG_MMU_NOTIFIER), and not under #if defined(CONFIG_RADEON_USERPTR), resp. #if defined(CONFIG_AMDGPU_USERPTR). It means that full userptr support may be included even if these options are disabled. I am not too familiar with MMU and this userptr stuff, but from where I stand, only two approaches make sense: * Either there is a good reason why people may want to disable full userptr support. In this case options CONFIG_RADEON_USERPTR and CONFIG_AMDGPU_USERPTR should really enable the code in question, it should not be built without these options. And a similar option should be introduced for the i915 driver to the same effect. Or alternatively a single option for the whole DRM subsystem may make more sense, as I doubt anyone would want to enable support in one driver and disable it in another. * Or there is no specific reason why people would want to disable full userptr support, in which case options CONFIG_RADEON_USERPTR and CONFIG_AMDGPU_USERPTR should be removed and all 3 drivers should unconditionally select CONFIG_MMU_NOTIFIER. If the sole purpose of these these settings is for development or debugging purposes, I'd go for option 1 with a run-time option to disable full userptr (drm.userptr=ro or some such.) As a general rule, fewer configuration options is better. Once a decision is made, I volunteer to write the patches. Thanks, -- Jean Delvare SUSE L3 Support
[Bug 60879] [radeonsi] X11 can't start with acceleration enabled
https://bugs.freedesktop.org/show_bug.cgi?id=60879 --- Comment #131 from madmalkav --- (In reply to John Bridgman from comment #130) > madmalkav, your dmesg log had messages from the fglrx kernel driver... not > saying that *is* your problem but it definitely can't help... any chance you > can test on a vanilla system that hasn't had fglrx installed ? > > [9.614226] <6>[fglrx] Maximum main memory to use for locked dma buffers: > 7714 MBytes. > [9.614510] <6>[fglrx] vendor: 1002 device: 679e revision: 0 count: 1 > [9.615005] <6>[fglrx] ioport: bar 4, base 0xe000, size: 0x100 > [9.615248] <6>[fglrx] Kernel PAT support is enabled > [9.615263] <6>[fglrx] module loaded - fglrx 15.20.3 [Sep 8 2015] with 1 > minors I can't at the moment as I need this computer for working. I can tell you the system had problems with OSS driver since minute 1, i.e. I had to use the option to use a kernel with propietary drivers in order to manage to install Linux in this machine. If any other option can be valid -booting the installer media with the OSS driver or installing a kernel without the fglrx module- I'll gladly try that. If not, I will try to format the system and do vanilla tests as soon as possible. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160216/fc8e1dec/attachment.html>
[PATCH 01/16] drm: fixes crct set_mode when crtc mode_fixup is null.
On Tue, Feb 16, 2016 at 08:37:29PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 02/16/2016 05:10 PM, Carlos Palminha wrote:
>
> >This patch set nukes all the dummy crtc mode_fixup implementations.
> >(made on top of Daniel topic/drm-misc branch)
> >
> >Signed-off-by: Carlos Palminha
> >---
> > drivers/gpu/drm/drm_crtc_helper.c | 9 ++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> >b/drivers/gpu/drm/drm_crtc_helper.c
> >index e70d064..7539eea 100644
> >--- a/drivers/gpu/drm/drm_crtc_helper.c
> >+++ b/drivers/gpu/drm/drm_crtc_helper.c
> >@@ -343,9 +343,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
> > }
> > }
> >
> >-if (!(ret = crtc_funcs->mode_fixup(crtc, mode, adjusted_mode))) {
> >-DRM_DEBUG_KMS("CRTC fixup failed\n");
> >-goto done;
> >+if (crtc_funcs->mode_fixup) {
> >+if (!(ret = crtc_funcs->mode_fixup(crtc, mode,
> >+adjusted_mode))) {
>
>You haven't run the patch thru scripts/checkpatch.pl, have you? :-)
> (It curses on assignment inside the *if* expression.)
pre-existing, so checkpatch.pl doesn't get a vote ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[PATCH 01/16] drm: fixes crct set_mode when crtc mode_fixup is null.
Hello.
On 02/16/2016 05:10 PM, Carlos Palminha wrote:
> This patch set nukes all the dummy crtc mode_fixup implementations.
> (made on top of Daniel topic/drm-misc branch)
>
> Signed-off-by: Carlos Palminha
> ---
> drivers/gpu/drm/drm_crtc_helper.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> b/drivers/gpu/drm/drm_crtc_helper.c
> index e70d064..7539eea 100644
> --- a/drivers/gpu/drm/drm_crtc_helper.c
> +++ b/drivers/gpu/drm/drm_crtc_helper.c
> @@ -343,9 +343,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
> }
> }
>
> - if (!(ret = crtc_funcs->mode_fixup(crtc, mode, adjusted_mode))) {
> - DRM_DEBUG_KMS("CRTC fixup failed\n");
> - goto done;
> + if (crtc_funcs->mode_fixup) {
> + if (!(ret = crtc_funcs->mode_fixup(crtc, mode,
> + adjusted_mode))) {
You haven't run the patch thru scripts/checkpatch.pl, have you? :-)
(It curses on assignment inside the *if* expression.)
[...]
MBR, Sergei
[Mesa-dev] [PATCH] [v2] intel: Add missing SKL device IDs
On Tue, Feb 16, 2016 at 03:42:45PM -0800, Ben Widawsky wrote: > A new list yielded new devices that apparently have shipped, or will ship. > > v2: I can't read. 0x192d is GT3 > > Signed-off-by: Ben Widawsky > --- > intel/intel_chipset.h | 11 --- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h > index 35148e5..9c24701 100644 > --- a/intel/intel_chipset.h > +++ b/intel/intel_chipset.h > @@ -168,6 +168,7 @@ > #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 > #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 > #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ > +#define PCI_CHIP_SKYLAKE_H_GT1 0x190B > #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ > #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 > #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ > @@ -182,6 +183,7 @@ > #define PCI_CHIP_SKYLAKE_GT3 0x1926 > #define PCI_CHIP_SKYLAKE_HALO_GT30x192B /* Reserved */ > #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A > +#define PCI_CHIP_SKYLAKE_MEDIA_SRV_GT3 0x192D > #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 > #define PCI_CHIP_SKYLAKE_SRV_GT4X0x193A > #define PCI_CHIP_SKYLAKE_H_GT4 0x193B > @@ -376,7 +378,8 @@ > #define IS_SKL_GT1(devid)((devid) == PCI_CHIP_SKYLAKE_ULT_GT1|| \ >(devid) == PCI_CHIP_SKYLAKE_ULX_GT1|| \ >(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ > - (devid) == PCI_CHIP_SKYLAKE_SRV_GT1) > + (devid) == PCI_CHIP_SKYLAKE_SRV_GT1|| \ > + (devid) == PCI_CHIP_SKYLAKE_H_GT1) > > #define IS_SKL_GT2(devid)((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ >(devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ > @@ -390,13 +393,15 @@ >(devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) > > #define IS_SKL_GT3(devid)((devid) == PCI_CHIP_SKYLAKE_GT3|| \ > - (devid) == PCI_CHIP_SKYLAKE_HALO_GT3) > + (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ > + (devid) == PCI_CHIP_SKYLAKE_MEDIA_SRV_GT3) > + > > #define IS_SKL_GT4(devid)((devid) == PCI_CHIP_SKYLAKE_SRV_GT4|| \ >(devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ >(devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ >(devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ > - (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) > + (devid) == PCI_CHIP_SKYLAKE_WKS_GT4|| \ Really sloppy on my part... This hunk is gone from my local patch. I'm not even sure really how I sent this out... > > #define IS_KBL_GT1(devid)((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ >(devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ > -- > 2.7.1 > > ___ > mesa-dev mailing list > mesa-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Bug 60879] [radeonsi] X11 can't start with acceleration enabled
https://bugs.freedesktop.org/show_bug.cgi?id=60879 --- Comment #130 from John Bridgman --- madmalkav, your dmesg log had messages from the fglrx kernel driver... not saying that *is* your problem but it definitely can't help... any chance you can test on a vanilla system that hasn't had fglrx installed ? [9.614226] <6>[fglrx] Maximum main memory to use for locked dma buffers: 7714 MBytes. [9.614510] <6>[fglrx] vendor: 1002 device: 679e revision: 0 count: 1 [9.615005] <6>[fglrx] ioport: bar 4, base 0xe000, size: 0x100 [9.615248] <6>[fglrx] Kernel PAT support is enabled [9.615263] <6>[fglrx] module loaded - fglrx 15.20.3 [Sep 8 2015] with 1 minors -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160216/1f30e017/attachment.html>
[Bug 94179] Marching cubes geometry shader locks GPU
https://bugs.freedesktop.org/show_bug.cgi?id=94179 Bug ID: 94179 Summary: Marching cubes geometry shader locks GPU Product: Mesa Version: 11.1 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/r600 Assignee: dri-devel at lists.freedesktop.org Reporter: pavol at klacansky.com QA Contact: dri-devel at lists.freedesktop.org Created attachment 121789 --> https://bugs.freedesktop.org/attachment.cgi?id=121789&action=edit test case When running the code on AMD 3650 Mobility it locks the GPU and reboot is necessary. Strangely when run in valgrind it works, also software rendering works. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160216/ccd648fe/attachment.html>
[Bug 60879] [radeonsi] X11 can't start with acceleration enabled
https://bugs.freedesktop.org/show_bug.cgi?id=60879 --- Comment #129 from summerrainbowz101 at gmail.com --- Just wondering guys, is there really nothing that can be done in order to fix this issue? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160216/c13d3d63/attachment.html>
[PATCH 11/16] drm/atmel-hldcd: removed optional dummy crtc mode_fixup function.
On Tue, 16 Feb 2016 14:19:06 +
Carlos Palminha wrote:
> This patch set nukes all the dummy crtc mode_fixup implementations.
> (made on top of Daniel topic/drm-misc branch)
There's 2 typos in the subject line (s/hldcd/hlcdc/ and
s/removed/remove/), and you're removing an empty line after
atmel_hlcdc_crtc_create() definition (which is correct, but I'm not
sure it should be part of the same patch).
Otherwise it looks good to me.
Once you've fixed those 2 things, you can add my
Acked-by: Boris Brezillon
>
> Signed-off-by: Carlos Palminha
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 9 -
> 1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 9863291..58c4f78 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -121,13 +121,6 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct
> drm_crtc *c)
> cfg);
> }
>
> -static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> -{
> - return true;
> -}
> -
> static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
> {
> struct drm_device *dev = c->dev;
> @@ -261,7 +254,6 @@ static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc
> *crtc,
> }
>
> static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
> - .mode_fixup = atmel_hlcdc_crtc_mode_fixup,
> .mode_set = drm_helper_crtc_mode_set,
> .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
> .mode_set_base = drm_helper_crtc_mode_set_base,
> @@ -349,4 +341,3 @@ fail:
> atmel_hlcdc_crtc_destroy(&crtc->base);
> return ret;
> }
> -
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[REGRESSION] i915: No HDMI output with 4.4
Here is full dmesg with verbose patch on 4.4.1 and dual-link DVI-HDMI cable: [1] Dual-link works OK: === лÑÑ 16 17:46:38 pfactum.lanet kernel: port C live status ## ## ## ## ## === Also: === [~]$ sudo intel_reg read 0xc4000 0xc4004 0xc4008 0xc400c 0xc4030 (0x000c4000): 0x0040 (0x000c4004): 0xf1b4 (0x000c4008): 0x (0x000c400c): 0x (0x000c4030): 0x00101010 [~]$ sudo intel_reg read 0xc2000 0xc2004 0xc2020 (0x000c2000): 0x (0x000c2004): 0x0001 (0x000c2020): 0x60004000 === Let me know if you need more info. [1] https://gist.github.com/dfbf237e74ed6e0b1bf7 16.02.2016 14:54, Daniel Vetter wrote: > On Tue, Feb 16, 2016 at 12:58:56PM +0200, Oleksandr Natalenko wrote: >> Ville, Daniel, >> >> I've just got another monitor and another DVI-HDMI cable, and here >> what I've >> got. >> >> ===Single Link DVI-D cable with 3 different monitors=== >> >> Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG >> 23MP65HQ-P >> === >> not working > > I presume the above LG screen is what you've called previously "old > monitor"? > >> Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG >> 23MP67HQ-P >> === >> not working >> Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG >> 23MP55HQ-P >> === >> works! >> >> ===Dual Link DVI-D cable with monitor that doesn't work with Single >> Link >> cable=== >> >> Computer DVI âââ DVI-D (Dual Link)/HDMI cable âââ HDMI LG >> 23MP65HQ-P >> === >> works! > > Funky. Can you pls grab the debug logs (with the special patches from > Ville) for this case? I wonder why suddenly different cable and it > works. > > Also: Is this one of these older-ish screens where you must have a > dual-link cable to drive it at full resolution&refresh rate? > -Daniel > > >> ===Laptop with HDMI output=== >> >> Laptop HDMI âââ HDMI/HDMI cable âââ HDMI LG 23MP65HQ-P === works! >> >> I'd say that single link DVI cables are broken with new kernel, but >> one of >> monitors could work with such a cable. So I have no idea :(. >> >> Regards, >> Oleksandr. >> >> 15.02.2016 17:42, Daniel Vetter wrote: >> >The other downside is that it'll make us non-compliant, which was the >> >point of this entire ordeal: HDMI spec forbids us from starting any i2c >> >transactions when the hpd isn't signalling a present screen. >> > >> >So maybe we need to buy one of these broken screens. >> > >> >Oleksandr, what exact model are you using? And any chance that you could >> >test this on some other machine with intel gfx and latest kernel, just to >> >make sure this really is some issue with the sink and not with the machine >> >itself? And I guess you've tested with some other hdmi sink, and that >> >works?
[Bug 94008] Grow Home colors are wrong with HD6950
https://bugs.freedesktop.org/show_bug.cgi?id=94008 --- Comment #2 from serge --- (In reply to Alejandro Pi�eiro (freenode IRC: apinheiro) from comment #1) > (In reply to serge from comment #0) > > > I also made an apitrace which you can find on the following link, if someone > > is interested into looking at this issue: > > > > https://drive.google.com/file/d/0B6bdV-rKtJnFWDlvWE1vZnFtaXc/view?usp=sharing > > Under the risk of adding noise here, I tried this apitrace on a intel HD4600 > (haswell). I got several visual artifacts (in addition to be really slow), > getting several performance related debug warnings. For example, at the > initial phase, where it is mostly compiling shaders: It does the same when playing the apitrace with my card, but those artifacts where not there at recording time. I think they are due to fake calls injections. There is an explanation for this on the tracing section of the following link: https://github.com/apitrace/apitrace/blob/master/docs/BUGS.markdown -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160216/798fa63d/attachment.html>
[PATCH v2 26/26] drm/amdgpu: Use dal driver for Carrizo, Tonga, and Fiji
Start to use dal by default on Carrizo, Tonga, and Fiji ASICs.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Kconfig | 3 +
drivers/gpu/drm/amd/amdgpu/Makefile| 17 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 69 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 5 -
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 20 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 54 ++-
drivers/gpu/drm/amd/amdgpu/vi.c| 250 +
9 files changed, 402 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig
b/drivers/gpu/drm/amd/amdgpu/Kconfig
index b30fcfa4b1f2..3a37e37bef28 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -15,3 +15,6 @@ config DRM_AMDGPU_USERPTR
help
This option selects CONFIG_MMU_NOTIFIER if it isn't already
selected to enabled full userptr support.
+
+source "drivers/gpu/drm/amd/dal/Kconfig"
+
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index c7fcdcedaadb..c434ee5c589f 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -3,13 +3,19 @@
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
FULL_AMD_PATH=$(src)/..
+DAL_FOLDER_NAME=dal
+FULL_AMD_DAL_PATH = $(FULL_AMD_PATH)/$(DAL_FOLDER_NAME)
ccflags-y := -Iinclude/drm -I$(FULL_AMD_PATH)/include/asic_reg \
-I$(FULL_AMD_PATH)/include \
-I$(FULL_AMD_PATH)/amdgpu \
-I$(FULL_AMD_PATH)/scheduler \
-I$(FULL_AMD_PATH)/powerplay/inc \
- -I$(FULL_AMD_PATH)/acp/include
+ -I$(FULL_AMD_PATH)/acp/include \
+ -I$(FULL_AMD_DAL_PATH) \
+ -I$(FULL_AMD_DAL_PATH)/include \
+ -I$(FULL_AMD_DAL_PATH)/dc \
+ -I$(FULL_AMD_DAL_PATH)/amdgpu_dm
amdgpu-y := amdgpu_drv.o
@@ -118,6 +124,15 @@ amdgpu-y += $(AMD_POWERPLAY_FILES)
endif
+ifneq ($(CONFIG_DRM_AMD_DAL),)
+
+RELATIVE_AMD_DAL_PATH = ../$(DAL_FOLDER_NAME)
+include $(FULL_AMD_DAL_PATH)/Makefile
+
+amdgpu-y += $(AMD_DAL_FILES)
+
+endif
+
obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o
CFLAGS_amdgpu_trace_points.o := -I$(src)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 99e660fec190..d154b3473ae8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -54,6 +54,7 @@
#include "amdgpu_gds.h"
#include "amd_powerplay.h"
#include "amdgpu_acp.h"
+#include "amdgpu_dm.h"
#include "gpu_scheduler.h"
@@ -85,6 +86,7 @@ extern int amdgpu_vm_debug;
extern int amdgpu_sched_jobs;
extern int amdgpu_sched_hw_submission;
extern int amdgpu_powerplay;
+extern int amdgpu_dal;
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
#define AMDGPU_MAX_USEC_TIMEOUT10 /* 100 ms */
@@ -2017,6 +2019,7 @@ struct amdgpu_device {
/* display */
struct amdgpu_mode_info mode_info;
+ /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
struct work_struct hotplug_work;
struct amdgpu_irq_src crtc_irq;
struct amdgpu_irq_src pageflip_irq;
@@ -2064,6 +2067,9 @@ struct amdgpu_device {
/* GDS */
struct amdgpu_gds gds;
+ /* display related functionality */
+ struct amdgpu_display_manager dm;
+
const struct amdgpu_ip_block_version *ip_blocks;
int num_ip_blocks;
struct amdgpu_ip_block_status *ip_block_status;
@@ -2100,7 +2106,7 @@ void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg,
u32 v);
u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
-
+bool amdgpu_device_has_dal_support(struct amdgpu_device *adev);
/*
* Cast helper
*/
@@ -2345,6 +2351,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_gds_switch(adev, r, v, d, w, a)
(adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
+#define amdgpu_has_dal_support(adev) (amdgpu_dal &&
amdgpu_device_has_dal_support(adev))
+
/* Common functions */
int amdgpu_gpu_reset(struct amdgpu_device *adev);
void amdgpu_pci_config_reset(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f0fb938457d9..3df6fe35ec63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1369,6 +1369,32 @@ static int amdgpu_resume(struct amdgpu_device *adev)
return 0;
}
+
+/**
+ * amdgpu_device_has_dal_support - check if dal is supported
+ *
+ * @adev: amdgpu_device_pointer
+ *
+ * Returns true for supported, false for not supported
+ */
+bool amdgpu_device_has_dal_support(struct amdgpu_dev
[PATCH v2 25/26] drm/amd/dal: Adding amdgpu_dm for dal
Implements DRM's atomic KMS interfaces using DC.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile | 17 +
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 1468 +++
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h | 168 ++
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 474
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 820 +++
drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h | 122 +
.../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c| 480
.../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h| 36 +
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 457
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c| 2577
.../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h| 100 +
drivers/gpu/drm/amd/dal/dc/dm_services.h | 17 -
12 files changed, 6719 insertions(+), 17 deletions(-)
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c
create mode 100644 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
new file mode 100644
index ..0f365c65342e
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile for the 'dm' sub-component of DAL.
+# It provides the control and status of dm blocks.
+
+
+
+AMDGPUDM = amdgpu_dm_types.o amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o
+
+ifneq ($(CONFIG_DRM_AMD_DAL),)
+AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o
+endif
+
+subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc
+
+AMDGPU_DM = $(addprefix $(AMDDALPATH)/amdgpu_dm/,$(AMDGPUDM))
+
+AMD_DAL_FILES += $(AMDGPU_DM)
diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
new file mode 100644
index ..0ceb505355e8
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c
@@ -0,0 +1,1468 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services_types.h"
+#include "dc.h"
+
+#include "vid.h"
+#include "amdgpu.h"
+#include "atom.h"
+#include "amdgpu_dm.h"
+#include "amdgpu_dm_types.h"
+
+#include "amd_shared.h"
+#include "amdgpu_dm_irq.h"
+#include "dm_helpers.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "dce/dce_11_0_enum.h"
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+#include "oss/oss_3_0_d.h"
+#include "oss/oss_3_0_sh_mask.h"
+#include "gmc/gmc_8_1_d.h"
+#include "gmc/gmc_8_1_sh_mask.h"
+
+#include
+#include
+
+#include
+#include
+#include
+
+/* TODO: Remove when mc access work around is removed */
+static const u32 crtc_offsets[] =
+{
+ CRTC0_REGISTER_OFFSET,
+ CRTC1_REGISTER_OFFSET,
+ CRTC2_REGISTER_OFFSET,
+ CRTC3_REGISTER_OFFSET,
+ CRTC4_REGISTER_OFFSET,
+ CRTC5_REGISTER_OFFSET,
+ CRTC6_REGISTER_OFFSET
+};
+/* TODO: End of when Remove mc access work around is removed */
+
+/* Define variables here
+ * These values will be passed to DAL for feature enable purpose
+ * Disable ALL for HDMI light up
+ * TODO: follow up if need this mechanism*/
+struct dal_override_parameters display_param = {
+
[PATCH v2 24/26] drm/amd/dal: Add display core
Adds a logical representation of our hardware. Provides ability to - dc_validate_resources - validate a display configuration - dc_commit_targets - commit a display configuration - dc_commit_surfaces_to_target - update surfaces - dc_link_detect - detect displays at link - dc_resume - resume display HW - dc_interrupt_set/ack - set and ack interrupts - etc. Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/Makefile | 28 + drivers/gpu/drm/amd/dal/dc/core/dc.c | 932 +++ drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c | 56 + drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 1644 drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c | 1151 ++ drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c | 1728 + drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c| 201 +++ drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 1243 +++ drivers/gpu/drm/amd/dal/dc/core/dc_sink.c | 116 ++ drivers/gpu/drm/amd/dal/dc/core/dc_stream.c | 188 +++ drivers/gpu/drm/amd/dal/dc/core/dc_surface.c | 123 ++ drivers/gpu/drm/amd/dal/dc/core/dc_target.c | 548 +++ 12 files changed, 7958 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_hw_sequencer.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_sink.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_stream.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_surface.c create mode 100644 drivers/gpu/drm/amd/dal/dc/core/dc_target.c diff --git a/drivers/gpu/drm/amd/dal/dc/Makefile b/drivers/gpu/drm/amd/dal/dc/Makefile new file mode 100644 index ..aed26eec81f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/Makefile @@ -0,0 +1,28 @@ +# +# Makefile for Display Core (dc) component. +# + +DC_LIBS = adapter asic_capability audio basics bios calcs \ +gpio gpu i2caux irq virtual + +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 +DC_LIBS += dce110 +endif + +ifdef CONFIG_DRM_AMD_DAL_DCE10_0 +DC_LIBS += dce100 +endif + +AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/dc/,$(DC_LIBS))) + +include $(AMD_DC) + +DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_target.o dc_sink.o dc_stream.o \ +dc_hw_sequencer.o dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o + +AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE)) + +AMD_DAL_FILES += $(AMD_DISPLAY_CORE) + + + diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c new file mode 100644 index ..0b8f158c0ec2 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c @@ -0,0 +1,932 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#include "dm_services.h" + +#include "dc.h" + +#include "core_status.h" +#include "core_types.h" +#include "hw_sequencer.h" + +#include "resource.h" + +#include "adapter_service_interface.h" +#include "clock_source.h" +#include "dc_bios_types.h" + +#include "bandwidth_calcs.h" +#include "include/irq_service_interface.h" +#include "transform.h" +#include "timing_generator.h" +#include "virtual/virtual_link_encoder.h" + +#include "link_hwss.h" +#include "link_encoder.h" + +#include "dc_link_ddc.h" + +/*** + * Private structures + **/ + +struct dc
[PATCH v2 23/26] drm/amd/dal: Add empty encoder programming for virtual HW
Adds empty encoder HW programming functions to support
enablement of virtual pipes (i.e. pipes without actual
display output).
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/virtual/Makefile| 9 ++
.../drm/amd/dal/dc/virtual/virtual_link_encoder.c | 133 +
.../drm/amd/dal/dc/virtual/virtual_link_encoder.h | 35 ++
.../amd/dal/dc/virtual/virtual_stream_encoder.c| 124 +++
.../amd/dal/dc/virtual/virtual_stream_encoder.h| 39 ++
5 files changed, 340 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/virtual/virtual_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
b/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
new file mode 100644
index ..0e2cbc0bb532
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the virtual sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o
+
+AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL))
+
+AMD_DAL_FILES += $(AMD_DAL_VIRTUAL)
diff --git a/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
new file mode 100644
index ..ade443d79c02
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/virtual/virtual_link_encoder.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services_types.h"
+
+#include "virtual_link_encoder.h"
+
+#define VIRTUAL_MAX_PIXEL_CLK_IN_KHZ 60
+
+static bool virtual_link_encoder_validate_output_with_stream(
+ struct link_encoder *enc,
+ struct core_stream *stream) { return true; }
+
+static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
+
+static void virtual_link_encoder_setup(
+ struct link_encoder *enc,
+ enum signal_type signal) {}
+
+static void virtual_link_encoder_enable_tmds_output(
+ struct link_encoder *enc,
+ enum clock_source_id clock_source,
+ enum dc_color_depth color_depth,
+ bool hdmi,
+ bool dual_link,
+ uint32_t pixel_clock) {}
+
+static void virtual_link_encoder_enable_dp_output(
+ struct link_encoder *enc,
+ const struct link_settings *link_settings,
+ enum clock_source_id clock_source) {}
+
+static void virtual_link_encoder_enable_dp_mst_output(
+ struct link_encoder *enc,
+ const struct link_settings *link_settings,
+ enum clock_source_id clock_source) {}
+
+static void virtual_link_encoder_disable_output(
+ struct link_encoder *link_enc,
+ enum signal_type signal) {}
+
+static void virtual_link_encoder_dp_set_lane_settings(
+ struct link_encoder *enc,
+ const struct link_training_settings *link_settings) {}
+
+static void virtual_link_encoder_dp_set_phy_pattern(
+ struct link_encoder *enc,
+ const struct encoder_set_dp_phy_pattern_param *param) {}
+
+static void virtual_link_encoder_update_mst_stream_allocation_table(
+ struct link_encoder *enc,
+ const struct link_mst_stream_allocation_table *table) {}
+
+static void virtual_link_encoder_set_lcd_backlight_level(
+ struct link_encoder *enc,
+ uint32_t level) {}
+
+static void virtual_link_encoder_edp_backlight_control(
+ struct link_encoder *enc,
+ bool enable) {}
+
+static void virtual_link_encoder_edp_power_control(
+ struct link_encoder *enc,
+ bool power_up) {}
+
+static void vir
[PATCH v2 22/26] drm/amd/dal: Add Tonga/Fiji HW sequencer and resource
Enables HW programming on Tonga and Fiji (DCE 10) ASICs. This
mostly re-uses DCE 11 programming code with minor exceptions
and using DCE 10 register offsets.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce100/Makefile | 23 +
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.c| 360 +++
.../drm/amd/dal/dc/dce100/dce100_hw_sequencer.h| 36 +
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c| 1135
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.h| 43 +
5 files changed, 1597 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
new file mode 100644
index ..656c38e1b0f5
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE100 = dce100_resource.o dce100_hw_sequencer.o
+
+AMD_DAL_DCE100 = $(addprefix $(AMDDALPATH)/dc/dce100/,$(DCE100))
+
+AMD_DAL_FILES += $(AMD_DAL_DCE100)
+
+
+###
+# DCE 10x
+###
+ifdef 0#CONFIG_DRM_AMD_DAL_DCE11_0
+TG_DCE100 = dce100_resource.o
+
+AMD_DAL_TG_DCE100 = $(addprefix \
+ $(AMDDALPATH)/dc/dce100/,$(TG_DCE100))
+
+AMD_DAL_FILES += $(AMD_DAL_TG_DCE100)
+endif
+
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
new file mode 100644
index ..a1dbac487366
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_hw_sequencer.c
@@ -0,0 +1,360 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dc.h"
+#include "core_dc.h"
+#include "core_types.h"
+#include "hw_sequencer.h"
+#include "dce100_hw_sequencer.h"
+#include "dce110/dce110_hw_sequencer.h"
+
+/* include DCE10 register header files */
+#include "dce/dce_10_0_d.h"
+#include "dce/dce_10_0_sh_mask.h"
+
+struct dce100_hw_seq_reg_offsets {
+ uint32_t blnd;
+ uint32_t crtc;
+};
+
+enum pipe_lock_control {
+ PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
+ PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
+ PIPE_LOCK_CONTROL_SCL = 1 << 2,
+ PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
+ PIPE_LOCK_CONTROL_MODE = 1 << 4
+};
+
+enum blender_mode {
+ BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ BLENDER_MODE_STEREO
+};
+
+static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
+{
+ .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .blnd = (mmBLND1_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .blnd = (mmBLND2_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+}
+};
+
+#define HW_REG_BLND(reg, id)\
+ (reg + reg_offsets[id].blnd)
+
+#define HW_REG_CRTC(reg, id)\
+ (reg + reg_offsets[id].crtc)
+
+
+/***
+ * Private definitions
+
**/
+/**
[PATCH v2 21/26] drm/amd/dal: Add Carrizo HW sequencer and resource
Adds dce110_resource and dce110_hw_sequencer files.
dce110_resource manages creation of HW resources, along with correct
ASIC register offset for each block.
dce110_hw_sequencers is responsible for programming HW sequences,
such as enable_stream, program_scaler, power_down_encoders, etc.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce110/Makefile | 15 +
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c| 1658
.../drm/amd/dal/dc/dce110/dce110_hw_sequencer.h| 36 +
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c| 1238 +++
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.h| 46 +
5 files changed, 2993 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
new file mode 100644
index ..ae9d2de92da2
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/Makefile
@@ -0,0 +1,15 @@
+#
+# Makefile for the 'controller' sub-component of DAL.
+# It provides the control and status of HW CRTC block.
+
+DCE110 = dce110_ipp.o dce110_ipp_cursor.o \
+dce110_ipp_gamma.o dce110_link_encoder.o dce110_opp.o \
+dce110_opp_formatter.o dce110_opp_regamma.o dce110_stream_encoder.o \
+dce110_timing_generator.o dce110_transform.o dce110_transform_gamut.o \
+dce110_transform_scl.o dce110_transform_sclv.o dce110_opp_csc.o\
+dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \
+dce110_resource.o dce110_transform_bit_depth.o dce110_clock_source.o
+
+AMD_DAL_DCE110 = $(addprefix $(AMDDALPATH)/dc/dce110/,$(DCE110))
+
+AMD_DAL_FILES += $(AMD_DAL_DCE110)
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
new file mode 100644
index ..71fa7b1f8061
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -0,0 +1,1658 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+#include "dc.h"
+#include "dc_bios_types.h"
+#include "core_types.h"
+#include "core_status.h"
+#include "resource.h"
+#include "hw_sequencer.h"
+#include "dm_helpers.h"
+#include "dce110_hw_sequencer.h"
+
+#include "gpu/dce110/dc_clock_gating_dce110.h"
+
+#include "timing_generator.h"
+#include "mem_input.h"
+#include "opp.h"
+#include "ipp.h"
+#include "transform.h"
+#include "stream_encoder.h"
+#include "link_encoder.h"
+#include "clock_source.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+struct dce110_hw_seq_reg_offsets {
+ uint32_t dcfe;
+ uint32_t blnd;
+ uint32_t crtc;
+};
+
+enum pipe_lock_control {
+ PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0,
+ PIPE_LOCK_CONTROL_BLENDER = 1 << 1,
+ PIPE_LOCK_CONTROL_SCL = 1 << 2,
+ PIPE_LOCK_CONTROL_SURFACE = 1 << 3,
+ PIPE_LOCK_CONTROL_MODE = 1 << 4
+};
+
+enum blender_mode {
+ BLENDER_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */
+ BLENDER_MODE_OTHER_PIPE, /* Data from other pipe only */
+ BLENDER_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */
+ BLENDER_MODE_STEREO
+};
+
+static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
+{
+ .dcfe = (mmDCFE0_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL),
+ .blnd = (mmBLND0_BLND_CONTROL - mmBLND_CONTROL),
+ .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
+},
+{
+ .dcfe = (mmDCFE1_DCFE_MEM_PWR_CTRL - mmDCFE_MEM_PWR_CTRL
[PATCH v2 20/26] drm/amd/dal: Add transform & scaler HW programming
Adds scaler, viewport, gamut remap, and pixel depth programming.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.c | 91 +++
.../gpu/drm/amd/dal/dc/dce110/dce110_transform.h | 87 +++
.../amd/dal/dc/dce110/dce110_transform_bit_depth.c | 851 +
.../amd/dal/dc/dce110/dce110_transform_bit_depth.h | 51 ++
.../drm/amd/dal/dc/dce110/dce110_transform_gamut.c | 296 +++
.../drm/amd/dal/dc/dce110/dce110_transform_scl.c | 818
.../drm/amd/dal/dc/dce110/dce110_transform_sclv.c | 531 +
7 files changed, 2725 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_bit_depth.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_gamut.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_scl.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform_sclv.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
new file mode 100644
index ..2654a965065d
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dc_types.h"
+#include "core_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/fixed31_32.h"
+#include "include/logger_interface.h"
+
+#include "dce110_transform.h"
+
+#include "dce110_transform_bit_depth.h"
+
+static struct transform_funcs dce110_transform_funcs = {
+ .transform_power_up =
+ dce110_transform_power_up,
+ .transform_set_scaler =
+ dce110_transform_set_scaler,
+ .transform_set_scaler_bypass =
+ dce110_transform_set_scaler_bypass,
+ .transform_update_viewport =
+ dce110_transform_update_viewport,
+ .transform_set_scaler_filter =
+ dce110_transform_set_scaler_filter,
+ .transform_set_gamut_remap =
+ dce110_transform_set_gamut_remap,
+ .transform_set_pixel_storage_depth =
+ dce110_transform_set_pixel_storage_depth,
+ .transform_get_current_pixel_storage_depth =
+ dce110_transform_get_current_pixel_storage_depth
+};
+
+/*/
+/* Constructor, Destructor */
+/*/
+
+bool dce110_transform_construct(
+ struct dce110_transform *xfm110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dce110_transform_reg_offsets *reg_offsets)
+{
+ xfm110->base.ctx = ctx;
+
+ xfm110->base.inst = inst;
+ xfm110->base.funcs = &dce110_transform_funcs;
+
+ xfm110->offsets = *reg_offsets;
+
+ xfm110->lb_pixel_depth_supported =
+ LB_PIXEL_DEPTH_18BPP |
+ LB_PIXEL_DEPTH_24BPP |
+ LB_PIXEL_DEPTH_30BPP;
+
+ return true;
+}
+
+bool dce110_transform_power_up(struct transform *xfm)
+{
+ return dce110_transform_power_up_line_buffer(xfm);
+}
+
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
new file mode 100644
index ..117aca337f9d
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_transform.h
@@ -0,0 +1,87 @@
+/* Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted,
[PATCH v2 19/26] drm/amd/dal: Add output pixel processing HW programming
Adds programming for color space conversion (CSC),
regamma, and formatter.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c | 272 +++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h | 143 ++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c | 904 +++
.../drm/amd/dal/dc/dce110/dce110_opp_formatter.c | 610 +
.../gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c | 2474
5 files changed, 4403 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_formatter.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_regamma.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
new file mode 100644
index ..acb405e7b2e7
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dce110_opp.h"
+
+#include "gamma_types.h"
+
+enum {
+ MAX_LUT_ENTRY = 256,
+ MAX_NUMBER_OF_ENTRIES = 256
+};
+
+static void build_evenly_distributed_points(
+ struct gamma_pixel *points,
+ uint32_t numberof_points,
+ struct fixed31_32 max_value,
+ struct fixed31_32 divider1,
+ struct fixed31_32 divider2,
+ struct fixed31_32 divider3)
+{
+ struct gamma_pixel *p = points;
+ struct gamma_pixel *p_last = p + numberof_points - 1;
+
+ uint32_t i = 0;
+
+ do {
+ struct fixed31_32 value = dal_fixed31_32_div_int(
+ dal_fixed31_32_mul_int(max_value, i),
+ numberof_points - 1);
+
+ p->r = value;
+ p->g = value;
+ p->b = value;
+
+ ++p;
+ ++i;
+ } while (i != numberof_points);
+
+ p->r = dal_fixed31_32_div(p_last->r, divider1);
+ p->g = dal_fixed31_32_div(p_last->g, divider1);
+ p->b = dal_fixed31_32_div(p_last->b, divider1);
+
+ ++p;
+
+ p->r = dal_fixed31_32_div(p_last->r, divider2);
+ p->g = dal_fixed31_32_div(p_last->g, divider2);
+ p->b = dal_fixed31_32_div(p_last->b, divider2);
+
+ ++p;
+
+ p->r = dal_fixed31_32_div(p_last->r, divider3);
+ p->g = dal_fixed31_32_div(p_last->g, divider3);
+ p->b = dal_fixed31_32_div(p_last->b, divider3);
+}
+
+/*/
+/* Constructor, Destructor */
+/*/
+
+struct opp_funcs funcs = {
+ .opp_map_legacy_and_regamma_hw_to_x_user =
dce110_opp_map_legacy_and_regamma_hw_to_x_user,
+ .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut,
+ .opp_program_bit_depth_reduction =
dce110_opp_program_bit_depth_reduction,
+ .opp_program_clamping_and_pixel_encoding =
dce110_opp_program_clamping_and_pixel_encoding,
+ .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment,
+ .opp_set_csc_default = dce110_opp_set_csc_default,
+ .opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
+ .opp_set_regamma = dce110_opp_set_regamma
+};
+
+bool dce110_opp_construct(struct dce110_opp *opp110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dce110_opp_reg_offsets *offsets)
+{
+
+ opp110->base.funcs = &funcs;
+
+ opp110->base.ctx = ctx;
+
+ opp110->base.inst = inst;
+
+ opp110->offs
[PATCH v2 18/26] drm/amd/dal: Add input pixel processing HW programming
Adds programming of cursor and input gamma.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c | 65 ++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h | 100 +++
.../gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c | 256 ++
.../gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c | 872 +
4 files changed, 1293 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_cursor.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp_gamma.c
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
new file mode 100644
index ..6ab35272f979
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dce110_ipp.h"
+
+static struct ipp_funcs funcs = {
+ .ipp_cursor_set_attributes = dce110_ipp_cursor_set_attributes,
+ .ipp_cursor_set_position = dce110_ipp_cursor_set_position,
+ .ipp_program_prescale = dce110_ipp_program_prescale,
+ .ipp_set_degamma = dce110_ipp_set_degamma,
+ .ipp_set_legacy_input_gamma_mode =
dce110_ipp_set_legacy_input_gamma_mode,
+ .ipp_set_legacy_input_gamma_ramp =
dce110_ipp_set_legacy_input_gamma_ramp,
+ .ipp_set_palette = dce110_ipp_set_palette,
+};
+
+bool dce110_ipp_construct(
+ struct dce110_ipp* ipp,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dce110_ipp_reg_offsets *offset)
+{
+ ipp->base.ctx = ctx;
+
+ ipp->base.inst = inst;
+
+ ipp->offsets = *offset;
+
+ ipp->base.funcs = &funcs;
+
+ return true;
+}
+
+void dce110_ipp_destroy(struct input_pixel_processor **ipp)
+{
+ dm_free((*ipp)->ctx, TO_DCE110_IPP(*ipp));
+ *ipp = NULL;
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
new file mode 100644
index ..709906face3f
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_ipp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_IPP_DCE110_H__
+#define __DC_IPP_DCE110_H__
+
+#include "inc/ipp.h"
+
+
+struct gamma_parameters;
+struct dev_c_lut;
+
+#define TO_DCE110_IPP(input_pixel_processor)\
+ container_of(input_pixel_processor, struct dce110_ipp,
[PATCH v2 17/26] drm/amd/dal: Add framebuffer compression HW programming
Adds framebuffer compression programming. Currently unused.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.c | 886 +
.../gpu/drm/amd/dal/dc/dce110/dce110_compressor.h | 84 ++
2 files changed, 970 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
new file mode 100644
index ..285d54439f4c
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_compressor.c
@@ -0,0 +1,886 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "gmc/gmc_8_2_sh_mask.h"
+#include "gmc/gmc_8_2_d.h"
+
+#include "include/logger_interface.h"
+#include "include/adapter_service_interface.h"
+
+#include "dce110_compressor.h"
+
+#define DCP_REG(reg)\
+ (reg + cp110->offsets.dcp_offset)
+#define DMIF_REG(reg)\
+ (reg + cp110->offsets.dmif_offset)
+
+static const struct dce110_compressor_reg_offsets reg_offsets[] = {
+{
+ .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+ .dmif_offset =
+ (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
+ - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
+},
+{
+ .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+ .dmif_offset =
+ (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
+ - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
+},
+{
+ .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
+ .dmif_offset =
+ (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
+ - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
+}
+};
+
+static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
+
+enum fbc_idle_force {
+ /* Bit 0 - Display registers updated */
+ FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x0001,
+
+ /* Bit 2 - FBC_GRPH_COMP_EN register updated */
+ FBC_IDLE_FORCE_GRPH_COMP_EN = 0x0002,
+ /* Bit 3 - FBC_SRC_SEL register updated */
+ FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x0004,
+ /* Bit 4 - FBC_MIN_COMPRESSION register updated */
+ FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x0008,
+ /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
+ FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x0010,
+ /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
+ FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x0020,
+ /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
+ FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x0040,
+
+ /* Bit 24 - Memory write to region 0 defined by MC registers. */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x0100,
+ /* Bit 25 - Memory write to region 1 defined by MC registers */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x0200,
+ /* Bit 26 - Memory write to region 2 defined by MC registers */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x0400,
+ /* Bit 27 - Memory write to region 3 defined by MC registers. */
+ FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x0800,
+
+ /* Bit 28 - Memory write from any client other than MCIF */
+ FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x1000,
+ /* Bit 29 - CG statics screen signal is inactive */
+ FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x2000,
+};
+
+static uint32_t lpt_size_alignment(struct dce110_compressor *cp110)
+{
+ /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
+ return cp110->base.raw_size * cp110->base.banks_num *
+ cp110->base.dram_channels_num;
+}
+
+static uint32_t lpt
[PATCH v2 16/26] drm/amd/dal: Add surface HW programming
Adds watermark, DMIF, and surface programming.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c | 965 +
.../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h | 117 +++
2 files changed, 1082 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
new file mode 100644
index ..3a928e63e647
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -0,0 +1,965 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dm_services.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+/* TODO: this needs to be looked at, used by Stella's workaround*/
+#include "gmc/gmc_8_2_d.h"
+#include "gmc/gmc_8_2_sh_mask.h"
+
+#include "include/logger_interface.h"
+#include "adapter_service_interface.h"
+#include "inc/bandwidth_calcs.h"
+
+#include "dce110_mem_input.h"
+
+#define MAX_WATERMARK 0x
+#define SAFE_NBP_MARK 0x7FFF
+
+#define DCP_REG(reg) (reg + mem_input110->offsets.dcp)
+#define DMIF_REG(reg) (reg + mem_input110->offsets.dmif)
+#define PIPE_REG(reg) (reg + mem_input110->offsets.pipe)
+
+static void set_flip_control(
+ struct dce110_mem_input *mem_input110,
+ bool immediate)
+{
+ uint32_t value = 0;
+
+ value = dm_read_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_FLIP_CONTROL));
+ set_reg_field_value(value, 0,
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
+ set_reg_field_value(value, 0,
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_H_RETRACE_EN);
+ if (immediate == true)
+ set_reg_field_value(value, 1,
+ GRPH_FLIP_CONTROL,
+ GRPH_SURFACE_UPDATE_IMMEDIATE_EN);
+
+ dm_write_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_FLIP_CONTROL),
+ value);
+}
+
+static void program_sec_addr(
+ struct dce110_mem_input *mem_input110,
+ PHYSICAL_ADDRESS_LOC address)
+{
+ uint32_t value = 0;
+ uint32_t temp = 0;
+ /*high register MUST be programmed first*/
+ temp = address.high_part &
+GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK;
+
+ set_reg_field_value(value, temp,
+ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
+ GRPH_SECONDARY_SURFACE_ADDRESS_HIGH);
+
+ dm_write_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH),
+ value);
+
+ temp = 0;
+ value = 0;
+ temp = address.low_part >>
+ GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT;
+
+ set_reg_field_value(value, temp,
+ GRPH_SECONDARY_SURFACE_ADDRESS,
+ GRPH_SECONDARY_SURFACE_ADDRESS);
+
+ dm_write_reg(
+ mem_input110->base.ctx,
+ DCP_REG(mmGRPH_SECONDARY_SURFACE_ADDRESS),
+ value);
+}
+
+static void program_pri_addr(
+ struct dce110_mem_input *mem_input110,
+ PHYSICAL_ADDRESS_LOC address)
+{
+ uint32_t value = 0;
+ uint32_t temp = 0;
+
+ /*high register MUST be programmed first*/
+ temp = address.high_part &
+GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK;
+
+ set_reg_field_value(value, temp,
+ GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
+ GRPH_PRIMARY_SURFACE_ADDR
[PATCH v2 15/26] drm/amd/dal: Add timing generator HW programming
Adds ability to validate and program timings, enable, disable, and blank
CRTCs, and get CRTC status information.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../amd/dal/dc/dce110/dce110_timing_generator.c| 1864
.../amd/dal/dc/dce110/dce110_timing_generator.h| 234 +++
2 files changed, 2098 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
new file mode 100644
index ..6e6a7a5cac6a
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
@@ -0,0 +1,1864 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dc_types.h"
+#include "dc_bios_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/adapter_service_interface.h"
+#include "include/logger_interface.h"
+#include "dce110_timing_generator.h"
+
+#include "../inc/timing_generator.h"
+
+enum black_color_format {
+ BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
+ BLACK_COLOR_FORMAT_RGB_LIMITED,
+ BLACK_COLOR_FORMAT_YUV_TV,
+ BLACK_COLOR_FORMAT_YUV_CV,
+ BLACK_COLOR_FORMAT_YUV_SUPER_AA,
+
+ BLACK_COLOR_FORMAT_COUNT
+};
+
+#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
+
+#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
+#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
+
+#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
+#define DCP_REG(reg) (reg + tg110->offsets.dcp)
+
+
+/***
+ * GSL Sync related values */
+
+/* In VSync mode, after 4 units of time, master pipe will generate
+ * flip_ready signal */
+#define VFLIP_READY_DELAY 4
+/* In HSync mode, after 2 units of time, master pipe will generate
+ * flip_ready signal */
+#define HFLIP_READY_DELAY 2
+/* 6 lines delay between forcing flip and checking all pipes ready */
+#define HFLIP_CHECK_DELAY 6
+/* 3 lines before end of frame */
+#define FLIP_READY_BACK_LOOKUP 3
+
+/* Trigger Source Select - ASIC-dependant, actual values for the
+ * register programming */
+enum trigger_source_select {
+ TRIGGER_SOURCE_SELECT_LOGIC_ZERO = 0,
+ TRIGGER_SOURCE_SELECT_CRTC_VSYNCA = 1,
+ TRIGGER_SOURCE_SELECT_CRTC_HSYNCA = 2,
+ TRIGGER_SOURCE_SELECT_CRTC_VSYNCB = 3,
+ TRIGGER_SOURCE_SELECT_CRTC_HSYNCB = 4,
+ TRIGGER_SOURCE_SELECT_GENERICF = 5,
+ TRIGGER_SOURCE_SELECT_GENERICE = 6,
+ TRIGGER_SOURCE_SELECT_VSYNCA = 7,
+ TRIGGER_SOURCE_SELECT_HSYNCA = 8,
+ TRIGGER_SOURCE_SELECT_VSYNCB = 9,
+ TRIGGER_SOURCE_SELECT_HSYNCB = 10,
+ TRIGGER_SOURCE_SELECT_HPD1 = 11,
+ TRIGGER_SOURCE_SELECT_HPD2 = 12,
+ TRIGGER_SOURCE_SELECT_GENERICD = 13,
+ TRIGGER_SOURCE_SELECT_GENERICC = 14,
+ TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE = 15,
+ TRIGGER_SOURCE_SELECT_GSL_GROUP0 = 16,
+ TRIGGER_SOURCE_SELECT_GSL_GROUP1 = 17,
+ TRIGGER_SOURCE_SELECT_GSL_GROUP2 = 18,
+ TRIGGER_SOURCE_SELECT_BLONY = 19,
+ TRIGGER_SOURCE_SELECT_GENERICA = 20,
+ TRIGGER_SOURCE_SELECT_GENERICB = 21,
+ TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP = 22,
+ TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER = 23
+};
+
+/* Trigger Source Select - ASIC-dependant, actual values for the
+ * register programming */
+enum trigger_polarity_select {
+ TRIGGER_POLARITY_SELECT_LOGIC_ZERO = 0,
+ TRIGGER_POLARITY_SELECT_CRTC = 1,
+ TRIGGER_POLARITY_SELECT_GENERICA = 2,
+ TRIGGER_POLARITY_S
[PATCH v2 14/26] drm/amd/dal: Add clock source HW programming
Adds pixel clock programming and functionality to
power down clock sources.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../drm/amd/dal/dc/dce110/dce110_clock_source.c| 1162
.../drm/amd/dal/dc/dce110/dce110_clock_source.h| 64 ++
2 files changed, 1226 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
new file mode 100644
index ..e1bac1f77b79
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
@@ -0,0 +1,1162 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+/* include DCE11 register header files */
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+
+#include "dc_types.h"
+#include "core_types.h"
+
+#include "include/grph_object_id.h"
+#include "include/logger_interface.h"
+
+#include "dce110_clock_source.h"
+
+#define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
+#define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
+#define MAX_PLL_CALC_ERROR 0x
+
+static const struct spread_spectrum_data *get_ss_data_entry(
+ struct dce110_clk_src *clk_src,
+ enum signal_type signal,
+ uint32_t pix_clk_khz)
+{
+
+ uint32_t entrys_num;
+ uint32_t i;
+ struct spread_spectrum_data *ss_parm = NULL;
+ struct spread_spectrum_data *ret = NULL;
+
+ switch (signal) {
+ case SIGNAL_TYPE_DVI_SINGLE_LINK:
+ case SIGNAL_TYPE_DVI_DUAL_LINK:
+ ss_parm = clk_src->dvi_ss_params;
+ entrys_num = clk_src->dvi_ss_params_cnt;
+ break;
+
+ case SIGNAL_TYPE_HDMI_TYPE_A:
+ ss_parm = clk_src->hdmi_ss_params;
+ entrys_num = clk_src->hdmi_ss_params_cnt;
+ break;
+
+ case SIGNAL_TYPE_DISPLAY_PORT:
+ case SIGNAL_TYPE_DISPLAY_PORT_MST:
+ case SIGNAL_TYPE_EDP:
+ ss_parm = clk_src->dp_ss_params;
+ entrys_num = clk_src->dp_ss_params_cnt;
+ break;
+
+ default:
+ ss_parm = NULL;
+ entrys_num = 0;
+ break;
+ }
+
+ if (ss_parm == NULL)
+ return ret;
+
+ for (i = 0; i < entrys_num; ++i, ++ss_parm) {
+ if (ss_parm->freq_range_khz >= pix_clk_khz) {
+ ret = ss_parm;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/**
+* Function: calculate_fb_and_fractional_fb_divider
+*
+* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
+*
+*PARAMETERS:
+* targetPixelClock Desired frequency in 10 KHz
+* ref_divider Reference divider (already known)
+* postDivider Post Divider (already known)
+* feedback_divider_param Pointer where to store
+* calculated feedback divider value
+* fract_feedback_divider_param Pointer where to store
+* calculated fract feedback divider value
+*
+*RETURNS:
+* It fills the locations pointed by feedback_divider_param
+* and fract_feedback_divider_param
+* It returns - true if feedback divider not 0
+* - false should never happen)
+*/
+static bool calculate_fb_and_fractional_fb_divider(
+ struct calc_pll_clock_source *calc_pll_cs,
+ uint32_t target_pix_clk_khz,
+ uint32_t ref_divider,
+ uint32_t post_divider,
+ uint32_t *feedback_divider_param,
+ uint32_t *fract_feedback_divider_param)
+{
+ uint64_t feedbac
[PATCH v2 13/26] drm/amd/dal: Add encoder HW programming
Responsible for programming back-end of display path, such as DIG,
UNIPHY, DP, DAC, and DVO.
Supports:
- DisplayPort (single stream)
- HDMI
- DVI
- eDP
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../drm/amd/dal/dc/dce110/dce110_link_encoder.c| 1927
.../drm/amd/dal/dc/dce110/dce110_link_encoder.h| 156 ++
.../drm/amd/dal/dc/dce110/dce110_stream_encoder.c | 1123
.../drm/amd/dal/dc/dce110/dce110_stream_encoder.h | 122 ++
4 files changed, 3328 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/dce110/dce110_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
new file mode 100644
index ..f714215c0dd5
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_link_encoder.c
@@ -0,0 +1,1927 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "core_types.h"
+#include "link_encoder.h"
+#include "stream_encoder.h"
+#include "dce110_link_encoder.h"
+
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "dce/dce_11_0_enum.h"
+
+#define LINK_REG(reg)\
+ (enc110->link_regs->reg)
+
+#define AUX_REG(reg)\
+ (enc110->aux_regs->reg)
+
+#define BL_REG(reg)\
+ (enc110->bl_regs->reg)
+
+/* For current ASICs pixel clock - 600MHz */
+#define MAX_ENCODER_CLK 60
+
+#define DCE11_UNIPHY_MAX_PIXEL_CLK_IN_KHZ 60
+
+#define DEFAULT_AUX_MAX_DATA_SIZE 16
+#define AUX_MAX_DEFER_WRITE_RETRY 20
+/*
+ * @brief
+ * Trigger Source Select
+ * ASIC-dependent, actual values for register programming
+ */
+#define DCE110_DIG_FE_SOURCE_SELECT_INVALID 0x0
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGA 0x1
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGB 0x2
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGC 0x4
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGD 0x08
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGE 0x10
+#define DCE110_DIG_FE_SOURCE_SELECT_DIGF 0x20
+
+/* all values are in milliseconds */
+/* For eDP, after power-up/power/down,
+ * 300/500 msec max. delay from LCDVCC to black video generation */
+#define PANEL_POWER_UP_TIMEOUT 300
+#define PANEL_POWER_DOWN_TIMEOUT 500
+#define HPD_CHECK_INTERVAL 10
+
+/* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
+#define TMDS_MIN_PIXEL_CLOCK 25000
+/* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
+#define TMDS_MAX_PIXEL_CLOCK 165000
+/* For current ASICs pixel clock - 600MHz */
+#define MAX_ENCODER_CLOCK 60
+
+enum {
+ DP_MST_UPDATE_MAX_RETRY = 50
+};
+
+#define DIG_REG(reg)\
+ (reg + enc110->offsets.dig)
+
+#define DP_REG(reg)\
+ (reg + enc110->offsets.dp)
+
+static struct link_encoder_funcs dce110_lnk_enc_funcs = {
+ .validate_output_with_stream =
+ dce110_link_encoder_validate_output_with_stream,
+ .hw_init = dce110_link_encoder_hw_init,
+ .setup = dce110_link_encoder_setup,
+ .enable_tmds_output = dce110_link_encoder_enable_tmds_output,
+ .enable_dp_output = dce110_link_encoder_enable_dp_output,
+ .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output,
+ .disable_output = dce110_link_encoder_disable_output,
+ .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings,
+ .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern,
+ .update_mst_stream_allocation_table =
+ dce110_link_encoder_update_mst_stream_allocation_table,
+ .set_lcd_backlight_level = dce110_link_encoder_set_lcd_backlight_level,
+
[PATCH v2 12/26] drm/amd/dal: Bandwidth calculations
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/calcs/Makefile | 10 +
drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c | 3941
drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c| 300 ++
drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c | 1992 ++
drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h | 74 +
5 files changed, 6317 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/bw_fixed.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/calcs/scaler_filter.h
diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
new file mode 100644
index ..7f1916b79b88
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile for the 'calcs' sub-component of DAL.
+# It calculates Bandwidth and Watermarks values for HW programming
+#
+
+BW_CALCS = bandwidth_calcs.o bw_fixed.o scaler_filter.o
+
+AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS))
+
+AMD_DAL_FILES += $(AMD_DAL_BW_CALCS)
diff --git a/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
new file mode 100644
index ..8faabbc12fd3
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/calcs/bandwidth_calcs.c
@@ -0,0 +1,3941 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "bandwidth_calcs.h"
+
+/***
+ * Private Functions
+
**/
+
+static void calculate_bandwidth(
+ const struct bw_calcs_dceip *dceip,
+ const struct bw_calcs_vbios *vbios,
+ const struct bw_calcs_mode_data_internal *mode_data,
+ struct bw_calcs_results *results)
+
+{
+ const int32_t pixels_per_chunk = 512;
+ const int32_t max_chunks_non_fbc_mode = 16;
+ const int32_t high = 2;
+ const int32_t mid = 1;
+ const int32_t low = 0;
+
+ int32_t i, j, k;
+ struct bw_fixed yclk[3];
+ struct bw_fixed sclk[3];
+ bool d0_underlay_enable;
+ bool d1_underlay_enable;
+ enum bw_defines sclk_message;
+ enum bw_defines yclk_message;
+ enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
+ enum bw_defines tiling_mode[maximum_number_of_surfaces];
+ enum bw_defines stereo_mode[maximum_number_of_surfaces];
+ enum bw_defines surface_type[maximum_number_of_surfaces];
+ enum bw_defines voltage;
+ enum bw_defines pipe_check;
+ enum bw_defines hsr_check;
+ enum bw_defines vsr_check;
+ enum bw_defines lb_size_check;
+ enum bw_defines fbc_check;
+ enum bw_defines rotation_check;
+ enum bw_defines mode_check;
+
+ yclk[low] = vbios->low_yclk;
+ yclk[mid] = vbios->high_yclk;
+ yclk[high] = vbios->high_yclk;
+ sclk[low] = vbios->low_sclk;
+ sclk[mid] = vbios->mid_sclk;
+ sclk[high] = vbios->high_sclk;
+ /* surface assignment:*/
+ /* 0: d0 underlay or underlay luma*/
+ /* 1: d0 underlay chroma*/
+ /* 2: d1 underlay or underlay luma*/
+ /* 3: d1 underlay chroma*/
+ /* 4: d0 graphics*/
+ /* 5: d1 graphics*/
+ /* 6: d2 graphics*/
+ /* 7: d3 graphics, same mode as d2*/
+ /* 8: d4 graphics, same mode as d2*/
+ /* 9: d5 graphics, same mode as d2*/
+ /* ...*/
+ /* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
+ /* maximum_number_of_surfaces-1: d1 display_write_back420 c
[PATCH v2 11/26] drm/amd/dal: Audio
Responsible for programming the audio encoder in the display path.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/audio/Makefile | 22 +
drivers/gpu/drm/amd/dal/dc/audio/audio.h | 195 ++
drivers/gpu/drm/amd/dal/dc/audio/audio_base.c | 470 +
.../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c | 453 +
.../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h | 42 +
.../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 1930
.../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h | 47 +
drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c| 771
drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h| 285 +++
9 files changed, 4215 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h
diff --git a/drivers/gpu/drm/amd/dal/dc/audio/Makefile
b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
new file mode 100644
index ..0999372cecf0
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/audio/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for the 'audio' sub-component of DAL.
+# It provides the control and status of HW adapter resources,
+# that are global for the ASIC and sharable between pipes.
+
+AUDIO = audio_base.o hw_ctx_audio.o
+
+AMD_DAL_AUDIO = $(addprefix $(AMDDALPATH)/dc/audio/,$(AUDIO))
+
+AMD_DAL_FILES += $(AMD_DAL_AUDIO)
+
+
+###
+# DCE 11x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+AUDIO_DCE11 = audio_dce110.o hw_ctx_audio_dce110.o
+
+AMD_DAL_AUDIO_DCE11 = $(addprefix
$(AMDDALPATH)/dc/audio/dce110/,$(AUDIO_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_AUDIO_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio.h
b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
new file mode 100644
index ..ad2dc18ef37b
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DAL_AUDIO_H__
+#define __DAL_AUDIO_H__
+
+#include "include/audio_interface.h"
+#include "hw_ctx_audio.h"
+#include "include/link_service_types.h"
+
+/* only for hook functions */
+/**
+ *which will be overwritten by derived audio object.
+ *audio hw context object is independent object
+ */
+
+struct audio;
+
+struct audio_funcs {
+ /*
+*get_object_id
+*get_object_type
+*enumerate_input_signals
+*enumerate_output_signals
+*is_input_signal_supported
+*is_output_signal_supported
+*set_object_properties
+*get_object_properties
+*/
+
+ void (*destroy)(struct audio **audio);
+ /*power_up
+*power_down
+*release_hw_base
+*/
+
+ /* setup audio */
+ enum audio_result (*setup)(
+ struct audio *audio,
+ struct audio_output *output,
+ struct audio_info *info);
+
+ enum audio_result (*enable_output)(
+ struct audio *audio,
+ enum engine_id engine_id,
+ enum signal_type signal);
+
+ enum audio_result (*disable_output)(
+ struct audio *audio,
+ enum engine_id engine_id,
[PATCH v2 10/26] drm/amd/dal: GPU
Encapsulates programming for HW blocks which are shared between display
paths, such as clock sources.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/gpu/Makefile| 22 +
.../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c| 92 ++
.../gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h| 63 ++
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c | 90 ++
.../amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h | 33 +
.../amd/dal/dc/gpu/dce110/display_clock_dce110.c | 968 +
.../amd/dal/dc/gpu/dce110/display_clock_dce110.h | 53 ++
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c | 205 +
drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h | 82 ++
drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c | 127 +++
drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h | 63 ++
11 files changed, 1798 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/gpu/dce110/dc_clock_gating_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/display_clock.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/gpu/divider_range.h
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
new file mode 100644
index ..b481a6d5c6bb
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/Makefile
@@ -0,0 +1,22 @@
+#
+# Makefile for the 'gpu' sub-component of DAL.
+# It provides the control and status of HW adapter resources,
+# that are global for the ASIC and sharable between pipes.
+
+GPU = dc_clock_generator.o display_clock.o divider_range.o
+
+AMD_DAL_GPU = $(addprefix $(AMDDALPATH)/dc/gpu/,$(GPU))
+
+AMD_DAL_FILES += $(AMD_DAL_GPU)
+
+
+###
+# DCE 110 family
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+GPU_DCE110 = display_clock_dce110.o dc_clock_gating_dce110.o
+
+AMD_DAL_GPU_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpu/dce110/,$(GPU_DCE110))
+
+AMD_DAL_FILES += $(AMD_DAL_GPU_DCE110)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
new file mode 100644
index ..b3b0f99933f7
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dc_clock_generator.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "dc_clock_generator.h"
+
+void dal_dc_clock_generator_destroy(struct dc_clock_generator **dc)
+{
+ if (dc == NULL || *dc == NULL) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ (*dc)->funcs->destroy(dc);
+
+ *dc = NULL;
+}
+
+void dal_dc_clock_generator_set_display_pipe_mapping(
+ struct dc_clock_generator *dc_clk_gen,
+ struct dccg_mapping_params *params)
+{
+ dc_clk_gen->funcs->set_display_pipe_mapping(dc_clk_gen, params);
+}
+
+bool dal_dc_clock_generator_get_dp_ref_clk_ds_params(
+ struct dc_clock_generator *dc_clk_gen,
+ struct dccg_dp_ref_clk_ds_params *params)
+{
+ return dc_clk_gen->funcs->get_dp_ref_clk_ds_params(dc_clk_gen, params);
+}
+
+bool dal_dc_clock_generator_enable_gtc_counter(
+ struct dc_clock_generator *dc_clk_gen,
+ uint3
[PATCH v2 09/26] drm/amd/dal: IRQ Service
Interface to set and ack DCE interrupts.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/irq/Makefile| 21 ++
.../drm/amd/dal/dc/irq/dce110/irq_service_dce110.c | 389 +
.../drm/amd/dal/dc/irq/dce110/irq_service_dce110.h | 34 ++
drivers/gpu/drm/amd/dal/dc/irq/irq_service.c | 177 ++
drivers/gpu/drm/amd/dal/dc/irq/irq_service.h | 85 +
5 files changed, 706 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.h
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/irq/irq_service.h
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/Makefile
b/drivers/gpu/drm/amd/dal/dc/irq/Makefile
new file mode 100644
index ..f1c5faf94b83
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/irq/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile for the 'audio' sub-component of DAL.
+# It provides the control and status of HW adapter resources,
+# that are global for the ASIC and sharable between pipes.
+
+IRQ = irq_service.o
+
+AMD_DAL_IRQ = $(addprefix $(AMDDALPATH)/dc/irq/,$(IRQ))
+
+AMD_DAL_FILES += $(AMD_DAL_IRQ)
+
+###
+# DCE 11x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+IRQ_DCE11 = irq_service_dce110.o
+
+AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_IRQ_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
new file mode 100644
index ..4085b6f6e7fd
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/irq/dce110/irq_service_dce110.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "irq_service_dce110.h"
+
+#include "dce/dce_11_0_d.h"
+#include "dce/dce_11_0_sh_mask.h"
+#include "ivsrcid/ivsrcid_vislands30.h"
+
+static bool hpd_ack(
+ struct irq_service *irq_service,
+ const struct irq_source_info *info)
+{
+ uint32_t addr = info->status_reg;
+ uint32_t value = dm_read_reg(irq_service->ctx, addr);
+ uint32_t current_status =
+ get_reg_field_value(
+ value,
+ DC_HPD_INT_STATUS,
+ DC_HPD_SENSE_DELAYED);
+
+ dal_irq_service_ack_generic(irq_service, info);
+
+ value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+ set_reg_field_value(
+ value,
+ current_status ? 0 : 1,
+ DC_HPD_INT_CONTROL,
+ DC_HPD_INT_POLARITY);
+
+ dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+ return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+ .set = NULL,
+ .ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+ .set = NULL,
+ .ack = NULL
+};
+
+#define hpd_int_entry(reg_num)\
+ [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+ .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
+ .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
+ .enable_value = {\
+ DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
+ ~DC
[PATCH v2 08/26] drm/amd/dal: I2C Aux Manager
Implements low-level communication layer over I2C and Aux lines using GPIO handles. Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/i2caux/Makefile | 33 + drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c | 567 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h | 119 +++ .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.c | 788 + .../amd/dal/dc/i2caux/dce110/aux_engine_dce110.h | 56 ++ .../i2caux/dce110/i2c_generic_hw_engine_dce110.h | 25 + .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c| 954 + .../dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h| 58 ++ .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c| 172 .../dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h| 43 + .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c | 266 ++ .../drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h | 39 + .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.c| 112 +++ .../amd/dal/dc/i2caux/diagnostics/i2caux_diag.h| 33 + drivers/gpu/drm/amd/dal/dc/i2caux/engine.h | 129 +++ drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c| 67 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c | 121 +++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h | 113 +++ .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c | 286 ++ .../drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h | 77 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c | 246 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h | 80 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c | 614 + drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h | 81 ++ drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c | 529 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h | 123 +++ 26 files changed, 5731 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/aux_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_generic_hw_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_hw_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2c_sw_engine_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/dce110/i2caux_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/diagnostics/i2caux_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/engine_base.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_generic_hw_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_hw_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2c_sw_engine.h create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.c create mode 100644 drivers/gpu/drm/amd/dal/dc/i2caux/i2caux.h diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile new file mode 100644 index ..390d83d649f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/i2caux/Makefile @@ -0,0 +1,33 @@ +# +# Makefile for the 'i2c' sub-component of DAL. +# It provides the control and status of HW i2c engine of the adapter. + +I2CAUX = aux_engine.o engine_base.o i2caux.o i2c_engine.o \ +i2c_generic_hw_engine.o i2c_hw_engine.o i2c_sw_engine.o + +AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX)) + +AMD_DAL_FILES += $(AMD_DAL_I2CAUX) + + +### +# DCE 11x family +### +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 +I2CAUX_DCE110 = i2caux_dce110.o i2c_sw_engine_dce110.o i2c_hw_engine_dce110.o \ + aux_engine_dce110.o + +AMD_DAL_I2CAUX_DCE110 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce110/,$(I2CAUX_DCE110)) + +AMD_DAL_FILES += $(AMD_DAL_I2CAUX_DCE110) +endif + +### +# Diagnostics on FPGA +##
[PATCH v2 07/26] drm/amd/dal: BIOS Parser
Wrapper to access Video BIOS command and data tables Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/bios/Makefile | 26 + drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c | 5029 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h | 84 + .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.c | 198 + .../gpu/drm/amd/dal/dc/bios/bios_parser_helper.h | 108 + drivers/gpu/drm/amd/dal/dc/bios/command_table.c| 2730 +++ drivers/gpu/drm/amd/dal/dc/bios/command_table.h| 117 + .../gpu/drm/amd/dal/dc/bios/command_table_helper.c | 285 ++ .../gpu/drm/amd/dal/dc/bios/command_table_helper.h | 90 + .../dal/dc/bios/dce110/bios_parser_helper_dce110.c | 484 ++ .../dal/dc/bios/dce110/bios_parser_helper_dce110.h | 34 + .../dc/bios/dce110/command_table_helper_dce110.c | 366 ++ .../dc/bios/dce110/command_table_helper_dce110.h | 34 + 13 files changed, 9585 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/bios_parser_helper.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/command_table_helper.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/bios_parser_helper_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/bios/dce110/command_table_helper_dce110.h diff --git a/drivers/gpu/drm/amd/dal/dc/bios/Makefile b/drivers/gpu/drm/amd/dal/dc/bios/Makefile new file mode 100644 index ..ddfe457e3a8b --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/bios/Makefile @@ -0,0 +1,26 @@ +# +# Makefile for the 'bios' sub-component of DAL. +# It provides the parsing and executing controls for atom bios image. + +BIOS = bios_parser.o bios_parser_helper.o command_table.o command_table_helper.o + +AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) + +AMD_DAL_FILES += $(AMD_DAL_BIOS) + +ifndef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT +AMD_DAL_FILES := $(filter-out $(AMDDALPATH)/dc/bios/bios_parser_helper.o,$(AMD_DAL_FILES)) +endif + + +### +# DCE 11x +### +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 + +ifdef CONFIG_DRM_AMD_DAL_VBIOS_PRESENT +AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/bios_parser_helper_dce110.o +endif + +AMD_DAL_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o +endif diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c new file mode 100644 index ..4ce5f9fcf907 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c @@ -0,0 +1,5029 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "atom.h" + +#include "dc_bios_types.h" +#include "include/adapter_service_interface.h" +#include "include/grph_object_ctrl_defs.h" +#include "include/bios_parser_interface.h" +#include "include/i2caux_interface.h" +#include "include/logger_interface.h" + +#include "command_table.h" +#if defined(CONFIG_DRM_AMD_DAL_VBIOS_PRESENT) +#include "bios_parser_helper.h" +#endif +#include "command_table_helper.h" +#include "bios_parser.h" +#include "bios_parser_interface.h"
[PATCH v2 06/26] drm/amd/dal: Adapter Service
Provides information about ASIC features and capabilities. Also provides access to ASIC resources such as VBIOS, GPIO and I2cAux Manager Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/adapter/Makefile| 24 + .../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 2089 .../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 71 + .../adapter/dce110/hw_ctx_adapter_service_dce110.c | 304 +++ .../adapter/dce110/hw_ctx_adapter_service_dce110.h | 40 + .../diagnostics/hw_ctx_adapter_service_diag.c | 133 ++ .../diagnostics/hw_ctx_adapter_service_diag.h | 33 + .../amd/dal/dc/adapter/hw_ctx_adapter_service.c| 164 ++ .../amd/dal/dc/adapter/hw_ctx_adapter_service.h| 86 + .../drm/amd/dal/dc/adapter/wireless_data_source.c | 208 ++ .../drm/amd/dal/dc/adapter/wireless_data_source.h | 80 + 11 files changed, 3232 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/dce110/hw_ctx_adapter_service_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/hw_ctx_adapter_service.h create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.c create mode 100644 drivers/gpu/drm/amd/dal/dc/adapter/wireless_data_source.h diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/Makefile b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile new file mode 100644 index ..2c6ca7a513bd --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/adapter/Makefile @@ -0,0 +1,24 @@ +# +# Makefile for the 'adapter' sub-component of DAL. +# It provides the control and status of HW adapter. + +ADAPTER = adapter_service.o hw_ctx_adapter_service.o wireless_data_source.o + +AMD_DAL_ADAPTER = $(addprefix $(AMDDALPATH)/dc/adapter/,$(ADAPTER)) + +AMD_DAL_FILES += $(AMD_DAL_ADAPTER) + + +### +# DCE 11x +### + +ifdef CONFIG_DRM_AMD_DAL_DCE11_0 +AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/dce110/hw_ctx_adapter_service_dce110.o +endif + +### +# FPGA Diagnositcs +### + +AMD_DAL_FILES += $(AMDDALPATH)/dc/adapter/diagnostics/hw_ctx_adapter_service_diag.o diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c new file mode 100644 index ..dd2f931fe9a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c @@ -0,0 +1,2089 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" + +#include "dc_bios_types.h" + +#include "include/adapter_service_interface.h" +#include "include/i2caux_interface.h" +#include "include/asic_capability_types.h" +#include "include/gpio_service_interface.h" +#include "include/asic_capability_interface.h" +#include "include/logger_interface.h" + +#include "adapter_service.h" + +#include "hw_ctx_adapter_service.h" +#include "wireless_data_source.h" + +#include "atom.h" + +#if defined(CONFIG_DRM_AMD_DAL_DCE11_0) +#include "dce110/hw_ctx_adapter_service_dce110.h" +#endif + +#include "diagnostics/hw_ctx_adapter
[PATCH v2 05/26] drm/amd/dal: GPIO (General Purpose IO)
Manages all DCE GPIO pins. The pins are represented as generic IO handles as well as handles dedicated for certain functions, such as DDC, HPD, and DVO. Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dc/gpio/Makefile | 32 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c | 882 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h | 46 ++ .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c | 81 ++ .../drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h | 32 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c | 366 + .../gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h | 47 ++ .../amd/dal/dc/gpio/dce110/hw_translate_dce110.c | 400 ++ .../amd/dal/dc/gpio/dce110/hw_translate_dce110.h | 34 + drivers/gpu/drm/amd/dal/dc/gpio/ddc.c | 290 +++ drivers/gpu/drm/amd/dal/dc/gpio/ddc.h | 45 ++ .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c | 97 +++ .../drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h | 34 + .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.c | 65 ++ .../amd/dal/dc/gpio/diagnostics/hw_factory_diag.h | 32 + .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c | 101 +++ .../drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h | 35 + .../dal/dc/gpio/diagnostics/hw_translate_diag.c| 41 + .../dal/dc/gpio/diagnostics/hw_translate_diag.h| 34 + drivers/gpu/drm/amd/dal/dc/gpio/gpio.h | 48 ++ drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c| 279 +++ drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c | 386 + drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h | 57 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c | 104 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h | 60 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c | 93 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h | 71 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c | 407 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h | 129 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c | 92 +++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h | 47 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c | 85 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.h | 79 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.c | 87 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_hpd.h | 45 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.c | 77 ++ drivers/gpu/drm/amd/dal/dc/gpio/hw_translate.h | 50 ++ drivers/gpu/drm/amd/dal/dc/gpio/irq.c | 180 + drivers/gpu/drm/amd/dal/dc/gpio/irq.h | 42 + 39 files changed, 5112 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_ddc_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_factory_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_hpd_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/dce110/hw_translate_dce110.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/ddc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_ddc_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_factory_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_hpd_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/diagnostics/hw_translate_diag.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_base.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/gpio_service.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_ddc.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_factory.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.c create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pad.h create mode 100644 drivers/gpu/drm/amd/dal/dc/gpio/hw_gpio_pin.c create mode 100644 drivers/gpu
[PATCH v2 04/26] drm/amd/dal: Asic Capabilities
Add a generic way to manage display HW capabilities
for different ASICs and implement it for Carrizo.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
.../gpu/drm/amd/dal/dc/asic_capability/Makefile| 35
.../amd/dal/dc/asic_capability/asic_capability.c | 190 +
.../dc/asic_capability/carrizo_asic_capability.c | 147
.../dc/asic_capability/carrizo_asic_capability.h | 36
.../dal/dc/asic_capability/tonga_asic_capability.c | 146
.../dal/dc/asic_capability/tonga_asic_capability.h | 36
6 files changed, 590 insertions(+)
create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
create mode 100644 drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.h
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
create mode 100644
drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.h
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
new file mode 100644
index ..8491b38ae726
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/Makefile
@@ -0,0 +1,35 @@
+#
+# Makefile for the 'asic_capability' sub-component of DAL.
+#
+
+ASIC_CAPABILITY = asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY)
+
+###
+# DCE 10x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE10_0
+ASIC_CAPABILITY_DCE10 = tonga_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE10 = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE10))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE10)
+endif
+
+
+###
+# DCE 11x
+###
+ifdef CONFIG_DRM_AMD_DAL_DCE11_0
+ASIC_CAPABILITY_DCE11 = carrizo_asic_capability.o
+
+AMD_DAL_ASIC_CAPABILITY_DCE11 = \
+ $(addprefix $(AMDDALPATH)/dc/asic_capability/,$(ASIC_CAPABILITY_DCE11))
+
+AMD_DAL_FILES += $(AMD_DAL_ASIC_CAPABILITY_DCE11)
+endif
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
new file mode 100644
index ..7a905f532040
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "include/asic_capability_interface.h"
+#include "include/asic_capability_types.h"
+#include "include/dal_types.h"
+#include "include/dal_asic_id.h"
+
+#if defined(CONFIG_DRM_AMD_DAL_DCE10_0)
+#include "tonga_asic_capability.h"
+#endif
+
+#if defined(CONFIG_DRM_AMD_DAL_DCE11_0)
+#include "carrizo_asic_capability.h"
+#endif
+
+/*
+ * Initializes asic_capability instance.
+ */
+static bool construct(
+ struct asic_capability *cap,
+ struct hw_asic_id *init,
+ struct dc_context *ctx)
+{
+ bool asic_supported = false;
+
+ cap->ctx = ctx;
+ dm_memset(cap->data, 0, sizeof(cap->data));
+
+ /* ASIC data */
+ cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
+ cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
+ cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
+ cap->runtime_flags = init->runtime_flags;
+ cap->data[ASIC_DATA_REVISION
[PATCH v2 03/26] drm/amd/dal: Fixed point arithmetic
Arithmetic operations on real numbers represented
as fixed-point numbers.
Signed-off-by: Harry Wentland
Reviewed-by: Alex Deucher
---
drivers/gpu/drm/amd/dal/dc/basics/Makefile | 2 +-
drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c | 692 +
drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c | 223
3 files changed, 916 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/fixpt32_32.c
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile
b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
index 6f382812fae3..93e23714e411 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile
@@ -3,7 +3,7 @@
# It provides the general basic services required by other DAL
# subcomponents.
-BASICS = conversion.o grph_object_id.o logger.o register_logger.o
signal_types.o vector.o
+BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o logger.o
register_logger.o signal_types.o vector.o
AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
new file mode 100644
index ..9f93b3b20634
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/basics/fixpt31_32.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/fixed31_32.h"
+
+static inline uint64_t abs_i64(
+ int64_t arg)
+{
+ if (arg > 0)
+ return (uint64_t)arg;
+ else
+ return (uint64_t)(-arg);
+}
+
+/*
+ * @brief
+ * result = dividend / divisor
+ * *remainder = dividend % divisor
+ */
+static inline uint64_t complete_integer_division_u64(
+ uint64_t dividend,
+ uint64_t divisor,
+ uint64_t *remainder)
+{
+ uint64_t result;
+
+ ASSERT(divisor);
+
+ result = div64_u64_rem(dividend, divisor, remainder);
+
+ return result;
+}
+
+#define BITS_PER_FRACTIONAL_PART \
+ 32
+
+#define FRACTIONAL_PART_MASK \
+ ((1ULL << BITS_PER_FRACTIONAL_PART) - 1)
+
+#define GET_INTEGER_PART(x) \
+ ((x) >> BITS_PER_FRACTIONAL_PART)
+
+#define GET_FRACTIONAL_PART(x) \
+ (FRACTIONAL_PART_MASK & (x))
+
+struct fixed31_32 dal_fixed31_32_from_fraction(
+ int64_t numerator,
+ int64_t denominator)
+{
+ struct fixed31_32 res;
+
+ bool arg1_negative = numerator < 0;
+ bool arg2_negative = denominator < 0;
+
+ uint64_t arg1_value = arg1_negative ? -numerator : numerator;
+ uint64_t arg2_value = arg2_negative ? -denominator : denominator;
+
+ uint64_t remainder;
+
+ /* determine integer part */
+
+ uint64_t res_value = complete_integer_division_u64(
+ arg1_value, arg2_value, &remainder);
+
+ ASSERT(res_value <= LONG_MAX);
+
+ /* determine fractional part */
+ {
+ uint32_t i = BITS_PER_FRACTIONAL_PART;
+
+ do {
+ remainder <<= 1;
+
+ res_value <<= 1;
+
+ if (remainder >= arg2_value) {
+ res_value |= 1;
+ remainder -= arg2_value;
+ }
+ } while (--i != 0);
+ }
+
+ /* round up LSB */
+ {
+ uint64_t summand = (remainder << 1) >= arg2_value;
+
+ ASSERT(res_value <= LLONG_MAX - summand);
+
+ res_value += summand;
+ }
+
+ res.value = (int64_t)res_value;
+
+ if (arg1_negative ^ arg2_negative)
+ res.value = -res.value;
+
+ return res;
+}
+
+struct fixed31_32 dal_fixed31_32_from_int(
+ int64_t arg)
+{
+ struct fixed31_32 res;
+
+ ASSERT
[PATCH v2 02/26] drm/amd/dal: Add DAL Basic Types and Logger
Laying the groundwork for the AMD DAL display driver. This patch includes the basic services and defines basic types required by the display driver, such as: - ASIC register access - VBIOS access - Vector and flat_set data structures - Display signal types - ASIC versions and IDs - HW IDs - Logging functionality This patch adds Kconfig options to enable the DAL display driver. - DRM_AMD_DAL - DRM_AMD_DAL_VBIOS_PRESENT - DRM_AMD_DAL_DCE11_0 - DRM_AMD_DAL_DCE10_0 - DEBUG_KERNEL_DAL Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/Kconfig| 48 ++ drivers/gpu/drm/amd/dal/Makefile | 21 + drivers/gpu/drm/amd/dal/dc/basics/Makefile | 10 + drivers/gpu/drm/amd/dal/dc/basics/conversion.c | 224 + drivers/gpu/drm/amd/dal/dc/basics/conversion.h | 49 ++ drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c | 134 +++ drivers/gpu/drm/amd/dal/dc/basics/logger.c | 954 + drivers/gpu/drm/amd/dal/dc/basics/logger.h | 64 ++ .../gpu/drm/amd/dal/dc/basics/register_logger.c| 197 + drivers/gpu/drm/amd/dal/dc/basics/signal_types.c | 116 +++ drivers/gpu/drm/amd/dal/dc/basics/vector.c | 309 +++ 11 files changed, 2126 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/Kconfig create mode 100644 drivers/gpu/drm/amd/dal/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/Makefile create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/conversion.h create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/grph_object_id.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/logger.h create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/register_logger.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/signal_types.c create mode 100644 drivers/gpu/drm/amd/dal/dc/basics/vector.c diff --git a/drivers/gpu/drm/amd/dal/Kconfig b/drivers/gpu/drm/amd/dal/Kconfig new file mode 100644 index ..2289c0b10dae --- /dev/null +++ b/drivers/gpu/drm/amd/dal/Kconfig @@ -0,0 +1,48 @@ +menu "Display Engine Configuration" + depends on DRM && (DRM_AMDSOC || DRM_AMDGPU) + +config DRM_AMD_DAL +bool "AMD DAL - Enable new display engine +help + Choose this option if you want to use the new display engine + support for AMD SOC. + + Will be deprecated when the DAL component becomes stable and + AMDSOC will fully switch to it. + +config DRM_AMD_DAL_VBIOS_PRESENT +bool "Video Bios available on board" +depends on DRM_AMD_DAL +help + This option is needed to allow a full range of feature +support when working on +x86 platforms and there is a VBIOS +present in the system + +config DRM_AMD_DAL_DCE11_0 +bool "Carrizo family" +depends on DRM_AMD_DAL +help + Choose this option +if you want to have +CZ family +for display engine + +config DRM_AMD_DAL_DCE10_0 +bool "VI family" +depends on DRM_AMD_DAL +help + Choose this option +if you want to have +VI family for display +engine. + +config DEBUG_KERNEL_DAL +bool "Enable kgdb break in DAL" +depends on DRM_AMD_DAL +help + Choose this option + if you want to hit + kdgb_break in assert. + +endmenu diff --git a/drivers/gpu/drm/amd/dal/Makefile b/drivers/gpu/drm/amd/dal/Makefile new file mode 100644 index ..25ae4646c4d3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/Makefile @@ -0,0 +1,21 @@ +# +# Makefile for the DAL (Display Abstract Layer), which is a sub-component +# of the AMDGPU drm driver. +# It provides the HW control for display related functionalities. + +AMDDALPATH = $(RELATIVE_AMD_DAL_PATH) + +subdir-ccflags-y += -Werror + +subdir-ccflags-y += -I$(AMDDALPATH)/ -I$(AMDDALPATH)/include + +subdir-ccflags-y += -I$(FULL_AMD_DAL_PATH)/dc/inc/ + +#TODO: remove when Timing Sync feature is complete +subdir-ccflags-y += -DBUILD_FEATURE_TIMING_SYNC=0 + +DAL_LIBS = amdgpu_dm dc + +AMD_DAL = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DAL_PATH)/,$(DAL_LIBS))) + +include $(AMD_DAL) diff --git a/drivers/gpu/drm/amd/dal/dc/basics/Makefile b/drivers/gpu/drm/amd/dal/dc/basics/Makefile new file mode 100644 index ..6f382812fae3 --- /dev/null +++ b/drivers/gpu/drm/amd/dal/dc/basics/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the 'utils' sub-component of DAL. +# It provides the general basic services required by other DAL +# subcomponents. + +BASICS = conversion.o grph_object_id.o logger.o register_logger.o signal_types.o vector.o + +AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS)) + +AMD_DAL_FILES += $(AMD_DAL_BASICS) diff --git a/drivers/gpu/drm/amd/dal/dc/basics/conversion.c b/drivers/gpu/drm/amd/dal/dc/b
[PATCH v2 01/26] drm/amd/dal: Add dal headers
Signed-off-by: Harry Wentland Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/dal/dal_services.h | 266 ++ drivers/gpu/drm/amd/dal/dal_services_types.h | 62 ++ drivers/gpu/drm/amd/dal/dc/dc.h| 462 ++ drivers/gpu/drm/amd/dal/dc/dc_bios_types.h | 277 ++ drivers/gpu/drm/amd/dal/dc/dc_types.h | 936 + drivers/gpu/drm/amd/dal/dc/dm_helpers.h| 98 +++ drivers/gpu/drm/amd/dal/dc/dm_services.h | 485 +++ drivers/gpu/drm/amd/dal/dc/dm_services_types.h | 167 drivers/gpu/drm/amd/dal/dc/inc/bandwidth_calcs.h | 510 +++ drivers/gpu/drm/amd/dal/dc/inc/bw_fixed.h | 64 ++ drivers/gpu/drm/amd/dal/dc/inc/clock_source.h | 176 drivers/gpu/drm/amd/dal/dc/inc/compressor.h| 140 +++ drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 54 ++ drivers/gpu/drm/amd/dal/dc/inc/core_status.h | 46 + drivers/gpu/drm/amd/dal/dc/inc/core_types.h| 357 drivers/gpu/drm/amd/dal/dc/inc/dc_link_ddc.h | 151 drivers/gpu/drm/amd/dal/dc/inc/dc_link_dp.h| 56 ++ drivers/gpu/drm/amd/dal/dc/inc/gamma_types.h | 118 +++ drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h | 126 +++ drivers/gpu/drm/amd/dal/dc/inc/ipp.h | 106 +++ drivers/gpu/drm/amd/dal/dc/inc/link_encoder.h | 138 +++ drivers/gpu/drm/amd/dal/dc/inc/link_hwss.h | 68 ++ drivers/gpu/drm/amd/dal/dc/inc/mem_input.h | 83 ++ drivers/gpu/drm/amd/dal/dc/inc/opp.h | 308 +++ drivers/gpu/drm/amd/dal/dc/inc/resource.h | 80 ++ drivers/gpu/drm/amd/dal/dc/inc/stream_encoder.h| 88 ++ drivers/gpu/drm/amd/dal/dc/inc/timing_generator.h | 155 drivers/gpu/drm/amd/dal/dc/inc/transform.h | 217 + drivers/gpu/drm/amd/dal/dc/irq_types.h | 199 + .../amd/dal/include/adapter_service_interface.h| 632 ++ .../drm/amd/dal/include/adapter_service_types.h| 71 ++ .../amd/dal/include/asic_capability_interface.h| 58 ++ .../drm/amd/dal/include/asic_capability_types.h| 134 +++ drivers/gpu/drm/amd/dal/include/audio_interface.h | 184 drivers/gpu/drm/amd/dal/include/audio_types.h | 277 ++ .../drm/amd/dal/include/bios_parser_interface.h| 98 +++ .../gpu/drm/amd/dal/include/bios_parser_types.h| 327 +++ drivers/gpu/drm/amd/dal/include/dal_asic_id.h | 117 +++ .../gpu/drm/amd/dal/include/dal_register_logger.h | 43 + drivers/gpu/drm/amd/dal/include/dal_types.h| 305 +++ .../amd/dal/include/dc_clock_generator_interface.h | 77 ++ drivers/gpu/drm/amd/dal/include/dcs_types.h| 742 drivers/gpu/drm/amd/dal/include/ddc_interface.h| 74 ++ .../gpu/drm/amd/dal/include/ddc_service_types.h| 221 + .../drm/amd/dal/include/display_clock_interface.h | 186 .../drm/amd/dal/include/display_path_interface.h | 436 ++ drivers/gpu/drm/amd/dal/include/dmcu_interface.h | 87 ++ drivers/gpu/drm/amd/dal/include/dmcu_types.h | 199 + drivers/gpu/drm/amd/dal/include/dpcd_defs.h| 873 +++ .../gpu/drm/amd/dal/include/encoder_interface.h| 278 ++ drivers/gpu/drm/amd/dal/include/fixed31_32.h | 389 + drivers/gpu/drm/amd/dal/include/fixed32_32.h | 82 ++ drivers/gpu/drm/amd/dal/include/gpio_interface.h | 93 ++ .../drm/amd/dal/include/gpio_service_interface.h | 81 ++ drivers/gpu/drm/amd/dal/include/gpio_types.h | 341 drivers/gpu/drm/amd/dal/include/grph_csc_types.h | 98 +++ .../drm/amd/dal/include/grph_object_ctrl_defs.h| 593 + drivers/gpu/drm/amd/dal/include/grph_object_defs.h | 328 drivers/gpu/drm/amd/dal/include/grph_object_id.h | 277 ++ .../drm/amd/dal/include/hw_sequencer_interface.h | 388 + .../gpu/drm/amd/dal/include/hw_sequencer_types.h | 304 +++ drivers/gpu/drm/amd/dal/include/i2caux_interface.h | 127 +++ drivers/gpu/drm/amd/dal/include/irq_interface.h| 53 ++ .../drm/amd/dal/include/irq_service_interface.h| 55 ++ .../drm/amd/dal/include/link_service_interface.h | 202 + .../gpu/drm/amd/dal/include/link_service_types.h | 427 ++ drivers/gpu/drm/amd/dal/include/logger_interface.h | 153 drivers/gpu/drm/amd/dal/include/logger_types.h | 356 drivers/gpu/drm/amd/dal/include/scaler_types.h | 196 + drivers/gpu/drm/amd/dal/include/set_mode_types.h | 142 drivers/gpu/drm/amd/dal/include/signal_types.h | 59 ++ drivers/gpu/drm/amd/dal/include/vector.h | 150 drivers/gpu/drm/amd/dal/include/video_csc_types.h | 135 +++ .../gpu/drm/amd/dal/include/video_gamma_types.h| 57 ++ 74 files changed, 16498 insertions(+) create mode 100644 drivers/gpu/drm/amd/dal/dal_services.h create mode 100644 drivers/gpu/drm/amd/dal/dal_services_types.h create mode 100644 d
[PATCH v2 00/26] Enabling new DAL display driver for amdgpu on Carrizo and Tonga
v2 Update: This is just a squash of the three small fixes into the main patches to make for an easier read. No other changes yet. This set of patches enables the new DAL display driver for amdgpu on Carrizo Tonga, and Fiji ASICs. This driver will allow us going forward to bring display features on the open amdgpu driver (mostly) on par with the Catalyst driver. This driver adds support for - Atomic KMS API - MST - HDMI 2.0 - Better powerplay integration - Support of HW bandwidth formula on Carrizo - Better multi-display support and handling of co-functionality - Broader support of display dongles - Timing synchronization between DP and HDMI This patch series is based on Alex Deucher's drm-next-4.6-wip tree. Harry Wentland (26): drm/amd/dal: Add dal headers drm/amd/dal: Add DAL Basic Types and Logger drm/amd/dal: Fixed point arithmetic drm/amd/dal: Asic Capabilities drm/amd/dal: GPIO (General Purpose IO) drm/amd/dal: Adapter Service drm/amd/dal: BIOS Parser drm/amd/dal: I2C Aux Manager drm/amd/dal: IRQ Service drm/amd/dal: GPU drm/amd/dal: Audio drm/amd/dal: Bandwidth calculations drm/amd/dal: Add encoder HW programming drm/amd/dal: Add clock source HW programming drm/amd/dal: Add timing generator HW programming drm/amd/dal: Add surface HW programming drm/amd/dal: Add framebuffer compression HW programming drm/amd/dal: Add input pixel processing HW programming drm/amd/dal: Add output pixel processing HW programming drm/amd/dal: Add transform & scaler HW programming drm/amd/dal: Add Carrizo HW sequencer and resource drm/amd/dal: Add Tonga/Fiji HW sequencer and resource drm/amd/dal: Add empty encoder programming for virtual HW drm/amd/dal: Add display core drm/amd/dal: Adding amdgpu_dm for dal drm/amdgpu: Use dal driver for Carrizo, Tonga, and Fiji drivers/gpu/drm/amd/amdgpu/Kconfig |3 + drivers/gpu/drm/amd/amdgpu/Makefile| 17 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 69 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|4 + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c |5 - drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c| 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 54 +- drivers/gpu/drm/amd/amdgpu/vi.c| 250 + drivers/gpu/drm/amd/dal/Kconfig| 48 + drivers/gpu/drm/amd/dal/Makefile | 21 + drivers/gpu/drm/amd/dal/amdgpu_dm/Makefile | 17 + drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.c | 1468 ++ drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm.h | 168 + .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_helpers.c | 474 ++ drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.c | 820 drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_irq.h | 122 + .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.c| 480 ++ .../drm/amd/dal/amdgpu_dm/amdgpu_dm_mst_types.h| 36 + .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c | 457 ++ .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.c| 2577 ++ .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_types.h| 100 + drivers/gpu/drm/amd/dal/dal_services.h | 266 ++ drivers/gpu/drm/amd/dal/dal_services_types.h | 62 + drivers/gpu/drm/amd/dal/dc/Makefile| 28 + drivers/gpu/drm/amd/dal/dc/adapter/Makefile| 24 + .../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 2089 .../gpu/drm/amd/dal/dc/adapter/adapter_service.h | 71 + .../adapter/dce110/hw_ctx_adapter_service_dce110.c | 304 ++ .../adapter/dce110/hw_ctx_adapter_service_dce110.h | 40 + .../diagnostics/hw_ctx_adapter_service_diag.c | 133 + .../diagnostics/hw_ctx_adapter_service_diag.h | 33 + .../amd/dal/dc/adapter/hw_ctx_adapter_service.c| 164 + .../amd/dal/dc/adapter/hw_ctx_adapter_service.h| 86 + .../drm/amd/dal/dc/adapter/wireless_data_source.c | 208 + .../drm/amd/dal/dc/adapter/wireless_data_source.h | 80 + .../gpu/drm/amd/dal/dc/asic_capability/Makefile| 35 + .../amd/dal/dc/asic_capability/asic_capability.c | 190 + .../dc/asic_capability/carrizo_asic_capability.c | 147 + .../dc/asic_capability/carrizo_asic_capability.h | 36 + .../dal/dc/asic_capability/tonga_asic_capability.c | 146 + .../dal/dc/asic_capability/tonga_asic_capability.h | 36 + drivers/gpu/drm/amd/dal/dc/audio/Makefile | 22 + drivers/gpu/drm/amd/dal/dc/audio/audio.h | 195 + drivers/gpu/drm/amd/dal/dc/audio/audio_base.c | 470 ++ .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.c | 453 ++ .../gpu/drm/amd/dal/dc/audio/dce110/audio_dce110.h | 42 + .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.c | 1930 .../amd/dal/dc/audio/dce110/hw_ctx_audio_dce110.h | 47 + drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.c| 771 +++ drivers/gpu/drm/amd/dal/dc/audio/hw_ctx_audio.h| 285 ++ drive
[PATCH v5 10/12] drm/i915: Defer probe if gmux is present but its driver isn't
On Tue, Feb 16, 2016 at 04:58:20PM +0100, Lukas Wunner wrote: > Hi, > > On Sun, Feb 14, 2016 at 01:46:28PM +0100, Daniel Vetter wrote: > > On Sun, Feb 14, 2016 at 1:10 PM, Lukas Wunner wrote: > > > /** > > > + * vga_switcheroo_client_probe_defer() - whether to defer probing a > > > given GPU > > > + * @pdev: pci device of GPU > > > + * > > > + * Determine whether any prerequisites are not fulfilled to probe a > > > given GPU. > > > > I'd phrase this as "Determine whether the vgaswitcheroor support is > > fully loaded" and drop the GPU part - it could be needed by snd > > drivers eventually too. > > Ok, I've rephrased the kerneldoc to refer to "client" instead of "GPU" > and moved the single existing check in an if block for > PCI_CLASS_DISPLAY_VGA devices. > > > > > + * DRM drivers should invoke this early on in their ->probe callback and > > > return > > > + * %-EPROBE_DEFER if it evaluates to %true. The GPU need not be > > > registered with > > > + * vga_switcheroo_register_client() beforehand. > > > > s/need not/must not/ ... is your native language German by any chance? > > In principle there's no harm in registering the client first, > then checking if probing should be deferred, as long as the > client is unregistered before deferring. Thus the language > above is intentionally "need not" (muss nicht) rather than > "must not" (darf nicht). I didn't want to mandate something > that isn't actually required. The above sentence is merely > an aid for driver developers who might be confused in which > order to call what. I'd reject any driver that does this, registering, then checking, then unregistering seems extermely unsafe. I'd really stick with mandatory language here to make this clear. > > Aside from that ... should vga_switcheroo_register_client call this > > helper instead directly and return the appropriate -EDEFER_PROBE > > error? I realize for some drivers it might be way too late to unrol > > from that point on, but e.g. i915 already uses -EDEFER_PROBE. And > > calling it unconditionally will make sure that it's easier to notice > > when people forget this. So maybe call it both from the register > > functions, and export as a separate hook? And for i915 we should be > > able to remove that early check entirely. > > I'm afraid that wouldn't be a good idea. The ->probe hook is > potentially called dozens of times during boot until it finally > succeeds and vga_switcheroo_register_client() is usually called > in a fairly late driver load stage. In i915, we already have a > working GEM at that point and an almost fully brought up GPU. > Repeating bring up and tear down dozens of times is a nice > stress test but nothing I'd inflict on production systems. > I imagine it would also severely impact boot time and > clutter the kernel log. > > So a separate helper seems to be the only sensible option. Ok, makes sense. I still think adding the check to the client_register function would be good, just as a safety measure. And I don't think you're case of register(), check(), unregister() in case of failure is a valid use-case. Let's not allow anyone to open-code that horror ;-) Cheers, Daniel > > > + * > > > + * Return: %false unless one of the following applies: > > > + * > > > + * * On pre-retina MacBook Pros, the apple-gmux driver is needed to > > > temporarily > > > + * switch DDC to the inactive GPU so that it can probe the panel's > > > EDID. > > > + * Therefore return %true if gmux is built into the machine, @pdev is > > > the > > > + * inactive GPU and the apple-gmux driver has not registered its > > > handler > > > + * flags, signifying it has not yet loaded or has not finished > > > initializing. > > > > I think the apple-specific comment here should be a separate comment > > right above the if condition below - it doesn't explain the interface, > > only one specific case. And we might grow more of those. > > Ok, I've moved that to a comment. > > Updated patch follows after the scissors & perforation. > > Thanks for the feedback! > > Lukas > > -- >8 -- > Subject: [PATCH] vga_switcheroo: Allow clients to determine whether to defer > probing > > So far we've got one condition when DRM drivers need to defer probing > on a dual GPU system and it's coded separately into each of the relevant > drivers. As suggested by Daniel Vetter, deduplicate that code in the > drivers and move it to a new vga_switcheroo helper. This yields better > encapsulation of concepts and lets us add further checks in a central > place. (The existing check pertains to pre-retina MacBook Pros and an > additional check is expected to be needed for retinas.) > > v2: This helper could eventually be used by audio clients as well, > so rephrase kerneldoc to refer to "client" instead of "GPU" > and move the single existing check in an if block specific > to PCI_CLASS_DISPLAY_VGA devices. Move documentation on > that check from kerneldoc to a comment. (Daniel Vetter) > > C
[PATCH v5 10/12] drm/i915: Defer probe if gmux is present but its driver isn't
Hi, On Sun, Feb 14, 2016 at 01:46:28PM +0100, Daniel Vetter wrote: > On Sun, Feb 14, 2016 at 1:10 PM, Lukas Wunner wrote: > > /** > > + * vga_switcheroo_client_probe_defer() - whether to defer probing a given > > GPU > > + * @pdev: pci device of GPU > > + * > > + * Determine whether any prerequisites are not fulfilled to probe a given > > GPU. > > I'd phrase this as "Determine whether the vgaswitcheroor support is > fully loaded" and drop the GPU part - it could be needed by snd > drivers eventually too. Ok, I've rephrased the kerneldoc to refer to "client" instead of "GPU" and moved the single existing check in an if block for PCI_CLASS_DISPLAY_VGA devices. > > + * DRM drivers should invoke this early on in their ->probe callback and > > return > > + * %-EPROBE_DEFER if it evaluates to %true. The GPU need not be registered > > with > > + * vga_switcheroo_register_client() beforehand. > > s/need not/must not/ ... is your native language German by any chance? In principle there's no harm in registering the client first, then checking if probing should be deferred, as long as the client is unregistered before deferring. Thus the language above is intentionally "need not" (muss nicht) rather than "must not" (darf nicht). I didn't want to mandate something that isn't actually required. The above sentence is merely an aid for driver developers who might be confused in which order to call what. > Aside from that ... should vga_switcheroo_register_client call this > helper instead directly and return the appropriate -EDEFER_PROBE > error? I realize for some drivers it might be way too late to unrol > from that point on, but e.g. i915 already uses -EDEFER_PROBE. And > calling it unconditionally will make sure that it's easier to notice > when people forget this. So maybe call it both from the register > functions, and export as a separate hook? And for i915 we should be > able to remove that early check entirely. I'm afraid that wouldn't be a good idea. The ->probe hook is potentially called dozens of times during boot until it finally succeeds and vga_switcheroo_register_client() is usually called in a fairly late driver load stage. In i915, we already have a working GEM at that point and an almost fully brought up GPU. Repeating bring up and tear down dozens of times is a nice stress test but nothing I'd inflict on production systems. I imagine it would also severely impact boot time and clutter the kernel log. So a separate helper seems to be the only sensible option. > > + * > > + * Return: %false unless one of the following applies: > > + * > > + * * On pre-retina MacBook Pros, the apple-gmux driver is needed to > > temporarily > > + * switch DDC to the inactive GPU so that it can probe the panel's EDID. > > + * Therefore return %true if gmux is built into the machine, @pdev is the > > + * inactive GPU and the apple-gmux driver has not registered its handler > > + * flags, signifying it has not yet loaded or has not finished > > initializing. > > I think the apple-specific comment here should be a separate comment > right above the if condition below - it doesn't explain the interface, > only one specific case. And we might grow more of those. Ok, I've moved that to a comment. Updated patch follows after the scissors & perforation. Thanks for the feedback! Lukas -- >8 -- Subject: [PATCH] vga_switcheroo: Allow clients to determine whether to defer probing So far we've got one condition when DRM drivers need to defer probing on a dual GPU system and it's coded separately into each of the relevant drivers. As suggested by Daniel Vetter, deduplicate that code in the drivers and move it to a new vga_switcheroo helper. This yields better encapsulation of concepts and lets us add further checks in a central place. (The existing check pertains to pre-retina MacBook Pros and an additional check is expected to be needed for retinas.) v2: This helper could eventually be used by audio clients as well, so rephrase kerneldoc to refer to "client" instead of "GPU" and move the single existing check in an if block specific to PCI_CLASS_DISPLAY_VGA devices. Move documentation on that check from kerneldoc to a comment. (Daniel Vetter) Cc: Daniel Vetter Cc: Ben Skeggs Cc: Alex Deucher Signed-off-by: Lukas Wunner --- drivers/gpu/drm/i915/i915_drv.c | 10 +- drivers/gpu/drm/nouveau/nouveau_drm.c | 10 +- drivers/gpu/drm/radeon/radeon_drv.c | 10 +- drivers/gpu/vga/vga_switcheroo.c | 28 include/linux/vga_switcheroo.h| 2 ++ 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index e8d0f17..01ef24a 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -35,11 +35,9 @@ #include "i915_trace.h" #include "intel_drv.h" -#include #include #include #include -#include #include #include
[PATCH v3 2/2] drm: remove drm_device_is_unplugged and related code
gt; int ret;
>
> - if (drm_device_is_unplugged(dev))
> - return -ENODEV;
> -
> mutex_lock(&dev->struct_mutex);
> ret = drm_mmap_locked(filp, vma);
> mutex_unlock(&dev->struct_mutex);
> diff --git a/drivers/gpu/drm/udl/udl_connector.c
> b/drivers/gpu/drm/udl/udl_connector.c
> index 4709b54..a6d5e21 100644
> --- a/drivers/gpu/drm/udl/udl_connector.c
> +++ b/drivers/gpu/drm/udl/udl_connector.c
> @@ -96,8 +96,6 @@ static int udl_mode_valid(struct drm_connector
> *connector,
> static enum drm_connector_status
> udl_detect(struct drm_connector *connector, bool force)
> {
> - if (drm_device_is_unplugged(connector->dev))
> - return connector_status_disconnected;
> return connector_status_connected;
> }
>
> diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
> index 200419d..29aca6c 100644
> --- a/drivers/gpu/drm/udl/udl_fb.c
> +++ b/drivers/gpu/drm/udl/udl_fb.c
> @@ -321,12 +321,6 @@ static void udl_fb_imageblit(struct fb_info *info,
> const struct fb_image *image)
> static int udl_fb_open(struct fb_info *info, int user)
> {
> struct udl_fbdev *ufbdev = info->par;
> - struct drm_device *dev = ufbdev->ufb.base.dev;
> - struct udl_device *udl = dev->dev_private;
> -
> - /* If the USB device is gone, we don't accept new opens */
> - if (drm_device_is_unplugged(udl->ddev))
> - return -ENODEV;
>
> ufbdev->fb_count++;
>
> diff --git a/include/drm/drmP.h b/include/drm/drmP.h
> index d7162cf..40c6099 100644
> --- a/include/drm/drmP.h
> +++ b/include/drm/drmP.h
> @@ -748,7 +748,6 @@ struct drm_device {
> struct drm_minor *control; /**< Control node */
> struct drm_minor *primary; /**< Primary node */
> struct drm_minor *render; /**< Render node */
> - atomic_t unplugged; /**< Flag whether dev is
> dead */
> struct inode *anon_inode; /**< inode for private
> address-space */
> char *unique; /**< unique name of the
> device */
> /*@} */
> @@ -879,19 +878,6 @@ static __inline__ int drm_core_check_feature(struct
> drm_device *dev,
> return ((dev->driver->driver_features & feature) ? 1 : 0);
> }
>
> -static inline void drm_device_set_unplugged(struct drm_device *dev)
> -{
> - smp_wmb();
> - atomic_set(&dev->unplugged, 1);
> -}
> -
> -static inline int drm_device_is_unplugged(struct drm_device *dev)
> -{
> - int ret = atomic_read(&dev->unplugged);
> - smp_rmb();
> - return ret;
> -}
> -
> static inline bool drm_is_render_client(const struct drm_file *file_priv)
> {
> return file_priv->minor->type == DRM_MINOR_RENDER;
> --
> 2.7.0.rc3.207.g0ac5344
>
>
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[PATCH v2 21/21] drm/tilcdc: Initialize crtc->port
Initialize port device node pointer in the tilcdc crtc. Fixes "Falling
back to first CRTC" warning from tda998x driver.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index e886277..cfd3fd1 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -124,6 +124,7 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+ of_node_put(crtc->port);
drm_crtc_cleanup(crtc);
drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
@@ -768,6 +769,7 @@ void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc,
struct drm_file *file)
struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
{
+ struct tilcdc_drm_private *priv = dev->dev_private;
struct tilcdc_crtc *tilcdc_crtc;
struct drm_crtc *crtc;
int ret;
@@ -794,6 +796,15 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
+ if (priv->is_componentized) {
+ crtc->port =
+ of_get_child_by_name(dev->dev->of_node, "port");
+ if (!crtc->port) {
+ dev_warn(dev->dev, "no port node found in %s\n",
+dev->dev->of_node->full_name);
+ }
+ }
+
return crtc;
fail:
--
1.9.1
[PATCH v2 20/21] drm/tilcdc: Disable sync lost interrupt if it fires on every frame
Disable the sync lost interrupt if it fires on every frame for 50
consecutive frames in a row. This is relatively sure sign of the sync
lost interrupt being stuck and firing on every frame even if the
display otherwise appears to work OK.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 87c4765..e886277 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -43,6 +43,9 @@ struct tilcdc_crtc {
/* Only set if an external encoder is connected */
bool simulate_vesa_sync;
+
+ int sync_lost_count;
+ bool frame_intact;
};
#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
@@ -662,6 +665,8 @@ out:
pm_runtime_put_sync(dev->dev);
}
+#define SYNC_LOST_COUNT_LIMIT 50
+
irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
{
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
@@ -707,6 +712,11 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev->event_lock, flags);
}
+
+ if (tilcdc_crtc->frame_intact)
+ tilcdc_crtc->sync_lost_count = 0;
+ else
+ tilcdc_crtc->frame_intact = true;
}
if (priv->rev == 2) {
@@ -717,9 +727,18 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
}
- if (stat & LCDC_SYNC_LOST)
+ if (stat & LCDC_SYNC_LOST) {
dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
__func__, stat);
+ tilcdc_crtc->frame_intact = false;
+ if (tilcdc_crtc->sync_lost_count++ > SYNC_LOST_COUNT_LIMIT) {
+ dev_err(dev->dev,
+ "%s(0x%08x): Sync lost flood detected,
disabling the interrupt",
+ __func__, stat);
+ tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
+LCDC_SYNC_LOST);
+ }
+ }
if (stat & LCDC_FIFO_UNDERFLOW)
dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
--
1.9.1
[PATCH v2 19/21] drm/tilcdc: Add prints on sync lost and FIFO underrun interrupts
Add ratelimited prints on sync lost and FIFO underrun interrupts. Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 8 drivers/gpu/drm/tilcdc/tilcdc_drv.c | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 7445356..87c4765 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -717,6 +717,14 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); } + if (stat & LCDC_SYNC_LOST) + dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", + __func__, stat); + + if (stat & LCDC_FIFO_UNDERFLOW) + dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow", + __func__, stat); + return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 3205ac2..3a39328 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -389,7 +389,7 @@ static int tilcdc_irq_postinstall(struct drm_device *dev) tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_END_OF_FRAME0_INT_ENA | - LCDC_FRAME_DONE); + LCDC_FRAME_DONE | LCDC_SYNC_LOST); } return 0; @@ -408,7 +408,7 @@ static void tilcdc_irq_uninstall(struct drm_device *dev) tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | LCDC_V2_END_OF_FRAME0_INT_ENA | - LCDC_FRAME_DONE); + LCDC_FRAME_DONE | LCDC_SYNC_LOST); } } -- 1.9.1
[PATCH v2 18/21] drm/tilcdc: Remove the duplicate LCDC_INT_ENABLE_SET_REG in registers[]
Removes the duplicate LCDC_INT_ENABLE_SET_REG-entry in registers array.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 3b36747..3205ac2 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -446,11 +446,10 @@ static const struct {
/* new in revision 2: */
REG(2, false, LCDC_RAW_STAT_REG),
REG(2, false, LCDC_MASKED_STAT_REG),
- REG(2, false, LCDC_INT_ENABLE_SET_REG),
+ REG(2, true, LCDC_INT_ENABLE_SET_REG),
REG(2, false, LCDC_INT_ENABLE_CLR_REG),
REG(2, false, LCDC_END_OF_INT_IND_REG),
REG(2, true, LCDC_CLK_ENABLE_REG),
- REG(2, true, LCDC_INT_ENABLE_SET_REG),
#undef REG
};
--
1.9.1
[PATCH v2 17/21] drm/tilcdc: Fix interrupt enable/disable code for version 2 tilcdc
Fix interrupt enable/disable code for version 2 tilcdc. In version 2
tilcdc there is a separate register for disabling interrupts. Writing
0 to enable registers bits does not have any effect. The interrupt
clear register works the same way, writing 1 to specific bit disables
the interrupt and writing 0 does not have any effect.
The "bug" that is fixed here does not really do any harm since the
interrupts are enabled only once in the power up and disabled before
power down.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 24f232b..3b36747 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -383,13 +383,14 @@ static int tilcdc_irq_postinstall(struct drm_device *dev)
struct tilcdc_drm_private *priv = dev->dev_private;
/* enable FIFO underflow irq: */
- if (priv->rev == 1)
+ if (priv->rev == 1) {
tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
LCDC_V1_UNDERFLOW_INT_ENA);
- else
- tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG,
+ } else {
+ tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
LCDC_V2_UNDERFLOW_INT_ENA |
LCDC_V2_END_OF_FRAME0_INT_ENA |
LCDC_FRAME_DONE);
+ }
return 0;
}
@@ -404,7 +405,7 @@ static void tilcdc_irq_uninstall(struct drm_device *dev)
LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
LCDC_V1_END_OF_FRAME_INT_ENA);
} else {
- tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
+ tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
LCDC_V2_END_OF_FRAME0_INT_ENA |
LCDC_FRAME_DONE);
@@ -449,7 +450,7 @@ static const struct {
REG(2, false, LCDC_INT_ENABLE_CLR_REG),
REG(2, false, LCDC_END_OF_INT_IND_REG),
REG(2, true, LCDC_CLK_ENABLE_REG),
- REG(2, true, LCDC_INT_ENABLE_SET_REG),
+ REG(2, true, LCDC_INT_ENABLE_SET_REG),
#undef REG
};
--
1.9.1
[PATCH v2 16/21] drm/tilcdc: Do not update the next frame buffer close to vertical blank
From: Tomi Valkeinen
Do not update the next frame buffer close to vertical blank. This is
to avoid situation when the frame changes between writing of
LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 61 +++-
1 file changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 7514d40..7445356 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -21,6 +21,8 @@
#include "tilcdc_drv.h"
#include "tilcdc_regs.h"
+#define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
+
struct tilcdc_crtc {
struct drm_crtc base;
@@ -29,8 +31,12 @@ struct tilcdc_crtc {
int dpms;
wait_queue_head_t frame_done_wq;
bool frame_done;
+ spinlock_t irq_lock;
+
+ ktime_t last_vblank;
struct drm_framebuffer *curr_fb;
+ struct drm_framebuffer *next_fb;
/* for deferred fb unref's: */
struct drm_flip_work unref_work;
@@ -146,6 +152,8 @@ static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
struct drm_device *dev = crtc->dev;
int r;
unsigned long flags;
+ s64 tdiff;
+ ktime_t next_vblank;
r = tilcdc_verify_fb(crtc, fb);
if (r)
@@ -162,12 +170,21 @@ static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
pm_runtime_get_sync(dev->dev);
+ spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
- set_scanout(crtc, fb);
+ next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
+ 100 / crtc->hwmode.vrefresh);
+
+ tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
+
+ if (tdiff >= TILCDC_VBLANK_SAFETY_THRESHOLD_US)
+ set_scanout(crtc, fb);
+ else
+ tilcdc_crtc->next_fb = fb;
- spin_lock_irqsave(&dev->event_lock, flags);
tilcdc_crtc->event = event;
- spin_unlock_irqrestore(&dev->event_lock, flags);
+
+ spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
pm_runtime_put_sync(dev->dev);
@@ -211,6 +228,12 @@ void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
pm_runtime_put_sync(dev->dev);
+ if (tilcdc_crtc->next_fb) {
+ drm_flip_work_queue(&tilcdc_crtc->unref_work,
+ tilcdc_crtc->next_fb);
+ tilcdc_crtc->next_fb = NULL;
+ }
+
if (tilcdc_crtc->curr_fb) {
drm_flip_work_queue(&tilcdc_crtc->unref_work,
tilcdc_crtc->curr_fb);
@@ -651,19 +674,39 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
if (stat & LCDC_END_OF_FRAME0) {
unsigned long flags;
+ bool skip_event = false;
+ ktime_t now;
+
+ now = ktime_get();
drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
+ spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
+
+ tilcdc_crtc->last_vblank = now;
+
+ if (tilcdc_crtc->next_fb) {
+ set_scanout(crtc, tilcdc_crtc->next_fb);
+ tilcdc_crtc->next_fb = NULL;
+ skip_event = true;
+ }
+
+ spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
+
drm_handle_vblank(dev, 0);
- spin_lock_irqsave(&dev->event_lock, flags);
+ if (!skip_event) {
+ struct drm_pending_vblank_event *event;
+
+ spin_lock_irqsave(&dev->event_lock, flags);
- if (tilcdc_crtc->event) {
- drm_send_vblank_event(dev, 0, tilcdc_crtc->event);
+ event = tilcdc_crtc->event;
tilcdc_crtc->event = NULL;
- }
+ if (event)
+ drm_send_vblank_event(dev, 0, event);
- spin_unlock_irqrestore(&dev->event_lock, flags);
+ spin_unlock_irqrestore(&dev->event_lock, flags);
+ }
}
if (priv->rev == 2) {
@@ -716,6 +759,8 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
drm_flip_work_init(&tilcdc_crtc->unref_work,
"unref", unref_worker);
+ spin_lock_init(&tilcdc_crtc->irq_lock);
+
ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
if (ret < 0)
goto fail;
--
1.9.1
[PATCH v2 15/21] drm/tilcdc: Get rid of complex ping-pong mechanism
From: Tomi Valkeinen
Get rid of complex ping-pong mechanism and replace it with simpler
single buffer flipping code.
The LCDC HW appears to be designed mainly static framebuffers in
mind. There are two modes of operation, either static single buffer,
or ping pong double buffering with two static buffers switching back
and forth. Luckily the framebuffer start address is fetched only in
the beginning of the frame and changing the address after that only
takes effect after the next vertical blank. The page flipping code can
simply write the address of the new framebuffer and the page is
flipped automatically after the next vertical blank. Using the ping
pong double buffering makes the flipping code way more complex and it
does not provide any benefit, so it is better to switch to single
buffer operation.
There is still one problem in updating the framebuffer dma address on
the fly. There are two registers defining the framebuffer dma area and
things may break if the dma address is fetched in while the registers
are are being updated.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 122 ++-
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 27 +---
2 files changed, 53 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 280c76a..7514d40 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -25,15 +25,12 @@ struct tilcdc_crtc {
struct drm_crtc base;
const struct tilcdc_panel_info *info;
- uint32_t dirty;
- dma_addr_t start, end;
struct drm_pending_vblank_event *event;
int dpms;
wait_queue_head_t frame_done_wq;
bool frame_done;
- /* fb currently set to scanout 0/1: */
- struct drm_framebuffer *scanout[2];
+ struct drm_framebuffer *curr_fb;
/* for deferred fb unref's: */
struct drm_flip_work unref_work;
@@ -54,62 +51,31 @@ static void unref_worker(struct drm_flip_work *work, void
*val)
mutex_unlock(&dev->mode_config.mutex);
}
-static void set_scanout(struct drm_crtc *crtc, int n)
+static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
{
- static const uint32_t base_reg[] = {
- LCDC_DMA_FB_BASE_ADDR_0_REG,
- LCDC_DMA_FB_BASE_ADDR_1_REG,
- };
- static const uint32_t ceil_reg[] = {
- LCDC_DMA_FB_CEILING_ADDR_0_REG,
- LCDC_DMA_FB_CEILING_ADDR_1_REG,
- };
- static const uint32_t stat[] = {
- LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
- };
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
struct drm_device *dev = crtc->dev;
- struct tilcdc_drm_private *priv = dev->dev_private;
-
- tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
- tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
- if (tilcdc_crtc->scanout[n]) {
- drm_flip_work_queue(&tilcdc_crtc->unref_work,
tilcdc_crtc->scanout[n]);
- drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
- }
- tilcdc_crtc->scanout[n] = crtc->primary->fb;
- drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
- tilcdc_crtc->dirty &= ~stat[n];
-}
-
-static void update_scanout(struct drm_crtc *crtc)
-{
- struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
- struct drm_device *dev = crtc->dev;
- struct drm_framebuffer *fb = crtc->primary->fb;
struct drm_gem_cma_object *gem;
unsigned int depth, bpp;
+ dma_addr_t start, end;
drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
gem = drm_fb_cma_get_gem_obj(fb, 0);
- tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
- (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
+ start = gem->paddr + fb->offsets[0] +
+ crtc->y * fb->pitches[0] +
+ crtc->x * bpp / 8;
- tilcdc_crtc->end = tilcdc_crtc->start +
- (crtc->mode.vdisplay * fb->pitches[0]);
+ end = start + (crtc->mode.vdisplay * fb->pitches[0]);
- if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
- /* already enabled, so just mark the frames that need
-* updating and they will be updated on vblank:
-*/
- tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
- drm_vblank_get(dev, 0);
- } else {
- /* not enabled yet, so update registers immediately: */
- set_scanout(crtc, 0);
- set_scanout(crtc, 1);
- }
+ tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
+ tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end);
+
+ if (tilcdc_crtc->curr_fb)
+ drm_flip_work_queue(&tilc
[PATCH v2 14/21] drm/tilcdc: cleanup irq handling
From: Tomi Valkeinen
Cleanup irq handling. Clear the irq status unconditionally and
restructure the status bit conditions.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index fe2aed7..280c76a 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -656,11 +656,12 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private;
- uint32_t stat = tilcdc_read_irqstatus(dev);
+ uint32_t stat;
- if (stat & LCDC_PL_LOAD_DONE) {
- tilcdc_clear_irqstatus(dev, stat);
- } else {
+ stat = tilcdc_read_irqstatus(dev);
+ tilcdc_clear_irqstatus(dev, stat);
+
+ if ((stat & LCDC_END_OF_FRAME0) || (stat & LCDC_END_OF_FRAME1)) {
struct drm_pending_vblank_event *event;
unsigned long flags;
uint32_t dirty = tilcdc_crtc->dirty & stat;
--
1.9.1
[PATCH v2 13/21] drm/tilcdc: remove broken error handling
From: Tomi Valkeinen
Remove broken error handling. The condition for handling the
LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW could never be satisfied as the
LCDC_SYNC_LOST interrupt is not enabled. Also the requirement to have
both LCDC_SYNC_LOST and LCDC_FIFO_UNDERFLOW fired at once before
handling the error looks weird.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index ec7be2c..fe2aed7 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -658,12 +658,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
struct tilcdc_drm_private *priv = dev->dev_private;
uint32_t stat = tilcdc_read_irqstatus(dev);
- if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
- stop(crtc);
- dev_err(dev->dev, "error: %08x\n", stat);
- tilcdc_clear_irqstatus(dev, stat);
- start(crtc);
- } else if (stat & LCDC_PL_LOAD_DONE) {
+ if (stat & LCDC_PL_LOAD_DONE) {
tilcdc_clear_irqstatus(dev, stat);
} else {
struct drm_pending_vblank_event *event;
--
1.9.1
[PATCH v2 12/21] drm/tilcdc: split reset to a separate function
From: Tomi Valkeinen
Split reset to a separate function and use usleep_range(250, 1000)
instead of msleep(1) to to keep the reset bit on long enough.
Signed-off-by: Tomi Valkeinen
[Added description to the patch, changed mdelay(500) to usleep_range(250, 1000)]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 21 ++---
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 3a6f11e..ec7be2c 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -112,17 +112,24 @@ static void update_scanout(struct drm_crtc *crtc)
}
}
-static void start(struct drm_crtc *crtc)
+static void reset(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private;
- if (priv->rev == 2) {
- tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
- msleep(1);
- tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
- msleep(1);
- }
+ if (priv->rev != 2)
+ return;
+
+ tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
+ usleep_range(250, 1000);
+ tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
+}
+
+static void start(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+
+ reset(crtc);
tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
--
1.9.1
[PATCH v2 11/21] drm/tilcdc: disable crtc on unload
From: Tomi Valkeinen
Disable crtc on unload. Call tilcdc_crtc_dpms() with DRM_MODE_DPMS_OFF
in the beginning of unload function.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index ecbf0fd..ab62aa4 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -112,6 +112,8 @@ static int tilcdc_unload(struct drm_device *dev)
{
struct tilcdc_drm_private *priv = dev->dev_private;
+ tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
+
tilcdc_remove_external_encoders(dev);
drm_fbdev_cma_fini(priv->fbdev);
--
1.9.1
[PATCH v2 10/21] drm/tilcdc: cleanup runtime PM handling
From: Tomi Valkeinen
Cleanup runtime PM handling. Before the patch the usage of pm_runtime
calls was inconsistent and hard to follow. After the update the
pm_runtime calls are removed from set_scanout() and called around
major operations that access the HW. After the patch the DPMS code does
not have pm_runtime_forbid/allow calls any more and
pm_runtime_irq_safe() is not set anymore.
Signed-off-by: Tomi Valkeinen
[Added description to the patch]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 19 +++
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 -
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index cc45818..3a6f11e 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -71,7 +71,6 @@ static void set_scanout(struct drm_crtc *crtc, int n)
struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private;
- pm_runtime_get_sync(dev->dev);
tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
if (tilcdc_crtc->scanout[n]) {
@@ -81,7 +80,6 @@ static void set_scanout(struct drm_crtc *crtc, int n)
tilcdc_crtc->scanout[n] = crtc->primary->fb;
drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
tilcdc_crtc->dirty &= ~stat[n];
- pm_runtime_put_sync(dev->dev);
}
static void update_scanout(struct drm_crtc *crtc)
@@ -186,8 +184,13 @@ static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
crtc->primary->fb = fb;
tilcdc_crtc->event = event;
+
+ pm_runtime_get_sync(dev->dev);
+
update_scanout(crtc);
+ pm_runtime_put_sync(dev->dev);
+
return 0;
}
@@ -206,10 +209,8 @@ void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
tilcdc_crtc->dpms = mode;
- pm_runtime_get_sync(dev->dev);
-
if (mode == DRM_MODE_DPMS_ON) {
- pm_runtime_forbid(dev->dev);
+ pm_runtime_get_sync(dev->dev);
start(crtc);
} else {
tilcdc_crtc->frame_done = false;
@@ -227,10 +228,9 @@ void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
if (ret == 0)
dev_err(dev->dev, "timeout waiting for
framedone\n");
}
- pm_runtime_allow(dev->dev);
- }
- pm_runtime_put_sync(dev->dev);
+ pm_runtime_put_sync(dev->dev);
+ }
}
static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
@@ -455,13 +455,16 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
+ struct drm_device *dev = crtc->dev;
int r;
r = tilcdc_verify_fb(crtc, crtc->primary->fb);
if (r)
return r;
+ pm_runtime_get_sync(dev->dev);
update_scanout(crtc);
+ pm_runtime_put_sync(dev->dev);
return 0;
}
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index ab1789b..ecbf0fd 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -230,7 +230,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned
long flags)
DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
pm_runtime_enable(dev->dev);
- pm_runtime_irq_safe(dev->dev);
/* Determine LCD IP Version */
pm_runtime_get_sync(dev->dev);
--
1.9.1
[PATCH v2 09/21] drm/tilcdc: Allocate register storage based on the actual number registers
Allocate suspend/resume register storage based on the actual number
registers the driver is aware of. The static allocation for register
storage had falen behind badly.
Reported-by: Michael Bode
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 21 -
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 +-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 893ef18..ab1789b 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -141,11 +141,14 @@ static int tilcdc_unload(struct drm_device *dev)
pm_runtime_disable(dev->dev);
+ kfree(priv->saved_register);
kfree(priv);
return 0;
}
+static size_t tilcdc_num_regs(void);
+
static int tilcdc_load(struct drm_device *dev, unsigned long flags)
{
struct platform_device *pdev = dev->platformdev;
@@ -157,7 +160,12 @@ static int tilcdc_load(struct drm_device *dev, unsigned
long flags)
int ret;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
- if (!priv) {
+ if (priv)
+ priv->saved_register = kcalloc(tilcdc_num_regs(),
+ sizeof(*priv->saved_register),
+ GFP_KERNEL);
+ if (!priv || !priv->saved_register) {
+ kfree(priv);
dev_err(dev->dev, "failed to allocate private data\n");
return -ENOMEM;
}
@@ -339,6 +347,7 @@ fail_free_wq:
fail_free_priv:
dev->dev_private = NULL;
+ kfree(priv->saved_register);
kfree(priv);
return ret;
}
@@ -463,6 +472,16 @@ static const struct {
REG(2, true, LCDC_INT_ENABLE_SET_REG),
#undef REG
};
+
+static size_t tilcdc_num_regs(void)
+{
+ return ARRAY_SIZE(registers);
+}
+#else
+static size_t tilcdc_num_regs(void)
+{
+ return 0;
+}
#endif
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index 77c600d..80badad 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -66,7 +66,7 @@ struct tilcdc_drm_private {
uint32_t max_width;
/* register contents saved across suspend/resume: */
- u32 saved_register[12];
+ u32 *saved_register;
bool ctx_valid;
#ifdef CONFIG_CPU_FREQ
--
1.9.1
[PATCH v2 08/21] drm/tilcdc: fix build error when !CONFIG_CPU_FREQ
From: Grygorii Strashko Fix build error when !CONFIG_CPU_FREQ drivers/gpu/drm/tilcdc/tilcdc_drv.c: In function 'tilcdc_load': drivers/gpu/drm/tilcdc/tilcdc_drv.c:327:1: error: label 'fail_put_clk' defined but not used [-Werror=unused-label] fail_put_clk: ^ Signed-off-by: Grygorii Strashko Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 4406cbd..893ef18 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -325,9 +325,9 @@ fail_cpufreq_unregister: #ifdef CONFIG_CPU_FREQ cpufreq_unregister_notifier(&priv->freq_transition, CPUFREQ_TRANSITION_NOTIFIER); -#endif fail_put_clk: +#endif clk_put(priv->clk); fail_iounmap: -- 1.9.1
[PATCH v2 07/21] drm/tilcdc: Implement dma-buf support for tilcdc
There is nothing special about tilcdc HW when the video memory is
concerned. Just using the standard drm helpers for implementation is
enough.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index d2533e26..4406cbd 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -549,7 +549,8 @@ static const struct file_operations fops = {
};
static struct drm_driver tilcdc_driver = {
- .driver_features= DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
+ .driver_features= (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
+ DRIVER_PRIME),
.load = tilcdc_load,
.unload = tilcdc_unload,
.preclose = tilcdc_preclose,
@@ -567,6 +568,16 @@ static struct drm_driver tilcdc_driver = {
.dumb_create= drm_gem_cma_dumb_create,
.dumb_map_offset= drm_gem_cma_dumb_map_offset,
.dumb_destroy = drm_gem_dumb_destroy,
+
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_prime_import = drm_gem_prime_import,
+ .gem_prime_export = drm_gem_prime_export,
+ .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+ .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+ .gem_prime_vmap = drm_gem_cma_prime_vmap,
+ .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+ .gem_prime_mmap = drm_gem_cma_prime_mmap,
#ifdef CONFIG_DEBUG_FS
.debugfs_init = tilcdc_debugfs_init,
.debugfs_cleanup= tilcdc_debugfs_cleanup,
--
1.9.1
[PATCH v2 06/21] drm/tilcdc: disable the lcd controller/dma engine when suspend invoked
From: Darren Etheridge
The LCD controller must be deactivated and all DMA transactions stopped
when the suspend power state is entered otherwise the PRCM causes the L3
bus to get stuck in transition state.
This commit forces the lcdc to be shut down and waits for all pending DMA
transactions to complete as part of the suspend handler for this driver.
Signed-off-by: Darren Etheridge
Tested-by: Dave Gerlach
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 3 +--
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 3 +++
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 1 +
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 105f286..cc45818 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -138,7 +138,6 @@ static void stop(struct drm_crtc *crtc)
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
}
-static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode);
static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
{
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
@@ -192,7 +191,7 @@ static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
return 0;
}
-static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
+void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
{
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
struct drm_device *dev = crtc->dev;
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 41720ad..d2533e26 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -600,6 +600,9 @@ static int tilcdc_pm_suspend(struct device *dev)
return 0;
}
+ /* Disable the LCDC controller, to avoid locking up the PRCM */
+ tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF);
+
/* Save register state: */
for (i = 0; i < ARRAY_SIZE(registers); i++)
if (registers[i].save && (priv->rev >= registers[i].rev))
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index 7d214cc..77c600d 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -172,5 +172,6 @@ void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc
*crtc,
bool simulate_vesa_sync);
int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode
*mode);
int tilcdc_crtc_max_width(struct drm_crtc *crtc);
+void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode);
#endif /* __TILCDC_DRV_H__ */
--
1.9.1
[PATCH v2 05/21] drm/tilcdc: make frame_done interrupt active at all times
From: Darren Etheridge
The frame_done interrupt was only being enabled when the vsync
interrupts were being enabled by DRM. However the frame_done is
used to determine if the LCD controller has successfully completed
the raster_enable, raster_disable commands and the vsync interrupts
are not always enabled during these operations.
Signed-off-by: Darren Etheridge
Tested-by: Dave Gerlach
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index d7b60b4..41720ad 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -376,7 +376,9 @@ static int tilcdc_irq_postinstall(struct drm_device *dev)
if (priv->rev == 1)
tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
LCDC_V1_UNDERFLOW_INT_ENA);
else
- tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG,
LCDC_V2_UNDERFLOW_INT_ENA);
+ tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG,
+ LCDC_V2_UNDERFLOW_INT_ENA |
+ LCDC_FRAME_DONE);
return 0;
}
@@ -410,7 +412,7 @@ static void enable_vblank(struct drm_device *dev, bool
enable)
} else {
reg = LCDC_INT_ENABLE_SET_REG;
mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
- LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
+ LCDC_V2_END_OF_FRAME1_INT_ENA;
}
if (enable)
--
1.9.1
[PATCH v2 04/21] drm/tilcdc: fix kernel panic on suspend when no hdmi monitor connected
From: Darren Etheridge
On BeagleBone Black if no HDMI monitor is connected and suspend
is requested a kernel panic will result:
root at am335x-evm:~# echo mem > /sys/power/state
[ 65.548710] PM: Syncing filesystems ... done.
[ 65.631311] Freezing user space processes ... (elapsed 0.006 seconds) done.
[ 65.648619] Freezing remaining freezable tasks ... (elapsed 0.005 seconds)
done.
[ 65.833500] Unhandled fault: external abort on non-linefetch (0x1028) at
0xfa30e004
[ 65.841692] Internal error: : 1028 [#1] SMP ARM
[ 66.105287] [] (platform_pm_suspend) from []
(dpm_run_callback+0x34/0x70)
[ 66.114370] [] (dpm_run_callback) from []
(__device_suspend+0x10c/0x2f4)
[ 66.123357] [] (__device_suspend) from []
(dpm_suspend+0x58/0x218)
[ 66.131796] [] (dpm_suspend) from []
(suspend_devices_and_enter+0x9c/0x3c0)
[ 66.141055] [] (suspend_devices_and_enter) from []
(pm_suspend+0x210/0x24c)
[ 66.150312] [] (pm_suspend) from [] (state_store+0x68/0xb8)
[ 66.158103] [] (state_store) from []
(kobj_attr_store+0x14/0x20)
[ 66.166355] [] (kobj_attr_store) from []
(sysfs_kf_write+0x4c/0x50)
[ 66.174883] [] (sysfs_kf_write) from []
(kernfs_fop_write+0xb4/0x150)
[ 66.183598] [] (kernfs_fop_write) from []
(vfs_write+0xa8/0x180)
[ 66.191846] [] (vfs_write) from [] (SyS_write+0x40/0x8c)
[ 66.199365] [] (SyS_write) from []
(ret_fast_syscall+0x0/0x48)
[ 66.207426] Code: e595c210 e5932000 e59cc000 e08c2002 (e592c000)
This is because the lcdc module is not enabled when no monitor is detected
to save power. However the suspend handler just blindly tries to save the
lcdc state by copying out the pertinent registers. However module is off
so no good things happen when you try and access it.
This patch only saves off the registers if the module is enabled, and
then only restores the registers on resume if they were saved off during
suspend.
Signed-off-by: Darren Etheridge
Tested-by: Dave Gerlach
Acked-by: Felipe Balbi
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 23 +--
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 1 +
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 64f1de2..d7b60b4 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -590,13 +590,20 @@ static int tilcdc_pm_suspend(struct device *dev)
drm_kms_helper_poll_disable(ddev);
+ /* Select sleep pin state */
+ pinctrl_pm_select_sleep_state(dev);
+
+ if (pm_runtime_suspended(dev)) {
+ priv->ctx_valid = false;
+ return 0;
+ }
+
/* Save register state: */
for (i = 0; i < ARRAY_SIZE(registers); i++)
if (registers[i].save && (priv->rev >= registers[i].rev))
priv->saved_register[n++] = tilcdc_read(ddev,
registers[i].reg);
- /* Select sleep pin state */
- pinctrl_pm_select_sleep_state(dev);
+ priv->ctx_valid = true;
return 0;
}
@@ -610,10 +617,14 @@ static int tilcdc_pm_resume(struct device *dev)
/* Select default pin state */
pinctrl_pm_select_default_state(dev);
- /* Restore register state: */
- for (i = 0; i < ARRAY_SIZE(registers); i++)
- if (registers[i].save && (priv->rev >= registers[i].rev))
- tilcdc_write(ddev, registers[i].reg,
priv->saved_register[n++]);
+ if (priv->ctx_valid == true) {
+ /* Restore register state: */
+ for (i = 0; i < ARRAY_SIZE(registers); i++)
+ if (registers[i].save &&
+ (priv->rev >= registers[i].rev))
+ tilcdc_write(ddev, registers[i].reg,
+priv->saved_register[n++]);
+ }
drm_kms_helper_poll_enable(ddev);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index c00f518..7d214cc 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -67,6 +67,7 @@ struct tilcdc_drm_private {
/* register contents saved across suspend/resume: */
u32 saved_register[12];
+ bool ctx_valid;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
--
1.9.1
[PATCH v2 03/21] drm/tilcdc: adopt pinctrl support
From: Dave Gerlach Update tilcdc driver to set the state of the pins to: - "default on resume - "sleep" on suspend By optionally putting the pins into sleep state in the suspend callback we can accomplish two things. - minimize current leakage from pins and thus save power, - prevent the IP from driving pins output in an uncontrolled manner, which may happen if the power domain drops the domain regulator. Signed-off-by: Dave Gerlach Signed-off-by: Darren Etheridge Signed-off-by: Jyri Sarha --- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 4d75ee3..64f1de2 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -18,6 +18,8 @@ /* LCDC DRM driver, based on da8xx-fb */ #include +#include +#include #include "tilcdc_drv.h" #include "tilcdc_regs.h" @@ -593,6 +595,9 @@ static int tilcdc_pm_suspend(struct device *dev) if (registers[i].save && (priv->rev >= registers[i].rev)) priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg); + /* Select sleep pin state */ + pinctrl_pm_select_sleep_state(dev); + return 0; } @@ -602,6 +607,9 @@ static int tilcdc_pm_resume(struct device *dev) struct tilcdc_drm_private *priv = ddev->dev_private; unsigned i, n = 0; + /* Select default pin state */ + pinctrl_pm_select_default_state(dev); + /* Restore register state: */ for (i = 0; i < ARRAY_SIZE(registers); i++) if (registers[i].save && (priv->rev >= registers[i].rev)) -- 1.9.1
[PATCH v2 02/21] drm/tilcdc: verify fb pitch
From: Tomi Valkeinen
LCDC hardware does not support fb pitch that is different (i.e. larger)
than the screen size. The driver currently does no checks for this, and
the results of too big pitch are are flickering and lower fps.
This issue easily happens when using libdrm's modetest tool with non-32
bpp modes. As modetest always allocated 4 bytes per pixel, it implies a
bigger pitch for 16 or 24 bpp modes.
This patch adds a check to reject pitches the hardware cannot support.
Signed-off-by: Tomi Valkeinen
Signed-off-by: Darren Etheridge
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 7b687ae..105f286 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -151,6 +151,22 @@ static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
kfree(tilcdc_crtc);
}
+static int tilcdc_verify_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb)
+{
+ struct drm_device *dev = crtc->dev;
+ unsigned int depth, bpp;
+
+ drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
+
+ if (fb->pitches[0] != crtc->mode.hdisplay * bpp / 8) {
+ dev_err(dev->dev,
+ "Invalid pitch: fb and crtc widths must be the same");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
@@ -158,6 +174,11 @@ static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
{
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
struct drm_device *dev = crtc->dev;
+ int r;
+
+ r = tilcdc_verify_fb(crtc, fb);
+ if (r)
+ return r;
if (tilcdc_crtc->event) {
dev_err(dev->dev, "already pending page flip!\n");
@@ -272,6 +293,10 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
if (WARN_ON(!info))
return -EINVAL;
+ ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
+ if (ret)
+ return ret;
+
pm_runtime_get_sync(dev->dev);
/* Configure the Burst Size and fifo threshold of DMA: */
@@ -431,6 +456,12 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
+ int r;
+
+ r = tilcdc_verify_fb(crtc, crtc->primary->fb);
+ if (r)
+ return r;
+
update_scanout(crtc);
return 0;
}
--
1.9.1
[PATCH v2 01/21] drm/tilcdc: rewrite pixel clock calculation
From: Darren Etheridge
Updating the tilcdc DRM driver code to calculate the LCD controller
pixel clock more accurately. Based on a suggested implementation by
Tomi Valkeinen.
The current code does not work correctly and produces wrong results
with many requested clock rates. It also oddly uses two different
clocks, a display pll clock and a divider clock (child of display
pll), instead of just using the clock coming to the lcdc.
This patch removes the use of the display pll clock, and rewrites the
code to calculate the clock rates. The idea is simply to request a
clock rate of pixelclock*2, as the LCD controller has an internal
divider which we set to 2.
Signed-off-by: Darren Etheridge
[Rewrapped description]
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 16
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 11 +--
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 1 -
3 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 7d07733..7b687ae 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -573,7 +573,8 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private;
int dpms = tilcdc_crtc->dpms;
- unsigned int lcd_clk, div;
+ unsigned long lcd_clk;
+ const unsigned clkdiv = 2; /* using a fixed divider of 2 */
int ret;
pm_runtime_get_sync(dev->dev);
@@ -581,22 +582,21 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
if (dpms == DRM_MODE_DPMS_ON)
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
- /* in raster mode, minimum divisor is 2: */
- ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
- if (ret) {
+ /* mode.clock is in KHz, set_rate wants parameter in Hz */
+ ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
+ if (ret < 0) {
dev_err(dev->dev, "failed to set display clock rate to: %d\n",
crtc->mode.clock);
goto out;
}
lcd_clk = clk_get_rate(priv->clk);
- div = lcd_clk / (crtc->mode.clock * 1000);
- DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock,
div);
- DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk),
clk_get_rate(priv->disp_clk));
+ DBG("lcd_clk=%lu, mode clock=%d, div=%u",
+ lcd_clk, crtc->mode.clock, clkdiv);
/* Configure the LCD clock divisor. */
- tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
+ tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
LCDC_RASTER_MODE);
if (priv->rev == 2)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index d7f5b89..4d75ee3 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -192,13 +192,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned
long flags)
goto fail_iounmap;
}
- priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
- if (IS_ERR(priv->clk)) {
- dev_err(dev->dev, "failed to get display clock\n");
- ret = -ENODEV;
- goto fail_put_clk;
- }
-
#ifdef CONFIG_CPU_FREQ
priv->lcd_fck_rate = clk_get_rate(priv->clk);
priv->freq_transition.notifier_call = cpufreq_transition;
@@ -206,7 +199,7 @@ static int tilcdc_load(struct drm_device *dev, unsigned
long flags)
CPUFREQ_TRANSITION_NOTIFIER);
if (ret) {
dev_err(dev->dev, "failed to register cpufreq notifier\n");
- goto fail_put_disp_clk;
+ goto fail_put_clk;
}
#endif
@@ -330,8 +323,6 @@ fail_cpufreq_unregister:
#ifdef CONFIG_CPU_FREQ
cpufreq_unregister_notifier(&priv->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
-fail_put_disp_clk:
- clk_put(priv->disp_clk);
#endif
fail_put_clk:
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index e863ad0..c00f518 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -49,7 +49,6 @@
struct tilcdc_drm_private {
void __iomem *mmio;
- struct clk *disp_clk;/* display dpll */
struct clk *clk; /* functional clock */
int rev; /* IP revision */
--
1.9.1
[PATCH v2 00/21] drm/ticdc: Accumulated fixes over the past couple of years
Changes since the first version of the series: - Dropped: "drm/tilcdc: disable console switching during pm operations" - Changed: "drm/tilcdc: Allocate register storage based on the actual number.." - Reversed kcalloc() nmemb and size parameters to correct order - Addeed: "drm/tilcdc: Initialize crtc->port" We have not been too active in pushing the tilcdc fixes to mainline. This series tries to bring the mainline tilcdc upto same level with TI ti-linux tree. Some patches that touch the same place over and over again have been squashed into one, leaving author of the last rewrite on top. Best regards, Jyri Darren Etheridge (4): drm/tilcdc: rewrite pixel clock calculation drm/tilcdc: fix kernel panic on suspend when no hdmi monitor connected drm/tilcdc: make frame_done interrupt active at all times drm/tilcdc: disable the lcd controller/dma engine when suspend invoked Dave Gerlach (1): drm/tilcdc: adopt pinctrl support Grygorii Strashko (1): drm/tilcdc: fix build error when !CONFIG_CPU_FREQ Jyri Sarha (7): drm/tilcdc: Implement dma-buf support for tilcdc drm/tilcdc: Allocate register storage based on the actual number registers drm/tilcdc: Fix interrupt enable/disable code for version 2 tilcdc drm/tilcdc: Remove the duplicate LCDC_INT_ENABLE_SET_REG in registers[] drm/tilcdc: Add prints on sync lost and FIFO underrun interrupts drm/tilcdc: Disable sync lost interrupt if it fires on every frame drm/tilcdc: Initialize crtc->port Tomi Valkeinen (8): drm/tilcdc: verify fb pitch drm/tilcdc: cleanup runtime PM handling drm/tilcdc: disable crtc on unload drm/tilcdc: split reset to a separate function drm/tilcdc: remove broken error handling drm/tilcdc: cleanup irq handling drm/tilcdc: Get rid of complex ping-pong mechanism drm/tilcdc: Do not update the next frame buffer close to vertical blank drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 303 +++ drivers/gpu/drm/tilcdc/tilcdc_drv.c | 123 -- drivers/gpu/drm/tilcdc/tilcdc_drv.h | 5 +- 3 files changed, 277 insertions(+), 154 deletions(-) -- 1.9.1
[PATCH] [v2] intel: Add missing SKL device IDs
A new list yielded new devices that apparently have shipped, or will ship. v2: I can't read. 0x192d is GT3 Signed-off-by: Ben Widawsky --- intel/intel_chipset.h | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 35148e5..9c24701 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -168,6 +168,7 @@ #define PCI_CHIP_SKYLAKE_DT_GT10x1902 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ +#define PCI_CHIP_SKYLAKE_H_GT1 0x190B #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ #define PCI_CHIP_SKYLAKE_DT_GT20x1912 #define PCI_CHIP_SKYLAKE_FUSED0_GT20x1913 /* Reserved */ @@ -182,6 +183,7 @@ #define PCI_CHIP_SKYLAKE_GT3 0x1926 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A +#define PCI_CHIP_SKYLAKE_MEDIA_SRV_GT3 0x192D #define PCI_CHIP_SKYLAKE_DT_GT40x1932 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A #define PCI_CHIP_SKYLAKE_H_GT4 0x193B @@ -376,7 +378,8 @@ #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ -(devid) == PCI_CHIP_SKYLAKE_SRV_GT1) +(devid) == PCI_CHIP_SKYLAKE_SRV_GT1|| \ +(devid) == PCI_CHIP_SKYLAKE_H_GT1) #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ @@ -390,13 +393,15 @@ (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_GT3|| \ -(devid) == PCI_CHIP_SKYLAKE_HALO_GT3) +(devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ +(devid) == PCI_CHIP_SKYLAKE_MEDIA_SRV_GT3) + #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4|| \ (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ -(devid) == PCI_CHIP_SKYLAKE_WKS_GT4) +(devid) == PCI_CHIP_SKYLAKE_WKS_GT4|| \ #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ -- 2.7.1
[Bug 94043] Distorted graphics when running Battle.net app under Wine with Radeon driver
https://bugs.freedesktop.org/show_bug.cgi?id=94043 --- Comment #6 from Erik Brangs --- Is there anything I can do to increase the chances that this gets fixed? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160216/99f10234/attachment.html>
[PATCH v2 00/17] drm encoders cleanup: nuke optional dummy encoder mode_fixup function.
On Mon, Feb 15, 2016 at 12:57:04PM +, Carlos Palminha wrote: > mode_fixup function for encoder drivers became optional with patch > http://patchwork.freedesktop.org/patch/msgid/1455106522-32307-1-git-send-email-palminha > at synopsys.com > > This patch set nukes all the dummy mode_fixup implementations. > > (made on top of Daniel topic/drm-misc branch) > > Changes v1->v2: incorporated Daniel comments > * added signed-off-by line to all patches > * threading enabled due to e-mail server constraints > * common blurb lines to all patches > * add reviewed by Alex, to patches 4 and 14 I've thrown them all into a topic branch for soaking, and plan to merge into drm-misc in the next few days. Thanks, Daniel > > Carlos Palminha (17): > drm/virtio: removed optional dummy encoder mode_fixup function. > drm/udl: removed optional dummy encoder mode_fixup function. > drm/exynos: removed optional dummy encoder mode_fixup function. > drm/amdgpu: removed optional dummy encoder mode_fixup function. > drm/ast: removed optional dummy encoder mode_fixup function. > drm/bochs: removed optional dummy encoder mode_fixup function. > drm/cirrus: removed optional dummy encoder mode_fixup function. > drm/exynos: removed optional dummy encoder mode_fixup function. > drm/gma500: removed optional dummy encoder mode_fixup function. > drm/imx: removed optional dummy encoder mode_fixup function. > drm/msm/mdp: removed optional dummy encoder mode_fixup function. > drm/mgag200: removed optional dummy encoder mode_fixup function. > drm/qxl: removed optional dummy encoder mode_fixup function. > drm/radeon: removed optional dummy encoder mode_fixup function. > drm/rockchip: removed optional dummy encoder mode_fixup function. > drm/sti: removed optional dummy encoder mode_fixup function. > drm/tilcdc: removed optional dummy encoder mode_fixup function. > > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 8 > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c| 8 > drivers/gpu/drm/ast/ast_mode.c | 8 > drivers/gpu/drm/bochs/bochs_kms.c| 8 > drivers/gpu/drm/cirrus/cirrus_mode.c | 9 - > drivers/gpu/drm/exynos/exynos_dp_core.c | 8 > drivers/gpu/drm/exynos/exynos_drm_dpi.c | 8 > drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8 > drivers/gpu/drm/exynos/exynos_drm_vidi.c | 8 > drivers/gpu/drm/gma500/cdv_intel_crt.c | 1 - > drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 1 - > drivers/gpu/drm/gma500/gma_display.c | 7 --- > drivers/gpu/drm/gma500/gma_display.h | 3 --- > drivers/gpu/drm/gma500/oaktrail_hdmi.c | 1 - > drivers/gpu/drm/imx/dw_hdmi-imx.c| 8 > drivers/gpu/drm/imx/imx-ldb.c| 8 > drivers/gpu/drm/imx/imx-tve.c| 8 > drivers/gpu/drm/imx/parallel-display.c | 8 > drivers/gpu/drm/mgag200/mgag200_mode.c | 8 > drivers/gpu/drm/msm/mdp/mdp4/mdp4_dsi_encoder.c | 8 > drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c | 8 > drivers/gpu/drm/msm/mdp/mdp4/mdp4_lcdc_encoder.c | 8 > drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 9 - > drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 8 > drivers/gpu/drm/qxl/qxl_display.c| 9 - > drivers/gpu/drm/radeon/atombios_encoders.c | 8 > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 8 > drivers/gpu/drm/sti/sti_tvout.c | 10 -- > drivers/gpu/drm/tilcdc/tilcdc_panel.c| 9 - > drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 9 - > drivers/gpu/drm/udl/udl_encoder.c| 8 > drivers/gpu/drm/virtio/virtgpu_display.c | 8 > 33 files changed, 244 deletions(-) > > -- > 2.5.0 > > ___ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[PATCH 01/16] drm: fixes crct set_mode when crtc mode_fixup is null.
On Tue, Feb 16, 2016 at 02:10:03PM +, Carlos Palminha wrote:
> This patch set nukes all the dummy crtc mode_fixup implementations.
> (made on top of Daniel topic/drm-misc branch)
>
> Signed-off-by: Carlos Palminha
Applied this one to drm-misc. I'll let the others hang out there for a bit
more to collect acks.
Thanks, Daniel
> ---
> drivers/gpu/drm/drm_crtc_helper.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc_helper.c
> b/drivers/gpu/drm/drm_crtc_helper.c
> index e70d064..7539eea 100644
> --- a/drivers/gpu/drm/drm_crtc_helper.c
> +++ b/drivers/gpu/drm/drm_crtc_helper.c
> @@ -343,9 +343,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
> }
> }
>
> - if (!(ret = crtc_funcs->mode_fixup(crtc, mode, adjusted_mode))) {
> - DRM_DEBUG_KMS("CRTC fixup failed\n");
> - goto done;
> + if (crtc_funcs->mode_fixup) {
> + if (!(ret = crtc_funcs->mode_fixup(crtc, mode,
> + adjusted_mode))) {
> + DRM_DEBUG_KMS("CRTC fixup failed\n");
> + goto done;
> + }
> }
> DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
>
> --
> 2.5.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[PATCH v8 0/2] Add Rockchip Inno-HDMI driver
Hi Mark, Am Dienstag, 16. Februar 2016, 08:44:41 schrieb Mark yao: > Ping, it seems inno hdmi driver is ready, So I'd like to merge it into > drm/rockchip if there is no doubt these days. I think you can just go ahead with picking them up, I think they have ripened enough :-) Heiko
[PATCH v2 03/17] drm/exynos: removed optional dummy encoder mode_fixup function.
On Mon, Feb 15, 2016 at 02:49:09PM +0100, Patrik Jakobsson wrote:
> Hi Carlos
>
> Any particular reason why this patch isn't squashed with patch 8/17?
I've squashed them while applying.
-Daniel
>
> Thanks
> Patrik
>
>
> On Mon, Feb 15, 2016 at 1:58 PM, Carlos Palminha
> wrote:
> > mode_fixup function for encoder drivers became optional with patch
> > http://patchwork.freedesktop.org/patch/msgid/1455106522-32307-1-git-send-email-palminha
> > at synopsys.com
> >
> > This patch set nukes all the dummy mode_fixup implementations.
> >
> > (made on top of Daniel topic/drm-misc branch)
> >
> > Signed-off-by: Carlos Palminha
> > ---
> > drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8
> > 1 file changed, 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> > b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> > index e977a81..736115c 100644
> > --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> > +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> > @@ -1597,13 +1597,6 @@ static int exynos_dsi_create_connector(struct
> > drm_encoder *encoder)
> > return 0;
> > }
> >
> > -static bool exynos_dsi_mode_fixup(struct drm_encoder *encoder,
> > - const struct drm_display_mode *mode,
> > - struct drm_display_mode *adjusted_mode)
> > -{
> > - return true;
> > -}
> > -
> > static void exynos_dsi_mode_set(struct drm_encoder *encoder,
> > struct drm_display_mode *mode,
> > struct drm_display_mode *adjusted_mode)
> > @@ -1623,7 +1616,6 @@ static void exynos_dsi_mode_set(struct drm_encoder
> > *encoder,
> > }
> >
> > static const struct drm_encoder_helper_funcs
> > exynos_dsi_encoder_helper_funcs = {
> > - .mode_fixup = exynos_dsi_mode_fixup,
> > .mode_set = exynos_dsi_mode_set,
> > .enable = exynos_dsi_enable,
> > .disable = exynos_dsi_disable,
> > --
> > 2.5.0
> >
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
[PATCH 01/16] drm: fixes crct set_mode when crtc mode_fixup is null.
Thanks!
On 16-02-2016 14:37, Daniel Vetter wrote:
> On Tue, Feb 16, 2016 at 02:10:03PM +, Carlos Palminha wrote:
>> This patch set nukes all the dummy crtc mode_fixup implementations.
>> (made on top of Daniel topic/drm-misc branch)
>>
>> Signed-off-by: Carlos Palminha
>
> Applied this one to drm-misc. I'll let the others hang out there for a bit
> more to collect acks.
>
> Thanks, Daniel
>
>> ---
>> drivers/gpu/drm/drm_crtc_helper.c | 9 ++---
>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_crtc_helper.c
>> b/drivers/gpu/drm/drm_crtc_helper.c
>> index e70d064..7539eea 100644
>> --- a/drivers/gpu/drm/drm_crtc_helper.c
>> +++ b/drivers/gpu/drm/drm_crtc_helper.c
>> @@ -343,9 +343,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
>> }
>> }
>>
>> -if (!(ret = crtc_funcs->mode_fixup(crtc, mode, adjusted_mode))) {
>> -DRM_DEBUG_KMS("CRTC fixup failed\n");
>> -goto done;
>> +if (crtc_funcs->mode_fixup) {
>> +if (!(ret = crtc_funcs->mode_fixup(crtc, mode,
>> +adjusted_mode))) {
>> +DRM_DEBUG_KMS("CRTC fixup failed\n");
>> +goto done;
>> +}
>> }
>> DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
>>
>> --
>> 2.5.0
>>
>
[PATCH v2] qxl: use kmalloc_array to alloc reloc_info in qxl_process_single_command
On Tue, Feb 16, 2016 at 02:25:00PM +0100, Gerd Hoffmann wrote: > This avoids integer overflows on 32bit machines when calculating > reloc_info size, as reported by Alan Cox. > > Cc: stable at vger.kernel.org > Cc: gnomes at lxorguk.ukuu.org.uk > Signed-off-by: Gerd Hoffmann Reviewed-by: Daniel Vetter > --- > drivers/gpu/drm/qxl/qxl_ioctl.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c > index 2ae8577..7c2e782 100644 > --- a/drivers/gpu/drm/qxl/qxl_ioctl.c > +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c > @@ -168,7 +168,8 @@ static int qxl_process_single_command(struct qxl_device > *qdev, > cmd->command_size)) > return -EFAULT; > > - reloc_info = kmalloc(sizeof(struct qxl_reloc_info) * cmd->relocs_num, > GFP_KERNEL); > + reloc_info = kmalloc_array(cmd->relocs_num, > +sizeof(struct qxl_reloc_info), GFP_KERNEL); > if (!reloc_info) > return -ENOMEM; > > -- > 1.8.3.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
[PATCH] intel: Add missing SKL device IDs
A new list yielded new devices that apparently have shipped, or will ship. Signed-off-by: Ben Widawsky --- intel/intel_chipset.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 35148e5..392f7ba 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -168,6 +168,7 @@ #define PCI_CHIP_SKYLAKE_DT_GT10x1902 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ +#define PCI_CHIP_SKYLAKE_H_GT1 0x190B #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ #define PCI_CHIP_SKYLAKE_DT_GT20x1912 #define PCI_CHIP_SKYLAKE_FUSED0_GT20x1913 /* Reserved */ @@ -182,6 +183,7 @@ #define PCI_CHIP_SKYLAKE_GT3 0x1926 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A +#define PCI_CHIP_SKYLAKE_MEDIA_SRV_GT4 0x192D #define PCI_CHIP_SKYLAKE_DT_GT40x1932 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A #define PCI_CHIP_SKYLAKE_H_GT4 0x193B @@ -376,7 +378,8 @@ #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1|| \ (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ -(devid) == PCI_CHIP_SKYLAKE_SRV_GT1) +(devid) == PCI_CHIP_SKYLAKE_SRV_GT1|| \ +(devid) == PCI_CHIP_SKYLAKE_H_GT1) #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ @@ -396,7 +399,8 @@ (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ -(devid) == PCI_CHIP_SKYLAKE_WKS_GT4) +(devid) == PCI_CHIP_SKYLAKE_WKS_GT4|| \ +(devid) == PCI_CHIP_SKYLAKE_MEDIA_SRV_GT4) #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ -- 2.7.1
[REGRESSION] i915: No HDMI output with 4.4
16.02.2016 14:54, Daniel Vetter wrote: >> Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG >> 23MP65HQ-P >> === >> not working > > I presume the above LG screen is what you've called previously "old > monitor"? Correct. >> Computer DVI âââ DVI-D (Dual Link)/HDMI cable âââ HDMI LG >> 23MP65HQ-P >> === >> works! > > Funky. Can you pls grab the debug logs (with the special patches from > Ville) for this case? I wonder why suddenly different cable and it > works. OK, but will have to steal it again, as it is the only dual link cable I could find on another workplace. > Also: Is this one of these older-ish screens where you must have a > dual-link cable to drive it at full resolution&refresh rate? > -Daniel Single-link cable is enough to empower LG 23MP65HQ-P as its standard resolution is 1920Ã1080 at 60, which is supported by single-link cable. Dual-link cable comes with 27MP55HQ-P where it is required to provide higher resolution. BTW, in my previous email one should read "27MP55HQ-P" (not "23MP55HQ-P"). It is 27" monitor. Also, this monitor works with single-link cable (but at lower resolution, I guess).
[Bug 112491] Radeon: HD 7400G / A4-4355M System overheats with 3D graphics active.
https://bugzilla.kernel.org/show_bug.cgi?id=112491 --- Comment #6 from Dionisus Torimens --- Actually, I forgot to mention I used to have problems without active 3D use as well, but I'm now switching the DPM profile to battery during boot. And that solved that part mostly. Also, high CPU use by itself is not a problem. Where not using DPM, I didn't switch to the battery/low power profile. -- You are receiving this mail because: You are watching the assignee of the bug.
[PATCH v2] qxl: use kmalloc_array to alloc reloc_info in qxl_process_single_command
This avoids integer overflows on 32bit machines when calculating reloc_info size, as reported by Alan Cox. Cc: stable at vger.kernel.org Cc: gnomes at lxorguk.ukuu.org.uk Signed-off-by: Gerd Hoffmann --- drivers/gpu/drm/qxl/qxl_ioctl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 2ae8577..7c2e782 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -168,7 +168,8 @@ static int qxl_process_single_command(struct qxl_device *qdev, cmd->command_size)) return -EFAULT; - reloc_info = kmalloc(sizeof(struct qxl_reloc_info) * cmd->relocs_num, GFP_KERNEL); + reloc_info = kmalloc_array(cmd->relocs_num, + sizeof(struct qxl_reloc_info), GFP_KERNEL); if (!reloc_info) return -ENOMEM; -- 1.8.3.1
[PATCH 16/16] drm/ast: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/ast/ast_mode.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index 0123458..0deeecd 100644
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -497,13 +497,6 @@ static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
}
}
-static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
/* ast is different - we will force move buffers out of VRAM */
static int ast_crtc_do_set_base(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
@@ -617,7 +610,6 @@ static void ast_crtc_commit(struct drm_crtc *crtc)
static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
.dpms = ast_crtc_dpms,
- .mode_fixup = ast_crtc_mode_fixup,
.mode_set = ast_crtc_mode_set,
.mode_set_base = ast_crtc_mode_set_base,
.disable = ast_crtc_disable,
--
2.5.0
[PATCH 15/16] drm/bochs: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/bochs/bochs_kms.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/bochs/bochs_kms.c
b/drivers/gpu/drm/bochs/bochs_kms.c
index 2849f1b..c922b48 100644
--- a/drivers/gpu/drm/bochs/bochs_kms.c
+++ b/drivers/gpu/drm/bochs/bochs_kms.c
@@ -30,13 +30,6 @@ static void bochs_crtc_dpms(struct drm_crtc *crtc, int mode)
}
}
-static bool bochs_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static int bochs_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb)
{
@@ -135,7 +128,6 @@ static const struct drm_crtc_funcs bochs_crtc_funcs = {
static const struct drm_crtc_helper_funcs bochs_helper_funcs = {
.dpms = bochs_crtc_dpms,
- .mode_fixup = bochs_crtc_mode_fixup,
.mode_set = bochs_crtc_mode_set,
.mode_set_base = bochs_crtc_mode_set_base,
.prepare = bochs_crtc_prepare,
--
2.5.0
[PATCH 14/16] drm/fsl-dcu: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index d8ab8f0..9aa6ad5 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -72,13 +72,6 @@ static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
dev_err(fsl_dev->dev, "Enable CRTC failed\n");
}
-static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -153,7 +146,6 @@ static const struct drm_crtc_helper_funcs
fsl_dcu_drm_crtc_helper_funcs = {
.atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
.disable = fsl_dcu_drm_disable_crtc,
.enable = fsl_dcu_drm_crtc_enable,
- .mode_fixup = fsl_dcu_drm_crtc_mode_fixup,
.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
};
--
2.5.0
[PATCH 13/16] drm/virtio: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/virtio/virtgpu_display.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c
b/drivers/gpu/drm/virtio/virtgpu_display.c
index a165f03..6a6cb73 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -237,13 +237,6 @@ virtio_gpu_framebuffer_init(struct drm_device *dev,
return 0;
}
-static bool virtio_gpu_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void virtio_gpu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -277,7 +270,6 @@ static int virtio_gpu_crtc_atomic_check(struct drm_crtc
*crtc,
static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = {
.enable= virtio_gpu_crtc_enable,
.disable = virtio_gpu_crtc_disable,
- .mode_fixup= virtio_gpu_crtc_mode_fixup,
.mode_set_nofb = virtio_gpu_crtc_mode_set_nofb,
.atomic_check = virtio_gpu_crtc_atomic_check,
};
--
2.5.0
[PATCH 12/16] drm/nouveau/dispnv04: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/nouveau/dispnv04/crtc.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 6f04397..55ccbf0 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -227,13 +227,6 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
}
-static bool
-nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void
nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
@@ -1093,7 +1086,6 @@ static const struct drm_crtc_helper_funcs
nv04_crtc_helper_funcs = {
.dpms = nv_crtc_dpms,
.prepare = nv_crtc_prepare,
.commit = nv_crtc_commit,
- .mode_fixup = nv_crtc_mode_fixup,
.mode_set = nv_crtc_mode_set,
.mode_set_base = nv04_crtc_mode_set_base,
.mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
--
2.5.0
[PATCH 11/16] drm/atmel-hldcd: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 9863291..58c4f78 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -121,13 +121,6 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc
*c)
cfg);
}
-static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
{
struct drm_device *dev = c->dev;
@@ -261,7 +254,6 @@ static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc
*crtc,
}
static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
- .mode_fixup = atmel_hlcdc_crtc_mode_fixup,
.mode_set = drm_helper_crtc_mode_set,
.mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
.mode_set_base = drm_helper_crtc_mode_set_base,
@@ -349,4 +341,3 @@ fail:
atmel_hlcdc_crtc_destroy(&crtc->base);
return ret;
}
-
--
2.5.0
[PATCH 10/16] drm/sti: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/sti/sti_crtc.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/sti/sti_crtc.c b/drivers/gpu/drm/sti/sti_crtc.c
index de11c7c..e04deed 100644
--- a/drivers/gpu/drm/sti/sti_crtc.c
+++ b/drivers/gpu/drm/sti/sti_crtc.c
@@ -51,14 +51,6 @@ static void sti_crtc_disabling(struct drm_crtc *crtc)
mixer->status = STI_MIXER_DISABLING;
}
-static bool sti_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- /* accept the provided drm_display_mode, do not fix it up */
- return true;
-}
-
static int
sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
@@ -229,7 +221,6 @@ static void sti_crtc_atomic_flush(struct drm_crtc *crtc,
static const struct drm_crtc_helper_funcs sti_crtc_helper_funcs = {
.enable = sti_crtc_enable,
.disable = sti_crtc_disabling,
- .mode_fixup = sti_crtc_mode_fixup,
.mode_set = drm_helper_crtc_mode_set,
.mode_set_nofb = sti_crtc_mode_set_nofb,
.mode_set_base = drm_helper_crtc_mode_set_base,
--
2.5.0
[PATCH 09/16] drm/shmobile: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/shmobile/shmob_drm_crtc.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
index 27342fd..88643ab 100644
--- a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
+++ b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
@@ -359,13 +359,6 @@ static void shmob_drm_crtc_dpms(struct drm_crtc *crtc, int
mode)
scrtc->dpms = mode;
}
-static bool shmob_drm_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void shmob_drm_crtc_mode_prepare(struct drm_crtc *crtc)
{
shmob_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
@@ -431,7 +424,6 @@ static int shmob_drm_crtc_mode_set_base(struct drm_crtc
*crtc, int x, int y,
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
.dpms = shmob_drm_crtc_dpms,
- .mode_fixup = shmob_drm_crtc_mode_fixup,
.prepare = shmob_drm_crtc_mode_prepare,
.commit = shmob_drm_crtc_mode_commit,
.mode_set = shmob_drm_crtc_mode_set,
--
2.5.0
[PATCH 08/16] drm/msm/mdp: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 8
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 8
2 files changed, 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index 909d742..38329a6 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -147,13 +147,6 @@ static void mdp4_crtc_destroy(struct drm_crtc *crtc)
kfree(mdp4_crtc);
}
-static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
/* statically (for now) map planes to mixer stage (z-order): */
static const int idxs[] = {
[VG1] = 1,
@@ -508,7 +501,6 @@ static const struct drm_crtc_funcs mdp4_crtc_funcs = {
};
static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
- .mode_fixup = mdp4_crtc_mode_fixup,
.mode_set_nofb = mdp4_crtc_mode_set_nofb,
.disable = mdp4_crtc_disable,
.enable = mdp4_crtc_enable,
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index 46682aa..d6b45eb 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -185,13 +185,6 @@ static void mdp5_crtc_destroy(struct drm_crtc *crtc)
kfree(mdp5_crtc);
}
-static bool mdp5_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
/*
* blend_setup() - blend all the planes of a CRTC
*
@@ -634,7 +627,6 @@ static const struct drm_crtc_funcs mdp5_crtc_funcs = {
};
static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
- .mode_fixup = mdp5_crtc_mode_fixup,
.mode_set_nofb = mdp5_crtc_mode_set_nofb,
.disable = mdp5_crtc_disable,
.enable = mdp5_crtc_enable,
--
2.5.0
[PATCH 07/16] drm/omapdrm: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/omapdrm/omap_crtc.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c
b/drivers/gpu/drm/omapdrm/omap_crtc.c
index d38fcbc..483acdb 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -330,13 +330,6 @@ static void omap_crtc_destroy(struct drm_crtc *crtc)
kfree(omap_crtc);
}
-static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void omap_crtc_enable(struct drm_crtc *crtc)
{
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
@@ -451,7 +444,6 @@ static const struct drm_crtc_funcs omap_crtc_funcs = {
};
static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
- .mode_fixup = omap_crtc_mode_fixup,
.mode_set_nofb = omap_crtc_mode_set_nofb,
.disable = omap_crtc_disable,
.enable = omap_crtc_enable,
--
2.5.0
[PATCH 06/16] drm/rcar-du: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 4ec80ae..627abc80 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -468,14 +468,6 @@ static void rcar_du_crtc_disable(struct drm_crtc *crtc)
rcrtc->outputs = 0;
}
-static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- /* TODO Fixup modes */
- return true;
-}
-
static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
@@ -502,7 +494,6 @@ static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
}
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
- .mode_fixup = rcar_du_crtc_mode_fixup,
.disable = rcar_du_crtc_disable,
.enable = rcar_du_crtc_enable,
.atomic_begin = rcar_du_crtc_atomic_begin,
--
2.5.0
[PATCH 05/16] drm/gma: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/gma500/cdv_intel_display.c | 13 ++---
drivers/gpu/drm/gma500/gma_display.c | 7 ---
drivers/gpu/drm/gma500/gma_display.h | 3 ---
drivers/gpu/drm/gma500/mdfld_intel_display.c | 2 --
drivers/gpu/drm/gma500/oaktrail_crtc.c | 1 -
drivers/gpu/drm/gma500/psb_intel_display.c | 1 -
6 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c
b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 6126546..17db4b4 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -116,7 +116,7 @@ static const struct gma_limit_t cdv_intel_limits[] = {
.p1 = {.min = 1, .max = 10},
.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
.find_pll = cdv_intel_find_dp_pll,
-}
+ }
};
#define _wait_for(COND, MS, W) ({ \
@@ -245,7 +245,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct
drm_crtc *crtc,
/* We don't know what the other fields of these regs are, so
* leave them in place.
*/
- /*
+ /*
* The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
* for the pipe A/B. Display spec 1.06 has wrong definition.
* Correct definition is like below:
@@ -256,7 +256,7 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct
drm_crtc *crtc,
*
* if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
*
-*/
+*/
ret = cdv_sb_read(dev, ref_sfr, &ref_value);
if (ret)
return ret;
@@ -646,7 +646,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
* for DP/eDP. When using SSC clock, the ref clk is
100MHz.Otherwise
* it will be 27MHz. From the VBIOS code it seems that the pipe
A choose
* 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
-*/
+*/
if (pipe == 0)
refclk = 27000;
else
@@ -659,7 +659,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
}
drm_mode_debug_printmodeline(adjusted_mode);
-
+
limit = gma_crtc->clock_funcs->limit(crtc, refclk);
ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
@@ -721,7 +721,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
pipeconf |= PIPE_6BPC;
} else
pipeconf |= PIPE_8BPC;
-
+
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -974,7 +974,6 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct
drm_device *dev,
const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
.dpms = gma_crtc_dpms,
- .mode_fixup = gma_crtc_mode_fixup,
.mode_set = cdv_intel_crtc_mode_set,
.mode_set_base = gma_pipe_set_base,
.prepare = gma_crtc_prepare,
diff --git a/drivers/gpu/drm/gma500/gma_display.c
b/drivers/gpu/drm/gma500/gma_display.c
index ff17af4..d6a5c77 100644
--- a/drivers/gpu/drm/gma500/gma_display.c
+++ b/drivers/gpu/drm/gma500/gma_display.c
@@ -485,13 +485,6 @@ bool gma_encoder_mode_fixup(struct drm_encoder *encoder,
return true;
}
-bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
-const struct drm_display_mode *mode,
-struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
void gma_crtc_prepare(struct drm_crtc *crtc)
{
const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
diff --git a/drivers/gpu/drm/gma500/gma_display.h
b/drivers/gpu/drm/gma500/gma_display.h
index ed569d8..fc64241 100644
--- a/drivers/gpu/drm/gma500/gma_display.h
+++ b/drivers/gpu/drm/gma500/gma_display.h
@@ -75,9 +75,6 @@ extern void gma_crtc_load_lut(struct drm_crtc *crtc);
extern void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
u16 *blue, u32 start, u32 size);
extern void gma_crtc_dpms(struct drm_crtc *crtc, int mode);
-extern bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode);
extern void gma_crtc_prepare(struct drm_crtc *crtc);
extern void gma_crtc_commit(struct drm_crtc *crtc);
extern void gma_crtc_disable(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/gma500/mdfld_intel_display.c
b/drivers/gpu/drm/gma500/mdfld_intel_display.c
index acd3834..92e3f93e 100644
--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
+++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
@@ -1026,10 +1026,8 @@ mrst_crtc_mode_set_exit:
const struct drm_crtc_helper_funcs mdfld_
[PATCH 04/16] drm/udl: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/udl/udl_modeset.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/udl/udl_modeset.c
b/drivers/gpu/drm/udl/udl_modeset.c
index 160ef2a..b87afee 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -279,14 +279,6 @@ static void udl_crtc_dpms(struct drm_crtc *crtc, int mode)
}
-static bool udl_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-
-{
- return true;
-}
-
#if 0
static int
udl_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
@@ -402,7 +394,6 @@ static void udl_crtc_commit(struct drm_crtc *crtc)
static const struct drm_crtc_helper_funcs udl_helper_funcs = {
.dpms = udl_crtc_dpms,
- .mode_fixup = udl_crtc_mode_fixup,
.mode_set = udl_crtc_mode_set,
.prepare = udl_crtc_prepare,
.commit = udl_crtc_commit,
--
2.5.0
[PATCH 03/16] drm/mgag200: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/mgag200/mgag200_mode.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c
b/drivers/gpu/drm/mgag200/mgag200_mode.c
index dc13c48..aa99c40 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -92,18 +92,6 @@ static inline void mga_wait_busy(struct mga_device *mdev)
} while ((status & 0x01) && time_before(jiffies, timeout));
}
-/*
- * The core passes the desired mode to the CRTC code to see whether any
- * CRTC-specific modifications need to be made to it. We're in a position
- * to just pass that straight through, so this does nothing
- */
-static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
#define P_ARRAY_SIZE 9
static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
@@ -1410,7 +1398,6 @@ static const struct drm_crtc_funcs mga_crtc_funcs = {
static const struct drm_crtc_helper_funcs mga_helper_funcs = {
.disable = mga_crtc_disable,
.dpms = mga_crtc_dpms,
- .mode_fixup = mga_crtc_mode_fixup,
.mode_set = mga_crtc_mode_set,
.mode_set_base = mga_crtc_mode_set_base,
.prepare = mga_crtc_prepare,
--
2.5.0
[PATCH 02/16] drm/cirrus: removed optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/cirrus/cirrus_mode.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/cirrus/cirrus_mode.c
b/drivers/gpu/drm/cirrus/cirrus_mode.c
index 4a02854..e7334a8 100644
--- a/drivers/gpu/drm/cirrus/cirrus_mode.c
+++ b/drivers/gpu/drm/cirrus/cirrus_mode.c
@@ -91,18 +91,6 @@ static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
WREG_GFX(0xe, gr0e);
}
-/*
- * The core passes the desired mode to the CRTC code to see whether any
- * CRTC-specific modifications need to be made to it. We're in a position
- * to just pass that straight through, so this does nothing
- */
-static bool cirrus_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
static void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
{
struct cirrus_device *cdev = crtc->dev->dev_private;
@@ -372,7 +360,6 @@ static const struct drm_crtc_funcs cirrus_crtc_funcs = {
static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
.dpms = cirrus_crtc_dpms,
- .mode_fixup = cirrus_crtc_mode_fixup,
.mode_set = cirrus_crtc_mode_set,
.mode_set_base = cirrus_crtc_mode_set_base,
.prepare = cirrus_crtc_prepare,
--
2.5.0
[PATCH 01/16] drm: fixes crct set_mode when crtc mode_fixup is null.
This patch set nukes all the dummy crtc mode_fixup implementations.
(made on top of Daniel topic/drm-misc branch)
Signed-off-by: Carlos Palminha
---
drivers/gpu/drm/drm_crtc_helper.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc_helper.c
b/drivers/gpu/drm/drm_crtc_helper.c
index e70d064..7539eea 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -343,9 +343,12 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
}
}
- if (!(ret = crtc_funcs->mode_fixup(crtc, mode, adjusted_mode))) {
- DRM_DEBUG_KMS("CRTC fixup failed\n");
- goto done;
+ if (crtc_funcs->mode_fixup) {
+ if (!(ret = crtc_funcs->mode_fixup(crtc, mode,
+ adjusted_mode))) {
+ DRM_DEBUG_KMS("CRTC fixup failed\n");
+ goto done;
+ }
}
DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
--
2.5.0
[PATCH 00/16] drm crtc cleanup: nuke optional dummy crtc mode_fixup function.
This patch set nukes all the dummy crtc mode_fixup implementations. (made on top of Daniel topic/drm-misc branch) Carlos Palminha (16): drm: fixes crct set_mode when crtc mode_fixup is null. drm/cirrus: removed optional dummy crtc mode_fixup function. drm/mgag200: removed optional dummy crtc mode_fixup function. drm/udl: removed optional dummy crtc mode_fixup function. drm/gma: removed optional dummy crtc mode_fixup function. drm/rcar-du: removed optional dummy crtc mode_fixup function. drm/omapdrm: removed optional dummy crtc mode_fixup function. drm/msm/mdp: removed optional dummy crtc mode_fixup function. drm/shmobile: removed optional dummy crtc mode_fixup function. drm/sti: removed optional dummy crtc mode_fixup function. drm/atmel-hldcd: removed optional dummy crtc mode_fixup function. drm/nouveau/dispnv04: removed optional dummy crtc mode_fixup function. drm/virtio: removed optional dummy crtc mode_fixup function. drm/fsl-dcu: removed optional dummy crtc mode_fixup function. drm/bochs: removed optional dummy crtc mode_fixup function. drm/ast: removed optional dummy crtc mode_fixup function. drivers/gpu/drm/ast/ast_mode.c | 8 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 9 - drivers/gpu/drm/bochs/bochs_kms.c | 8 drivers/gpu/drm/cirrus/cirrus_mode.c | 13 - drivers/gpu/drm/drm_crtc_helper.c | 9 ++--- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 drivers/gpu/drm/gma500/cdv_intel_display.c | 13 ++--- drivers/gpu/drm/gma500/gma_display.c | 7 --- drivers/gpu/drm/gma500/gma_display.h | 3 --- drivers/gpu/drm/gma500/mdfld_intel_display.c | 2 -- drivers/gpu/drm/gma500/oaktrail_crtc.c | 1 - drivers/gpu/drm/gma500/psb_intel_display.c | 1 - drivers/gpu/drm/mgag200/mgag200_mode.c | 13 - drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c | 8 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 8 drivers/gpu/drm/nouveau/dispnv04/crtc.c| 8 drivers/gpu/drm/omapdrm/omap_crtc.c| 8 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 9 - drivers/gpu/drm/shmobile/shmob_drm_crtc.c | 8 drivers/gpu/drm/sti/sti_crtc.c | 9 - drivers/gpu/drm/udl/udl_modeset.c | 9 - drivers/gpu/drm/virtio/virtgpu_display.c | 8 22 files changed, 12 insertions(+), 158 deletions(-) -- 2.5.0
[REGRESSION] i915: No HDMI output with 4.4
On Tue, Feb 16, 2016 at 12:58:56PM +0200, Oleksandr Natalenko wrote: > Ville, Daniel, > > I've just got another monitor and another DVI-HDMI cable, and here what I've > got. > > ===Single Link DVI-D cable with 3 different monitors=== > > Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG > 23MP65HQ-P === > not working I presume the above LG screen is what you've called previously "old monitor"? > Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG > 23MP67HQ-P === > not working > Computer DVI âââ DVI-D (Single Link)/HDMI cable âââ HDMI LG > 23MP55HQ-P === > works! > > ===Dual Link DVI-D cable with monitor that doesn't work with Single Link > cable=== > > Computer DVI âââ DVI-D (Dual Link)/HDMI cable âââ HDMI LG > 23MP65HQ-P === > works! Funky. Can you pls grab the debug logs (with the special patches from Ville) for this case? I wonder why suddenly different cable and it works. Also: Is this one of these older-ish screens where you must have a dual-link cable to drive it at full resolution&refresh rate? -Daniel > ===Laptop with HDMI output=== > > Laptop HDMI âââ HDMI/HDMI cable âââ HDMI LG 23MP65HQ-P === works! > > I'd say that single link DVI cables are broken with new kernel, but one of > monitors could work with such a cable. So I have no idea :(. > > Regards, > Oleksandr. > > 15.02.2016 17:42, Daniel Vetter wrote: > >The other downside is that it'll make us non-compliant, which was the > >point of this entire ordeal: HDMI spec forbids us from starting any i2c > >transactions when the hpd isn't signalling a present screen. > > > >So maybe we need to buy one of these broken screens. > > > >Oleksandr, what exact model are you using? And any chance that you could > >test this on some other machine with intel gfx and latest kernel, just to > >make sure this really is some issue with the sink and not with the machine > >itself? And I guess you've tested with some other hdmi sink, and that > >works? -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
