[PATCH v2] drm/amd/powerplay: use ARRAY_SIZE() to calculate array size.
Am 13.05.2016 um 19:36 schrieb Muhammad Falak R Wani:
> It is preferred to use ARRAY_SIZE() for size calculation, instead
> using sizeof(array)/sizeof(*array). It makes the code more readable.
>
> Signed-off-by: Muhammad Falak R Wani
Reviewed-by: Christian König
Thanks for the cleanup,
Christian.
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> index da18f44..87c023e 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
> @@ -639,7 +639,7 @@ static int cz_smu_populate_firmware_entries(struct
> pp_smumgr *smumgr)
>
> cz_smu->driver_buffer_length = 0;
>
> - for (i = 0; i < sizeof(firmware_list)/sizeof(*firmware_list); i++) {
> + for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
>
> firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
> firmware_list[i]);
[PATCH v2] drm/nouveau: check function before using it
Do not unconditionally invoke function 0x1B without checking for its
availability, it leads to an infinite loop on some firmware.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=104791
Fixes: 5addcf0a5f0fad ("nouveau: add runtime PM support (v0.9)")
Signed-off-by: Peter Wu
---
v2: only write optimus_funcs when an Optimus DSM is found.
---
drivers/gpu/drm/nouveau/nouveau_acpi.c | 43 ++
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index cdf5227..009712a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -45,6 +45,7 @@
static struct nouveau_dsm_priv {
bool dsm_detected;
bool optimus_detected;
+ bool flags_func_detected;
acpi_handle dhandle;
acpi_handle rom_handle;
} nouveau_dsm_priv;
@@ -58,7 +59,6 @@ bool nouveau_is_v1_dsm(void) {
}
#define NOUVEAU_DSM_HAS_MUX 0x1
-#define NOUVEAU_DSM_HAS_OPT 0x2
#ifdef CONFIG_VGA_SWITCHEROO
static const char nouveau_dsm_muid[] = {
@@ -110,9 +110,9 @@ static int nouveau_optimus_dsm(acpi_handle handle, int
func, int arg, uint32_t *
* requirements on the fourth parameter, so a private implementation
* instead of using acpi_check_dsm().
*/
-static int nouveau_check_optimus_dsm(acpi_handle handle)
+static uint32_t nouveau_check_optimus_dsm(acpi_handle handle)
{
- int result;
+ uint32_t result;
/*
* Function 0 returns a Buffer containing available functions.
@@ -123,9 +123,13 @@ static int nouveau_check_optimus_dsm(acpi_handle handle)
/*
* ACPI Spec v4 9.14.1: if bit 0 is zero, no function is supported.
-* If the n-th bit is enabled, function n is supported
+* If the n-th bit is enabled, function n is supported.
+* Check for both bit zero and the NOUVEAU_DSM_OPTIMUS_CAPS since
+* some implementations return 0x8001 on invalid parameters.
*/
- return result & 1 && result & (1 << NOUVEAU_DSM_OPTIMUS_CAPS);
+ if (result & 1 && result & (1 << NOUVEAU_DSM_OPTIMUS_CAPS))
+ return result;
+ return 0;
}
static int nouveau_dsm(acpi_handle handle, int func, int arg)
@@ -212,10 +216,11 @@ static const struct vga_switcheroo_handler
nouveau_dsm_handler = {
.get_client_id = nouveau_dsm_get_client_id,
};
-static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
+static int nouveau_dsm_pci_probe(struct pci_dev *pdev, uint32_t *optimus_funcs)
{
acpi_handle dhandle;
int retval = 0;
+ uint32_t supported_funcs;
dhandle = ACPI_HANDLE(&pdev->dev);
if (!dhandle)
@@ -228,11 +233,10 @@ static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
1 << NOUVEAU_DSM_POWER))
retval |= NOUVEAU_DSM_HAS_MUX;
- if (nouveau_check_optimus_dsm(dhandle))
- retval |= NOUVEAU_DSM_HAS_OPT;
-
- if (retval & NOUVEAU_DSM_HAS_OPT) {
+ supported_funcs = nouveau_check_optimus_dsm(dhandle);
+ if (supported_funcs) {
uint32_t result;
+ *optimus_funcs = supported_funcs;
nouveau_optimus_dsm(dhandle, NOUVEAU_DSM_OPTIMUS_CAPS, 0,
&result);
dev_info(&pdev->dev, "optimus capabilities: %s, status %s%s\n",
@@ -252,7 +256,7 @@ static bool nouveau_dsm_detect(void)
struct acpi_buffer buffer = {sizeof(acpi_method_name),
acpi_method_name};
struct pci_dev *pdev = NULL;
int has_dsm = 0;
- int has_optimus = 0;
+ uint32_t optimus_funcs = 0;
int vga_count = 0;
bool guid_valid;
int retval;
@@ -268,30 +272,28 @@ static bool nouveau_dsm_detect(void)
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) !=
NULL) {
vga_count++;
- retval = nouveau_dsm_pci_probe(pdev);
+ retval = nouveau_dsm_pci_probe(pdev, &optimus_funcs);
if (retval & NOUVEAU_DSM_HAS_MUX)
has_dsm |= 1;
- if (retval & NOUVEAU_DSM_HAS_OPT)
- has_optimus = 1;
}
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pdev)) != NULL)
{
vga_count++;
- retval = nouveau_dsm_pci_probe(pdev);
+ retval = nouveau_dsm_pci_probe(pdev, &optimus_funcs);
if (retval & NOUVEAU_DSM_HAS_MUX)
has_dsm |= 1;
- if (retval & NOUVEAU_DSM_HAS_OPT)
- has_optimus = 1;
}
/* find the optimus DSM or the old v1 DSM */
- if (has_optimus == 1) {
+ if (optimus_funcs) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
&buffer);
printk(KERN_INFO "VGA switcheroo: detected Optimus DSM method
%s handle\n",
[Bug 95358] Tonga no hdmi audio on DAL 4.7 works on DAL 4.6
https://bugs.freedesktop.org/show_bug.cgi?id=95358 --- Comment #4 from Andy Furniss --- Possible progress with the git aspect - while reading about reflog I saw a comment which lead me to doing - git log --walk-reflogs origin/drm-next-4.7-wip-dal which apparently gets me a sha for every time I did git fetch origin and dal got updated. Looks promising, but I haven't had time to test it out yet. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/95d44d8b/attachment.html>
[PATCH 4/4] tests/amdgpu: adapt to new polaris10/11 uvd fw
Am 14.05.2016 um 16:19 schrieb Emil Velikov:
> Hi all,
>
> On 13 May 2016 at 17:48, Alex Deucher wrote:
>> From: Sonny Jiang
>>
>> Signed-off-by: Sonny Jiang
>> Reviewed-by: Alex Deucher
>> Signed-off-by: Alex Deucher
>> ---
>> tests/amdgpu/cs_tests.c | 48
>> ++--
>> 1 file changed, 42 insertions(+), 6 deletions(-)
>>
>> diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
>> index c6930c0..a01ee48 100644
>> --- a/tests/amdgpu/cs_tests.c
>> +++ b/tests/amdgpu/cs_tests.c
>> @@ -43,6 +43,8 @@ static amdgpu_device_handle device_handle;
>> static uint32_t major_version;
>> static uint32_t minor_version;
>> static uint32_t family_id;
>> +static uint32_t chip_rev;
>> +static uint32_t chip_id;
>>
>> static amdgpu_context_handle context_handle;
>> static amdgpu_bo_handle ib_handle;
>> @@ -78,6 +80,9 @@ int suite_cs_tests_init(void)
>> return CUE_SINIT_FAILED;
>>
>> family_id = device_handle->info.family_id;
>> + /* VI asic POLARIS10/11 have specific external_rev_id */
>> + chip_rev = device_handle->info.chip_rev;
>> + chip_id = device_handle->info.chip_external_rev;
>>
>> r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>> if (r)
>> @@ -200,8 +205,17 @@ static void amdgpu_cs_uvd_create(void)
>> CU_ASSERT_EQUAL(r, 0);
>>
>> memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
>> - if (family_id >= AMDGPU_FAMILY_VI)
>> + if (family_id >= AMDGPU_FAMILY_VI) {
>> ((uint8_t*)msg)[0x10] = 7;
>> + /* chip polaris 10/11 */
>> + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
>> + /* dpb size */
>> + ((uint8_t*)msg)[0x28] = 0x00;
>> + ((uint8_t*)msg)[0x29] = 0x94;
>> + ((uint8_t*)msg)[0x2A] = 0x6B;
>> + ((uint8_t*)msg)[0x2B] = 0x00;
> I realise that many of the UVD stuff is 'top secret', although one
> should really try and give symbolic names for magic numbers. With them
> it's be easier and less error prone when/if the above value changes.
Actually we have exposed mostly everything in the UVD headers in mesa
and those binary values here are just captured example streams.
Saying so I would also prefer that we don't patch the messages on the
fly as necessary, but rather have a full copy for each chipset family
they differ. On the other hand it's just the unit tests.
Regards,
Christian.
>
>> + }
>> + }
>>
>> r = amdgpu_bo_cpu_unmap(buf_handle);
>> CU_ASSERT_EQUAL(r, 0);
>> @@ -230,8 +244,8 @@ static void amdgpu_cs_uvd_create(void)
>>
>> static void amdgpu_cs_uvd_decode(void)
>> {
>> - const unsigned dpb_size = 15923584, dt_size = 737280;
>> - uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr;
>> + const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size =
>> 737280;
>> + uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr,
>> it_addr;
>> struct amdgpu_bo_alloc_request req = {0};
>> amdgpu_bo_handle buf_handle;
>> amdgpu_va_handle va_handle;
>> @@ -269,8 +283,21 @@ static void amdgpu_cs_uvd_decode(void)
>> memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
>> if (family_id >= AMDGPU_FAMILY_VI) {
>> ptr[0x10] = 7;
>> - ptr[0x98] = 0xb0;
>> - ptr[0x99] = 0x1;
>> + ptr[0x98] = 0x00;
>> + ptr[0x99] = 0x02;
>> + /* chip polaris10/11 */
>> + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
>> + /*dpb size */
>> + ptr[0x24] = 0x00;
>> + ptr[0x25] = 0x94;
>> + ptr[0x26] = 0x6B;
>> + ptr[0x27] = 0x00;
> Based on the const dpb_size a few lines above... this value is
> incorrect. So either the comment is off, or one/both of the values ?
>
>
>> + /*ctx size */
>> + ptr[0x2C] = 0x00;
>> + ptr[0x2D] = 0xAF;
>> + ptr[0x2E] = 0x50;
>> + ptr[0x2F] = 0x00;
>> + }
> While this one does match ctx_size above, one should really set a
> macro for these magic values and use them throughout. Also considering
> that there's three almost identical places where this happens perhaps
> it's better to have a common helper ?
>
> Regards,
> Emil
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 92059] [radeonsi, apitrace] Missing textures and geometry in "Middle-earth: Shadow of Mordor"
https://bugs.freedesktop.org/show_bug.cgi?id=92059 Vedran MiletiÄ changed: What|Removed |Added CC||rivanvx at gmail.com --- Comment #23 from Vedran MiletiÄ --- Created attachment 123752 --> https://bugs.freedesktop.org/attachment.cgi?id=123752&action=edit Screenshot on Tonga 380X with Mesa git-59156b2 Great progress, but there are still some glitches. Game is running with MESA_GL_VERSION_OVERRIDE=4.3 MESA_GLSL_VERSION_OVERRIDE=430 %command% -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/f3d7b912/attachment.html>
[Bug 104791] ACPI errors on Lenovo C50-30 (AE_AML_INFINITE_LOOP, argument type mismatch)
https://bugzilla.kernel.org/show_bug.cgi?id=104791
Peter Wu changed:
What|Removed |Added
CC||peter at lekensteyn.nl
--- Comment #6 from Peter Wu ---
The problem is that nouveau_switcheroo_optimus_dsm() unconditionally calls
function 0x1B ("NOUVEAU_DSM_OPTIMUS_FLAGS") without checking that this function
is actually supported. Lenovo's firmware decides to run into an infinite loop
in this case instead of returning an error code.
Proposed patch:
https://lkml.kernel.org/r/1463244575-3515-1-git-send-email-peter at
lekensteyn.nl
--
You are receiving this mail because:
You are watching the assignee of the bug.
[PATCH] drm.h: Handle DragonFly like Linux
Hi François, On 14 May 2016 at 08:13, François Tigeot wrote: > The drm code in DragonFly uses a local Linux implementation which doesn't > define the __linux__ macro. > > Use __DragonFly__ instead in order to not try to compile non-Linux code. Does that meant that the workarounds in the else statements don't work ? I doubt that anyone will mind if we update/correct them. Alternatively if one insists on using the __linux__ route here, imho it's better to just set the define it in your build. All that aside, for next revision/future work please check the documentation [1] and add your s-o-b line. Also, please base your work against Dave's drm-next branch [2] Thank you Emil [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/SubmittingPatches See section 11 [2] https://cgit.freedesktop.org/~airlied/linux
[PATCH 17/17] drm/amdgpu: enable SI DPM
From: Maruthi Srinivas Bayyavarapu
Signed-off-by: Maruthi Bayyavarapu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 10 ++
drivers/gpu/drm/amd/amdgpu/si.c | 8
3 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index eab90ae..9b722137 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -30,7 +30,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o
kv_dpm.o \
ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o
vce_v2_0.o \
amdgpu_amdkfd_gfx_v7.o
-amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o
dce_v6_0.o
+amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o
dce_v6_0.o si_dpm.o si_smc.o
amdgpu-y += \
vi.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 6bd961f..2452dc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -30,6 +30,7 @@
#include "amdgpu_pm.h"
#include
#include "amdgpu_powerplay.h"
+#include "si_dpm.h"
#include "cik_dpm.h"
#include "vi_dpm.h"
@@ -60,6 +61,15 @@ static int amdgpu_powerplay_init(struct amdgpu_device *adev)
amd_pp->pp_handle = (void *)adev;
switch (adev->asic_type) {
+#ifdef CONFIG_DRM_AMDGPU_SI
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+ amd_pp->ip_funcs = &si_dpm_ip_funcs;
+ break;
+#endif
#ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_BONAIRE:
case CHIP_HAWAII:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 337b387..03aeade 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1046,6 +1046,7 @@ u32 si_get_xclk(struct amdgpu_device *adev)
return reference_clock;
}
+
//xxx:not implemented
static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
{
@@ -1799,14 +1800,13 @@ static const struct amdgpu_ip_block_version
verde_ip_blocks[] =
.rev = 0,
.funcs = &si_ih_ip_funcs,
},
-/* {
+ {
.type = AMD_IP_BLOCK_TYPE_SMC,
.major = 6,
.minor = 0,
.rev = 0,
- .funcs = &si_null_ip_funcs,
+ .funcs = &amdgpu_pp_ip_funcs,
},
- */
{
.type = AMD_IP_BLOCK_TYPE_DCE,
.major = 6,
@@ -1874,7 +1874,7 @@ static const struct amdgpu_ip_block_version
hainan_ip_blocks[] =
.major = 6,
.minor = 0,
.rev = 0,
- .funcs = &si_null_ip_funcs,
+ .funcs = &amdgpu_pp_ip_funcs,
},
{
.type = AMD_IP_BLOCK_TYPE_GFX,
--
2.5.5
[PATCH 16/17] drm/amdgpu: add SI DPM support (v3)
From: Maruthi Srinivas Bayyavarapu
v2: corrected register offset shift
v3: rebase fixes
Signed-off-by: Maruthi Bayyavarapu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h |5 +
drivers/gpu/drm/amd/amdgpu/r600_dpm.h | 127 +
drivers/gpu/drm/amd/amdgpu/si_dpm.c | 7982 +
drivers/gpu/drm/amd/amdgpu/si_dpm.h | 1015 +
4 files changed, 9129 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/r600_dpm.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dpm.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dpm.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e7b28d7..f59938f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1824,6 +1824,9 @@ struct amdgpu_asic_funcs {
/* MM block clocks */
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
+ /* static power management */
+ int (*get_pcie_lanes)(struct amdgpu_device *adev);
+ void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
};
/*
@@ -2208,6 +2211,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
#define amdgpu_asic_set_uvd_clocks(adev, v, d)
(adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
#define amdgpu_asic_set_vce_clocks(adev, ev, ec)
(adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
+#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
+#define amdgpu_set_pcie_lanes(adev, l)
(adev)->asic_funcs->set_pcie_lanes((adev), (l))
#define amdgpu_asic_get_gpu_clock_counter(adev)
(adev)->asic_funcs->get_gpu_clock_counter((adev))
#define amdgpu_asic_read_disabled_bios(adev)
(adev)->asic_funcs->read_disabled_bios((adev))
#define amdgpu_asic_read_bios_from_rom(adev, b, l)
(adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/r600_dpm.h
b/drivers/gpu/drm/amd/amdgpu/r600_dpm.h
new file mode 100644
index 000..055321f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/r600_dpm.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __R600_DPM_H__
+#define __R600_DPM_H__
+
+#define R600_ASI_DFLT1
+#define R600_BSP_DFLT0x41EB
+#define R600_BSU_DFLT0x2
+#define R600_AH_DFLT 5
+#define R600_RLP_DFLT25
+#define R600_RMP_DFLT65
+#define R600_LHP_DFLT40
+#define R600_LMP_DFLT15
+#define R600_TD_DFLT 0
+#define R600_UTC_DFLT_00 0x24
+#define R600_UTC_DFLT_01 0x22
+#define R600_UTC_DFLT_02 0x22
+#define R600_UTC_DFLT_03 0x22
+#define R600_UTC_DFLT_04 0x22
+#define R600_UTC_DFLT_05 0x22
+#define R600_UTC_DFLT_06 0x22
+#define R600_UTC_DFLT_07 0x22
+#define R600_UTC_DFLT_08 0x22
+#define R600_UTC_DFLT_09 0x22
+#define R600_UTC_DFLT_10 0x22
+#define R600_UTC_DFLT_11 0x22
+#define R600_UTC_DFLT_12 0x22
+#define R600_UTC_DFLT_13 0x22
+#define R600_UTC_DFLT_14 0x22
+#define R600_DTC_DFLT_00 0x24
+#define R600_DTC_DFLT_01
[PATCH 15/17] drm/amdgpu: add SI SMC support
From: Maruthi Srinivas Bayyavarapu
Signed-off-by: Maruthi Bayyavarapu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_smc.c | 280
drivers/gpu/drm/amd/amdgpu/sislands_smc.h | 423 ++
2 files changed, 703 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_smc.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/sislands_smc.h
diff --git a/drivers/gpu/drm/amd/amdgpu/si_smc.c
b/drivers/gpu/drm/amd/amdgpu/si_smc.c
new file mode 100644
index 000..214f37c
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/si_smc.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+
+#include
+#include "drmP.h"
+#include "amdgpu.h"
+#include "si/sid.h"
+#include "ppsmc.h"
+#include "amdgpu_ucode.h"
+#include "sislands_smc.h"
+
+static int si_set_smc_sram_address(struct amdgpu_device *adev,
+ u32 smc_address, u32 limit)
+{
+ if (smc_address & 3)
+ return -EINVAL;
+ if ((smc_address + 3) > limit)
+ return -EINVAL;
+
+ WREG32(SMC_IND_INDEX_0, smc_address);
+ WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
+
+ return 0;
+}
+
+int si_copy_bytes_to_smc(struct amdgpu_device *adev,
+u32 smc_start_address,
+const u8 *src, u32 byte_count, u32 limit)
+{
+ unsigned long flags;
+ int ret = 0;
+ u32 data, original_data, addr, extra_shift;
+
+ if (smc_start_address & 3)
+ return -EINVAL;
+ if ((smc_start_address + byte_count) > limit)
+ return -EINVAL;
+
+ addr = smc_start_address;
+
+ spin_lock_irqsave(&adev->smc_idx_lock, flags);
+ while (byte_count >= 4) {
+ /* SMC address space is BE */
+ data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
+
+ ret = si_set_smc_sram_address(adev, addr, limit);
+ if (ret)
+ goto done;
+
+ WREG32(SMC_IND_DATA_0, data);
+
+ src += 4;
+ byte_count -= 4;
+ addr += 4;
+ }
+
+ /* RMW for the final bytes */
+ if (byte_count > 0) {
+ data = 0;
+
+ ret = si_set_smc_sram_address(adev, addr, limit);
+ if (ret)
+ goto done;
+
+ original_data = RREG32(SMC_IND_DATA_0);
+
+ extra_shift = 8 * (4 - byte_count);
+
+ while (byte_count > 0) {
+ /* SMC address space is BE */
+ data = (data << 8) + *src++;
+ byte_count--;
+ }
+
+ data <<= extra_shift;
+
+ data |= (original_data & ~((~0UL) << extra_shift));
+
+ ret = si_set_smc_sram_address(adev, addr, limit);
+ if (ret)
+ goto done;
+
+ WREG32(SMC_IND_DATA_0, data);
+ }
+
+done:
+ spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
+
+ return ret;
+}
+
+void si_start_smc(struct amdgpu_device *adev)
+{
+ u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
+
+ tmp &= ~RST_REG;
+
+ WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
+}
+
+void si_reset_smc(struct amdgpu_device *adev)
+{
+ u32 tmp;
+
+ RREG32(CB_CGTT_SCLK_CTRL);
+ RREG32(CB_CGTT_SCLK_CTRL);
+ RREG32(CB_CGTT_SCLK_CTRL);
+ RREG32(CB_CGTT_SCLK_CTRL);
+
+ tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
+ tmp |= RST_REG;
+ WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
+}
+
+int si_program_jump_on_start(struct amdgpu_device *adev)
+{
+ static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
+
+ return si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
+}
+
+void
[PATCH 14/17] drm/amdgpu: add si dpm support in amdgpu_atombios
From: Maruthi Srinivas Bayyavarapu
v2: renamed _atom_ to _atombios_ for consistency
added ulClockParams to _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 and
_COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 to avoid build break
Signed-off-by: Maruthi Bayyavarapu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 158 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 16 ++-
drivers/gpu/drm/amd/include/atombios.h | 2 +
3 files changed, 175 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 9df1bcb..033a22c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -960,6 +960,48 @@ int amdgpu_atombios_get_clock_dividers(struct
amdgpu_device *adev,
return -EINVAL;
switch (crev) {
+ case 2:
+ case 3:
+ case 5:
+ /* r6xx, r7xx, evergreen, ni, si.
+* TODO: add support for asic_type <= CHIP_RV770*/
+ if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
+ args.v3.ulClockParams = cpu_to_le32((clock_type << 24)
| clock);
+
+ amdgpu_atom_execute_table(adev->mode_info.atom_context,
index, (uint32_t *)&args);
+
+ dividers->post_div = args.v3.ucPostDiv;
+ dividers->enable_post_div = (args.v3.ucCntlFlag &
+
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
+ dividers->enable_dithen = (args.v3.ucCntlFlag &
+
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
+ dividers->whole_fb_div =
le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
+ dividers->frac_fb_div =
le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
+ dividers->ref_div = args.v3.ucRefDiv;
+ dividers->vco_mode = (args.v3.ucCntlFlag &
+ ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE)
? 1 : 0;
+ } else {
+ /* for SI we use ComputeMemoryClockParam for memory
plls */
+ if (adev->asic_type >= CHIP_TAHITI)
+ return -EINVAL;
+ args.v5.ulClockParams = cpu_to_le32((clock_type << 24)
| clock);
+ if (strobe_mode)
+ args.v5.ucInputFlag =
ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
+
+ amdgpu_atom_execute_table(adev->mode_info.atom_context,
index, (uint32_t *)&args);
+
+ dividers->post_div = args.v5.ucPostDiv;
+ dividers->enable_post_div = (args.v5.ucCntlFlag &
+
ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
+ dividers->enable_dithen = (args.v5.ucCntlFlag &
+
ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
+ dividers->whole_fb_div =
le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
+ dividers->frac_fb_div =
le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
+ dividers->ref_div = args.v5.ucRefDiv;
+ dividers->vco_mode = (args.v5.ucCntlFlag &
+ ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE)
? 1 : 0;
+ }
+ break;
case 4:
/* fusion */
args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
@@ -1104,6 +1146,32 @@ void amdgpu_atombios_set_engine_dram_timings(struct
amdgpu_device *adev,
amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
(uint32_t *)&args);
}
+void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
+ u16 *vddc, u16 *vddci, u16 *mvdd)
+{
+ struct amdgpu_mode_info *mode_info = &adev->mode_info;
+ int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
+ u8 frev, crev;
+ u16 data_offset;
+ union firmware_info *firmware_info;
+
+ *vddc = 0;
+ *vddci = 0;
+ *mvdd = 0;
+
+ if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
+ &frev, &crev, &data_offset)) {
+ firmware_info =
+ (union firmware_info *)(mode_info->atom_context->bios +
+ data_offset);
+ *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
+ if ((frev == 2) && (crev >= 2)) {
+ *vddci =
le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
+ *mvdd =
le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
+
[PATCH 13/17] drm/amdgpu: add si pciids v2
From: Ken Wang
Acked-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6ff5879..001e7af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -169,6 +169,80 @@ MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0:
autodetect (default))");
module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
static const struct pci_device_id pciidlist[] = {
+#ifdef CONFIG_DRM_AMDGPU_SI
+ {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
+ {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|AMD_IS_MOBILITY},
+ {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|AMD_IS_MOBILITY},
+ {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|AMD_IS_MOBILITY},
+ {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
+ {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
+ {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
+ {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
+ {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
+ {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|AMD_IS_MOBILITY},
+ {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
+ {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
+ {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
+ {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
+ {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|AMD_IS_MOBILITY},
+ {0x10
[PATCH 12/17] drm/amdgpu: add si specific logic into the device initialize function v2
From: Ken Wang
Reviewed-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c335538..d269740 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -52,6 +52,11 @@ static int amdgpu_debugfs_regs_init(struct amdgpu_device
*adev);
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
static const char *amdgpu_asic_name[] = {
+ "TAHITI",
+ "PITCAIRN",
+ "VERDE",
+ "OLAND",
+ "HAINAN",
"BONAIRE",
"KAVERI",
"KABINI",
@@ -1467,8 +1472,13 @@ int amdgpu_device_init(struct amdgpu_device *adev,
spin_lock_init(&adev->didt_idx_lock);
spin_lock_init(&adev->audio_endpt_idx_lock);
- adev->rmmio_base = pci_resource_start(adev->pdev, 5);
- adev->rmmio_size = pci_resource_len(adev->pdev, 5);
+ if (adev->asic_type >= CHIP_BONAIRE) {
+ adev->rmmio_base = pci_resource_start(adev->pdev, 5);
+ adev->rmmio_size = pci_resource_len(adev->pdev, 5);
+ } else {
+ adev->rmmio_base = pci_resource_start(adev->pdev, 2);
+ adev->rmmio_size = pci_resource_len(adev->pdev, 2);
+ }
adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
if (adev->rmmio == NULL) {
return -ENOMEM;
@@ -1476,8 +1486,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
- /* doorbell bar mapping */
- amdgpu_doorbell_init(adev);
+ if (adev->asic_type >= CHIP_BONAIRE) {
+ /* doorbell bar mapping */
+ amdgpu_doorbell_init(adev);
+ }
/* io port mapping */
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
--
2.5.5
[PATCH 11/17] drm/amdgpu: add si ip blocks setup v3
From: Ken Wang Reviewed-by: Christian König Signed-off-by: Ken Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bb8b149..c335538 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -39,6 +39,9 @@ #include "atom.h" #include "amdgpu_atombios.h" #include "amd_pcie.h" +#ifdef CONFIG_DRM_AMDGPU_SI +#include "si.h" +#endif #ifdef CONFIG_DRM_AMDGPU_CIK #include "cik.h" #endif @@ -1155,6 +1158,17 @@ static int amdgpu_early_init(struct amdgpu_device *adev) if (r) return r; break; +#ifdef CONFIG_DRM_AMDGPU_SI + case CHIP_VERDE: + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_OLAND: + case CHIP_HAINAN: + r = si_set_ip_blocks(adev); + if (r) + return r; + break; +#endif #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: case CHIP_HAWAII: -- 2.5.5
[PATCH 10/17] drm/amdgpu: add all the components for si into Makefile/kconfig v3
From: Ken Wang Reviewed-by: Christian König Signed-off-by: Ken Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Kconfig | 7 +++ drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 7335c04..39e5172 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -1,3 +1,10 @@ +config DRM_AMDGPU_SI + bool "Enable amdgpu support for SI parts" + depends on DRM_AMDGPU + help + Choose this option if you want to enable experimental support + for SI asics. + config DRM_AMDGPU_CIK bool "Enable amdgpu support for CIK parts" depends on DRM_AMDGPU diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index c7fcdce..eab90ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -30,6 +30,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \ amdgpu_amdkfd_gfx_v7.o +amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o + amdgpu-y += \ vi.o -- 2.5.5
[PATCH 09/17] drm/amdgpu: add si implementation v7
From: Ken Wang
v5: rebase fixes
v6: add mgcg arrays
v7: rebase fixes
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si.c | 1914 +
drivers/gpu/drm/amd/amdgpu/si.h | 33 +
drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 31 +
3 files changed, 1978 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/si.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/si.h
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
new file mode 100644
index 000..337b387
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -0,0 +1,1914 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_atombios.h"
+#include "amdgpu_ih.h"
+#include "amdgpu_uvd.h"
+#include "amdgpu_vce.h"
+#include "atom.h"
+#include "amdgpu_powerplay.h"
+#include "si/sid.h"
+#include "si_ih.h"
+#include "gfx_v6_0.h"
+#include "gmc_v6_0.h"
+#include "si_dma.h"
+#include "dce_v6_0.h"
+#include "si.h"
+
+static const u32 tahiti_golden_registers[] =
+{
+ 0x2684, 0x0001, 0x00018208,
+ 0x260c, 0x, 0x,
+ 0x260d, 0xf00f, 0x0400,
+ 0x260e, 0x0002021c, 0x00020200,
+ 0x031e, 0x0080, 0x,
+ 0x340c, 0x000300c0, 0x00800040,
+ 0x360c, 0x000300c0, 0x00800040,
+ 0x16ec, 0x00f0, 0x0070,
+ 0x16f0, 0x0020, 0x5010,
+ 0x1c0c, 0x31000311, 0x0011,
+ 0x09df, 0x0003, 0x07ff,
+ 0x0903, 0x07ff, 0x,
+ 0x2285, 0xf01f, 0x0007,
+ 0x22c9, 0x, 0x00ff,
+ 0x22c4, 0xff0f, 0x,
+ 0xa293, 0x07ff, 0x4e00,
+ 0xa0d4, 0x3f3f3fff, 0x2a00126a,
+ 0x000c, 0x00ff, 0x0040,
+ 0x000d, 0x0040, 0x4040,
+ 0x2440, 0x07ff, 0x0300,
+ 0x23a2, 0x01ff1f3f, 0x,
+ 0x23a1, 0x01ff1f3f, 0x,
+ 0x2418, 0x007f, 0x0020,
+ 0x2542, 0x0001, 0x0001,
+ 0x2b05, 0x0200, 0x02fb,
+ 0x2b04, 0x, 0x543b,
+ 0x2b03, 0x, 0xa9210876,
+ 0x2234, 0x, 0x000fff40,
+ 0x2235, 0x001f, 0x0010,
+ 0x0504, 0x2000, 0x20fffed8,
+ 0x0570, 0x000c0fc0, 0x000c0400
+};
+
+static const u32 tahiti_golden_registers2[] =
+{
+ 0x0319, 0x0001, 0x0001
+};
+
+static const u32 tahiti_golden_rlc_registers[] =
+{
+ 0x3109, 0x, 0x00601005,
+ 0x311f, 0x, 0x10104040,
+ 0x3122, 0x, 0x010a,
+ 0x30c5, 0x, 0x0800,
+ 0x30c3, 0x, 0x80f4,
+ 0x3d2a, 0x, 0x
+};
+
+static const u32 pitcairn_golden_registers[] =
+{
+ 0x2684, 0x0001, 0x00018208,
+ 0x260c, 0x, 0x,
+ 0x260d, 0xf00f, 0x0400,
+ 0x260e, 0x0002021c, 0x00020200,
+ 0x031e, 0x0080, 0x,
+ 0x340c, 0x000300c0, 0x00800040,
+ 0x360c, 0x000300c0, 0x00800040,
+ 0x16ec, 0x00f0, 0x0070,
+ 0x16f0, 0x0020, 0x5010,
+ 0x1c0c, 0x31000311, 0x0011,
+ 0x0ab9, 0x00073ffe, 0x22a2,
+ 0x0903, 0x07ff, 0x,
+ 0x2285, 0xf01f, 0x0007,
+ 0x22c9, 0x, 0x00ff,
+ 0x22c4, 0xff0f, 0x,
+ 0xa293, 0x07ff, 0x4e00,
+ 0xa0d4, 0x3f3f3fff, 0x2a00126a,
+ 0x000c, 0x00ff, 0x0040,
+ 0x000d, 0x0040, 0x4040,
+ 0x2440, 0x07ff, 0x0300,
+ 0x2418, 0x007f, 0x0020,
+ 0x2542, 0x0001, 0x0001,
+ 0x2b05, 0x03ff, 0x00f7,
+ 0x2b04, 0x, 0x,
+ 0x2b03, 0x, 0x32761054,
+ 0x2235, 0x001f, 0x0010,
+ 0x0570, 0x000c0fc0, 0x000
[PATCH 08/17] drm/amdgpu: add DMA implementation for si v6
From: Ken Wang
v4: rebase fixes
v5: use the generic nop fill
v6: rebase fixes
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +
drivers/gpu/drm/amd/amdgpu/si_dma.c | 963 ++
drivers/gpu/drm/amd/amdgpu/si_dma.h | 29 +
drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 2 +
4 files changed, 998 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dma.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dma.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 367dbc4..e7b28d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1705,6 +1705,10 @@ struct amdgpu_sdma_instance {
struct amdgpu_sdma {
struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
+#ifdef CONFIG_DRM_AMDGPU_SI
+ //SI DMA has a difference trap irq number for the second engine
+ struct amdgpu_irq_src trap_irq_1;
+#endif
struct amdgpu_irq_src trap_irq;
struct amdgpu_irq_src illegal_inst_irq;
int num_instances;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
b/drivers/gpu/drm/amd/amdgpu/si_dma.c
new file mode 100644
index 000..873dd49
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -0,0 +1,963 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+#include
+#include "amdgpu.h"
+#include "amdgpu_trace.h"
+#include "si/sid.h"
+
+const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
+{
+ DMA0_REGISTER_OFFSET,
+ DMA1_REGISTER_OFFSET
+};
+
+static void si_dma_set_ring_funcs(struct amdgpu_device *adev);
+static void si_dma_set_buffer_funcs(struct amdgpu_device *adev);
+static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev);
+static void si_dma_set_irq_funcs(struct amdgpu_device *adev);
+
+static uint32_t si_dma_ring_get_rptr(struct amdgpu_ring *ring)
+{
+ u32 rptr;
+
+ rptr = ring->adev->wb.wb[ring->rptr_offs/4];
+
+ return rptr;
+}
+
+static uint32_t si_dma_ring_get_wptr(struct amdgpu_ring *ring)
+{
+
+ struct amdgpu_device *adev = ring->adev;
+ u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
+
+ return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
+}
+
+static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
+
+ WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
+}
+
+static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_ib *ib,
+ unsigned vm_id, bool ctx_switch)
+{
+ u32 next_rptr = ring->wptr + 4;
+
+ while ((next_rptr & 7) != 5)
+ next_rptr++;
+ next_rptr += 3;
+ amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1));
+ amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffc);
+ amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
+ amdgpu_ring_write(ring, next_rptr);
+
+ /* The indirect buffer packet must end on an 8 DW boundary in the DMA
ring.
+* Pad as necessary with NOPs.
+*/
+ while ((ring->wptr & 7) != 5)
+ amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
+ amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER,
vm_id, 0));
+ amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFE0));
+ amdgpu_ring_write(ring, (ib->length_dw << 12) |
(upper_32_bits(ib->gpu_addr) & 0xFF));
+
+}
+
+static void si_dma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
+{
+ amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
+ amdgpu_ring_write(ring, (0xf << 16
[PATCH 07/17] drm/amdgpu: add graphic pipeline implementation for si v6
From: Ken Wang
v5: rebase fixes
v6: rebase fixes
Acked-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3280 +
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h | 36 +
2 files changed, 3316 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
new file mode 100644
index 000..a8cf04f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -0,0 +1,3280 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include
+#include "amdgpu.h"
+#include "amdgpu_ih.h"
+#include "amdgpu_gfx.h"
+#include "amdgpu_ucode.h"
+#include "si/clearstate_si.h"
+#include "si/sid.h"
+
+#define GFX6_NUM_GFX_RINGS 1
+#define GFX6_NUM_COMPUTE_RINGS 2
+#define STATIC_PER_CU_PG_ENABLE(1 << 3)
+#define DYN_PER_CU_PG_ENABLE (1 << 2)
+#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
+#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET0x3D
+
+
+static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
+static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
+static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
+
+MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
+MODULE_FIRMWARE("radeon/tahiti_me.bin");
+MODULE_FIRMWARE("radeon/tahiti_ce.bin");
+MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
+
+MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
+MODULE_FIRMWARE("radeon/pitcairn_me.bin");
+MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
+MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
+
+MODULE_FIRMWARE("radeon/verde_pfp.bin");
+MODULE_FIRMWARE("radeon/verde_me.bin");
+MODULE_FIRMWARE("radeon/verde_ce.bin");
+MODULE_FIRMWARE("radeon/verde_rlc.bin");
+
+MODULE_FIRMWARE("radeon/oland_pfp.bin");
+MODULE_FIRMWARE("radeon/oland_me.bin");
+MODULE_FIRMWARE("radeon/oland_ce.bin");
+MODULE_FIRMWARE("radeon/oland_rlc.bin");
+
+MODULE_FIRMWARE("radeon/hainan_pfp.bin");
+MODULE_FIRMWARE("radeon/hainan_me.bin");
+MODULE_FIRMWARE("radeon/hainan_ce.bin");
+MODULE_FIRMWARE("radeon/hainan_rlc.bin");
+
+static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
+static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32
*buffer);
+//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
+static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
+
+
+static const u32 verde_rlc_save_restore_register_list[] =
+{
+ (0x8000 << 16) | (0x98f4 >> 2),
+ 0x,
+ (0x8040 << 16) | (0x98f4 >> 2),
+ 0x,
+ (0x8000 << 16) | (0xe80 >> 2),
+ 0x,
+ (0x8040 << 16) | (0xe80 >> 2),
+ 0x,
+ (0x8000 << 16) | (0x89bc >> 2),
+ 0x,
+ (0x8040 << 16) | (0x89bc >> 2),
+ 0x,
+ (0x8000 << 16) | (0x8c1c >> 2),
+ 0x,
+ (0x8040 << 16) | (0x8c1c >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x98f0 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0xe7c >> 2),
+ 0x,
+ (0x8000 << 16) | (0x9148 >> 2),
+ 0x,
+ (0x8040 << 16) | (0x9148 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x9150 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x897c >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x8d8c >> 2),
+ 0x,
+ (0x9c00 << 16) | (0xac54 >> 2),
+ 0X,
+ 0x3,
+ (0x9c00 << 16) | (0x98f8 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x9910 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x9914 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x9918 >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x991c >> 2),
+ 0x,
+ (0x9c00 << 16) | (0x9920 >> 2),
+ 0x,
+ (0x9c00
[PATCH 06/17] drm/amdgpu: atombios change for dce6 to work v3
From: Ken Wang
v3: white space fixes
Reviewed-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
index 49a39b1..f7d236f 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
@@ -497,7 +497,13 @@ void amdgpu_atombios_crtc_set_disp_eng_pll(struct
amdgpu_device *adev,
* SetPixelClock provides the dividers
*/
args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
- args.v6.ucPpll = ATOM_EXT_PLL1;
+ if (adev->asic_type == CHIP_TAHITI ||
+ adev->asic_type == CHIP_PITCAIRN ||
+ adev->asic_type == CHIP_VERDE ||
+ adev->asic_type == CHIP_OLAND)
+ args.v6.ucPpll = ATOM_PPLL0;
+ else
+ args.v6.ucPpll = ATOM_EXT_PLL1;
break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
--
2.5.5
[PATCH 05/17] drm/amdgpu: add display controller implementation for si v7
From: Ken Wang
v4: rebase fixups
v5: more fixes based on dce8 code
v6: squash in dmif offset fix
v7: rebase fixups
Acked-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3204 +
drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 29 +
2 files changed, 3233 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v6_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
new file mode 100644
index 000..28dc554
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -0,0 +1,3204 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_pm.h"
+#include "amdgpu_i2c.h"
+#include "atom.h"
+#include "amdgpu_atombios.h"
+#include "atombios_crtc.h"
+#include "atombios_encoders.h"
+#include "amdgpu_pll.h"
+#include "amdgpu_connectors.h"
+#include "si/si_reg.h"
+#include "si/sid.h"
+
+static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
+static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
+
+static const u32 crtc_offsets[6] =
+{
+ SI_CRTC0_REGISTER_OFFSET,
+ SI_CRTC1_REGISTER_OFFSET,
+ SI_CRTC2_REGISTER_OFFSET,
+ SI_CRTC3_REGISTER_OFFSET,
+ SI_CRTC4_REGISTER_OFFSET,
+ SI_CRTC5_REGISTER_OFFSET
+};
+
+static const uint32_t dig_offsets[] = {
+ SI_CRTC0_REGISTER_OFFSET,
+ SI_CRTC1_REGISTER_OFFSET,
+ SI_CRTC2_REGISTER_OFFSET,
+ SI_CRTC3_REGISTER_OFFSET,
+ SI_CRTC4_REGISTER_OFFSET,
+ SI_CRTC5_REGISTER_OFFSET,
+ (0x13830 - 0x7030) >> 2,
+};
+
+static const struct {
+ uint32_treg;
+ uint32_tvblank;
+ uint32_tvline;
+ uint32_thpd;
+
+} interrupt_status_offsets[6] = { {
+ .reg = DISP_INTERRUPT_STATUS,
+ .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
+ .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
+ .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
+}, {
+ .reg = DISP_INTERRUPT_STATUS_CONTINUE,
+ .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
+ .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
+ .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
+}, {
+ .reg = DISP_INTERRUPT_STATUS_CONTINUE2,
+ .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
+ .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
+ .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
+}, {
+ .reg = DISP_INTERRUPT_STATUS_CONTINUE3,
+ .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
+ .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
+ .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
+}, {
+ .reg = DISP_INTERRUPT_STATUS_CONTINUE4,
+ .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
+ .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
+ .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
+}, {
+ .reg = DISP_INTERRUPT_STATUS_CONTINUE5,
+ .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
+ .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
+ .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
+} };
+
+static const uint32_t hpd_int_control_offsets[6] = {
+ DC_HPD1_INT_CONTROL,
+ DC_HPD2_INT_CONTROL,
+ DC_HPD3_INT_CONTROL,
+ DC_HPD4_INT_CONTROL,
+ DC_HPD5_INT_CONTROL,
+ DC_HPD6_INT_CONTROL,
+};
+
+static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
+
[PATCH 04/17] drm/amdgpu: add interupt handler implementation for si v3
From: Ken Wang
v3: rebase fixups
Reviewed-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/si_ih.c | 313 +
drivers/gpu/drm/amd/amdgpu/si_ih.h | 29
2 files changed, 342 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_ih.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/si_ih.h
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
b/drivers/gpu/drm/amd/amdgpu/si_ih.c
new file mode 100644
index 000..994ff02
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright 2015 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "drmP.h"
+#include "amdgpu.h"
+#include "amdgpu_ih.h"
+#include "si/sid.h"
+#include "si_ih.h"
+
+static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
+
+static void si_ih_enable_interrupts(struct amdgpu_device *adev)
+{
+ u32 ih_cntl = RREG32(IH_CNTL);
+ u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+
+ ih_cntl |= ENABLE_INTR;
+ ih_rb_cntl |= IH_RB_ENABLE;
+ WREG32(IH_CNTL, ih_cntl);
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+ adev->irq.ih.enabled = true;
+}
+
+static void si_ih_disable_interrupts(struct amdgpu_device *adev)
+{
+ u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+ u32 ih_cntl = RREG32(IH_CNTL);
+
+ ih_rb_cntl &= ~IH_RB_ENABLE;
+ ih_cntl &= ~ENABLE_INTR;
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+ WREG32(IH_CNTL, ih_cntl);
+ WREG32(IH_RB_RPTR, 0);
+ WREG32(IH_RB_WPTR, 0);
+ adev->irq.ih.enabled = false;
+ adev->irq.ih.rptr = 0;
+}
+
+static int si_ih_irq_init(struct amdgpu_device *adev)
+{
+ int ret = 0;
+ int rb_bufsz;
+ u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
+ u64 wptr_off;
+
+ si_ih_disable_interrupts(adev);
+ WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
+ interrupt_cntl = RREG32(INTERRUPT_CNTL);
+ interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
+ interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
+ WREG32(INTERRUPT_CNTL, interrupt_cntl);
+
+ WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
+ rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
+
+ ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
+ IH_WPTR_OVERFLOW_CLEAR |
+ (rb_bufsz << 1));
+
+ ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
+
+ wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
+ WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
+ WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+
+ WREG32(IH_RB_RPTR, 0);
+ WREG32(IH_RB_WPTR, 0);
+
+ ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
+ if (adev->irq.msi_enabled)
+ ih_cntl |= RPTR_REARM;
+ WREG32(IH_CNTL, ih_cntl);
+
+ pci_set_master(adev->pdev);
+
+ si_ih_enable_interrupts(adev);
+
+ return ret;
+}
+
+static void si_ih_irq_disable(struct amdgpu_device *adev)
+{
+ si_ih_disable_interrupts(adev);
+ mdelay(1);
+}
+
+static u32 si_ih_get_wptr(struct amdgpu_device *adev)
+{
+ u32 wptr, tmp;
+
+ wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+
+ if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
+ wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
+ dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X,
0x%08X)\n",
+ wptr, adev->irq.ih.rptr, (wptr + 16) &
adev->irq.ih.ptr_mask);
+ adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+ tmp = RREG32(IH_RB_CNTL);
+ tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
+ WREG32(IH_RB_CNTL, tmp);
+ }
+ return (wptr & adev->irq.ih.ptr_mask);
+}
+
+static void si_ih_decode_iv(struct amdgpu_device *adev,
+
[PATCH 03/17] drm/amdgpu: add graphic memory controller implementation for si v5
From: Ken Wang
v4: rebase fixups
v5: rebase fixups
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1077 +
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h | 36 ++
2 files changed, 1113 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
new file mode 100644
index 000..d6e00ca
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -0,0 +1,1077 @@
+
+/*
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include
+#include "drmP.h"
+#include "amdgpu.h"
+#include "gmc_v6_0.h"
+#include "amdgpu_ucode.h"
+#include "si/sid.h"
+
+static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev);
+static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
+
+MODULE_FIRMWARE("radeon/tahiti_mc.bin");
+MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
+MODULE_FIRMWARE("radeon/verde_mc.bin");
+MODULE_FIRMWARE("radeon/oland_mc.bin");
+
+int gmc_v6_0_mc_wait_for_idle(struct amdgpu_device *adev)
+{
+ unsigned i;
+ u32 tmp;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ tmp = RREG32(SRBM_STATUS) & 0x1F00;
+ if (!tmp)
+ return 0;
+ udelay(1);
+ }
+ return -1;
+}
+
+static const u32 crtc_offsets[6] =
+{
+ SI_CRTC0_REGISTER_OFFSET,
+ SI_CRTC1_REGISTER_OFFSET,
+ SI_CRTC2_REGISTER_OFFSET,
+ SI_CRTC3_REGISTER_OFFSET,
+ SI_CRTC4_REGISTER_OFFSET,
+ SI_CRTC5_REGISTER_OFFSET
+};
+
+void gmc_v6_0_mc_stop(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save)
+{
+ u32 blackout;
+
+ if (adev->mode_info.num_crtc)
+ amdgpu_display_stop_mc_access(adev, save);
+
+ amdgpu_asic_wait_for_mc_idle(adev);
+
+ blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
+ if (REG_GET_FIELD(blackout, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE)
!= 1) {
+ /* Block CPU access */
+ WREG32(BIF_FB_EN, 0);
+ /* blackout the MC */
+ blackout = REG_SET_FIELD(blackout,
+mmMC_SHARED_BLACKOUT_CNTL,
xxBLACKOUT_MODE, 0);
+ WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
+ }
+ /* wait for the MC to settle */
+ udelay(100);
+
+}
+
+void gmc_v6_0_mc_resume(struct amdgpu_device *adev,
+ struct amdgpu_mode_mc_save *save)
+{
+ u32 tmp;
+
+ /* unblackout the MC */
+ tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
+ tmp = REG_SET_FIELD(tmp, mmMC_SHARED_BLACKOUT_CNTL, xxBLACKOUT_MODE, 0);
+ WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
+ /* allow CPU access */
+ tmp = REG_SET_FIELD(0, mmBIF_FB_EN, xxFB_READ_EN, 1);
+ tmp = REG_SET_FIELD(tmp, mmBIF_FB_EN, xxFB_WRITE_EN, 1);
+ WREG32(BIF_FB_EN, tmp);
+
+ if (adev->mode_info.num_crtc)
+ amdgpu_display_resume_mc_access(adev, save);
+
+}
+
+static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
+{
+ const char *chip_name;
+ char fw_name[30];
+ int err;
+
+ DRM_DEBUG("\n");
+
+ switch (adev->asic_type) {
+ case CHIP_TAHITI:
+ chip_name = "tahiti";
+ break;
+ case CHIP_PITCAIRN:
+ chip_name = "pitcairn";
+ break;
+ case CHIP_VERDE:
+ chip_name = "verde";
+ break;
+ case CHIP_OLAND:
+ chip_name = "oland";
+ break;
+ case CHIP_HAINAN:
+ chip_name = "hainan";
+ break;
+ default: BUG();
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
+ err = request_fir
[PATCH 02/17] drm/amdgpu: add si header files v3
From: Ken Wang
Acked-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
.../drm/amd/include/asic_reg/si/clearstate_si.h| 941
drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h | 105 +
drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 2409
3 files changed, 3455 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/sid.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h
b/drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h
new file mode 100644
index 000..66e39cd
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h
@@ -0,0 +1,941 @@
+/*
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+static const u32 si_SECT_CONTEXT_def_1[] =
+{
+0x, // DB_RENDER_CONTROL
+0x, // DB_COUNT_CONTROL
+0x, // DB_DEPTH_VIEW
+0x, // DB_RENDER_OVERRIDE
+0x, // DB_RENDER_OVERRIDE2
+0x, // DB_HTILE_DATA_BASE
+0, // HOLE
+0, // HOLE
+0x, // DB_DEPTH_BOUNDS_MIN
+0x, // DB_DEPTH_BOUNDS_MAX
+0x, // DB_STENCIL_CLEAR
+0x, // DB_DEPTH_CLEAR
+0x, // PA_SC_SCREEN_SCISSOR_TL
+0x40004000, // PA_SC_SCREEN_SCISSOR_BR
+0, // HOLE
+0x, // DB_DEPTH_INFO
+0x, // DB_Z_INFO
+0x, // DB_STENCIL_INFO
+0x, // DB_Z_READ_BASE
+0x, // DB_STENCIL_READ_BASE
+0x, // DB_Z_WRITE_BASE
+0x, // DB_STENCIL_WRITE_BASE
+0x, // DB_DEPTH_SIZE
+0x, // DB_DEPTH_SLICE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0x, // TA_BC_BASE_ADDR
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0, // HOLE
+0x, // COHER_DEST_BASE_2
+0x, // COHER_DEST_BASE_3
+0x, // PA_SC_WINDOW_OFFSET
+0x8000, // PA_SC_WINDOW_SCISSOR_TL
+0x40004000, // PA_SC_WINDOW_SCISSOR_BR
+0x, // PA_SC_CLIPRECT_RULE
+0x, // PA_SC_CLIPRECT_0_TL
+0x40004000, // PA_SC_CLIPRECT_0_BR
+0x, // PA_SC_CLIPRECT_1_TL
+0x40004000, // PA_SC_CLIPRECT_1_BR
+0x, // PA_SC_CLIPRECT_2_TL
+0x40004000, // PA_SC_CLIP
[PATCH 01/17] drm/amdgpu: add SI asics types v2
From: Ken Wang
Reviewed-by: Christian König
Signed-off-by: Ken Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/include/amd_shared.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
b/drivers/gpu/drm/amd/include/amd_shared.h
index 6080951..3aa709e 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -38,7 +38,12 @@
* Supported ASIC types
*/
enum amd_asic_type {
- CHIP_BONAIRE = 0,
+ CHIP_TAHITI = 0,
+ CHIP_PITCAIRN,
+ CHIP_VERDE,
+ CHIP_OLAND,
+ CHIP_HAINAN,
+ CHIP_BONAIRE,
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
--
2.5.5
[PATCH 00/17] SI support for amdgpu
This is an initial port of SI support from radeon to amdgpu. This should be considered developer level code. It's not ready for users. GFX and DMA are mostly working. DPM (power management) is implemented, but not working yet. UVD and VCE support have not yet been ported. It uses the same ucode as radeon, just like CIK. What works: - FB console - Unaccelerated X - Basic OGL tests (e.g. piglit) using gbm The code can also be found on the drm-next-4.8-wip-si branch of my fdo tree: https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.8-wip-si Alex Ken Wang (13): drm/amdgpu: add SI asics types v2 drm/amdgpu: add si header files v3 drm/amdgpu: add graphic memory controller implementation for si v5 drm/amdgpu: add interupt handler implementation for si v3 drm/amdgpu: add display controller implementation for si v7 drm/amdgpu: atombios change for dce6 to work v3 drm/amdgpu: add graphic pipeline implementation for si v6 drm/amdgpu: add DMA implementation for si v6 drm/amdgpu: add si implementation v7 drm/amdgpu: add all the components for si into Makefile/kconfig v3 drm/amdgpu: add si ip blocks setup v3 drm/amdgpu: add si specific logic into the device initialize function v2 drm/amdgpu: add si pciids v2 Maruthi Srinivas Bayyavarapu (4): drm/amdgpu: add si dpm support in amdgpu_atombios drm/amdgpu: add SI SMC support drm/amdgpu: add SI DPM support (v3) drm/amdgpu: enable SI DPM drivers/gpu/drm/amd/amdgpu/Kconfig |7 + drivers/gpu/drm/amd/amdgpu/Makefile|2 + drivers/gpu/drm/amd/amdgpu/amdgpu.h|9 + drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 158 + drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 16 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 34 +- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 74 + drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 10 + drivers/gpu/drm/amd/amdgpu/atombios_crtc.c |8 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 3204 drivers/gpu/drm/amd/amdgpu/dce_v6_0.h | 29 + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 3280 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h | 36 + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1077 +++ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h | 36 + drivers/gpu/drm/amd/amdgpu/r600_dpm.h | 127 + drivers/gpu/drm/amd/amdgpu/si.c| 1914 + drivers/gpu/drm/amd/amdgpu/si.h| 33 + drivers/gpu/drm/amd/amdgpu/si_dma.c| 963 +++ drivers/gpu/drm/amd/amdgpu/si_dma.h| 29 + drivers/gpu/drm/amd/amdgpu/si_dpm.c| 7982 drivers/gpu/drm/amd/amdgpu/si_dpm.h| 1015 +++ drivers/gpu/drm/amd/amdgpu/si_ih.c | 313 + drivers/gpu/drm/amd/amdgpu/si_ih.h | 29 + drivers/gpu/drm/amd/amdgpu/si_smc.c| 280 + drivers/gpu/drm/amd/amdgpu/sislands_smc.h | 423 ++ drivers/gpu/drm/amd/include/amd_shared.h |7 +- .../drm/amd/include/asic_reg/si/clearstate_si.h| 941 +++ drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h | 105 + drivers/gpu/drm/amd/include/asic_reg/si/sid.h | 2442 ++ drivers/gpu/drm/amd/include/atombios.h |2 + 31 files changed, 24578 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/dce_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.h create mode 100644 drivers/gpu/drm/amd/amdgpu/r600_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/si.c create mode 100644 drivers/gpu/drm/amd/amdgpu/si.h create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dma.c create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dma.h create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dpm.c create mode 100644 drivers/gpu/drm/amd/amdgpu/si_dpm.h create mode 100644 drivers/gpu/drm/amd/amdgpu/si_ih.c create mode 100644 drivers/gpu/drm/amd/amdgpu/si_ih.h create mode 100644 drivers/gpu/drm/amd/amdgpu/si_smc.c create mode 100644 drivers/gpu/drm/amd/amdgpu/sislands_smc.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/clearstate_si.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/si_reg.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/si/sid.h -- 2.5.5
[PATCH 4/4] tests/amdgpu: adapt to new polaris10/11 uvd fw
Hi all,
On 13 May 2016 at 17:48, Alex Deucher wrote:
> From: Sonny Jiang
>
> Signed-off-by: Sonny Jiang
> Reviewed-by: Alex Deucher
> Signed-off-by: Alex Deucher
> ---
> tests/amdgpu/cs_tests.c | 48 ++--
> 1 file changed, 42 insertions(+), 6 deletions(-)
>
> diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c
> index c6930c0..a01ee48 100644
> --- a/tests/amdgpu/cs_tests.c
> +++ b/tests/amdgpu/cs_tests.c
> @@ -43,6 +43,8 @@ static amdgpu_device_handle device_handle;
> static uint32_t major_version;
> static uint32_t minor_version;
> static uint32_t family_id;
> +static uint32_t chip_rev;
> +static uint32_t chip_id;
>
> static amdgpu_context_handle context_handle;
> static amdgpu_bo_handle ib_handle;
> @@ -78,6 +80,9 @@ int suite_cs_tests_init(void)
> return CUE_SINIT_FAILED;
>
> family_id = device_handle->info.family_id;
> + /* VI asic POLARIS10/11 have specific external_rev_id */
> + chip_rev = device_handle->info.chip_rev;
> + chip_id = device_handle->info.chip_external_rev;
>
> r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> if (r)
> @@ -200,8 +205,17 @@ static void amdgpu_cs_uvd_create(void)
> CU_ASSERT_EQUAL(r, 0);
>
> memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg));
> - if (family_id >= AMDGPU_FAMILY_VI)
> + if (family_id >= AMDGPU_FAMILY_VI) {
> ((uint8_t*)msg)[0x10] = 7;
> + /* chip polaris 10/11 */
> + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
> + /* dpb size */
> + ((uint8_t*)msg)[0x28] = 0x00;
> + ((uint8_t*)msg)[0x29] = 0x94;
> + ((uint8_t*)msg)[0x2A] = 0x6B;
> + ((uint8_t*)msg)[0x2B] = 0x00;
I realise that many of the UVD stuff is 'top secret', although one
should really try and give symbolic names for magic numbers. With them
it's be easier and less error prone when/if the above value changes.
> + }
> + }
>
> r = amdgpu_bo_cpu_unmap(buf_handle);
> CU_ASSERT_EQUAL(r, 0);
> @@ -230,8 +244,8 @@ static void amdgpu_cs_uvd_create(void)
>
> static void amdgpu_cs_uvd_decode(void)
> {
> - const unsigned dpb_size = 15923584, dt_size = 737280;
> - uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, dt_addr, it_addr;
> + const unsigned dpb_size = 15923584, ctx_size = 5287680, dt_size =
> 737280;
> + uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr,
> it_addr;
> struct amdgpu_bo_alloc_request req = {0};
> amdgpu_bo_handle buf_handle;
> amdgpu_va_handle va_handle;
> @@ -269,8 +283,21 @@ static void amdgpu_cs_uvd_decode(void)
> memcpy(ptr, uvd_decode_msg, sizeof(uvd_create_msg));
> if (family_id >= AMDGPU_FAMILY_VI) {
> ptr[0x10] = 7;
> - ptr[0x98] = 0xb0;
> - ptr[0x99] = 0x1;
> + ptr[0x98] = 0x00;
> + ptr[0x99] = 0x02;
> + /* chip polaris10/11 */
> + if (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A) {
> + /*dpb size */
> + ptr[0x24] = 0x00;
> + ptr[0x25] = 0x94;
> + ptr[0x26] = 0x6B;
> + ptr[0x27] = 0x00;
Based on the const dpb_size a few lines above... this value is
incorrect. So either the comment is off, or one/both of the values ?
> + /*ctx size */
> + ptr[0x2C] = 0x00;
> + ptr[0x2D] = 0xAF;
> + ptr[0x2E] = 0x50;
> + ptr[0x2F] = 0x00;
> + }
While this one does match ctx_size above, one should really set a
macro for these magic values and use them throughout. Also considering
that there's three almost identical places where this happens perhaps
it's better to have a common helper ?
Regards,
Emil
[PATCH 4/6] drm/amd/powerplay: add sclk OD support on Fiji
Hi all,
On 13 May 2016 at 19:48, Alex Deucher wrote:
> From: Eric Huang
>
> This implements sclk overdrive(OD) overclocking support for Fiji,
> and the maximum overdrive percentage is 20.
>
> Reviewed-by: Alex Deucher
> Signed-off-by: Eric Huang
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 43
>
> 1 file changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> index 6f1bad4..bf7bf5f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
> @@ -5274,6 +5274,47 @@ bool
> fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h
> return is_update_required;
> }
>
> +static int fiji_get_sclk_od(struct pp_hwmgr *hwmgr)
> +{
> + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
> + struct fiji_single_dpm_table *sclk_table =
> &(data->dpm_table.sclk_table);
> + struct fiji_single_dpm_table *golden_sclk_table =
> + &(data->golden_dpm_table.sclk_table);
> + int value;
> +
> + value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
> +
> golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
> + 100 /
> +
> golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
> +
> + return value;
> +}
> +
> +static int fiji_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
> +{
> + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
> + struct fiji_single_dpm_table *golden_sclk_table =
> + &(data->golden_dpm_table.sclk_table);
> + struct pp_power_state *ps;
> + struct fiji_power_state *fiji_ps;
> +
> + if (value > 20)
> + value = 20;
> +
> + ps = hwmgr->request_ps;
> +
> + if (ps == NULL)
> + return -EINVAL;
> +
> + fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
> +
> + fiji_ps->performance_levels[fiji_ps->performance_level_count -
> 1].engine_clock =
> +
> golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
> + value / 100 +
> +
> golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
> +
> + return 0;
> +}
>
Is it me or this patch 5/6 and 6/6 are identical ? Apart from the
structs of course which... seems to be identical as well despite that
they are copied across different headers and given different names.
Imho one should try to hold them alongside this (and other related)
code as opposed to duplicating even more code ?
Sadly, I won't be able to do any of it, plus I'm not a amdgpu
contributor so "my 2c" as they say.
Regards,
Emil
[Bug 95358] Tonga no hdmi audio on DAL 4.7 works on DAL 4.6
https://bugs.freedesktop.org/show_bug.cgi?id=95358 --- Comment #3 from Andy Furniss --- (In reply to Felix Schwarz from comment #2) > (In reply to Andy Furniss from comment #1) > > If I had more builds I guess I could narrow it down like that - but I don't > > and I don't know how get the historic head versions from git - is that > > possible? > > Maybe I completely misunderstood your question but did you try "git checkout > "? As far as I can see the main challenge might be to get these > commit ids as the DAL branches are rebased regularly, right? Yea, I mainly test the non dal branch so it is the commit hashes I am missing. I would need to be able to checkout based on date really I think. >"git reflog" > might be an option but it might be a bit tedious to search through the big > amount of commits. Thanks, I've never used that before, it seems to be just a history of what I did, which doesn't really help as I wasn't on the dal branch mostly, but is useful to know for the future as its now worth me just switching around various branches even if I know I don't have time to build and test every one. Saying that it looks like I did switch to it but didn't build, so I do have something else to try. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/caa0d741/attachment-0001.html>
[Bug 43698] On PPC, OpenGL programs use incorrect texture colors.
https://bugs.freedesktop.org/show_bug.cgi?id=43698 --- Comment #20 from erhard_f at mailbox.org --- Compiled and using Mesa 11.3.0-devel (git-59156b2) now on my PowerMac G5 7,3 with an AGP Radeon 9600, rv350 class card. Tested so far: AssaultCube, Extreme TuxRacer, RedEclipse, Sauerbraten. All installed from Ubuntu MATE 16.04 repositories. Garbled textures: RedEclipse, Sauerbraten. Extreme TuxRacer runs and is actually playable! However the colors are wrong and the backgrounnd sky is flickering constantly. AssaultCube crashes after showing the "Loading..." window. See https://bugs.launchpad.net/ubuntu/+source/assaultcube/+bug/1581805 Extreme TuxRacer and Sauerbraten have problems while changing the resolution. Both get REALLY sluggish then, hardware acceleration does not seem to work any longer. The console output starts showing "radeon 000:f0:10.0: ring 0 stalled for more than msec" messages during these resolution change problems in Extreme TuxRacer. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/71c45ee3/attachment.html>
[Bug 95358] Tonga no hdmi audio on DAL 4.7 works on DAL 4.6
https://bugs.freedesktop.org/show_bug.cgi?id=95358 --- Comment #2 from Felix Schwarz --- (In reply to Andy Furniss from comment #1) > If I had more builds I guess I could narrow it down like that - but I don't > and I don't know how get the historic head versions from git - is that > possible? Maybe I completely misunderstood your question but did you try "git checkout "? As far as I can see the main challenge might be to get these commit ids as the DAL branches are rebased regularly, right? "git reflog" might be an option but it might be a bit tedious to search through the big amount of commits. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/d9ba6b29/attachment.html>
[Bug 93144] [radeonsi] Alien: Isolation feature request
https://bugs.freedesktop.org/show_bug.cgi?id=93144 --- Comment #38 from Christoph Haag --- (In reply to Nicolai Hähnle from comment #37) > Can you open a new bug report for this and provide an apitrace? To tie up this loose end: I put it off because this would have been a massive apitrace with walking to that room etc. I first made a video of how it had become even worse with the NPCs being completely black/white and how it was this way with high and with low settings: https://youtu.be/Hk9VrJ99jcc?t=110 After restarting the game, I can not reproduce it anymore, not even with the exact same settings I had previously in the video. I can see neither the blue/red lighting problem nor the black/white problem anymore and everything seems to render fine now. My guess is that it wasn't a driver problem in the first place and that it was caused by the game itself caching something and invalidating it after changing the settings and restarting the game. So if anyone has a similar problem: Try changing *all* graphics settings and restarting the game. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/bd778dfc/attachment.html>
[Bug 80419] XCOM: Enemy Unknown Causes lockup
https://bugs.freedesktop.org/show_bug.cgi?id=80419 --- Comment #131 from Davin McCall --- Edwin Smith: > It might be useful to see what the Intel and/or r600 series drivers do as > neither of these driver exhibit this crash in similar circumstances. I think you missed the significance of my second paragraph above - I have established that the hang is _not_ caused by the mis-use of the glDrawRangeElementsBaseVertex() function. So comparing how the radeonsi and Intel/r600 drivers handle this function is not likely to help in resolving this issue. Davin -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/b435133e/attachment.html>
[Bug 95358] Tonga no hdmi audio on DAL 4.7 works on DAL 4.6
https://bugs.freedesktop.org/show_bug.cgi?id=95358 --- Comment #1 from Andy Furniss --- FWIW I found an old build of 4.7-dal that did have sound - though it was early, 23rd March and I don't have any builds in between. I see if I git reset --hard 4.5.0-rc7-g629edea (the version of that build) I can get a new working build and seemingly git history from that time. If I had more builds I guess I could narrow it down like that - but I don't and I don't know how get the historic head versions from git - is that possible? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/f57386e0/attachment.html>
[Bug 95399] Tonga agd5f drm-next-4.8-wip-dal Oops on startx
https://bugs.freedesktop.org/show_bug.cgi?id=95399 Bug ID: 95399 Summary: Tonga agd5f drm-next-4.8-wip-dal Oops on startx Product: DRI Version: DRI git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel at lists.freedesktop.org Reporter: adf.lists at gmail.com Created attachment 123746 --> https://bugs.freedesktop.org/attachment.cgi?id=123746&action=edit dmesg showing oops I get an Oops on startx with drm-next-4.8-wip-dal I tried a few builds going back in the branch but couldn't find a working. 4.7-wip-dal doesn't have the issue. dmesg attached -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160514/2c9af582/attachment.html>
[PATCH] drm.h: Handle DragonFly like Linux
The drm code in DragonFly uses a local Linux implementation which doesn't define the __linux__ macro. Use __DragonFly__ instead in order to not try to compile non-Linux code. --- include/uapi/drm/drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index a0ebfe7..76bea05 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -36,7 +36,7 @@ #ifndef _DRM_H_ #define _DRM_H_ -#if defined(__KERNEL__) || defined(__linux__) +#if defined(__KERNEL__) || defined(__linux__) || defined(__DragonFly__) #include #include -- 2.7.2
[PATCH 3/6] drm/amdgpu: add powerplay sclk OD support through sysfs
dgpu_device *adev)
> device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
> device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
> device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
> + device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 8e345bf..e0f2440 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -530,6 +530,10 @@ int pp_dpm_dispatch_tasks(void *handle, enum
> amd_pp_event event_id, void *input,
> case AMD_PP_EVENT_COMPLETE_INIT:
> ret = pem_handle_event(pp_handle->eventmgr, event_id,
> &data);
> break;
> + case AMD_PP_EVENT_READJUST_POWER_STATE:
> + pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;
> + ret = pem_handle_event(pp_handle->eventmgr, event_id,
> &data);
> + break;
> default:
> break;
> }
> @@ -800,6 +804,44 @@ static int pp_dpm_print_clock_levels(void *handle,
> return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
> }
>
> +static int pp_dpm_get_sclk_od(void *handle)
> +{
> + struct pp_hwmgr *hwmgr;
> +
> + if (!handle)
> + return -EINVAL;
> +
> + hwmgr = ((struct pp_instance *)handle)->hwmgr;
> +
> + PP_CHECK_HW(hwmgr);
> +
> + if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
> + printk(KERN_INFO "%s was not implemented.\n", __func__);
> + return 0;
> + }
> +
> + return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
> +}
> +
> +static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
> +{
> + struct pp_hwmgr *hwmgr;
> +
> + if (!handle)
> + return -EINVAL;
> +
> + hwmgr = ((struct pp_instance *)handle)->hwmgr;
> +
> + PP_CHECK_HW(hwmgr);
> +
> + if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
> + printk(KERN_INFO "%s was not implemented.\n", __func__);
> + return 0;
> + }
> +
> + return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
> +}
> +
> const struct amd_powerplay_funcs pp_dpm_funcs = {
> .get_temperature = pp_dpm_get_temperature,
> .load_firmware = pp_dpm_load_fw,
> @@ -822,6 +864,8 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
> .set_pp_table = pp_dpm_set_pp_table,
> .force_clock_level = pp_dpm_force_clock_level,
> .print_clock_levels = pp_dpm_print_clock_levels,
> + .get_sclk_od = pp_dpm_get_sclk_od,
> + .set_sclk_od = pp_dpm_set_sclk_od,
> };
>
> static int amd_pp_instance_init(struct amd_pp_init *pp_init,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> index 50b367d..154d406 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
> @@ -342,6 +342,8 @@ struct amd_powerplay_funcs {
> int (*set_pp_table)(void *handle, const char *buf, size_t size);
> int (*force_clock_level)(void *handle, enum pp_clock_type type,
> uint32_t mask);
> int (*print_clock_levels)(void *handle, enum pp_clock_type type,
> char *buf);
> + int (*get_sclk_od)(void *handle);
> + int (*set_sclk_od)(void *handle, uint32_t value);
> };
>
> struct amd_powerplay {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 28f5714..37ebfa2 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -338,6 +338,8 @@ struct pp_hwmgr_func {
> int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum
> pp_clock_type type, uint32_t mask);
> int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum
> pp_clock_type type, char *buf);
> int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool
> enable);
> + int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
> + int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
> };
>
> struct pp_table_func {
> --
> 2.5.5
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
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