[PATCH] drm/virtgpu: Delete unnecessary checks before drm_gem_object_unreference_unlocked()

[SF Markus Elfring]

From: Markus Elfring 
Date: Fri, 15 Jul 2016 22:38:42 +0200

The drm_gem_object_unreference_unlocked() function tests whether
its argument is NULL and then returns immediately.
Thus the test around the calls is not needed.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/virtio/virtgpu_display.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c 
b/drivers/gpu/drm/virtio/virtgpu_display.c
index ac758cd..fdfc711 100644
--- a/drivers/gpu/drm/virtio/virtgpu_display.c
+++ b/drivers/gpu/drm/virtio/virtgpu_display.c
@@ -53,8 +53,7 @@ static void virtio_gpu_user_framebuffer_destroy(struct 
drm_framebuffer *fb)
struct virtio_gpu_framebuffer *virtio_gpu_fb
= to_virtio_gpu_framebuffer(fb);

-   if (virtio_gpu_fb->obj)
-   drm_gem_object_unreference_unlocked(virtio_gpu_fb->obj);
+   drm_gem_object_unreference_unlocked(virtio_gpu_fb->obj);
drm_framebuffer_cleanup(fb);
kfree(virtio_gpu_fb);
 }
@@ -326,8 +325,7 @@ virtio_gpu_user_framebuffer_create(struct drm_device *dev,
ret = virtio_gpu_framebuffer_init(dev, virtio_gpu_fb, mode_cmd, obj);
if (ret) {
kfree(virtio_gpu_fb);
-   if (obj)
-   drm_gem_object_unreference_unlocked(obj);
+   drm_gem_object_unreference_unlocked(obj);
return NULL;
}

-- 
2.9.1

[PATCH 2/2] drm/amd/powerplay: Delete unused functions in ppevvmath.h

[Nils Wallménius]

*/
>> > -static int GetRoundedValue(fInt A) /*For now, round the 3rd decimal
>> place */
>> > -{
>> > -   /* ROUNDING TEMPORARLY DISABLED
>> > -   int temp = A.full;
>> > -   int decimal_cutoff, decimal_mask = 0x01FF;
>> > -   decimal_cutoff = temp & decimal_mask;
>> > -   if (decimal_cutoff > 0x147) {
>> > -   temp += 673;
>> > -   }*/
>> > -
>> > -   return ConvertBackToInteger(A)/1; /*Temporary - in case
>> this was used somewhere else */
>> > -}
>> > -
>> > -static fInt Multiply (int X, int Y)
>> > -{
>> > -   fInt A, B, Product;
>> > -
>> > -   A.full = X << SHIFT_AMOUNT;
>> > -   B.full = Y << SHIFT_AMOUNT;
>> > -
>> > -   Product = fMultiply(A, B);
>> > -
>> > -   return Product;
>> > -}
>> > -
>> >  static fInt Divide (int X, int Y)
>> >  {
>> > fInt A, B, Quotient;
>> > @@ -578,14 +529,6 @@ static int uPow(int base, int power)
>> > return (base)*uPow(base, power - 1);
>> >  }
>> >
>> > -static fInt fAbs(fInt A)
>> > -{
>> > -   if (A.partial.real < 0)
>> > -   return (fMultiply(A, ConvertToFraction(-1)));
>> > -   else
>> > -   return A;
>> > -}
>> > -
>> >  static int uAbs(int X)
>> >  {
>> > if (X < 0)
>> > --
>> > 2.8.0.rc3
>> >
>> > ___
>> > dri-devel mailing list
>> > dri-devel at lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>
>
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[PATCH] drm/arcpgu: Delete an unnecessary check before drm_fbdev_cma_hotplug_event()

[SF Markus Elfring]

From: Markus Elfring 
Date: Fri, 15 Jul 2016 21:52:40 +0200

The drm_fbdev_cma_hotplug_event() function tests whether its argument
is NULL and then returns immediately.
Thus the test around the call is not needed.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/arc/arcpgu_drv.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/arc/arcpgu_drv.c b/drivers/gpu/drm/arc/arcpgu_drv.c
index ccbdadb..740d8ba 100644
--- a/drivers/gpu/drm/arc/arcpgu_drv.c
+++ b/drivers/gpu/drm/arc/arcpgu_drv.c
@@ -28,8 +28,7 @@ static void arcpgu_fb_output_poll_changed(struct drm_device 
*dev)
 {
struct arcpgu_drm_private *arcpgu = dev->dev_private;

-   if (arcpgu->fbdev)
-   drm_fbdev_cma_hotplug_event(arcpgu->fbdev);
+   drm_fbdev_cma_hotplug_event(arcpgu->fbdev);
 }

 static struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs = {
-- 
2.9.1

[PATCH 11/11] drm/doc: Spinx leftovers

[Daniel Vetter]

This is unfortunately not all the sphinx noise when building the gpu
documentations. But the remaining warnings have completely bogus line
and probably also file sources, and I just can't find them.

Probably some serious debuggging of the line annotations in the
sphinx/kernel-doc toolchain needed first.

Signed-off-by: Daniel Vetter 
---
 Documentation/gpu/drm-internals.rst | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/Documentation/gpu/drm-internals.rst 
b/Documentation/gpu/drm-internals.rst
index 490d655cda20..3bb26135971f 100644
--- a/Documentation/gpu/drm-internals.rst
+++ b/Documentation/gpu/drm-internals.rst
@@ -188,7 +188,8 @@ Manual IRQ Registration
 Drivers that require multiple interrupt handlers can't use the managed
 IRQ registration functions. In that case IRQs must be registered and
 unregistered manually (usually with the :c:func:`request_irq()` and
-:c:func:`free_irq()` functions, or their devm_\* equivalent).
+:c:func:`free_irq()` functions, or their :c:func:`devm_request_irq()` and
+:c:func:`devm_free_irq()` equivalents).

 When manually registering IRQs, drivers must not set the
 DRIVER_HAVE_IRQ driver feature flag, and must not provide the
@@ -242,11 +243,13 @@ Open/Close, File Operations and IOCTLs
 Open and Close
 --

-int (\*firstopen) (struct drm_device \*); void (\*lastclose) (struct
-drm_device \*); int (\*open) (struct drm_device \*, struct drm_file
-\*); void (\*preclose) (struct drm_device \*, struct drm_file \*);
-void (\*postclose) (struct drm_device \*, struct drm_file \*);
-Open and close handlers. None of those methods are mandatory.
+Open and close handlers. None of those methods are mandatory::
+
+int (*firstopen) (struct drm_device *);
+void (*lastclose) (struct drm_device *);
+int (*open) (struct drm_device *, struct drm_file *);
+void (*preclose) (struct drm_device *, struct drm_file *);
+void (*postclose) (struct drm_device *, struct drm_file *);

 The firstopen method is called by the DRM core for legacy UMS (User Mode
 Setting) drivers only when an application opens a device that has no
-- 
2.8.1

[PATCH 10/11] drm/i915: Update missing kerneldoc

[Daniel Vetter]

Not sure why so much slips through when 0day is catching these. Hopefully
the much faster sphinx toolchain helps in unlazying people.

Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/i915_gem.c  | 2 +-
 drivers/gpu/drm/i915/i915_vgpu.c | 3 ++-
 drivers/gpu/drm/i915/intel_fbc.c | 2 ++
 drivers/gpu/drm/i915/intel_hotplug.c | 1 -
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cf0e8aa8035c..0151c0ce037d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -916,7 +916,7 @@ fast_user_write(struct io_mapping *mapping,
 /**
  * This is the fast pwrite path, where we copy the data directly from the
  * user into the GTT, uncached.
- * @dev: drm device pointer
+ * @i915: i915 device private data
  * @obj: i915 gem object
  * @args: pwrite arguments structure
  * @file: drm file pointer
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index f6acb5a0e701..142bac976919 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -97,6 +97,7 @@ static struct _balloon_info_ bl_info;

 /**
  * intel_vgt_deballoon - deballoon reserved graphics address trunks
+ * @dev_priv: i915 device private data
  *
  * This function is called to deallocate the ballooned-out graphic memory, when
  * driver is unloaded or when ballooning fails.
@@ -138,7 +139,7 @@ static int vgt_balloon_space(struct drm_mm *mm,

 /**
  * intel_vgt_balloon - balloon out reserved graphics address trunks
- * @dev: drm device
+ * @dev_priv: i915 device private data
  *
  * This function is called at the initialization stage, to balloon out the
  * graphic address space allocated to other vGPUs, by marking these spaces as
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 6a7ad3ed1463..781e2f5f7cd8 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1075,6 +1075,8 @@ out:
 /**
  * intel_fbc_enable: tries to enable FBC on the CRTC
  * @crtc: the CRTC
+ * @crtc_state: corresponding _crtc_state for @crtc
+ * @plane_state: corresponding _plane_state for the primary plane of @crtc
  *
  * This function checks if the given CRTC was chosen for FBC, then enables it 
if
  * possible. Notice that it doesn't activate FBC. It is valid to call
diff --git a/drivers/gpu/drm/i915/intel_hotplug.c 
b/drivers/gpu/drm/i915/intel_hotplug.c
index f271f1452b98..40ce263d715f 100644
--- a/drivers/gpu/drm/i915/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/intel_hotplug.c
@@ -527,7 +527,6 @@ void i915_hpd_poll_init_work(struct work_struct *work) {
 /**
  * intel_hpd_poll_init - enables/disables polling for connectors with hpd
  * @dev_priv: i915 device instance
- * @enabled: Whether to enable or disable polling
  *
  * This function enables polling for all connectors, regardless of whether or
  * not they support hotplug detection. Under certain conditions HPD may not be
-- 
2.8.1

[PATCH 09/11] drm/i915: Clean up kerneldoc for intel_lrc.c

[Daniel Vetter]

Fairly minimal, there's still lots of functions without any docs, and
which aren't static. But probably we want to first clean this up some more.

- Drop the bogus const. Marking argument pointers themselves (instead of
  what they point at) as const provides roughly 0 value. And it's confusing,
  since the data the pointer points at _is_ being changed.

- Remove kerneldoc for static functions. Keep comments where they seem valuable.

- Indent and whitespace fixes.

- Blockquote the bit field definitions of the descriptor for correct layouting.

Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/intel_lrc.c | 99 
 1 file changed, 30 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b6af635e3a0f..2e670f15881c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -288,7 +288,6 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *engine)
 /**
  * intel_lr_context_descriptor_update() - calculate & cache the descriptor
  *   descriptor for a pinned context
- *
  * @ctx: Context to work on
  * @engine: Engine the descriptor will be used with
  *
@@ -297,12 +296,13 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *engine)
  * expensive to calculate, we'll just do it once and cache the result,
  * which remains valid until the context is unpinned.
  *
- * This is what a descriptor looks like, from LSB to MSB:
- *bits  0-11:flags, GEN8_CTX_* (cached in ctx_desc_template)
- *bits 12-31:LRCA, GTT address of (the HWSP of) this context
- *bits 32-52:ctx ID, a globally unique tag
- *bits 53-54:mbz, reserved for use by hardware
- *bits 55-63:group ID, currently unused and set to 0
+ * This is what a descriptor looks like, from LSB to MSB::
+ *
+ *  bits  0-11:flags, GEN8_CTX_* (cached in ctx_desc_template)
+ *  bits 12-31:LRCA, GTT address of (the HWSP of) this context
+ *  bits 32-52:ctx ID, a globally unique tag
+ *  bits 53-54:mbz, reserved for use by hardware
+ *  bits 55-63:group ID, currently unused and set to 0
  */
 static void
 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
@@ -539,10 +539,7 @@ get_context_status(struct intel_engine_cs *engine, 
unsigned int read_pointer,
return status;
 }

-/**
- * intel_lrc_irq_handler() - handle Context Switch interrupts
- * @data: tasklet handler passed in unsigned long
- *
+/*
  * Check the unread Context Status Buffers and manage the submission of new
  * contexts to the ELSP accordingly.
  */
@@ -807,7 +804,7 @@ intel_logical_ring_advance_and_submit(struct 
drm_i915_gem_request *request)
 }

 /**
- * execlists_submission() - submit a batchbuffer for execution, Execlists style
+ * intel_execlists_submission() - submit a batchbuffer for execution, 
Execlists style
  * @params: execbuffer call parameters.
  * @args: execbuffer call arguments.
  * @vmas: list of vmas.
@@ -1094,7 +1091,7 @@ static int intel_logical_ring_workarounds_emit(struct 
drm_i915_gem_request *req)
  * code duplication.
  */
 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
-   uint32_t *const batch,
+   uint32_t *batch,
uint32_t index)
 {
uint32_t l3sqc4_flush = (0x4040 | GEN8_LQSC_FLUSH_COHERENT_LINES);
@@ -1155,37 +1152,24 @@ static inline int wa_ctx_end(struct i915_wa_ctx_bb 
*wa_ctx,
return 0;
 }

-/**
- * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
- *
- * @engine: only applicable for RCS
- * @wa_ctx: structure representing wa_ctx
- *  offset: specifies start of the batch, should be cache-aligned. This is 
updated
- *with the offset value received as input.
- *  size: size of the batch in DWORDS but HW expects in terms of cachelines
- * @batch: page in which WA are loaded
- * @offset: This field specifies the start of the batch, it should be
- *  cache-aligned otherwise it is adjusted accordingly.
- *  Typically we only have one indirect_ctx and per_ctx batch buffer which are
- *  initialized at the beginning and shared across all contexts but this field
- *  helps us to have multiple batches at different offsets and select them 
based
- *  on a criteria. At the moment this batch always start at the beginning of 
the page
- *  and at this point we don't have multiple wa_ctx batch buffers.
- *
- *  The number of WA applied are not known at the beginning; we use this field
- *  to return the no of DWORDS written.
+/*
+ * Typically we only have one indirect_ctx and per_ctx batch buffer which are
+ * initialized at the beginning and shared across all contexts but this field
+ * helps us to have multiple batches at different offsets and select them based
+ * on a criteria. At the 

[PATCH 08/11] drm/i915: Fixup kerneldoc code snippets in intel_uncore.c

[Daniel Vetter]

We need :: before, blank lines around and indentation with 4 _additional_
spaces to make it work. Also, don't use @param in code snippets, it results
in confusion.

Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/intel_uncore.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index eeb4cbce19ff..43f833901b8e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1618,8 +1618,10 @@ static int gen6_reset_engines(struct drm_i915_private 
*dev_priv,
  * @timeout_ms: timeout in millisecond
  *
  * This routine waits until the target register @reg contains the expected
- * @value after applying the @mask, i.e. it waits until
- *   (I915_READ_FW(@reg) & @mask) == @value
+ * @value after applying the @mask, i.e. it waits until ::
+ *
+ * (I915_READ_FW(reg) & mask) == value
+ *
  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
  *
  * Note that this routine assumes the caller holds forcewake asserted, it is
@@ -1652,8 +1654,10 @@ int intel_wait_for_register_fw(struct drm_i915_private 
*dev_priv,
  * @timeout_ms: timeout in millisecond
  *
  * This routine waits until the target register @reg contains the expected
- * @value after applying the @mask, i.e. it waits until
- *   (I915_READ(@reg) & @mask) == @value
+ * @value after applying the @mask, i.e. it waits until ::
+ *
+ * (I915_READ(reg) & mask) == value
+ *
  * Otherwise, the wait will timeout after @timeout_ms milliseconds.
  *
  * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
-- 
2.8.1

[PATCH 07/11] drm/dp-mst: Missing kernel doc

[Daniel Vetter]

Cc: Dave Airlie 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_dp_mst_topology.c |   1 +
 include/drm/drm_dp_mst_helper.h   | 140 --
 2 files changed, 117 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 5020a2aaffeb..04e457117980 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -2365,6 +2365,7 @@ EXPORT_SYMBOL(drm_dp_mst_hpd_irq);

 /**
  * drm_dp_mst_detect_port() - get connection status for an MST port
+ * @connector: DRM connector for this port
  * @mgr: manager for this port
  * @port: unverified pointer to a port
  *
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index c49bbfaf3cbb..003207670597 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -87,7 +87,15 @@ struct drm_dp_mst_port {
struct drm_connector *connector;
struct drm_dp_mst_topology_mgr *mgr;

-   struct edid *cached_edid; /* for DP logical ports - make tiling work */
+   /**
+* @cached_edid: for DP logical ports - make tiling work by ensuring
+* that the EDID for all connectors is read immediately.
+*/
+   struct edid *cached_edid;
+   /**
+* @has_audio: Tracks whether the sink connector to this port is
+* audio-capable.
+*/
bool has_audio;
 };

@@ -397,70 +405,154 @@ struct drm_dp_payload {

 /**
  * struct drm_dp_mst_topology_mgr - DisplayPort MST manager
- * @dev: device pointer for adding i2c devices etc.
- * @cbs: callbacks for connector addition and destruction.
- * @max_dpcd_transaction_bytes - maximum number of bytes to read/write in one 
go.
- * @aux: aux channel for the DP connector.
- * @max_payloads: maximum number of payloads the GPU can generate.
- * @conn_base_id: DRM connector ID this mgr is connected to.
- * @down_rep_recv: msg receiver state for down replies.
- * @up_req_recv: msg receiver state for up requests.
- * @lock: protects mst state, primary, dpcd.
- * @mst_state: if this manager is enabled for an MST capable port.
- * @mst_primary: pointer to the primary branch device.
- * @dpcd: cache of DPCD for primary port.
- * @pbn_div: PBN to slots divisor.
  *
  * This struct represents the toplevel displayport MST topology manager.
  * There should be one instance of this for every MST capable DP connector
  * on the GPU.
  */
 struct drm_dp_mst_topology_mgr {
-
+   /**
+* @dev: device pointer for adding i2c devices etc.
+*/
struct device *dev;
+   /**
+* @cbs: callbacks for connector addition and destruction.
+*/
const struct drm_dp_mst_topology_cbs *cbs;
+   /**
+* @max_dpcd_transaction_bytes: maximum number of bytes to read/write
+* in one go.
+*/
int max_dpcd_transaction_bytes;
-   struct drm_dp_aux *aux; /* auxch for this topology mgr to use */
+   /**
+* @aux: AUX channel for the DP MST connector this topolgy mgr is
+* controlling.
+*/
+   struct drm_dp_aux *aux;
+   /**
+* @max_payloads: maximum number of payloads the GPU can generate.
+*/
int max_payloads;
+   /**
+* @conn_base_id: DRM connector ID this mgr is connected to. Only used
+* to build the MST connector path value.
+*/
int conn_base_id;

-   /* only ever accessed from the workqueue - which should be serialised */
+   /**
+* @down_rep_recv: Message receiver state for down replies. This and
+* @up_req_recv are only ever access from the work item, which is
+* serialised.
+*/
struct drm_dp_sideband_msg_rx down_rep_recv;
+   /**
+* @up_req_recv: Message receiver state for up requests. This and
+* @down_rep_recv are only ever access from the work item, which is
+* serialised.
+*/
struct drm_dp_sideband_msg_rx up_req_recv;

-   /* pointer to info about the initial MST device */
-   struct mutex lock; /* protects mst_state + primary + dpcd */
+   /**
+* @lock: protects mst state, primary, dpcd.
+*/
+   struct mutex lock;

+   /**
+* @mst_state: If this manager is enabled for an MST capable port. False
+* if no MST sink/branch devices is connected.
+*/
bool mst_state;
+   /**
+* @mst_primary: Pointer to the primary/first branch device.
+*/
struct drm_dp_mst_branch *mst_primary;

+   /**
+* @dpcd: Cache of DPCD for primary port.
+*/
u8 dpcd[DP_RECEIVER_CAP_SIZE];
+   /**
+* @sink_count: Sink count from DEVICE_SERVICE_IRQ_VECTOR_ESI0.
+*/
u8 sink_count;
+   /**
+* @pbn_div: PBN to slots divisor.
+*/
int pbn_div;
+   /**
+* @total_slots: Total slots that can be allocated.

[PATCH 06/11] drm/dp-mst: Remove tx_down_in_progress

[Daniel Vetter]

Just replicates whether the list is empty or not. Nuke code
to avoid writing docs for it!

Cc: Dave Airlie 
Signed-off-by: Daniel Vetter 
---
 drivers/gpu/drm/drm_dp_mst_topology.c | 13 +++--
 include/drm/drm_dp_mst_helper.h   |  1 -
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 6537908050d7..5020a2aaffeb 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -1493,11 +1493,8 @@ static void process_single_down_tx_qlock(struct 
drm_dp_mst_topology_mgr *mgr)
WARN_ON(!mutex_is_locked(>qlock));

/* construct a chunk from the first msg in the tx_msg queue */
-   if (list_empty(>tx_msg_downq)) {
-   mgr->tx_down_in_progress = false;
+   if (list_empty(>tx_msg_downq))
return;
-   }
-   mgr->tx_down_in_progress = true;

txmsg = list_first_entry(>tx_msg_downq, struct 
drm_dp_sideband_msg_tx, next);
ret = process_single_tx_qlock(mgr, txmsg, false);
@@ -1512,10 +1509,6 @@ static void process_single_down_tx_qlock(struct 
drm_dp_mst_topology_mgr *mgr)
txmsg->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
wake_up(>tx_waitq);
}
-   if (list_empty(>tx_msg_downq)) {
-   mgr->tx_down_in_progress = false;
-   return;
-   }
 }

 /* called holding qlock */
@@ -1538,7 +1531,7 @@ static void drm_dp_queue_down_tx(struct 
drm_dp_mst_topology_mgr *mgr,
 {
mutex_lock(>qlock);
list_add_tail(>next, >tx_msg_downq);
-   if (!mgr->tx_down_in_progress)
+   if (list_is_singular(>tx_msg_downq))
process_single_down_tx_qlock(mgr);
mutex_unlock(>qlock);
 }
@@ -2887,7 +2880,7 @@ static void drm_dp_tx_work(struct work_struct *work)
struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct 
drm_dp_mst_topology_mgr, tx_work);

mutex_lock(>qlock);
-   if (mgr->tx_down_in_progress)
+   if (!list_empty(>tx_msg_downq))
process_single_down_tx_qlock(mgr);
mutex_unlock(>qlock);
 }
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index fdb47051d549..c49bbfaf3cbb 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -446,7 +446,6 @@ struct drm_dp_mst_topology_mgr {
   the mstb tx_slots and txmsg->state once they are queued */
struct mutex qlock;
struct list_head tx_msg_downq;
-   bool tx_down_in_progress;

/* payload info + lock for it */
struct mutex payload_lock;
-- 
2.8.1

[PATCH 05/11] drm/doc: Fix missing kerneldoc for drm_dp_helper.c

[Daniel Vetter]

Never added when the DP validation code was added.

Signed-off-by: Daniel Vetter 
---
 include/drm/drm_dp_helper.h | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 4d85cf2874af..72dee1213268 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -747,7 +747,14 @@ struct drm_dp_aux {
struct mutex hw_mutex;
ssize_t (*transfer)(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg);
-   unsigned i2c_nack_count, i2c_defer_count;
+   /**
+* @i2c_nack_count: Counts I2C NACKs, used for DP validation.
+*/
+   unsigned i2c_nack_count;
+   /**
+* @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
+*/
+   unsigned i2c_defer_count;
 };

 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
-- 
2.8.1

[PATCH 04/11] drm: Extract drm_irq.h

[Daniel Vetter]

The drm_irq docs want one function from drmP.h, but that one is a
serious mess. Extract it, and while at it improve the docs a bit.
There's a bit a header loop issue since core data structures like
drm_device and drm_driver aren't in their own headers yet, which means
the drm_irq.h include in drmP.h needs to be in just the right spot :(

Also noticed that drm_vblank_crtc->last_wait is entirely unused,
remove it.

Signed-off-by: Daniel Vetter 
---
 Documentation/gpu/drm-kms.rst |  4 +--
 drivers/gpu/drm/drm_irq.c |  1 -
 include/drm/drmP.h| 83 ++-
 3 files changed, 5 insertions(+), 83 deletions(-)

diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 675221f0a64b..8dfa4b214b96 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -649,5 +649,5 @@ Vertical Blanking and Interrupt Handling Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_irq.c
:export:

-.. kernel-doc:: include/drm/drmP.h
-   :functions: drm_crtc_vblank_waitqueue
+.. kernel-doc:: include/drm/drm_irq.h
+   :internal:
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 49e83b190e01..b49a4a6e97cd 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -1664,7 +1664,6 @@ int drm_wait_vblank(struct drm_device *dev, void *data,

DRM_DEBUG("waiting on vblank count %d, crtc %u\n",
  vblwait->request.sequence, pipe);
-   vblank->last_wait = vblwait->request.sequence;
DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
(((drm_vblank_count(dev, pipe) -
   vblwait->request.sequence) <= (1 << 23)) ||
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 19cbd7f8d302..5f9caf7ee949 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -52,7 +52,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -87,6 +86,7 @@ struct drm_device_dma;
 struct drm_dma_handle;
 struct drm_gem_object;
 struct drm_master;
+struct drm_vblank_crtc;

 struct device_node;
 struct videomode;
@@ -684,35 +684,6 @@ struct drm_minor {
struct mutex debugfs_lock; /* Protects debugfs_list. */
 };

-
-struct drm_pending_vblank_event {
-   struct drm_pending_event base;
-   unsigned int pipe;
-   struct drm_event_vblank event;
-};
-
-struct drm_vblank_crtc {
-   struct drm_device *dev; /* pointer to the drm_device */
-   wait_queue_head_t queue;/**< VBLANK wait queue */
-   struct timer_list disable_timer;/* delayed disable 
timer */
-
-   seqlock_t seqlock;  /* protects vblank count and time */
-
-   u32 count;  /* vblank counter */
-   struct timeval time;/* vblank timestamp */
-
-   atomic_t refcount;  /* number of users of vblank 
interruptsper crtc */
-   u32 last;   /* protected by dev->vbl_lock, used */
-   /* for wraparound handling */
-   u32 last_wait;  /* Last vblank seqno waited per CRTC */
-   unsigned int inmodeset; /* Display driver is setting mode */
-   unsigned int pipe;  /* crtc index */
-   int framedur_ns;/* frame/field duration in ns */
-   int linedur_ns; /* line duration in ns */
-   bool enabled;   /* so we don't call enable more than
-  once per disable */
-};
-
 /**
  * DRM device structure. This structure represent a complete card that
  * may contain multiple heads.
@@ -847,6 +818,8 @@ struct drm_device {
int switch_power_state;
 };

+#include 
+
 #define DRM_SWITCH_POWER_ON 0
 #define DRM_SWITCH_POWER_OFF 1
 #define DRM_SWITCH_POWER_CHANGING 2
@@ -933,56 +906,6 @@ void drm_clflush_virt_range(void *addr, unsigned long 
length);
  * DMA quiscent + idle. DMA quiescent usually requires the hardware lock.
  */

-   /* IRQ support (drm_irq.h) */
-extern int drm_irq_install(struct drm_device *dev, int irq);
-extern int drm_irq_uninstall(struct drm_device *dev);
-
-extern int drm_vblank_init(struct drm_device *dev, unsigned int num_crtcs);
-extern int drm_wait_vblank(struct drm_device *dev, void *data,
-  struct drm_file *filp);
-extern u32 drm_vblank_count(struct drm_device *dev, unsigned int pipe);
-extern u32 drm_crtc_vblank_count(struct drm_crtc *crtc);
-extern u32 drm_crtc_vblank_count_and_time(struct drm_crtc *crtc,
- struct timeval *vblanktime);
-extern void drm_crtc_send_vblank_event(struct drm_crtc *crtc,
-  struct drm_pending_vblank_event *e);
-extern void drm_crtc_arm_vblank_event(struct drm_crtc *crtc,
- struct drm_pending_vblank_event *e);
-extern bool drm_handle_vblank(struct drm_device 

[PATCH 03/11] drm/doc: document all the properties in drm_mode_config

[Daniel Vetter]

I'm fed up with the warning noise from kernel-doc.

Aside: I stumbled over dirty_info_property, which is only set by udl
and qxl. But we have a _lot_ more drivers implementing a dirty
callback on framebuffers. Not entirely sure what the ABI is supposed
to be here, but it seems confusing for sure.

Signed-off-by: Daniel Vetter 
---
 include/drm/drm_crtc.h | 196 +
 1 file changed, 180 insertions(+), 16 deletions(-)

diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 656f189f1198..6a702a484a23 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2351,18 +2351,8 @@ struct drm_mode_config_funcs {
  * @property_blob_list: list of all the blob property objects
  * @blob_lock: mutex for blob property allocation and management
  * @*_property: core property tracking
- * @degamma_lut_property: LUT used to convert the framebuffer's colors to 
linear
- * gamma
- * @degamma_lut_size_property: size of the degamma LUT as supported by the
- * driver (read-only)
- * @ctm_property: Matrix used to convert colors after the lookup in the
- * degamma LUT
- * @gamma_lut_property: LUT used to convert the colors, after the CSC matrix, 
to
- * the gamma space of the connected screen (read-only)
- * @gamma_lut_size_property: size of the gamma LUT as supported by the driver
  * @preferred_depth: preferred RBG pixel depth, used by fb helpers
  * @prefer_shadow: hint to userspace to prefer shadow-fb rendering
- * @async_page_flip: does this device support async flips on the primary plane?
  * @cursor_width: hint to userspace for max cursor width
  * @cursor_height: hint to userspace for max cursor height
  * @helper_private: mid-layer private data
@@ -2457,64 +2447,238 @@ struct drm_mode_config {

/* pointers to standard properties */
struct list_head property_blob_list;
+   /**
+* @edid_property: Default connector property to hold the EDID of the
+* currently connected sink, if any.
+*/
struct drm_property *edid_property;
+   /**
+* @dpms_property: Default connector property to control the
+* connector's DPMS state.
+*/
struct drm_property *dpms_property;
+   /**
+* @path_property: Default connector property to hold the DP MST path
+* for the port.
+*/
struct drm_property *path_property;
+   /**
+* @tile_property: Default connector property to store the tile
+* position of a tiled screen, for sinks which need to be driven with
+* multiple CRTCs.
+*/
struct drm_property *tile_property;
+   /**
+* @plane_type_property: Default plane property to differentiate
+* CURSOR, PRIMARY and OVERLAY legacy uses of planes.
+*/
struct drm_property *plane_type_property;
+   /**
+* @rotation_property: Optional property for planes or CRTCs to specifiy
+* rotation.
+*/
struct drm_property *rotation_property;
+   /**
+* @prop_src_x: Default atomic plane property for the plane source
+* position in the connected _framebuffer.
+*/
struct drm_property *prop_src_x;
+   /**
+* @prop_src_y: Default atomic plane property for the plane source
+* position in the connected _framebuffer.
+*/
struct drm_property *prop_src_y;
+   /**
+* @prop_src_w: Default atomic plane property for the plane source
+* position in the connected _framebuffer.
+*/
struct drm_property *prop_src_w;
+   /**
+* @prop_src_h: Default atomic plane property for the plane source
+* position in the connected _framebuffer.
+*/
struct drm_property *prop_src_h;
+   /**
+* @prop_crtc_x: Default atomic plane property for the plane destination
+* position in the _crtc is is being shown on.
+*/
struct drm_property *prop_crtc_x;
+   /**
+* @prop_crtc_y: Default atomic plane property for the plane destination
+* position in the _crtc is is being shown on.
+*/
struct drm_property *prop_crtc_y;
+   /**
+* @prop_crtc_w: Default atomic plane property for the plane destination
+* position in the _crtc is is being shown on.
+*/
struct drm_property *prop_crtc_w;
+   /**
+* @prop_crtc_h: Default atomic plane property for the plane destination
+* position in the _crtc is is being shown on.
+*/
struct drm_property *prop_crtc_h;
+   /**
+* @prop_fb_id: Default atomic plane property to specify the
+* _framebuffer.
+*/
struct drm_property *prop_fb_id;
+   /**
+* @prop_crtc_id: Default atomic plane property to specify the
+* _crtc.
+*/
struct drm_property *prop_crtc_id;
+   /**
+* @prop_active: Default atomic CRTC property 

[PATCH 02/11] drm/doc: Add kerneldoc for @index

[Daniel Vetter]

Was forgotten when adding them all over. 0-day should complain about
new missing kernel-doc, not sure why that wasn't caught/fixed.

Cc: Chris Wilson 
Signed-off-by: Daniel Vetter 
---
 include/drm/drm_crtc.h | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index ebf078685f86..656f189f1198 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -783,7 +783,10 @@ struct drm_crtc {
struct drm_plane *primary;
struct drm_plane *cursor;

-   /* position inside the mode_config.list, can be used as a [] idx */
+   /**
+* @index: Position inside the mode_config.list, can be used as an array
+* index.
+*/
unsigned index;

/* position of cursor plane on crtc */
@@ -1210,7 +1213,10 @@ struct drm_encoder {
char *name;
int encoder_type;

-   /* position inside the mode_config.list, can be used as a [] idx */
+   /**
+* @index: Position inside the mode_config.list, can be used as an array
+* index.
+*/
unsigned index;

uint32_t possible_crtcs;
@@ -1713,7 +1719,10 @@ struct drm_plane {

enum drm_plane_type type;

-   /* position inside the mode_config.list, can be used as a [] idx */
+   /**
+* @index: Position inside the mode_config.list, can be used as an array
+* index.
+*/
unsigned index;

const struct drm_plane_helper_funcs *helper_private;
@@ -2321,8 +2330,6 @@ struct drm_mode_config_funcs {
  * @fb_lock: mutex to protect fb state and lists
  * @num_fb: number of fbs available
  * @fb_list: list of framebuffers available
- * @num_connector: number of connectors on this device
- * @connector_list: list of connector objects
  * @num_encoder: number of encoders on this device
  * @encoder_list: list of encoder objects
  * @num_overlay_plane: number of overlay planes on this device
@@ -2397,8 +2404,17 @@ struct drm_mode_config {
int num_fb;
struct list_head fb_list;

+   /**
+* @num_connector: Number of connectors on this device.
+*/
int num_connector;
+   /**
+* @connector_ida: ID allocator for connector indices.
+*/
struct ida connector_ida;
+   /**
+* @connector_list: List of connector objects.
+*/
struct list_head connector_list;

/**
-- 
2.8.1

[PATCH 01/11] drm/drm-kms.rst: Remove unused drm_fourcc.h include directive

[Daniel Vetter]

Right now there's nothing, and kernel-doc produces a warning because
of that. Remove it until we need it for a clean build.

Cc: Laurent Pinchart 
Signed-off-by: Daniel Vetter 
---
 Documentation/gpu/drm-kms.rst | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 0e1c80436c1d..675221f0a64b 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -67,9 +67,6 @@ drivers can manually clean up a framebuffer at module unload 
time with
 DRM Format Handling
 ---

-.. kernel-doc:: include/drm/drm_fourcc.h
-   :internal:
-
 .. kernel-doc:: drivers/gpu/drm/drm_fourcc.c
:export:

-- 
2.8.1

[Nouveau] [PATCH v3] drm/nouveau/fb/nv50: set DMA mask before mapping scratch page

[Ard Biesheuvel]

On 15 July 2016 at 07:52, Alexandre Courbot  wrote:
> On Fri, Jul 8, 2016 at 1:59 AM, Ard Biesheuvel
>  wrote:
>> The 100c08 scratch page is mapped using dma_map_page() before the TTM
>> layer has had a chance to set the DMA mask. This means we are still
>> running with the default of 32 when this code executes, and this causes
>> problems for platforms with no memory below 4 GB (such as AMD Seattle)
>>
>> So move the dma_map_page() to the .init hook, and set the streaming DMA
>> mask based on the MMU subdev parameters before performing the call.
>>
>> Signed-off-by: Ard Biesheuvel 
>> ---
>> I am sure there is a much better way to address this, but this fixes the
>> problem I get on AMD Seattle with a GeForce 210 PCIe card:
>>
>>nouveau :02:00.0: enabling device ( -> 0003)
>>nouveau :02:00.0: NVIDIA GT218 (0a8280b1)
>>nouveau :02:00.0: bios: version 70.18.a6.00.00
>>nouveau :02:00.0: fb ctor failed, -14
>>nouveau: probe of :02:00.0 failed with error -14
>>
>> v2: replace incorrect comparison of dma_addr_t type var against NULL
>> v3: rework code to get rid of DMA_ERROR_CODE references, which is not
>> defined on all architectures
>>
>>  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 40 ++--
>>  1 file changed, 29 insertions(+), 11 deletions(-)
>
> I think the same problem exists in fb/gf100.c, would be nice to fix it
> there as well.
>
> I have faced similar issues on Tegra before. I wonder whether this
> could not be addressed the same way I did, i.e. by setting a
> temporary, fail-safe DMA mask in nvkm_device_pci_new()? That would
> allow all subdevs to map pages to the device safely in their init.
> With your solution, each subdev in that scenario needs to set a DMA
> mask to be safe.
>
> Not sure whether that's practical as I suppose you want to make the
> DMA mask larger than 32 bits?
>

Yes. This particular device supports 40 bits (judging from the MMU
driver code) of physical address space, and RAM starts at
0x80__ on AMD Seattle, so we need all 40 bits.

> If you absolutely need to do this in the device, can we move the DMA
> mask setting logic in nouveau_ttm into its own function and call it
> from the FB driver to make sure the mask is correctly set? Maybe this
> could even be made a MMU function and called during MMU ctor or init
> (in the latter case we would also need to reorder MMU init to make it
> happen before FB and INSTMEM).

Happy to have stab at implementing this, but I'd like some buy in from
the maintainer first before I dive into this. Ben is the person to
give his blessing, I suppose? He has not responded to any of my
postings so far, unfortunately.

Thanks,
Ard.

[PATCH] drm/vc4: Delete unnecessary checks before two function calls

[SF Markus Elfring]

From: Markus Elfring 
Date: Fri, 15 Jul 2016 21:15:37 +0200

The following functions test whether their argument is NULL
and then return immediately.
* drm_fbdev_cma_hotplug_event
* drm_fbdev_cma_restore_mode

Thus the tests around their calls are not needed.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/vc4/vc4_drv.c | 3 +--
 drivers/gpu/drm/vc4/vc4_kms.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index 54d0471..ce74d86 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -47,8 +47,7 @@ static void vc4_lastclose(struct drm_device *dev)
 {
struct vc4_dev *vc4 = to_vc4_dev(dev);

-   if (vc4->fbdev)
-   drm_fbdev_cma_restore_mode(vc4->fbdev);
+   drm_fbdev_cma_restore_mode(vc4->fbdev);
 }

 static const struct file_operations vc4_drm_fops = {
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 9a217fd..4ac894d 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -26,8 +26,7 @@ static void vc4_output_poll_changed(struct drm_device *dev)
 {
struct vc4_dev *vc4 = to_vc4_dev(dev);

-   if (vc4->fbdev)
-   drm_fbdev_cma_hotplug_event(vc4->fbdev);
+   drm_fbdev_cma_hotplug_event(vc4->fbdev);
 }

 struct vc4_commit {
-- 
2.9.1

[PATCH 02/11] drm/doc: Add kerneldoc for @index

[Chris Wilson]

On Fri, Jul 15, 2016 at 09:47:59PM +0200, Daniel Vetter wrote:
> Was forgotten when adding them all over. 0-day should complain about
> new missing kernel-doc, not sure why that wasn't caught/fixed.
> 
> Cc: Chris Wilson 
> Signed-off-by: Daniel Vetter 
> ---
>  include/drm/drm_crtc.h | 26 +-
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index ebf078685f86..656f189f1198 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -783,7 +783,10 @@ struct drm_crtc {
>   struct drm_plane *primary;
>   struct drm_plane *cursor;
>  
> - /* position inside the mode_config.list, can be used as a [] idx */
> + /**
> +  * @index: Position inside the mode_config.list, can be used as an array

For all:

@index: Fixed position inside the mode_config.list, can be used as an
array index. The @index is assigned when the crtc is inserted into the
list, and it will remain at that position inside the list until the
module is unloaded.

Just want to emphasis the unchanging nature of the @index. Second
sentence may be overkill.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[Intel-gfx] [PATCH 09/11] drm/i915: Clean up kerneldoc for intel_lrc.c

[Chris Wilson]

On Fri, Jul 15, 2016 at 09:48:06PM +0200, Daniel Vetter wrote:
> Fairly minimal, there's still lots of functions without any docs, and
> which aren't static. But probably we want to first clean this up some more.
> 
> - Drop the bogus const. Marking argument pointers themselves (instead of
>   what they point at) as const provides roughly 0 value. And it's confusing,
>   since the data the pointer points at _is_ being changed.

It served its purpose of getting the compiler to sanity check that batch
was unchanged as we passed it around the various obscuration macros.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[Intel-gfx] [PATCH 06/11] drm/dp-mst: Remove tx_down_in_progress

[Chris Wilson]

On Fri, Jul 15, 2016 at 09:48:03PM +0200, Daniel Vetter wrote:
> Just replicates whether the list is empty or not. Nuke code
> to avoid writing docs for it!
> 
> Cc: Dave Airlie 
> Signed-off-by: Daniel Vetter 

Reviewed-by: Chris Wilson 

Unless Dave to planned to use it elsewhere, tx_msg_downq is indeed
redundant.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

[PATCH] drm/ttm: Delete an unnecessary check before the function call "ttm_tt_destroy"

[SF Markus Elfring]

From: Markus Elfring 
Date: Fri, 15 Jul 2016 20:20:48 +0200

The ttm_tt_destroy() function tests whether its argument is NULL
and then returns immediately. Thus the test around the call is not needed.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/ttm/ttm_bo.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 39386f5..23809d0 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -146,9 +146,7 @@ static void ttm_bo_release_list(struct kref *list_kref)
BUG_ON(bo->mem.mm_node != NULL);
BUG_ON(!list_empty(>lru));
BUG_ON(!list_empty(>ddestroy));
-
-   if (bo->ttm)
-   ttm_tt_destroy(bo->ttm);
+   tm_tt_destroy(bo->ttm);
atomic_dec(>glob->bo_count);
if (bo->resv == >ttm_resv)
reservation_object_fini(>ttm_resv);
-- 
2.9.1

[Bug 115321] radeon runpm falsely disabled on Clevo P170EM

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=115321

--- Comment #9 from Peter Wu  ---
For that to work on stable v4.6 you have to revert dfc4f59d901b and
bfaddd9fc8ac. My .config and compiler generates the same (inlined) code for
both sources:

// (radeon.ko) mask & (1 << 1) => (mask >> 1) & 1
   ed828:   d1 ea   shredx,1
   ed82a:   83 e2 01andedx,0x1
   ed82d:   88 15 00 00 00 00   movBYTE PTR [rip+0x0],dl

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[PATCH] drm/edid: move DDC_SEGMENT_ADDR into drm_edid.h

[Shawn Guo]

On Fri, Jul 15, 2016 at 09:24:36AM +0200, Daniel Vetter wrote:
> On Thu, Jul 14, 2016 at 09:21:03PM +0800, Shawn Guo wrote:
> > On Thu, Jul 14, 2016 at 02:45:41PM +0200, Daniel Vetter wrote:
> > > On Thu, Jul 14, 2016 at 05:00:28PM +0800, Shawn Guo wrote:
> > > > The same definition of DDC_SEGMENT_ADDR is currently defined in two
> > > > places, drm_edid.c and inno_hdmi.h.  Let's consolidate the definition
> > > > into drm_edid.h in the same way that DDC_ADDR is defined.
> > > > 
> > > > Signed-off-by: Shawn Guo 
> > > 
> > > What really should be done here is nuke the fake i2c adapter in
> > > inno_hdmi.c and instead just directly read the edid from the hdim IP.
> > > Using drm_get_edid for something that's not backed by a real i2c bus is
> > > bonghits.
> > 
> > This patch just makes some change literally.  I do not understand how
> > the IP block works at all.  I thought the HDMI IP talks to monitors
> > using I2C protocol implemented inside the IP block.  I added Rockchip
> > folks to see if we can get any clarifications from them.
> 
> btw drm_edid.c gained a special variant for this case a while ago:
> drm_do_get_edid(). With that you can retain all the robustness/retrying
> logic, while providing your own special function to read an entire edid
> block. I think that's the function which should be used here.

Thanks much for the info, Daniel.  It's now clear where I should go for
my WIP HDMI driver.

Shawn

[Bug 115321] radeon runpm falsely disabled on Clevo P170EM

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=115321

--- Comment #8 from Peter Wu  ---
Created attachment 224001
  --> https://bugzilla.kernel.org/attachment.cgi?id=224001=edit
possible patch (force integers into bools)

Yay, I found documentation for the SGMD (SG Mode) field:
0 - None
1 - Switchable Graphics (Muxed)
2 - Switchable Graphics (Muxless)
3 - Discrete only

(Related: SGFL stands for Switchable Graphics Feature List.)

By the way, the functions mask 0x33 still covers ATPX_POWER_CONTROL_SUPPORTED
((1<<1) == 2). Something else must be broken.

Based on the dmesg, we can see that:

if (radeon_modeset == 1) {
DRM_INFO("radeon kernel modesetting enabled.\n"); // <-- called
driver = _driver;
// ...
radeon_register_atpx_handler(); // called, see dmesg:
// "[3.245994] vga_switcheroo: enabled"
// radeon_atpx_init is called after the previous printk.
// radeon_atpx_verify_interface is called and returns 0, see dmesg:
// "[3.246040] ATPX version 1, functions 0x0033"
// now radeon_atpx_parse_functions(..., 0x33) is called which:
// f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED;
// = 0x33 & (1 << 1) = 2 (which is a truth value)
}

/* let modprobe override vga console setting */
return drm_pci_init(driver, pdriver);
// driver.load (radeon_driver_load_kms) ->
//   radeon_device_init() ->
// radeon_has_atpx_dgpu_power_cntl() ->
//   return radeon_atpx_priv.atpx.functions.power_cntl // 2 per above

Maybe there is a compiler bug... can you try the attached patch?

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[PATCH v4.1 3/4] drm/bridge: analogix_dp: add the PSR function support

[Yakir Yang]

The full name of PSR is Panel Self Refresh, panel device could refresh
itself with the hardware framebuffer in panel, this would make lots of
sense to save the power consumption.

This patch have exported two symbols for platform driver to implement
the PSR function in hardware side:
- analogix_dp_active_psr()
- analogix_dp_inactive_psr()

Signed-off-by: Yakir Yang 
---
Changes in v4.1:
- Take use of existing edp_psr_vsc struct to swap HBx and DBx setting. (Sean)
- Remove PSR_VID_CRC_FLUSH setting analogix_dp_enable_psr_crc().
- Add comment about PBx magic numbers. (Sean)

Changes in v4:
- Downgrade the PSR version print message to debug level. (Sean)
- Return 'void' instead of 'int' in analogix_dp_enable_sink_psr(). (Sean)
- Delete the unused read dpcd operations in analogix_dp_enable_sink_psr(). 
(Sean)
- Delete the arbitrary usleep_range in analogix_dp_enable_psr_crc. (Sean).
- Clean up the hardcoded values in analogix_dp_send_psr_spd(). (Sean)
- Rename "active/inactive" to "enable/disable". (Sean, Dominik)
- Keep set the PSR_VID_CRC_FLUSH gate in analogix_dp_enable_psr_crc().

Changes in v3:
- split analogix_dp_enable_psr(), make it more clearly
analogix_dp_detect_sink_psr()
analogix_dp_enable_sink_psr()
- remove some nosie register setting comments

Changes in v2:
- introduce in v2, splite the common Analogix DP changes out

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 81 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  5 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 51 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h  | 34 +
 include/drm/bridge/analogix_dp.h   |  3 +
 5 files changed, 174 insertions(+)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 32715da..381b25e 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -97,6 +97,83 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device 
*dp)
return 0;
 }

+int analogix_dp_enable_psr(struct device *dev)
+{
+   struct analogix_dp_device *dp = dev_get_drvdata(dev);
+   struct edp_vsc_psr psr_vsc;
+
+   if (!dp->psr_support)
+   return -EINVAL;
+
+   /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
+   memset(_vsc, 0, sizeof(psr_vsc));
+   psr_vsc.sdp_header.HB0 = 0;
+   psr_vsc.sdp_header.HB1 = 0x7;
+   psr_vsc.sdp_header.HB2 = 0x2;
+   psr_vsc.sdp_header.HB3 = 0x8;
+
+   psr_vsc.DB0 = 0;
+   psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
+
+   analogix_dp_send_psr_spd(dp, _vsc);
+   return 0;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
+
+int analogix_dp_disable_psr(struct device *dev)
+{
+   struct analogix_dp_device *dp = dev_get_drvdata(dev);
+   struct edp_vsc_psr psr_vsc;
+
+   if (!dp->psr_support)
+   return -EINVAL;
+
+   /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
+   memset(_vsc, 0, sizeof(psr_vsc));
+   psr_vsc.sdp_header.HB0 = 0;
+   psr_vsc.sdp_header.HB1 = 0x7;
+   psr_vsc.sdp_header.HB2 = 0x2;
+   psr_vsc.sdp_header.HB3 = 0x8;
+
+   psr_vsc.DB0 = 0;
+   psr_vsc.DB1 = 0;
+
+   analogix_dp_send_psr_spd(dp, _vsc);
+   return 0;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
+
+static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
+{
+   unsigned char psr_version;
+
+   analogix_dp_read_byte_from_dpcd(dp, DP_PSR_SUPPORT, _version);
+   dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
+
+   return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
+}
+
+static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
+{
+   unsigned char psr_en;
+
+   /* Disable psr function */
+   analogix_dp_read_byte_from_dpcd(dp, DP_PSR_EN_CFG, _en);
+   psr_en &= ~DP_PSR_ENABLE;
+   analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en);
+
+   /* Main-Link transmitter remains active during PSR active states */
+   psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
+   analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en);
+
+   /* Enable psr function */
+   psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
+DP_PSR_CRC_VERIFICATION;
+   analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en);
+
+   analogix_dp_enable_psr_crc(dp);
+}
+
 static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 {
int i;
@@ -921,6 +998,10 @@ static void analogix_dp_commit(struct analogix_dp_device 
*dp)

/* Enable video */
analogix_dp_start_video(dp);
+
+   dp->psr_support = analogix_dp_detect_sink_psr(dp);
+   if (dp->psr_support)
+   analogix_dp_enable_sink_psr(dp);
 }

 int analogix_dp_get_modes(struct drm_connector *connector)
diff --git 

[PATCH v4.1 1/4] drm/rockchip: vop: export line flag function

[Yakir Yang]

VOP have integrated a hardware counter which indicate the exact display
line that vop is scanning. And if we're interested in a specific line,
we can set the line number to vop line_flag register, and then vop would
generate a line_flag interrupt for it.

For example eDP PSR function is interested in the vertical blanking
period, then driver could set the line number to zero.

This patch have exported a symbol that allow other driver to listen the
line flag event with given timeout limit:
-  rockchip_drm_wait_line_flag()

Signed-off-by: Yakir Yang 
---
Changes in v4.1:
- Remove the completion_done() check in irq handler (Sean)

Changes in v4:
- Avoid the weird behavior in rockchip_drm_wait_line_flag(). (Sean)
- Make line_flag_num_x to an array. (Sean)
- Remove the unused vop_cfg_done() in vop_line_flag_irq_enable(). (Stephane, 
reviewed in Google gerrit)

[https://chromium-review.googlesource.com/#/c/349084/33/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
 at 466]

Changes in v3:
- Export the 'rockchip_drm_wait_line_flag' symbol, and document it.
- Add 'line_flag_num_0' for RK3288/RK3036
- Remove the notify for waiting line_flag event (Daniel)

Changes in v2:
- Introduce in v2, split VOP line flag changes out

 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   3 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 117 
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   2 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |   4 +
 4 files changed, 126 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h 
b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index ea39329..239b830 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -70,4 +70,7 @@ int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
   struct device *dev);
 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
struct device *dev);
+int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
+   unsigned int mstimeout);
+
 #endif /* _ROCKCHIP_DRM_DRV_H_ */
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index c8a62a8..8a4f36e 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -121,6 +121,8 @@ struct vop {
/* protected by dev->event_lock */
struct drm_pending_vblank_event *event;

+   struct completion line_flag_completion;
+
const struct vop_data *data;

uint32_t *regsbak;
@@ -431,6 +433,71 @@ static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
spin_unlock_irqrestore(>irq_lock, flags);
 }

+/*
+ * (1) each frame starts at the start of the Vsync pulse which is signaled by
+ * the "FRAME_SYNC" interrupt.
+ * (2) the active data region of each frame ends at dsp_vact_end
+ * (3) we should program this same number (dsp_vact_end) into 
dsp_line_frag_num,
+ *  to get "LINE_FLAG" interrupt at the end of the active on screen data.
+ *
+ * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
+ * Interrupts
+ * LINE_FLAG ---+
+ * FRAME_SYNC + |
+ *| |
+ *v v
+ *| Vsync | Vbp |  Vactive  | Vfp |
+ *^ ^   ^ ^
+ *| |   | |
+ *| |   | |
+ * dsp_vs_end + |   | |   VOP_DSP_VTOTAL_VS_END
+ * dsp_vact_start --+   | |   VOP_DSP_VACT_ST_END
+ * dsp_vact_end + |   VOP_DSP_VACT_ST_END
+ * dsp_total -+   VOP_DSP_VTOTAL_VS_END
+ */
+static bool vop_line_flag_irq_is_enabled(struct vop *vop)
+{
+   uint32_t line_flag_irq;
+   unsigned long flags;
+
+   spin_lock_irqsave(>irq_lock, flags);
+
+   line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
+
+   spin_unlock_irqrestore(>irq_lock, flags);
+
+   return !!line_flag_irq;
+}
+
+static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
+{
+   unsigned long flags;
+
+   if (WARN_ON(!vop->is_enabled))
+   return;
+
+   spin_lock_irqsave(>irq_lock, flags);
+
+   VOP_CTRL_SET(vop, line_flag_num[0], line_num);
+   VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
+
+   spin_unlock_irqrestore(>irq_lock, flags);
+}
+
+static void vop_line_flag_irq_disable(struct vop *vop)
+{
+   unsigned long flags;
+
+   if (WARN_ON(!vop->is_enabled))
+   return;
+
+   spin_lock_irqsave(>irq_lock, flags);
+
+   VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
+
+   spin_unlock_irqrestore(>irq_lock, flags);
+}
+
 static void 

[Nouveau] [PATCH v3 0/4] nouveau RPM fixes for Optimus (final)

[Peter Wu]

On Fri, Jul 15, 2016 at 12:41:49PM -0400, Ilia Mirkin wrote:
> On Fri, Jul 15, 2016 at 12:36 PM, Peter Wu  wrote:
> > On Fri, Jul 15, 2016 at 12:10:23PM -0400, Ilia Mirkin wrote:
> >> On Fri, Jul 15, 2016 at 9:12 AM, Peter Wu  wrote:
> >> > Hi,
> >> >
> >> > Here are two patches to fix an issue reported on kernel bugzilla 
> >> > (infinite loop
> >> > due to unchecked function) and a more important fix to fix hanging 
> >> > Optimus
> >> > machines when runtime PM is enabled (with pm/pci patches).
> >> >
> >> > These are the final patches targeting v4.8. Changes compared to v2[1]:
> >> > collected R-b from Hans and Mika and fixed a minor comment style issue.
> >> >
> >> > I recommend it to be merged before the pci/pm patches[2], otherwise 
> >> > there is a
> >> > window where newer Nvidia Optimus laptops might fail to runtime resume 
> >> > and/or
> >> > lock up.  Once the pci/pm branch is merged I will propose another patch 
> >> > to
> >> > improve reliability[3].
> >> >
> >> > Known issue with patch 4: when a Nvidia HDMI audio function is present, 
> >> > the
> >> > bridge will not suspend and hence the Nvidia card will still be powered. 
> >> > Fixing
> >>
> >> That's basically all optimus gpu's, right? Anything GT21x+ has a HDMI
> >> audio subfunction, and prior to that, the nvidia gpu tended to be the
> >> only gpu, or hard-muxed.
> >>
> >> If that's the case, that's pretty much a non-starter, IMO.
> >
> > For some reason the audio function tends to disappear/hide, so maybe it
> > is not as problematic as it appears (see
> > https://bugs.freedesktop.org/show_bug.cgi?id=75985). For my laptop I
> 
> I'm aware of that bug. I believe this is an exceedingly rare scenario
> or it would have been reported a lot more.
> 
> > also had to runtime suspend/resume before lspci -H1 shows the device,
> > loading with runpm=0 didn't return my HDMI audio device.
> 
> Hm ok. Do you have the same laptop as the reporter of that bug?

Nope, I have a Clevo P651RA (GTX965M). That reporter has a Dell XPS 15,
but it also seems present for the Lenovo ThinkPad T420s (see comment on
bug), Asus N56VZ, MSI GT60 2PE, Dell L502x (Launchpad 1377653), Asus
G46vw (Ask Ubuntu user). There is another AU report for a GT 525M
(laptop brand/model unknown).

Maybe there are more affected users, but then they did not notice it
because they did not use HDMI audio.

> >
> > The powered on issue will also only appear on devices produced in 2013
> > and newer that happen to have this ACPI _PR3 ACPI method (which is quite
> > common for new machines supporting Windows 8 though).
> >
> > For these newer laptops, after the pci/pm merge and after a patch like
> > http://www.spinics.net/lists/linux-pci/msg52601.html, the user can
> > revert to the old DSM method by booting with pcie_port_pm=off which will
> > retain the current behavior.
> >
> > The advantage of this patch is that it fixes memory corruption on some
> > devices. The risk is that the card stays on because the audio subsystem
> > needs some more work.  FWIW, I was working on some patches that properly
> > suspended in presence of the HDA controller, but somehow the audio
> > device was not properly resumed resulting in "no AFG or MFG node found"
> > and "snd_hda_intel :01:00.1: no codecs initialized".
> 
> Does this restriction (runpm being broken in presence of the audio
> subfunction) only affect devices with _PR3? If so, that's a lot more
> palatable - I bet Windows 8+ is in an era when the display-less thing
> became more popular, and thus less likely to affect a ton of people.

Yes it only affects those devices with _PR3.
-- 
Kind regards,
Peter Wu
https://lekensteyn.nl

[PATCH v4 3/4] drm/bridge: analogix_dp: add the PSR function support

[Yakir Yang]

)
>>> +{
>>> +   unsigned int val;
>>> +   unsigned int i;
>>> +
>>> +   /* don't send info frame */
>>> +   val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>>> +   val &= ~IF_EN;
>>> +   writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>>> +
>>> +   /* configure single frame update mode */
>>> +   writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE,
>>> +  dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL);
>>> +
>>> +   /* configure VSC HB0~HB3 and PB0~PB3 */
>>> +   for (i = 0; i < 4; i++)
>>> +   writel(psr_spd_hbx[i], dp->reg_base + ANALOGIX_DP_SPD_HB + i*4);
>>> +   for (i = 0; i < 4; i++)
>>> +   writel(psr_spd_pbx[i], dp->reg_base + ANALOGIX_DP_SPD_PB + i*4);
>>> +
>>> +   /* configure DB0 / DB1 values */
>>> +   writel(0x0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
>>> +   writel(db1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
>>> +
>>> +   /* set reuse spd inforframe */
>>> +   val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>>> +   val |= REUSE_SPD_EN;
>>> +   writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>>> +
>>> +   /* mark info frame update */
>>> +   val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>>> +   val = (val | IF_UP) & ~IF_EN;
>>> +   writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>>> +
>>> +   /* send info frame */
>>> +   val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>>> +   val |= IF_EN;
>>> +   writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>>> +}
>>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
>>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>>> index cdcc6c5..fd232b2 100644
>>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>>> @@ -22,6 +22,8 @@
>>>   #define ANALOGIX_DP_VIDEO_CTL_8   0x3C
>>>   #define ANALOGIX_DP_VIDEO_CTL_10  0x44
>>>   
>>> +#define ANALOGIX_DP_SPDIF_AUDIO_CTL_0  0xD8
>>> +
>>>   #define ANALOGIX_DP_PLL_REG_1 0xfc
>>>   #define ANALOGIX_DP_PLL_REG_2 0x9e4
>>>   #define ANALOGIX_DP_PLL_REG_3 0x9e8
>>> @@ -30,6 +32,15 @@
>>>   
>>>   #define ANALOGIX_DP_PD0x12c
>>>   
>>> +#define ANALOGIX_DP_IF_TYPE0x244
>>> +#define ANALOGIX_DP_IF_PKT_DB1 0x254
>>> +#define ANALOGIX_DP_IF_PKT_DB2 0x258
>>> +#define ANALOGIX_DP_SPD_HB 0x2F8
>>> +#define ANALOGIX_DP_SPD_PB 0x308
>>> +#define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL  0x318
>>> +#define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C
>>> +#define ANALOGIX_DP_VSC_SHADOW_DB1 0x320
>>> +
>>>   #define ANALOGIX_DP_LANE_MAP  0x35C
>>>   
>>>   #define ANALOGIX_DP_ANALOG_CTL_1  0x370
>>> @@ -103,6 +114,8 @@
>>>   
>>>   #define ANALOGIX_DP_SOC_GENERAL_CTL   0x800
>>>   
>>> +#define ANALOGIX_DP_CRC_CON0x890
>>> +
>>>   /* ANALOGIX_DP_TX_SW_RESET */
>>>   #define RESET_DP_TX   (0x1 << 0)
>>>   
>>> @@ -151,6 +164,7 @@
>>>   #define VID_CHK_UPDATE_TYPE_SHIFT (4)
>>>   #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
>>>   #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
>>> +#define REUSE_SPD_EN   (0x1 << 3)
>>>   
>>>   /* ANALOGIX_DP_VIDEO_CTL_8 */
>>>   #define VID_HRES_TH(x)(((x) & 0xf) << 4)
>>> @@ -167,6 +181,12 @@
>>>   #define REF_CLK_27M   (0x0 << 0)
>>>   #define REF_CLK_MASK  (0x1 << 0)
>>>   
>>> +/* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */
>>> +#define PSR_FRAME_UP_TYPE_BURST(0x1 << 0)
>>> +#define PSR_FRAME_UP_TYPE_SINGLE   (0x0 << 0)
>>> +#define PSR_CRC_SEL_HARDWARE   (0x1 << 1)
>>> +#define PSR_CRC_SEL_MANUALLY   (0x0 << 1)
>>> +
>>>   /* ANALOGIX_DP_LANE_MAP */
>>>   #define LANE3_MAP_LOGIC_LANE_0(0x0 << 6)
>>>   #define LANE3_MAP_LOGIC_LANE_1(0x1 << 6)
>>> @@ -376,4 +396,12 @@
>>>   #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
>>>   #define VIDEO_MODE_MASTER_MODE(0x0 << 0)
>>>   
>>> +/* ANALOGIX_DP_PKT_SEND_CTL */
>>> +#define IF_UP  (0x1 << 4)
>>> +#define IF_EN  (0x1 << 0)
>>> +
>>> +/* ANALOGIX_DP_CRC_CON */
>>> +#define PSR_VID_CRC_FLUSH  (0x1 << 2)
>>> +#define PSR_VID_CRC_ENABLE (0x1 << 0)
>>> +
>>>   #endif /* _ANALOGIX_DP_REG_H */
>>> diff --git a/include/drm/bridge/analogix_dp.h 
>>> b/include/drm/bridge/analogix_dp.h
>>> index 261b86d..9cd8838 100644
>>> --- a/include/drm/bridge/analogix_dp.h
>>> +++ b/include/drm/bridge/analogix_dp.h
>>> @@ -38,6 +38,9 @@ struct analogix_dp_plat_data {
>>>  struct drm_connector *);
>>>   };
>>>   
>>> +int analogix_dp_enable_psr(struct device *dev);
>>> +int analogix_dp_disable_psr(struct device *dev);
>>> +
>>>   int analogix_dp_resume(struct device *dev);
>>>   int analogix_dp_suspend(struct device *dev);
>>>   
>>> -- 
>>> 1.9.1
>>>
>>>
>>> ___
>>> dri-devel mailing list
>>> dri-devel at lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>

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[Nouveau] [PATCH v3 0/4] nouveau RPM fixes for Optimus (final)

[Peter Wu]

On Fri, Jul 15, 2016 at 12:10:23PM -0400, Ilia Mirkin wrote:
> On Fri, Jul 15, 2016 at 9:12 AM, Peter Wu  wrote:
> > Hi,
> >
> > Here are two patches to fix an issue reported on kernel bugzilla (infinite 
> > loop
> > due to unchecked function) and a more important fix to fix hanging Optimus
> > machines when runtime PM is enabled (with pm/pci patches).
> >
> > These are the final patches targeting v4.8. Changes compared to v2[1]:
> > collected R-b from Hans and Mika and fixed a minor comment style issue.
> >
> > I recommend it to be merged before the pci/pm patches[2], otherwise there 
> > is a
> > window where newer Nvidia Optimus laptops might fail to runtime resume 
> > and/or
> > lock up.  Once the pci/pm branch is merged I will propose another patch to
> > improve reliability[3].
> >
> > Known issue with patch 4: when a Nvidia HDMI audio function is present, the
> > bridge will not suspend and hence the Nvidia card will still be powered. 
> > Fixing
> 
> That's basically all optimus gpu's, right? Anything GT21x+ has a HDMI
> audio subfunction, and prior to that, the nvidia gpu tended to be the
> only gpu, or hard-muxed.
> 
> If that's the case, that's pretty much a non-starter, IMO.

For some reason the audio function tends to disappear/hide, so maybe it
is not as problematic as it appears (see
https://bugs.freedesktop.org/show_bug.cgi?id=75985). For my laptop I
also had to runtime suspend/resume before lspci -H1 shows the device,
loading with runpm=0 didn't return my HDMI audio device.

The powered on issue will also only appear on devices produced in 2013
and newer that happen to have this ACPI _PR3 ACPI method (which is quite
common for new machines supporting Windows 8 though).

For these newer laptops, after the pci/pm merge and after a patch like
http://www.spinics.net/lists/linux-pci/msg52601.html, the user can
revert to the old DSM method by booting with pcie_port_pm=off which will
retain the current behavior.

The advantage of this patch is that it fixes memory corruption on some
devices. The risk is that the card stays on because the audio subsystem
needs some more work.  FWIW, I was working on some patches that properly
suspended in presence of the HDA controller, but somehow the audio
device was not properly resumed resulting in "no AFG or MFG node found"
and "snd_hda_intel :01:00.1: no codecs initialized".
-- 
Kind regards,
Peter Wu
https://lekensteyn.nl

[PATCH] drm/i915/skl: Fix redundant cursor update, fix cursor underruns

[Lyude]

At long last, the time has finally come for Skylake users to plug their
external displays back in.

During intel_atomic_commit() on Skylake, we've actually been arming the
registers to update the cursor information twice instead of just once.
Once in i9xx_update_cursor(), and once in skl_wm_flush_pipe(). This
isn't actually necessary, and removing the later update in
skl_wm_flush_pipe() has completely stopped the underruns on this T460p
from occurring when moving the mouse cursor from one monitor to another.

Signed-off-by: Lyude 
Cc: Radhakrishna Sripada 
Cc: Hans de Goede 
Cc: stable at vger.kernel.org
---
 drivers/gpu/drm/i915/intel_pm.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7ac71ec..4771a03 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3860,7 +3860,6 @@ skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum 
pipe pipe, int pass)
I915_WRITE(PLANE_SURF(pipe, plane),
   I915_READ(PLANE_SURF(pipe, plane)));
}
-   I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
 }

 static bool
-- 
2.7.4

[GIT PULL] drm/fsl-dcu: add drm bridge for v4.8

[Stefan Agner]

Hi Dave,

This adds drm bridge support for the NXP/Freescale DCU. The patchset
has been discussed on the mailing list since quite some time...
Plus there is a small fix provided by Peter.

--
Stefan

The following changes since commit f82c13722275b6aca3a956a82846465ec789b367:

  Merge branch 'exynos-drm-next' of 
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next 
(2016-07-15 14:05:41 +1000)

are available in the git repository at:

  http://git.agner.ch/git/linux-drm-fsl-dcu.git for-next

for you to fetch changes up to c4a304d3b1dc9d1732b5d78cc190b5c3e41870d4:

  drm/fsl-dcu: add support for drm bridge (2016-07-15 18:06:28 -0700)


Meng Yi (2):
  drm/fsl-dcu: rework codes to support of_graph dt binding for panel
  drm/fsl-dcu: add support for drm bridge

Peter Chen (1):
  drm/fsl-dcu: add missing of_node_put after calling of_parse_phandle

 .../devicetree/bindings/display/fsl,dcu.txt|  9 ++-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c  |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h   |  3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c  | 78 --
 drivers/gpu/drm/fsl-dcu/fsl_tcon.c |  1 +
 5 files changed, 68 insertions(+), 25 deletions(-)

[PATCH v4 8/8] arm: dts: mt2701: Add display subsystem related nodes for MT2701

[YT Shen]

This patch adds the device nodes for the DISP function blocks for MT2701

Signed-off-by: YT Shen 
---
 arch/arm/boot/dts/mt2701.dtsi |  100 +
 1 file changed, 100 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 363de0d..7da9310 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -24,6 +24,11 @@
compatible = "mediatek,mt2701";
interrupt-parent = <>;

+   aliases {
+   rdma0 = 
+   rdma1 = 
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -171,6 +176,16 @@
power-domains = < MT2701_POWER_DOMAIN_DISP>;
};

+   mipi_tx0: mipi-dphy at 1001 {
+   compatible = "mediatek,mt2701-mipi-tx";
+   reg = <0 0x1001 0 0x90>;
+   clocks = <>;
+   clock-output-names = "mipi_tx0_pll";
+   #clock-cells = <0>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
sysirq: interrupt-controller at 10200100 {
compatible = "mediatek,mt2701-sysirq",
 "mediatek,mt6577-sysirq";
@@ -255,6 +270,68 @@
status = "disabled";
};

+   ovl at 14007000 {
+   compatible = "mediatek,mt2701-disp-ovl";
+   reg = <0 0x14007000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DISP_OVL>;
+   iommus = < MT2701_M4U_PORT_DISP_OVL_0>;
+   mediatek,larb = <>;
+   };
+
+   rdma0: rdma at 14008000 {
+   compatible = "mediatek,mt2701-disp-rdma";
+   reg = <0 0x14008000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DISP_RDMA>;
+   iommus = < MT2701_M4U_PORT_DISP_RDMA>;
+   mediatek,larb = <>;
+   };
+
+   wdma at 14009000 {
+   compatible = "mediatek,mt2701-disp-wdma";
+   reg = <0 0x14009000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DISP_WDMA>;
+   iommus = < MT2701_M4U_PORT_DISP_WDMA>;
+   mediatek,larb = <>;
+   };
+
+   bls at 1400a000 {
+   compatible = "mediatek,mt2701-disp-pwm";
+   reg = <0 0x1400a000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DISP_BLS>;
+   };
+
+   color at 1400b000 {
+   compatible = "mediatek,mt2701-disp-color";
+   reg = <0 0x1400b000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DISP_COLOR>;
+   };
+
+   dsi0: dsi at 1400c000 {
+   compatible = "mediatek,mt2701-dsi";
+   reg = <0 0x1400c000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DSI_ENGINE>, < CLK_MM_DSI_DIG>,
+<_tx0>;
+   clock-names = "engine", "digital", "hs";
+   mediatek,syscon-dsi = < 0x138>;
+   mediatek,ssc-range = <5>;
+   phys = <_tx0>;
+   phy-names = "dphy";
+   status = "disabled";
+   };
+
+   mutex: mutex at 1400e000 {
+   compatible = "mediatek,mt2701-disp-mutex";
+   reg = <0 0x1400e000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_MUTEX_32K>;
+   };
+
larb0: larb at 1401 {
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x1401 0 0x1000>;
@@ -265,6 +342,29 @@
power-domains = < MT2701_POWER_DOMAIN_DISP>;
};

+   rdma1: rdma at 14012000 {
+   compatible = "mediatek,mt2701-disp-rdma";
+   reg = <0 0x14012000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DISP_RDMA1>;
+   iommus = < MT2701_M4U_PORT_DISP_RDMA1>;
+   mediatek,larb = <>;
+   };
+
+   dpi0: dpi at 14014000 {
+   compatible = "mediatek,mt2701-dpi";
+   reg = <0 0x14014000 0 0x1000>;
+   interrupts = ;
+   clocks = < CLK_MM_DPI1_DIGL>,
+< CLK_MM_DPI1_ENGINE>,
+< CLK_TOP_DPI1_SEL>,
+< CLK_TOP_TVDPLL>,
+< CLK_TOP_TVDPLL_D2>,
+< CLK_TOP_TVDPLL_D4>;
+   clock-names = "pixel", "engine", "sel","div1","div2","div4";
+   status = "disabled";
+   };
+
imgsys: syscon at 1500 {
compatible = "mediatek,mt2701-imgsys", "syscon";
reg = <0 0x1500 0 0x1000>;
-- 
1.7.9.5

[PATCH v4 7/8] drm/mediatek: add mipi panel support

[YT Shen]

From: shaoming chen 

add dsi and mipi tx driver for mipi panel support

Signed-off-by: shaoming chen 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c |  169 ++--
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c |   82 +++-
 2 files changed, 173 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 1f99894..4eae63c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -29,9 +29,6 @@

 #include "mtk_drm_ddp_comp.h"

-#define DSI_VIDEO_FIFO_DEPTH   (1920 / 4)
-#define DSI_HOST_FIFO_DEPTH64
-
 #define DSI_START  0x00

 #define DSI_INTEN  0x08
@@ -55,7 +52,7 @@
 #define MIX_MODE   BIT(17)

 #define DSI_TXRX_CTRL  0x18
-#define VC_NUM (2 << 0)
+#define VC_NUM BIT(1)
 #define LANE_NUM   (0xf << 2)
 #define DIS_EOTBIT(6)
 #define NULL_ENBIT(7)
@@ -94,6 +91,8 @@
 #define DSI_RACK   0x84
 #define RACK   BIT(0)

+#define DSI_MEM_CONTI  0x90
+
 #define DSI_PHY_LCCON  0x104
 #define LC_HS_TX_ENBIT(0)
 #define LC_ULPM_EN BIT(1)
@@ -126,6 +125,10 @@
 #define CLK_HS_POST(0xff << 8)
 #define CLK_HS_EXIT(0xff << 16)

+#define DSI_VM_CMD_CON 0x130
+#define VM_CMD_EN  BIT(0)
+#define TS_VFP_EN  BIT(5)
+
 #define DSI_CMDQ0  0x180

 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
@@ -239,11 +242,11 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, 
u32 mask, u32 data)
writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 }

-static void dsi_phy_timconfig(struct mtk_dsi *dsi)
+static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 {
u32 timcon0, timcon1, timcon2, timcon3;
-   unsigned int ui, cycle_time;
-   unsigned int lpx;
+   u32 ui, cycle_time;
+   u32 lpx;

ui = 1000 / dsi->data_rate + 0x01;
cycle_time = 8000 / dsi->data_rate + 0x01;
@@ -273,7 +276,7 @@ static void mtk_dsi_disable(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 }

-static void mtk_dsi_reset(struct mtk_dsi *dsi)
+static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
@@ -293,7 +296,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
 * we set mipi_ratio is 1.05.
 */
-   dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10);
+   dsi->data_rate = dsi->vm.pixelclock * 12 * 21;
+   dsi->data_rate /= (dsi->lanes * 1000 * 10);
+   dev_info(dev, "set mipitx's data rate: %dMHz\n", dsi->data_rate);

ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 100);
if (ret < 0) {
@@ -315,10 +320,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
goto err_disable_engine_clk;
}

-   mtk_dsi_enable(dsi);
-   mtk_dsi_reset(dsi);
-   dsi_phy_timconfig(dsi);
-
return 0;

 err_disable_engine_clk:
@@ -330,33 +331,33 @@ err_refcount:
return ret;
 }

-static void dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
+static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
-   mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
+   mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, LC_ULPM_EN);
 }

-static void dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
+static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 }

-static void dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
+static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
-   mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
+   mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, LD0_ULPM_EN);
 }

-static void dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
+static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 }

-static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
+static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 {
u32 tmp_reg1;

@@ -364,15 +365,15 @@ static bool dsi_clk_hs_state(struct mtk_dsi *dsi)
return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 }

-static 

[PATCH v4 6/8] drm/mediatek: add dsi transfer function

[YT Shen]

From: shaoming chen 

add dsi read/write commands for transfer function

Signed-off-by: shaoming chen 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c |  322 
 1 file changed, 322 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index de5ad7f..1f99894 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 

 #include "mtk_drm_ddp_comp.h"
@@ -80,8 +81,16 @@
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58

+#define DSI_CMDQ_SIZE  0x60
+#define CMDQ_SIZE  0x3f
+
 #define DSI_HSTX_CKL_WC0x64

+#define DSI_RX_DATA0   0x74
+#define DSI_RX_DATA1   0x78
+#define DSI_RX_DATA2   0x7c
+#define DSI_RX_DATA3   0x80
+
 #define DSI_RACK   0x84
 #define RACK   BIT(0)

@@ -117,8 +126,25 @@
 #define CLK_HS_POST(0xff << 8)
 #define CLK_HS_EXIT(0xff << 16)

+#define DSI_CMDQ0  0x180
+
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))

+#define MTK_DSI_HOST_IS_READ(type) \
+   ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
+   (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
+   (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
+   (type == MIPI_DSI_DCS_READ))
+
+#define MTK_DSI_HOST_IS_WRITE(type) \
+   ((type == MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM) || \
+   (type == MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM) || \
+   (type == MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM) || \
+   (type == MIPI_DSI_DCS_SHORT_WRITE) || \
+   (type == MIPI_DSI_DCS_SHORT_WRITE_PARAM) || \
+   (type == MIPI_DSI_GENERIC_LONG_WRITE) || \
+   (type == MIPI_DSI_DCS_LONG_WRITE))
+
 struct phy;

 struct mtk_dsi {
@@ -148,6 +174,38 @@ struct mtk_dsi {
int irq_num, irq_data;
 };

+struct dsi_cmd_t0 {
+   u8 config;
+   u8 type;
+   u8 data0;
+   u8 data1;
+};
+
+struct dsi_cmd_t2 {
+   u8 config;
+   u8 type;
+   u16 wc16;
+   u8 *pdata;
+};
+
+struct dsi_rx_data {
+   u8 byte0;
+   u8 byte1;
+   u8 byte2;
+   u8 byte3;
+};
+
+struct dsi_tx_cmdq {
+   u8 byte0;
+   u8 byte1;
+   u8 byte2;
+   u8 byte3;
+};
+
+struct dsi_tx_cmdq_regs {
+   struct dsi_tx_cmdq data[128];
+};
+
 enum {
DSI_INT_SLEEPOUT_DONE_FLAG  = BIT(6),
DSI_INT_VM_CMD_DONE_FLAG= BIT(5),
@@ -858,9 +916,273 @@ static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
return 0;
 }

+static void mtk_dsi_set_cmdq(void __iomem *reg, u32 mask, u32 data)
+{
+   u32 temp = readl(reg);
+
+   writel((temp & ~mask) | (data & mask), reg);
+}
+
+static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
+{
+   u32 timeout_ms = 50; /* total 1s ~ 2s timeout */
+
+   while (timeout_ms--) {
+   if (!(readl(dsi->regs + DSI_INTSTA) & DSI_BUSY))
+   break;
+
+   usleep_range(2, 4);
+   }
+
+   if (timeout_ms == 0) {
+   dev_info(dsi->dev, "polling dsi wait not busy timeout!\n");
+
+   mtk_dsi_enable(dsi);
+   mtk_dsi_reset_engine(dsi);
+   }
+}
+
+static ssize_t mtk_dsi_host_read_cmd(struct mtk_dsi *dsi,
+const struct mipi_dsi_msg *msg)
+{
+   u8 max_try_count = 5;
+   u32 recv_data_cnt, tmp_val;
+   u32 recv_data0, recv_data1, recv_data2, recv_data3;
+   struct dsi_rx_data read_data0, read_data1, read_data2, read_data3;
+   struct dsi_cmd_t0 t0;
+   s32 ret;
+
+   u8 *buffer = msg->rx_buf;
+   u8 buffer_size = msg->rx_len;
+   u8 packet_type;
+
+   if (readl(dsi->regs + DSI_MODE_CTRL) & 0x03) {
+   dev_info(dsi->dev, "dsi engine is not command mode\n");
+   return -1;
+   }
+
+   if (!buffer) {
+   dev_info(dsi->dev, "dsi receive buffer size may be NULL\n");
+   return -1;
+   }
+
+   do {
+   if (max_try_count == 0) {
+   dev_info(dsi->dev, "dsi engine read counter has been 
maxinum\n");
+   return -1;
+   }
+
+   max_try_count--;
+   recv_data_cnt = 0;
+
+   mtk_dsi_wait_for_idle(dsi);
+
+   t0.config = 0x04;
+   t0.data0 = *((u8 *)(msg->tx_buf));
+
+   if (buffer_size < 0x3)
+   t0.type = MIPI_DSI_DCS_READ;
+   else
+   t0.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
+
+   t0.data1 = 0;
+
+   tmp_val = (t0.data1 << 24) | (t0.data0 << 16) | (t0.type << 8) |
+   t0.config;
+
+   writel(tmp_val, dsi->regs + DSI_CMDQ0);
+   mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, 

[PATCH v4 5/8] drm/mediatek: add dsi interrupt control

[YT Shen]

From: shaoming chen 

add dsi interrupt control

Signed-off-by: shaoming chen 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c |  130 
 1 file changed, 130 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 2d808e5..de5ad7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -32,6 +33,13 @@

 #define DSI_START  0x00

+#define DSI_INTEN  0x08
+
+#define DSI_INTSTA 0x0c
+#define LPRX_RD_RDY_INT_FLAG   BIT(0)
+#define CMD_DONE_INT_FLAG  BIT(1)
+#define DSI_BUSY   BIT(31)
+
 #define DSI_CON_CTRL   0x10
 #define DSI_RESET  BIT(0)
 #define DSI_EN BIT(1)
@@ -74,6 +82,9 @@

 #define DSI_HSTX_CKL_WC0x64

+#define DSI_RACK   0x84
+#define RACK   BIT(0)
+
 #define DSI_PHY_LCCON  0x104
 #define LC_HS_TX_ENBIT(0)
 #define LC_ULPM_EN BIT(1)
@@ -134,6 +145,18 @@ struct mtk_dsi {
struct videomode vm;
int refcount;
bool enabled;
+   int irq_num, irq_data;
+};
+
+enum {
+   DSI_INT_SLEEPOUT_DONE_FLAG  = BIT(6),
+   DSI_INT_VM_CMD_DONE_FLAG= BIT(5),
+   DSI_INT_EXT_TE_RDY_FLAG = BIT(4),
+   DSI_INT_VM_DONE_FLAG= BIT(3),
+   DSI_INT_TE_RDY_FLAG = BIT(2),
+   DSI_INT_CMD_DONE_FLAG   = BIT(1),
+   DSI_INT_LPRX_RD_RDY_FLAG= BIT(0),
+   DSI_INT_ALL_BITS= (0x7f)
 };

 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -440,6 +463,94 @@ static void mtk_dsi_start(struct mtk_dsi *dsi)
writel(1, dsi->regs + DSI_START);
 }

+static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
+{
+   u32 inten = DSI_INT_ALL_BITS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO)
+   inten &= ~(DSI_INT_TE_RDY_FLAG | DSI_INT_EXT_TE_RDY_FLAG);
+
+   writel(inten, dsi->regs + DSI_INTEN);
+}
+
+static void mtk_dsi_irq_wakeup(struct mtk_dsi *dsi, u32 irq_bit)
+{
+   dsi->irq_data |= irq_bit;
+}
+
+static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
+{
+   struct mtk_dsi *dsi = dev_id;
+
+   u32 status, tmp;
+
+   status = readl(dsi->regs + DSI_INTSTA);
+
+   if (status & DSI_INT_LPRX_RD_RDY_FLAG) {
+   /* write clear RD_RDY interrupt */
+   /* write clear RD_RDY interrupt must be before DSI_RACK */
+   /* because CMD_DONE will raise after DSI_RACK, */
+   /* so write clear RD_RDY after that will clear CMD_DONE too */
+   do {
+   /* send read ACK */
+   mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
+   tmp = readl(dsi->regs + DSI_INTSTA);
+   } while (tmp & DSI_BUSY);
+
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_LPRX_RD_RDY_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_LPRX_RD_RDY_FLAG);
+   }
+
+   if (status & DSI_INT_CMD_DONE_FLAG) {
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_CMD_DONE_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_CMD_DONE_FLAG);
+   }
+
+   if (status & DSI_INT_TE_RDY_FLAG) {
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_TE_RDY_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_TE_RDY_FLAG);
+   }
+
+   if (status & DSI_INT_VM_DONE_FLAG) {
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_DONE_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_DONE_FLAG);
+   }
+
+   if (status & DSI_INT_EXT_TE_RDY_FLAG) {
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_EXT_TE_RDY_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_EXT_TE_RDY_FLAG);
+   }
+
+   if (status & DSI_INT_VM_CMD_DONE_FLAG) {
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_VM_CMD_DONE_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_VM_CMD_DONE_FLAG);
+   }
+
+   if (status & DSI_INT_SLEEPOUT_DONE_FLAG) {
+   mtk_dsi_mask(dsi, DSI_INTSTA, DSI_INT_SLEEPOUT_DONE_FLAG, 0);
+   mtk_dsi_irq_wakeup(dsi, DSI_INT_SLEEPOUT_DONE_FLAG);
+   }
+
+   return IRQ_HANDLED;
+}
+
+static s32 mtk_dsi_wait_for_irq_timeout(struct mtk_dsi *dsi, u32 irq_bit,
+   u32 timeout_ms)
+{
+   while (timeout_ms--) {
+   if (dsi->irq_data & irq_bit) {
+   dsi->irq_data &= ~irq_bit;
+   return 0;
+   }
+
+   usleep_range(1000, 1100);
+   }
+
+   dsi->irq_data = 0;
+
+   return -1;
+}
+
 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 {
if (WARN_ON(dsi->refcount == 0))
@@ -488,6 +599,7 @@ static void 

[PATCH v4 4/8] drm/mediatek: add support for Mediatek SoC MT2701

[YT Shen]

This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.

Signed-off-by: YT Shen 
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |6 
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|6 
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  |   41 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |7 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   31 
 6 files changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index eb5c05e..1da0a71 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -286,11 +286,17 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
return 0;
 }

+static const struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = {
+   .ovl = {0x0040, 1 << 12, 0}
+};
+
 static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = {
.ovl = {0x0f40, 0, 1 << 12}
 };

 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-ovl",
+ .data = _ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
  .data = _ovl_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index fb0db50..506a353 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -225,11 +225,17 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
return 0;
 }

+static const struct mtk_ddp_comp_driver_data mt2701_rdma_driver_data = {
+   .rdma_fifo_pseudo_size = SZ_4K,
+};
+
 static const struct mtk_ddp_comp_driver_data mt8173_rdma_driver_data = {
.rdma_fifo_pseudo_size = SZ_8K,
 };

 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
+   { .compatible = "mediatek,mt2701-disp-rdma",
+ .data = _rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
  .data = _rdma_driver_data},
{},
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index fa53806..ee0326a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -32,6 +32,10 @@
 #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
 #define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100

+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+
 #define DISP_REG_MUTEX_EN(n)   (0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)  (0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)  (0x28 + 0x20 * (n))
@@ -54,6 +58,13 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
 #define MT8173_MUTEX_MOD_DISP_OD   BIT(25)

+#define MT2701_MUTEX_MOD_DISP_OVL  BIT(3)
+#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
+#define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
+#define MT2701_MUTEX_MOD_DISP_BLS  BIT(9)
+#define MT2701_MUTEX_MOD_DISP_RDMA0BIT(10)
+#define MT2701_MUTEX_MOD_DISP_RDMA1BIT(12)
+
 #define MUTEX_SOF_SINGLE_MODE  0
 #define MUTEX_SOF_DSI0 1
 #define MUTEX_SOF_DSI1 2
@@ -69,6 +80,10 @@
 #define DPI0_SEL_IN_RDMA1  0x1
 #define COLOR1_SEL_IN_OVL1 0x1

+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define DSI_SEL_IN_BLS 0x0
+
 struct mtk_disp_mutex {
int id;
bool claimed;
@@ -82,6 +97,15 @@ struct mtk_ddp {
const unsigned int  *mutex_mod;
 };

+static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
+   [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
+   [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
+   [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
+   [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
+};
+
 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -109,6 +133,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id 
cur,
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
+   } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+   value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) 

[PATCH v4 3/8] drm/mediatek: add shadow register support

[YT Shen]

We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.

Signed-off-by: YT Shen 
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |   75 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  |   22 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |1 +
 4 files changed, 71 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 24aa3ba..80d9641 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -315,6 +315,42 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc 
*mtk_crtc)
pm_runtime_put(drm->dev);
 }

+static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
+{
+   struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+   struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
+   struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+   unsigned int i;
+
+   /*
+* TODO: instead of updating the registers here, we should prepare
+* working registers in atomic_commit and let the hardware command
+* queue update module registers on vblank.
+*/
+   if (state->pending_config) {
+   mtk_ddp_comp_config(ovl, state->pending_width,
+   state->pending_height,
+   state->pending_vrefresh);
+
+   state->pending_config = false;
+   }
+
+   if (mtk_crtc->pending_planes) {
+   for (i = 0; i < OVL_LAYER_NR; i++) {
+   struct drm_plane *plane = _crtc->planes[i].base;
+   struct mtk_plane_state *plane_state;
+
+   plane_state = to_mtk_plane_state(plane->state);
+
+   if (plane_state->pending.config) {
+   mtk_ddp_comp_layer_config(ovl, i, plane_state);
+   plane_state->pending.config = false;
+   }
+   }
+   mtk_crtc->pending_planes = false;
+   }
+}
+
 static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
@@ -391,6 +427,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  struct drm_crtc_state *old_crtc_state)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+   struct mtk_drm_private *priv = crtc->dev->dev_private;
unsigned int pending_planes = 0;
int i;

@@ -409,6 +446,12 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc 
*crtc,
}
if (pending_planes)
mtk_crtc->pending_planes = true;
+
+   if (priv->data->shadow_register) {
+   mtk_disp_mutex_acquire(mtk_crtc->mutex);
+   mtk_crtc_ddp_config(crtc);
+   mtk_disp_mutex_release(mtk_crtc->mutex);
+   }
 }

 static const struct drm_crtc_funcs mtk_crtc_funcs = {
@@ -453,36 +496,10 @@ err_cleanup_crtc:
 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
 {
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
-   struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
-   unsigned int i;
+   struct mtk_drm_private *priv = crtc->dev->dev_private;

-   /*
-* TODO: instead of updating the registers here, we should prepare
-* working registers in atomic_commit and let the hardware command
-* queue update module registers on vblank.
-*/
-   if (state->pending_config) {
-   mtk_ddp_comp_config(ovl, state->pending_width,
-   state->pending_height,
-   state->pending_vrefresh);
-
-   state->pending_config = false;
-   }
-
-   if (mtk_crtc->pending_planes) {
-   for (i = 0; i < OVL_LAYER_NR; i++) {
-   struct drm_plane *plane = _crtc->planes[i].base;
-   struct mtk_plane_state *plane_state;
-
-   plane_state = to_mtk_plane_state(plane->state);
-
-   if (plane_state->pending.config) {
-   mtk_ddp_comp_layer_config(ovl, i, plane_state);
-   plane_state->pending.config = false;
-   }
-   }
-   mtk_crtc->pending_planes = false;
-   }
+   if (!priv->data->shadow_register)
+   mtk_crtc_ddp_config(crtc);

mtk_drm_finish_page_flip(mtk_crtc);
 }
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8030769..fa53806 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -12,6 +12,7 @@
  */

 #include 
+#include 
 #include 
 

[PATCH v4 2/8] drm/mediatek: add *driver_data for different hardware settings

[YT Shen]

There are some hardware settings changed, between MT8173 & MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod.

Signed-off-by: YT Shen 
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |   26 --
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|   11 +--
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  |   11 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |   27 +--
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   13 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   25 ++---
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |8 
 7 files changed, 92 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8f62671f..eb5c05e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -40,8 +40,6 @@
 #defineOVL_RDMA_MEM_GMC0x40402020

 #define OVL_CON_BYTE_SWAP  BIT(24)
-#define OVL_CON_CLRFMT_RGB565  (0 << 12)
-#define OVL_CON_CLRFMT_RGB888  (1 << 12)
 #define OVL_CON_CLRFMT_RGBA(2 << 12)
 #define OVL_CON_CLRFMT_ARGB(3 << 12)
 #defineOVL_CON_AEN BIT(8)
@@ -136,18 +134,18 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, 
unsigned int idx)
writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
 }

-static unsigned int ovl_fmt_convert(unsigned int fmt)
+static unsigned int ovl_fmt_convert(struct mtk_ddp_comp *comp, unsigned int 
fmt)
 {
switch (fmt) {
default:
case DRM_FORMAT_RGB565:
-   return OVL_CON_CLRFMT_RGB565;
+   return comp->data->ovl.fmt_rgb565;
case DRM_FORMAT_BGR565:
-   return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
+   return comp->data->ovl.fmt_rgb565 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGB888:
-   return OVL_CON_CLRFMT_RGB888;
+   return comp->data->ovl.fmt_rgb888;
case DRM_FORMAT_BGR888:
-   return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
+   return comp->data->ovl.fmt_rgb888 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGBX:
case DRM_FORMAT_RGBA:
return OVL_CON_CLRFMT_ARGB;
@@ -177,7 +175,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, 
unsigned int idx,
if (!pending->enable)
mtk_ovl_layer_off(comp, idx);

-   con = ovl_fmt_convert(fmt);
+   con = ovl_fmt_convert(comp, fmt);
if (idx != 0)
con |= OVL_CON_AEN | OVL_CON_ALPHA;

@@ -185,7 +183,8 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, 
unsigned int idx,
writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
-   writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
+   writel_relaxed(addr, comp->regs + comp->data->ovl.addr_offset
+   + idx * 0x20);

if (pending->enable)
mtk_ovl_layer_on(comp, idx);
@@ -269,6 +268,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
return ret;
}

+   priv->ddp_comp.data = of_device_get_match_data(dev);
+
platform_set_drvdata(pdev, priv);

ret = component_add(dev, _disp_ovl_component_ops);
@@ -285,8 +286,13 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
return 0;
 }

+static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = {
+   .ovl = {0x0f40, 0, 1 << 12}
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
-   { .compatible = "mediatek,mt8173-disp-ovl", },
+   { .compatible = "mediatek,mt8173-disp-ovl",
+ .data = _ovl_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 5fb80cb..fb0db50 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -122,7 +122,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, 
unsigned int width,
 */
threshold = width * height * vrefresh * 4 * 7 / 100;
reg = RDMA_FIFO_UNDERFLOW_EN |
- RDMA_FIFO_PSEUDO_SIZE(SZ_8K) |
+ RDMA_FIFO_PSEUDO_SIZE(comp->data->rdma_fifo_pseudo_size) |
  RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
 }
@@ -207,6 +207,8 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
return ret;
}

+   priv->ddp_comp.data = of_device_get_match_data(dev);
+
 

[PATCH v4 1/8] drm/mediatek: rename macros, add chip prefix

[YT Shen]

Add MT8173 prefix for hardware related macros.

Signed-off-by: YT Shen 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c |   60 
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 17ba935..2fc4321 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -36,21 +36,21 @@
 #define DISP_REG_MUTEX_MOD(n)  (0x2c + 0x20 * (n))
 #define DISP_REG_MUTEX_SOF(n)  (0x30 + 0x20 * (n))

-#define MUTEX_MOD_DISP_OVL0BIT(11)
-#define MUTEX_MOD_DISP_OVL1BIT(12)
-#define MUTEX_MOD_DISP_RDMA0   BIT(13)
-#define MUTEX_MOD_DISP_RDMA1   BIT(14)
-#define MUTEX_MOD_DISP_RDMA2   BIT(15)
-#define MUTEX_MOD_DISP_WDMA0   BIT(16)
-#define MUTEX_MOD_DISP_WDMA1   BIT(17)
-#define MUTEX_MOD_DISP_COLOR0  BIT(18)
-#define MUTEX_MOD_DISP_COLOR1  BIT(19)
-#define MUTEX_MOD_DISP_AAL BIT(20)
-#define MUTEX_MOD_DISP_GAMMA   BIT(21)
-#define MUTEX_MOD_DISP_UFOEBIT(22)
-#define MUTEX_MOD_DISP_PWM0BIT(23)
-#define MUTEX_MOD_DISP_PWM1BIT(24)
-#define MUTEX_MOD_DISP_OD  BIT(25)
+#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
+#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_RDMA0BIT(13)
+#define MT8173_MUTEX_MOD_DISP_RDMA1BIT(14)
+#define MT8173_MUTEX_MOD_DISP_RDMA2BIT(15)
+#define MT8173_MUTEX_MOD_DISP_WDMA0BIT(16)
+#define MT8173_MUTEX_MOD_DISP_WDMA1BIT(17)
+#define MT8173_MUTEX_MOD_DISP_COLOR0   BIT(18)
+#define MT8173_MUTEX_MOD_DISP_COLOR1   BIT(19)
+#define MT8173_MUTEX_MOD_DISP_AAL  BIT(20)
+#define MT8173_MUTEX_MOD_DISP_GAMMABIT(21)
+#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
+#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
+#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
+#define MT8173_MUTEX_MOD_DISP_OD   BIT(25)

 #define MUTEX_SOF_SINGLE_MODE  0
 #define MUTEX_SOF_DSI0 1
@@ -80,21 +80,21 @@ struct mtk_ddp {
 };

 static const unsigned int mutex_mod[DDP_COMPONENT_ID_MAX] = {
-   [DDP_COMPONENT_AAL] = MUTEX_MOD_DISP_AAL,
-   [DDP_COMPONENT_COLOR0] = MUTEX_MOD_DISP_COLOR0,
-   [DDP_COMPONENT_COLOR1] = MUTEX_MOD_DISP_COLOR1,
-   [DDP_COMPONENT_GAMMA] = MUTEX_MOD_DISP_GAMMA,
-   [DDP_COMPONENT_OD] = MUTEX_MOD_DISP_OD,
-   [DDP_COMPONENT_OVL0] = MUTEX_MOD_DISP_OVL0,
-   [DDP_COMPONENT_OVL1] = MUTEX_MOD_DISP_OVL1,
-   [DDP_COMPONENT_PWM0] = MUTEX_MOD_DISP_PWM0,
-   [DDP_COMPONENT_PWM1] = MUTEX_MOD_DISP_PWM1,
-   [DDP_COMPONENT_RDMA0] = MUTEX_MOD_DISP_RDMA0,
-   [DDP_COMPONENT_RDMA1] = MUTEX_MOD_DISP_RDMA1,
-   [DDP_COMPONENT_RDMA2] = MUTEX_MOD_DISP_RDMA2,
-   [DDP_COMPONENT_UFOE] = MUTEX_MOD_DISP_UFOE,
-   [DDP_COMPONENT_WDMA0] = MUTEX_MOD_DISP_WDMA0,
-   [DDP_COMPONENT_WDMA1] = MUTEX_MOD_DISP_WDMA1,
+   [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
+   [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
+   [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
+   [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
+   [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
+   [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
+   [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
+   [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
+   [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
+   [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
+   [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
+   [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
+   [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
+   [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
 };

 static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
-- 
1.7.9.5

[PATCH v4 0/8] MT2701 DRM support

[YT Shen]

This is MT2701 DRM support PATCH v4, based on 4.7-rc1.
We add DSI interrupt control, transfer function for MIPI DSI panel support.
Most codes are the same, except some register changed.

For example:
 - DISP_OVL address offset changed, color format definition changed.
 - DISP_RDMA fifo size changed.
 - DISP_COLOR offset changed.

We add a new component DDP_COMPONENT_BLS, and the settings are updated.
And we have shadow register support in MT2701.

Changes since v3:
- Add DSI support for MIPI DSI panels
- Update BLS binding to PWM nodes
- Remove ufoe device nodes
- Remove redundant parentheses
- Remove global variable initialization

Changes since v2:
- Rename mtk_ddp_mux_sel to mtk_ddp_sout_sel
- Update mt2701_mtk_ddp_ext components
- Changed to prefix naming
- Reorder the patch series
- Use of_device_get_match_data() to get driver private data
- Use iopoll macros to implement mtk_disp_mutex_acquire()
- Removed empty device tree nodes

Changes since v1:
- Removed BLS bindings and codes, which belong to pwm driver
- Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
- Split patch into smaller parts
- Added const keyword to constant structure
- Removed codes for special memory align

The PATCH depends on the following patch:
https://patchwork.kernel.org/patch/8832441/ ("dt-bindings: ARM: Mediatek: 
Document bindings for MT2701"),
https://patchwork.kernel.org/patch/9140487/ ("dt-bindings: pwm: Add MediaTek 
display PWM bindings"),
https://patchwork.kernel.org/patch/9137919/ ("dt-bindings: mediatek: add 
descriptions for mediatek mt2701 iommu and smi"),
https://patchwork.kernel.org/patch/9137923/ ("iommu/mediatek: move the common 
struct into header file"),
https://patchwork.kernel.org/patch/9137921/ ("memory/mediatek: add support for 
mt2701"),
https://patchwork.kernel.org/patch/9137927/ ("iommu/mediatek: add support for 
mtk iommu generation one HW"),
https://patchwork.kernel.org/patch/9137931/ ("ARM: dts: mt2701: add iommu/smi 
dtsi node for mt2701"),

Thanks,
yt.shen

YT Shen (5):
  drm/mediatek: rename macros, add chip prefix
  drm/mediatek: add *driver_data for different hardware settings
  drm/mediatek: add shadow register support
  drm/mediatek: add support for Mediatek SoC MT2701
  arm: dts: mt2701: Add display subsystem related nodes for MT2701

shaoming chen (3):
  drm/mediatek: add dsi interrupt control
  drm/mediatek: add dsi transfer function
  drm/mediatek: add mipi panel support

 arch/arm/boot/dts/mt2701.dtsi   |  100 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |   32 +-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|   17 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |   75 ++--
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  |  134 --
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |2 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |   34 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   14 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   56 ++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |9 +
 drivers/gpu/drm/mediatek/mtk_dsi.c  |  619 ---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c  |   82 ++--
 12 files changed, 1009 insertions(+), 165 deletions(-)

-- 
1.7.9.5

[PATCH v5 1/2] drm/fsl-dcu: rework codes to support of_graph dt binding for panel

[Stefan Agner]

On 2016-07-14 23:53, Meng Yi wrote:
> This patch rework the output code to add of_graph dt binding support
> for panel device and also keeps the backward compatibility
> 
> Signed-off-by: Meng Yi 

Applied, with Rob's Ack from the earlier documentation only patch for
the Documentation part.

--
Stefan


> ---
> Changes in V5:
> -remove unused variable 'ret'
> Changes in V4:
> -simplify return value statements
> -merge corresponding documentation to this patch
> Changes in V3:
> -simplify return value statements
> Changes in V2:
> -fix some coding style issue
> -add fsl_dev->connector.panel check
> -use fsl_dev->np and drop fsl_dev->dev->of_node
> -return 'ret' when fsl_dcu_attach_panel failed
> ---
>  .../devicetree/bindings/display/fsl,dcu.txt|  9 ++-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c  |  2 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h   |  3 +-
>  drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c  | 68 
> +++---
>  4 files changed, 57 insertions(+), 25 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> index ae55cde..63ec2a6 100644
> --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
> +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
> @@ -12,7 +12,7 @@ Required properties:
>  - clock-names:   Should be "dcu" and "pix"
>   See ../clocks/clock-bindings.txt for details.
>  - big-endian Boolean property, LS1021A DCU registers are big-endian.
> -- fsl,panel: The phandle to panel node.
> +- port   Video port for the panel output
>  
>  Optional properties:
>  - fsl,tcon:  The phandle to the timing controller node.
> @@ -24,6 +24,11 @@ dcu: dcu at 2ce {
>   clocks = <_clk 0>, <_clk 0>;
>   clock-names = "dcu", "pix";
>   big-endian;
> - fsl,panel = <>;
>   fsl,tcon = <>;
> +
> + port {
> + dcu_out: endpoint {
> + remote-endpoint = <_out>;
> +  };
> + };
>  };
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
> index a6e4cd5..d9d6cc1 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
> @@ -43,7 +43,7 @@ int fsl_dcu_drm_modeset_init(struct
> fsl_dcu_drm_device *fsl_dev)
>   if (ret)
>   goto err;
>  
> - ret = fsl_dcu_drm_connector_create(fsl_dev, _dev->encoder);
> + ret = fsl_dcu_create_outputs(fsl_dev);
>   if (ret)
>   goto err;
>  
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
> index 7093109..5a7b88e 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
> @@ -25,9 +25,8 @@ to_fsl_dcu_connector(struct drm_connector *con)
>: NULL;
>  }
>  
> -int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
> -  struct drm_encoder *encoder);
>  int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
>  struct drm_crtc *crtc);
> +int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev);
>  
>  #endif /* __FSL_DCU_DRM_CONNECTOR_H__ */
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
> index 0b0989e..ba1edb1 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
> @@ -10,6 +10,7 @@
>   */
>  
>  #include 
> +#include 
>  
>  #include 
>  #include 
> @@ -132,12 +133,12 @@ static const struct drm_connector_helper_funcs
> connector_helper_funcs = {
>   .mode_valid = fsl_dcu_drm_connector_mode_valid,
>  };
>  
> -int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
> -  struct drm_encoder *encoder)
> +static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
> +  struct drm_panel *panel)
>  {
> + struct drm_encoder *encoder = _dev->encoder;
>   struct drm_connector *connector = _dev->connector.base;
>   struct drm_mode_config *mode_config = _dev->drm->mode_config;
> - struct device_node *panel_node;
>   int ret;
>  
>   fsl_dev->connector.encoder = encoder;
> @@ -161,21 +162,7 @@ int fsl_dcu_drm_connector_create(struct
> fsl_dcu_drm_device *fsl_dev,
> mode_config->dpms_property,
> DRM_MODE_DPMS_OFF);
>  
> - panel_node = of_parse_phandle(fsl_dev->np, "fsl,panel", 0);
> - if (!panel_node) {
> - dev_err(fsl_dev->dev, "fsl,panel property not found\n");
> - ret = -ENODEV;
> - goto err_sysfs;
> - }
> -
> - fsl_dev->connector.panel = of_drm_find_panel(panel_node);
> - if (!fsl_dev->connector.panel) {
> - 

[PATCH v4 3/4] drm/bridge: analogix_dp: add the PSR function support

[Yakir Yang]

tel(db1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
>> +
>> +/* set reuse spd inforframe */
>> +val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>> +val |= REUSE_SPD_EN;
>> +writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
>> +
>> +/* mark info frame update */
>> +val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>> +val = (val | IF_UP) & ~IF_EN;
>> +writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>> +
>> +/* send info frame */
>> +val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>> +val |= IF_EN;
>> +writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
>> +}
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h 
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> index cdcc6c5..fd232b2 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> @@ -22,6 +22,8 @@
>>   #define ANALOGIX_DP_VIDEO_CTL_80x3C
>>   #define ANALOGIX_DP_VIDEO_CTL_10   0x44
>>   
>> +#define ANALOGIX_DP_SPDIF_AUDIO_CTL_0   0xD8
>> +
>>   #define ANALOGIX_DP_PLL_REG_1  0xfc
>>   #define ANALOGIX_DP_PLL_REG_2  0x9e4
>>   #define ANALOGIX_DP_PLL_REG_3  0x9e8
>> @@ -30,6 +32,15 @@
>>   
>>   #define ANALOGIX_DP_PD 0x12c
>>   
>> +#define ANALOGIX_DP_IF_TYPE 0x244
>> +#define ANALOGIX_DP_IF_PKT_DB1  0x254
>> +#define ANALOGIX_DP_IF_PKT_DB2  0x258
>> +#define ANALOGIX_DP_SPD_HB  0x2F8
>> +#define ANALOGIX_DP_SPD_PB  0x308
>> +#define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL   0x318
>> +#define ANALOGIX_DP_VSC_SHADOW_DB0  0x31C
>> +#define ANALOGIX_DP_VSC_SHADOW_DB1  0x320
>> +
>>   #define ANALOGIX_DP_LANE_MAP   0x35C
>>   
>>   #define ANALOGIX_DP_ANALOG_CTL_1   0x370
>> @@ -103,6 +114,8 @@
>>   
>>   #define ANALOGIX_DP_SOC_GENERAL_CTL0x800
>>   
>> +#define ANALOGIX_DP_CRC_CON 0x890
>> +
>>   /* ANALOGIX_DP_TX_SW_RESET */
>>   #define RESET_DP_TX(0x1 << 0)
>>   
>> @@ -151,6 +164,7 @@
>>   #define VID_CHK_UPDATE_TYPE_SHIFT  (4)
>>   #define VID_CHK_UPDATE_TYPE_1  (0x1 << 4)
>>   #define VID_CHK_UPDATE_TYPE_0  (0x0 << 4)
>> +#define REUSE_SPD_EN(0x1 << 3)
>>   
>>   /* ANALOGIX_DP_VIDEO_CTL_8 */
>>   #define VID_HRES_TH(x) (((x) & 0xf) << 4)
>> @@ -167,6 +181,12 @@
>>   #define REF_CLK_27M(0x0 << 0)
>>   #define REF_CLK_MASK   (0x1 << 0)
>>   
>> +/* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */
>> +#define PSR_FRAME_UP_TYPE_BURST (0x1 << 0)
>> +#define PSR_FRAME_UP_TYPE_SINGLE(0x0 << 0)
>> +#define PSR_CRC_SEL_HARDWARE(0x1 << 1)
>> +#define PSR_CRC_SEL_MANUALLY(0x0 << 1)
>> +
>>   /* ANALOGIX_DP_LANE_MAP */
>>   #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
>>   #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
>> @@ -376,4 +396,12 @@
>>   #define VIDEO_MODE_SLAVE_MODE  (0x1 << 0)
>>   #define VIDEO_MODE_MASTER_MODE (0x0 << 0)
>>   
>> +/* ANALOGIX_DP_PKT_SEND_CTL */
>> +#define IF_UP   (0x1 << 4)
>> +#define IF_EN   (0x1 << 0)
>> +
>> +/* ANALOGIX_DP_CRC_CON */
>> +#define PSR_VID_CRC_FLUSH   (0x1 << 2)
>> +#define PSR_VID_CRC_ENABLE  (0x1 << 0)
>> +
>>   #endif /* _ANALOGIX_DP_REG_H */
>> diff --git a/include/drm/bridge/analogix_dp.h 
>> b/include/drm/bridge/analogix_dp.h
>> index 261b86d..9cd8838 100644
>> --- a/include/drm/bridge/analogix_dp.h
>> +++ b/include/drm/bridge/analogix_dp.h
>> @@ -38,6 +38,9 @@ struct analogix_dp_plat_data {
>>   struct drm_connector *);
>>   };
>>   
>> +int analogix_dp_enable_psr(struct device *dev);
>> +int analogix_dp_disable_psr(struct device *dev);
>> +
>>   int analogix_dp_resume(struct device *dev);
>>   int analogix_dp_suspend(struct device *dev);
>>   
>> -- 
>> 1.9.1
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>

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iommu/rockchip: Fix bugs and enable on ARM64

[Matthias Brugger]

On 08/07/16 03:01, Mark yao wrote:
> On 2016年06月27日 20:57, Joerg Roedel wrote:
>> On Fri, Jun 24, 2016 at 10:13:25AM +0800, Shunqian Zheng wrote:
>>>   drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 100 +++--
>>>   drivers/gpu/drm/rockchip/rockchip_drm_drv.h |   3 +
>>>   drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 221
>>> ++--
>>>   drivers/gpu/drm/rockchip/rockchip_drm_gem.h |   9 ++
>>>   drivers/iommu/Kconfig   |   2 +-
>>>   drivers/iommu/rockchip-iommu.c  | 181
>>> +--
>>>   6 files changed, 413 insertions(+), 103 deletions(-)
>> Applied the IOMMU patches, thanks.
>>
>>
>> Joerg
>>
>>
>>
>>
>
> Hi Joerg
>
> The drm rockchip patches are dependent on iommu/rockchip patches, can
> you also apply these patches together? So that can avoid compile problem.
>

While at it. I don't see patch 8 (iommu/Kconfig) in linux-next.
I suppose you forgot to pick that one.

Regards,
Matthias

[PATCH v3 1/2] drm/mediatek: Add gamma correction

[CK Hu]

Hi, Bibby:

Some comments inline.

On Thu, 2016-07-07 at 15:37 +0800, Bibby Hsieh wrote:
> Apply gamma function to correct brightness values.
> It applies arbitrary mapping curve to compensate the
> incorrect transfer function of the panel.
> 
> Signed-off-by: Bibby Hsieh 
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |8 +++
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h |1 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |   89 
> ++-
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   10 +++
>  4 files changed, 106 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 24aa3ba..ee219bb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -409,6 +409,10 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc 
> *crtc,
>   }
>   if (pending_planes)
>   mtk_crtc->pending_planes = true;
> + if (crtc->state->color_mgmt_changed)
> + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> + mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> +
>  }
>  
>  static const struct drm_crtc_funcs mtk_crtc_funcs = {
> @@ -418,6 +422,7 @@ static const struct drm_crtc_funcs mtk_crtc_funcs = {
>   .reset  = mtk_drm_crtc_reset,
>   .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
>   .atomic_destroy_state   = mtk_drm_crtc_destroy_state,
> + .gamma_set  = drm_atomic_helper_legacy_gamma_set,
>  };
>  
>  static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
> @@ -569,6 +574,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>   if (ret < 0)
>   goto unprepare;
>  
> + drm_mode_crtc_set_gamma_size(_crtc->base, MTK_LUT_SIZE);
> + drm_helper_crtc_enable_color_mgmt(_crtc->base, MTK_LUT_SIZE,
> +   MTK_LUT_SIZE);
>   priv->crtc[pipe] = _crtc->base;
>   priv->num_pipes++;
>  
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h 
> b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 81e5566..d332564 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -19,6 +19,7 @@
>  #include "mtk_drm_plane.h"
>  
>  #define OVL_LAYER_NR 4
> +#define MTK_LUT_SIZE 512
>  
>  int mtk_drm_crtc_enable_vblank(struct drm_device *drm, unsigned int pipe);
>  void mtk_drm_crtc_disable_vblank(struct drm_device *drm, unsigned int pipe);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 3970fcf..56c5894 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -24,6 +24,7 @@
>  #include "mtk_drm_drv.h"
>  #include "mtk_drm_plane.h"
>  #include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_crtc.h"
>  
>  #define DISP_OD_EN   0x
>  #define DISP_OD_INTEN0x0008
> @@ -38,6 +39,21 @@
>  #define DISP_COLOR_WIDTH 0x0c50
>  #define DISP_COLOR_HEIGHT0x0c54
>  
> +#define DISP_AAL_EN  0x000
> +#define DISP_AAL_SIZE0x030
> +
> +#define DISP_GAMMA_EN0x000
> +#define DISP_GAMMA_CFG   0x020
> +#define DISP_GAMMA_SIZE  0x030
> +#define DISP_GAMMA_LUT   0x700

It's better that the digits of register address of OD, COLOR, AAL, and
GAMMA are the same. Maybe you can align all to 4 digits.

> +
> +#define LUT_10BIT_MASK   0x3ff
> +
> +#define AAL_EN   BIT(0)
> +
> +#define GAMMA_EN BIT(0)
> +#define GAMMA_LUT_EN BIT(1)
> +
>  #define  OD_RELAY_MODE   BIT(0)
>  
>  #define  UFO_BYPASS  BIT(2)
> @@ -76,6 +92,61 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
>   writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
>  }
>  
> +static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
> +unsigned int h, unsigned int vrefresh)
> +{
> + writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
> +}
> +
> +static void mtk_aal_start(struct mtk_ddp_comp *comp)
> +{
> + writel(AAL_EN, comp->regs  + DISP_AAL_EN);
> +}
> +
> +static void mtk_aal_stop(struct mtk_ddp_comp *comp)
> +{
> + writel_relaxed(0x0, comp->regs  + DISP_AAL_EN);
> +}

I think AAL is somewhat different from GAMMA and this patch include 3
modifications:

1. AAL basic config
2. GAMMA basic config
3. Add gamma function of AAL and GAMMA

So you should split this patch into 3 patches.

> +
> +static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
> +  unsigned int h, unsigned int vrefresh)
> +{
> + writel(h << 16 | w, comp->regs + 

[PATCH 2/2] drm/amd/powerplay: Delete unused functions in ppevvmath.h

[Alex Deucher]

On Fri, Jul 15, 2016 at 4:09 PM, Nils Wallménius
 wrote:
> Ping?

We don't seem to be using them.  Can you respin?  It doesn't seem to
apply any longer.

Alex


>
>
> Den 6 juni 2016 21:32 skrev "Nils Wallménius" :
>>
>> Hi Alex,
>>
>> Any response from the powerplay team?
>>
>> If they are unresponsive, would you prefer to #IF 0 the code instead of
>> deleting?
>>
>> Regards
>> Nils
>>
>> On Mon, Apr 25, 2016 at 10:08 PM, Alex Deucher 
>> wrote:
>>>
>>> On Sun, Apr 24, 2016 at 7:22 AM, Nils Wallménius
>>>  wrote:
>>> > Signed-off-by: Nils Wallménius 
>>>
>>> Let me check with the powerplay team and make sure they are planning
>>> to use these in the near future.
>>>
>>> Alex
>>>
>>>
>>> > ---
>>> >  drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h | 59
>>> > +
>>> >  1 file changed, 1 insertion(+), 58 deletions(-)
>>> >
>>> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
>>> > b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
>>> > index a9b40eb..8f50a03 100644
>>> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
>>> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppevvmath.h
>>> > @@ -64,7 +64,6 @@ static fInt fGetSquare(fInt);
>>> > /* Returns the square
>>> >  static fInt fSqrt(fInt);  /* Returns
>>> > the Square Root of a fInt number */
>>> >
>>> >  static int uAbs(int); /* Returns
>>> > the Absolute value of the Int */
>>> > -static fInt fAbs(fInt);   /* Returns
>>> > the Absolute value of the fInt */
>>> >  static int uPow(int base, int exponent);  /* Returns
>>> > base^exponent an INT */
>>> >
>>> >  static void SolveQuadracticEqn(fInt, fInt, fInt, fInt[]); /* Returns
>>> > the 2 roots via the array */
>>> > @@ -85,21 +84,12 @@ static fInt fDecodeLeakageID (uint32_t
>>> > leakageID_fuse, fInt ln_max_div_min, fInt
>>> >   *
>>> > -
>>> >   * Some of the following functions take two INTs as their input - This
>>> > is unsafe for a variety of reasons.
>>> >   */
>>> > -static fInt Add (int, int);   /* Add two
>>> > INTs and return Sum as FINT */
>>> > -static fInt Multiply (int, int);  /* Multiply
>>> > two INTs and return Product as FINT */
>>> > -static fInt Divide (int, int);/* You get
>>> > the idea... */
>>> > +static fInt Divide (int, int);/* Divide
>>> > two INTs and return result as FINT */
>>> >  static fInt fNegate(fInt);
>>> >
>>> >  static int uGetScaledDecimal (fInt);  /* Internal
>>> > function */
>>> >  static int GetReal (fInt A);  /* Internal
>>> > function */
>>> >
>>> > -/* Future Additions and Incomplete Functions
>>> > - *
>>> > -
>>> > - */
>>> > -static int GetRoundedValue(fInt); /*
>>> > Incomplete function - Useful only when Precision is lacking */
>>> > -  /* Let us
>>> > say we have 2.126 but can only handle 2 decimal points. We could */
>>> > -  /* either
>>> > chop of 6 and keep 2.12 or use this function to get 2.13, which is more
>>> > accurate */
>>> > -
>>> >  /*
>>> > -
>>> >   * TROUBLESHOOTING INFORMATION
>>> >   *
>>> > -
>>> > @@ -498,51 +488,12 @@ static void SolveQuadracticEqn(fInt A, fInt B,
>>> > fInt C, fInt Roots[])
>>> >   *
>>> > -
>>> >   */
>>> >
>>> > -/* Addition using two normal ints - Temporary - Use only for testing
>>> > purposes?. */
>>> > -static fInt Add (int X, int Y)
>>> > -{
>>> > -   fInt A, B, Sum;
>>> > -
>>> > -   A.full = (X << SHIFT_AMOUNT);
>>> > -   B.full = (Y << SHIFT_AMOUNT);
>>> > -
>>> > -   Sum.full = A.full + B.full;
>>> > -
>>> > -   return Sum;
>>> > -}
>>> > -
>>> >  /* Conversion Functions */
>>> >  static int GetReal (fInt A)
>>> >  {
>>> > return (A.full >> SHIFT_AMOUNT);
>>> >  }
>>> >
>>> > -/* Temporarily Disabled */
>>> > -static int GetRoundedValue(fInt A) /*For now, round the 3rd decimal
>>> > place */
>>> > -{
>>> > -   /* ROUNDING TEMPORARLY DISABLED
>>> > -   int temp = A.full;
>>> > -   int decimal_cutoff, decimal_mask = 0x01FF;
>>> > -   decimal_cutoff = temp & decimal_mask;
>>> > -   if (decimal_cutoff > 0x147) {
>>> > -   temp += 673;
>>> > -   }*/
>>> > -
>>> > -   return ConvertBackToInteger(A)/1; /*Temporary - in case
>>> > this was used somewhere else */
>>> > -}
>>> > -
>>> > 

[PATCH] drm/fsl-dcu: Add gamma set for crtc

[Meng Yi]

Gamma correction is optional and can be used to adjust the color
output values to match the gamut of a particular TFT LCD panel

Signed-off-by: Meng Yi 
---
 drivers/gpu/drm/fsl-dcu/Kconfig|  6 +++
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 63 ++
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h  |  7 
 3 files changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/fsl-dcu/Kconfig b/drivers/gpu/drm/fsl-dcu/Kconfig
index b9c714d..ddfe3c4 100644
--- a/drivers/gpu/drm/fsl-dcu/Kconfig
+++ b/drivers/gpu/drm/fsl-dcu/Kconfig
@@ -16,3 +16,9 @@ config DRM_FSL_DCU
help
  Choose this option if you have an Freescale DCU chipset.
  If M is selected the module will be called fsl-dcu-drm.
+
+config DRM_FSL_DCU_GAMMA
+   bool "Gamma Correction Support for NXP/Freescale DCU"
+   depends on DRM_FSL_DCU
+   help
+ Enable support for gamma correction.
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..d8426b1 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -46,6 +46,11 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)

drm_crtc_vblank_off(crtc);

+#ifdef CONFIG_DRM_FSL_DCU_GAMMA
+   regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
+  DCU_MODE_EN_GAMMA_MASK,
+  DCU_MODE_GAMMA_DISABLE);
+#endif
regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
   DCU_MODE_DCU_MODE_MASK,
   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
@@ -58,6 +63,11 @@ static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;

+#ifdef CONFIG_DRM_FSL_DCU_GAMMA
+   regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
+  DCU_MODE_EN_GAMMA_MASK,
+  DCU_MODE_GAMMA_ENABLE);
+#endif
regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
   DCU_MODE_DCU_MODE_MASK,
   DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
@@ -128,6 +138,58 @@ static const struct drm_crtc_helper_funcs 
fsl_dcu_drm_crtc_helper_funcs = {
.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
 };

+/*
+ * Gamma_R, Gamma_G and Gamma_B registers are little-endian registers while
+ * the rest of the address-space in 2D-ACE is big-endian. 2D-ACE Gamma_R,
+ * Gamma_G and Gamma_B registers are 32 bit registers, where the first 24
+ * bits are reserved and last 8 bits denote the gamma value. Because of a
+ * connection issue in the device, the first 8-bit [31:24] is connected and
+ * the rest of the 24-bits[23:0] are reserved.
+ * Workaround: Perform the byte_swapping for Gamma_[R/G/B]_registers.
+ * For example: While writing _00ABh to any of the gamma registers, byte
+ * swap the data so it results in AB00_h. Write this value to the gamma
+ * register.
+ */
+static u32 swap_bytes(u16 var)
+{
+   union res {
+   char byte[4];
+   u32 val;
+   };
+   union res in, out;
+   unsigned int i = 0;
+
+   in.val = var;
+   for (i = 0; i < 4; i++)
+   out.byte[i] = in.byte[3-i];
+
+   return out.val;
+}
+
+static int fsl_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
+   uint32_t size)
+{
+   struct rgb {
+   u32 r[size], g[size], b[size];
+   };
+
+   struct drm_device *dev = crtc->dev;
+   struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
+   unsigned int i;
+   struct rgb glut;
+
+   for (i = 0; i < size; i++) {
+   glut.r[i] = swap_bytes(r[i]);
+   glut.g[i] = swap_bytes(g[i]);
+   glut.b[i] = swap_bytes(b[i]);
+   regmap_write(fsl_dev->regmap, FSL_GAMMA_R + 4 * i, glut.r[i]);
+   regmap_write(fsl_dev->regmap, FSL_GAMMA_G + 4 * i, glut.g[i]);
+   regmap_write(fsl_dev->regmap, FSL_GAMMA_B + 4 * i, glut.b[i]);
+   }
+
+   return 0;
+}
+
 static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
@@ -135,6 +197,7 @@ static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = 
{
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.set_config = drm_atomic_helper_set_config,
+   .gamma_set = fsl_crtc_gamma_set,
 };

 int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
index 3b371fe7..d3bc540 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h
@@ -25,6 +25,9 @@
 #define DCU_MODE_NORMAL

[PATCH 00/21] drm: make fbdev support really optional

[Tobias Jakobi]

Emil Velikov wrote:
> On 15 July 2016 at 14:37, Tobias Jakobi  
> wrote:
>> Hello Emil,
>>
>> Emil Velikov wrote:
>>> On 15 July 2016 at 13:47, Tobias Jakobi  
>>> wrote:
 Hello,

 as request by Daniel here 
 (http://www.spinics.net/lists/dri-devel/msg112592.html) I went ahead and 
 also cleaned up the other Kconfig files. I have mostly compile tested the 
 changes on an ARMv7 system (COMPILE_TEST).

>>> Yay :-) IIRC some drivers don't fully use the fb_helpers (for example
>>> vmwgfx still references the cfb_* API), so they should be updated as
>>> well.
>> I can only do this on ARM atm, so I suggest to just drop insufficient
>> patches.
>>
> Without checking (build and/or grep) it'll be a bit hard to figure out
> which patches are insufficient. At the end of the day it's up-to you
> and DRM maintainer(s).
I kind of was expecting this, so I asked Daniel on IRC if I was supposed
to only inspect the Kconfigs. Seems like this doesn't suffice in every
case. :(

- Tobias

> 
> Thanks for sorting out these. The negative diffstat is always appreciated ;-)
> -Emil
> 

[v5.2 PATCH 5/5] drm/rockchip: cdn-dp: add cdn DP support for rk3399

[Chris Zhong]

Add support for cdn DP controller which is embedded in the rk3399
SoCs. The DP is compliant with DisplayPort Specification,
Version 1.3, This IP is compatible with the rockchip type-c PHY IP.
There is a uCPU in DP controller, it need a firmware to work,
please put the firmware file to /lib/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.

Signed-off-by: Chris Zhong 

---

Changes in v5.2:
- fixed the fw_wait always 0

Changes in v5.1:
- modify according to Sean Paul's comments

Changes in v5:
- alphabetical order
- do not use long, use u32 or u64
- return MODE_CLOCK_HIGH when requested > actual
- Optimized Coding Style
- add a formula to get better tu size and symbol value.

Changes in v4:
- use phy framework to control DP phy
- support 2 phys

Changes in v3:
- use EXTCON_DISP_DP and EXTCON_DISP_DP_ALT cable to get dp port state.
- reset spdif before config it
- modify the firmware clk to 100Mhz
- retry load firmware if fw file is requested too early

Changes in v2:
- Alphabetic order
- remove excess error message
- use define clk_rate
- check all return value
- remove dev_set_name(dp->dev, "cdn-dp");
- use schedule_delayed_work
- remove never-called functions
- remove some unnecessary ()

Changes in v1:
- use extcon API
- use hdmi-codec for the DP Asoc
- do not initialize the "ret"
- printk a err log when drm_of_encoder_active_endpoint_id
- modify the dclk pin_pol to a single line

 drivers/gpu/drm/rockchip/Kconfig|   9 +
 drivers/gpu/drm/rockchip/Makefile   |   1 +
 drivers/gpu/drm/rockchip/cdn-dp-core.c  | 842 ++
 drivers/gpu/drm/rockchip/cdn-dp-core.h  |  99 +++
 drivers/gpu/drm/rockchip/cdn-dp-reg.c   | 898 
 drivers/gpu/drm/rockchip/cdn-dp-reg.h   | 479 +++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  11 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |   9 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |   2 +
 9 files changed, 2347 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c
 create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index d30bdc3..a04446a 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,6 +25,15 @@ config ROCKCHIP_ANALOGIX_DP
  for the Analogix Core DP driver. If you want to enable DP
  on RK3288 based SoC, you should selet this option.

+config ROCKCHIP_CDN_DP
+tristate "Rockchip cdn DP"
+depends on DRM_ROCKCHIP
+help
+ This selects support for Rockchip SoC specific extensions
+ for the cdn DP driver. If you want to enable Dp on
+ RK3399 based SoC, you should select this
+ option.
+
 config ROCKCHIP_DW_HDMI
 tristate "Rockchip specific extensions for Synopsys DW HDMI"
 depends on DRM_ROCKCHIP
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
index 05d0713..abdecd5 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
 rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o

 obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
+obj-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
 obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
 obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c 
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
new file mode 100644
index 000..ed38dbc
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -0,0 +1,842 @@
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Chris Zhong 
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "cdn-dp-core.h"
+#include "cdn-dp-reg.h"
+#include "rockchip_drm_vop.h"
+
+#define connector_to_dp(c) \
+   container_of(c, struct cdn_dp_device, connector)
+
+#define encoder_to_dp(c) \
+   container_of(c, struct cdn_dp_device, 

[PATCH 12/16] gpu: ipu-v3: Fix CSI0 blur in NTSC format

[Steve Longerbeam]

On 07/15/2016 05:58 AM, Philipp Zabel wrote:
> Am Mittwoch, den 13.07.2016, 16:02 -0700 schrieb Steve Longerbeam:
>> On 07/10/2016 09:33 AM, Steve Longerbeam wrote:
>>>
>>> On 07/08/2016 10:34 AM, Philipp Zabel wrote:
 Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> From: Suresh Dhandapani 
>
> This patch will change the register IPU_CSI0_CCIR_CODE_2 value from
> 0x40596 to 0x405A6. The change is related to the Start of field 1
> first blanking line command bit[5-3] for NTSC format only. This
> change is dependent with ADV chip where the NEWAVMODE is set to 0
> in register 0x31. Setting NEWAVMODE to "0" in ADV means "EAV/SAV
> codes generated to suit analog devices encoders".
>
> Signed-off-by: Suresh Dhandapani 
> ---
>drivers/gpu/ipu-v3/ipu-csi.c | 2 +-
>1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
> index 0eac28c..ec81958 100644
> --- a/drivers/gpu/ipu-v3/ipu-csi.c
> +++ b/drivers/gpu/ipu-v3/ipu-csi.c
> @@ -422,7 +422,7 @@ int ipu_csi_init_interface(struct ipu_csi *csi,
>  ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
>  CSI_CCIR_CODE_1);
> -ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
> +ipu_csi_write(csi, 0x405A6, CSI_CCIR_CODE_2);
>ipu_csi_write(csi, 0xFF, CSI_CCIR_CODE_3);
>} else {
>dev_err(csi->ipu->dev,
 This looks like a very hardware specific hack? I'll at least have to
 test if that also works with other analog decoders.
>>> Hi Philipp,
>>>
>>> Yes it's a hack, but it has always been a hack (hardcoded values). And the
>>> reason is simple, nobody AFAIK (including me) understands how to program
>>> these CSI_CCIR_CODE registers, the description in the reference manual is
>>> complete gibberish.
>> Hi Philipp, Ian over at linux-media helped me to understand these registers a
>> little better, although there are still mysteries given the poor 
>> documentation.
>> You should have been copied on that linux-media thread.
>>
>>> The reason we made this change is that, in discussions with Analog Devices,
>>> they recommended setting NEWAVMODE, which changes the positions of
>>> the AV codes sent by the ADV7180 on the bt.656 bus. It took Suresh at least
>>> a full day of reverse engineering (Suresh correct me if I am wrong) to hit
>>> on the correct values in these registers to regain stable video after 
>>> switching
>>> the ADV7180 to NEWAVMODE.
>> So this NEWAVMODE is somehow breaking from the BT.656 standard, which
>> necessitated the change to CSI_CCIR_CODE_2. So NEWAVMODE if enabled in
>> the ADV7180 will break other capture backends that are expecting standard
>> BT.656 SAV/EAV codes. So NEWAVMODE should not be used and I will remove
>> this patch in the next version.
> Ok. To use that mode, first a new v4l2 mbus type and corresponding DT
> bindings would have to be added.

Hmm, do you mean define something like a V4L2_MBUS_BT656_NEWAVMODE,
and then add a new "newavmode" boolean DT binding parsed by
v4l2_of_parse_endpoint()?

I don't know if that would make sense given that this NEWAVMODE is a kind
of hack of the BT.656 standard, only used by Analog Devices 
encoders/decoders.

Although there a _lot_ of AD encoder/decoder chips (and subdev drivers 
written for
them), so maybe it would make sense to do this.

Adding Hans.

Steve

[PATCH 00/21] drm: make fbdev support really optional

[Tobias Jakobi]

Hello Emil,

Emil Velikov wrote:
> On 15 July 2016 at 13:47, Tobias Jakobi  
> wrote:
>> Hello,
>>
>> as request by Daniel here 
>> (http://www.spinics.net/lists/dri-devel/msg112592.html) I went ahead and 
>> also cleaned up the other Kconfig files. I have mostly compile tested the 
>> changes on an ARMv7 system (COMPILE_TEST).
>>
> Yay :-) IIRC some drivers don't fully use the fb_helpers (for example
> vmwgfx still references the cfb_* API), so they should be updated as
> well.
I can only do this on ARM atm, so I suggest to just drop insufficient
patches.

With best wishes,
Tobias

> A few quick greps (check the exported symbols in drm_fb_helper.c and
> you'll see the respective fbdev/wrapper functions) and some build
> warning/errors will show you the way.
> 
> Regards,
> Emil
> 

[PATCH 01/16] gpu: ipu-v3: Add Video Deinterlacer unit

[Steve Longerbeam]

On 07/10/2016 05:02 PM, Paul Gortmaker wrote:
>
> +#include 
> +#include 
> You have a u32 field in a struct called "modules" but aside from that, I do 
> not
> see anything in this code requiring module.h -- did I miss something?
>
> You might want export.h for EXPORT_SYMBOL though.
>
>

Hi Paul, yes module.h wasn't needed. Fixed in next version.

Steve

[PATCH] drm/rockchip: Delete an unnecessary check before drm_gem_object_unreference_unlocked()

[SF Markus Elfring]

From: Markus Elfring 
Date: Fri, 15 Jul 2016 15:23:22 +0200

The drm_gem_object_unreference_unlocked() function tests whether
its argument is NULL and then returns immediately.
Thus the test around the call is not needed.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring 
---
 drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c 
b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
index 20f12bc..6f64e79 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
@@ -43,14 +43,10 @@ struct drm_gem_object *rockchip_fb_get_gem_obj(struct 
drm_framebuffer *fb,
 static void rockchip_drm_fb_destroy(struct drm_framebuffer *fb)
 {
struct rockchip_drm_fb *rockchip_fb = to_rockchip_fb(fb);
-   struct drm_gem_object *obj;
int i;

-   for (i = 0; i < ROCKCHIP_MAX_FB_BUFFER; i++) {
-   obj = rockchip_fb->obj[i];
-   if (obj)
-   drm_gem_object_unreference_unlocked(obj);
-   }
+   for (i = 0; i < ROCKCHIP_MAX_FB_BUFFER; i++)
+   drm_gem_object_unreference_unlocked(rockchip_fb->obj[i]);

drm_framebuffer_cleanup(fb);
kfree(rockchip_fb);
-- 
2.9.1

[GIT PULL] drm-vc4-next-2016-07-15 (loops)

[Eric Anholt]

Thanks for pulling the other changes.  Here's my last set of new code
for 4.8, my series for enabling real loops in GLSL.  This is pretty
exciting, as it's a major hardware feature that the closed source
driver never supported.

The commits are quite fresh, as kbuild test robot caught a stray ';'
that I cleaned up.  I booted it and touch-tested loops after fixing.

The following changes since commit deb4765db386db67626ffd075d8b5eb5fdf9c4f6:

  drm/vc4: remove redundant ret status check (2016-07-11 17:23:50 -0700)

are available in the git repository at:

  https://github.com/anholt/linux tags/drm-vc4-next-2016-07-15

for you to fetch changes up to a20d5fa61c32a0c94d237da642326db2ef3c7433:

  drm/vc4: Fix a "the the" typo in a comment. (2016-07-15 15:19:52 -0700)


This pull request brings in vc4 shader validation for branching,
allowing GLSL shaders with non-unrolled loops.


Eric Anholt (7):
  drm/vc4: Add a getparam ioctl for getting the V3D identity regs.
  drm/vc4: Move validation's current/max ip into the validation struct.
  drm/vc4: Add a bitmap of branch targets during shader validation.
  drm/vc4: Add support for branching in shader validation.
  drm/vc4: Add a getparam to signal support for branches.
  drm/vc4: Fix definition of QPU_R_MS_REV_FLAGS
  drm/vc4: Fix a "the the" typo in a comment.

 drivers/gpu/drm/vc4/vc4_drv.c  |  45 +++
 drivers/gpu/drm/vc4/vc4_drv.h  |   3 +
 drivers/gpu/drm/vc4/vc4_qpu_defines.h  |  17 +-
 drivers/gpu/drm/vc4/vc4_validate.c |  13 +-
 drivers/gpu/drm/vc4/vc4_validate_shaders.c | 449 ++---
 include/uapi/drm/vc4_drm.h |  13 +
 6 files changed, 496 insertions(+), 44 deletions(-)

[PATCH 3/7] drm/vc4: Add a bitmap of branch targets during shader validation.

[Eric Anholt]

Eric Anholt  writes:

> This isn't used yet, it's just a first step toward loop validation.
> During the main parsing of instructions, we need to know when we hit a
> new basic block so that we can reset validated state.
>
> Signed-off-by: Eric Anholt 
> ---
>  drivers/gpu/drm/vc4/vc4_qpu_defines.h  |  12 +++
>  drivers/gpu/drm/vc4/vc4_validate_shaders.c | 114 
> -
>  2 files changed, 124 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_qpu_defines.h 
> b/drivers/gpu/drm/vc4/vc4_qpu_defines.h
> index d5c2f3c85ebb..82ef0e525d55 100644
> --- a/drivers/gpu/drm/vc4/vc4_qpu_defines.h
> +++ b/drivers/gpu/drm/vc4/vc4_qpu_defines.h

> + /* The actual branch target is the instruction after the delay
> +  * slots, plus whatever byte offset is in the low 32 bits of
> +  * the instruction.  Make sure we're not branching beyond the
> +  * end of the shader object.
> +  */
> + if (branch_imm % sizeof(inst) != 0) {
> + DRM_ERROR("branch target not aligned\n");
> + return false;
> + };

Last change before pull request: I dropped the stray ';' that kbuild
test robot caught.
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[Bug 115321] radeon runpm falsely disabled on Clevo P170EM

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=115321

--- Comment #7 from Christoph Haag  ---
No, the stock BIOS of the Clevo P170EM has *very* limited settings and I
believe the radeon GPU has no physical connectors connected at all.

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[Bug 115321] radeon runpm falsely disabled on Clevo P170EM

[bugzilla-dae...@bugzilla.kernel.org]

https://bugzilla.kernel.org/show_bug.cgi?id=115321

--- Comment #6 from Peter Wu  ---
Yes, that is what I was looking for.

[3.278214] ACPI Error: Field [TMPB] at 294912 exceeds Buffer [ROM1] size
262144 (bits) (20160108/dsopcode-236)
[3.278218] ACPI Error: Method parse/execution failed [\_SB.PCI0.GFX0.ATRM]
(Node 88080e8daa50), AE_AML_BUFFER_LIMIT (20160108/psparse-542)
[3.278224] failed to evaluate ATRM got AE_AML_BUFFER_LIMIT

This is harmless, apparently the radeon driver tries to fetch blocks of 4K
until no more results are available. Your videorom is only 32 KiB, so fetching
more than that will fail.


ATPX Supported Functions is 0x33 if \SGMD == 0x02 and 0xBF otherwise. Do you
have a BIOS option that allows you to select between hybrid graphics and
discrete mode?

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[PATCH 00/21] drm: make fbdev support really optional

[Emil Velikov]

On 15 July 2016 at 14:37, Tobias Jakobi  
wrote:
> Hello Emil,
>
> Emil Velikov wrote:
>> On 15 July 2016 at 13:47, Tobias Jakobi  
>> wrote:
>>> Hello,
>>>
>>> as request by Daniel here 
>>> (http://www.spinics.net/lists/dri-devel/msg112592.html) I went ahead and 
>>> also cleaned up the other Kconfig files. I have mostly compile tested the 
>>> changes on an ARMv7 system (COMPILE_TEST).
>>>
>> Yay :-) IIRC some drivers don't fully use the fb_helpers (for example
>> vmwgfx still references the cfb_* API), so they should be updated as
>> well.
> I can only do this on ARM atm, so I suggest to just drop insufficient
> patches.
>
Without checking (build and/or grep) it'll be a bit hard to figure out
which patches are insufficient. At the end of the day it's up-to you
and DRM maintainer(s).

Thanks for sorting out these. The negative diffstat is always appreciated ;-)
-Emil

[PATCH v3 4/4] drm/nouveau/acpi: fix lockup with PCIe runtime PM

[Peter Wu]

Since "PCI: Add runtime PM support for PCIe ports", the parent PCIe port
can be runtime-suspended which disables power resources via ACPI. This
is incompatible with DSM, resulting in a GPU device which is still in D3
and locks up the kernel on resume (on a Clevo P651RA, GTX965M).

Mirror the behavior of Windows 8 and newer[1] (as observed via an AMLi
debugger trace) and stop using the DSM functions for D3cold when power
resources are available on the parent PCIe port.

pci_d3cold_disable() is not used because on some machines, the old DSM
method is broken. On a Lenovo T440p (GT 730M) memory and disk corruption
would occur, but that is fixed with this patch[2].

 [1]: 
https://msdn.microsoft.com/windows/hardware/drivers/bringup/firmware-requirements-for-d3cold
 [2]: 
https://github.com/Bumblebee-Project/bbswitch/issues/78#issuecomment-223549072

 v2: simply check directly for _PR3. Added affected machines.
 v3: fixed block comment coding style.

Reviewed-by: Mika Westerberg 
Signed-off-by: Peter Wu 
---
 drivers/gpu/drm/nouveau/nouveau_acpi.c | 35 ++
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c 
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index ad273ad..f2ad17a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -46,6 +46,7 @@ static struct nouveau_dsm_priv {
bool dsm_detected;
bool optimus_detected;
bool optimus_flags_detected;
+   bool optimus_skip_dsm;
acpi_handle dhandle;
acpi_handle rom_handle;
 } nouveau_dsm_priv;
@@ -212,9 +213,28 @@ static const struct vga_switcheroo_handler 
nouveau_dsm_handler = {
.get_client_id = nouveau_dsm_get_client_id,
 };

+/*
+ * Firmware supporting Windows 8 or later do not use _DSM to put the device 
into
+ * D3cold, they instead rely on disabling power resources on the parent.
+ */
+static bool nouveau_pr3_present(struct pci_dev *pdev)
+{
+   struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
+   struct acpi_device *parent_adev;
+
+   if (!parent_pdev)
+   return false;
+
+   parent_adev = ACPI_COMPANION(_pdev->dev);
+   if (!parent_adev)
+   return false;
+
+   return acpi_has_method(parent_adev->handle, "_PR3");
+}
+
 static void nouveau_dsm_pci_probe(struct pci_dev *pdev, acpi_handle 
*dhandle_out,
  bool *has_mux, bool *has_opt,
- bool *has_opt_flags)
+ bool *has_opt_flags, bool *has_pr3)
 {
acpi_handle dhandle;
bool supports_mux;
@@ -239,6 +259,7 @@ static void nouveau_dsm_pci_probe(struct pci_dev *pdev, 
acpi_handle *dhandle_out
*has_mux = supports_mux;
*has_opt = !!optimus_funcs;
*has_opt_flags = optimus_funcs & (1 << NOUVEAU_DSM_OPTIMUS_FLAGS);
+   *has_pr3 = false;

if (optimus_funcs) {
uint32_t result;
@@ -248,6 +269,8 @@ static void nouveau_dsm_pci_probe(struct pci_dev *pdev, 
acpi_handle *dhandle_out
 (result & OPTIMUS_ENABLED) ? "enabled" : "disabled",
 (result & OPTIMUS_DYNAMIC_PWR_CAP) ? "dynamic power, " 
: "",
 (result & OPTIMUS_HDA_CODEC_MASK) ? "hda bios codec 
supported" : "");
+
+   *has_pr3 = nouveau_pr3_present(pdev);
}
 }

@@ -260,6 +283,7 @@ static bool nouveau_dsm_detect(void)
bool has_mux = false;
bool has_optimus = false;
bool has_optimus_flags = false;
+   bool has_power_resources = false;
int vga_count = 0;
bool guid_valid;
bool ret = false;
@@ -275,14 +299,14 @@ static bool nouveau_dsm_detect(void)
vga_count++;

nouveau_dsm_pci_probe(pdev, , _mux, _optimus,
- _optimus_flags);
+ _optimus_flags, _power_resources);
}

while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pdev)) != NULL) 
{
vga_count++;

nouveau_dsm_pci_probe(pdev, , _mux, _optimus,
- _optimus_flags);
+ _optimus_flags, _power_resources);
}

/* find the optimus DSM or the old v1 DSM */
@@ -292,8 +316,11 @@ static bool nouveau_dsm_detect(void)
);
printk(KERN_INFO "VGA switcheroo: detected Optimus DSM method 
%s handle\n",
acpi_method_name);
+   if (has_power_resources)
+   pr_info("nouveau: detected PR support, will not use 
DSM\n");
nouveau_dsm_priv.optimus_detected = true;
nouveau_dsm_priv.optimus_flags_detected = has_optimus_flags;
+   nouveau_dsm_priv.optimus_skip_dsm = has_power_resources;
ret = true;
} else if (vga_count == 2 && has_mux 

[PATCH v3 3/4] drm/nouveau/acpi: check for function 0x1B before using it

[Peter Wu]

Do not unconditionally invoke function 0x1B without checking for its
availability, it leads to an infinite loop on some firmware.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=104791
Fixes: 5addcf0a5f0fad ("nouveau: add runtime PM support (v0.9)")
Reviewed-by: Hans de Goede 
Signed-off-by: Peter Wu 
---
 drivers/gpu/drm/nouveau/nouveau_acpi.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c 
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 572ac30..ad273ad 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -45,6 +45,7 @@
 static struct nouveau_dsm_priv {
bool dsm_detected;
bool optimus_detected;
+   bool optimus_flags_detected;
acpi_handle dhandle;
acpi_handle rom_handle;
 } nouveau_dsm_priv;
@@ -212,7 +213,8 @@ static const struct vga_switcheroo_handler 
nouveau_dsm_handler = {
 };

 static void nouveau_dsm_pci_probe(struct pci_dev *pdev, acpi_handle 
*dhandle_out,
- bool *has_mux, bool *has_opt)
+ bool *has_mux, bool *has_opt,
+ bool *has_opt_flags)
 {
acpi_handle dhandle;
bool supports_mux;
@@ -236,6 +238,7 @@ static void nouveau_dsm_pci_probe(struct pci_dev *pdev, 
acpi_handle *dhandle_out
*dhandle_out = dhandle;
*has_mux = supports_mux;
*has_opt = !!optimus_funcs;
+   *has_opt_flags = optimus_funcs & (1 << NOUVEAU_DSM_OPTIMUS_FLAGS);

if (optimus_funcs) {
uint32_t result;
@@ -256,6 +259,7 @@ static bool nouveau_dsm_detect(void)
acpi_handle dhandle = NULL;
bool has_mux = false;
bool has_optimus = false;
+   bool has_optimus_flags = false;
int vga_count = 0;
bool guid_valid;
bool ret = false;
@@ -270,13 +274,15 @@ static bool nouveau_dsm_detect(void)
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
vga_count++;

-   nouveau_dsm_pci_probe(pdev, , _mux, _optimus);
+   nouveau_dsm_pci_probe(pdev, , _mux, _optimus,
+ _optimus_flags);
}

while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pdev)) != NULL) 
{
vga_count++;

-   nouveau_dsm_pci_probe(pdev, , _mux, _optimus);
+   nouveau_dsm_pci_probe(pdev, , _mux, _optimus,
+ _optimus_flags);
}

/* find the optimus DSM or the old v1 DSM */
@@ -287,6 +293,7 @@ static bool nouveau_dsm_detect(void)
printk(KERN_INFO "VGA switcheroo: detected Optimus DSM method 
%s handle\n",
acpi_method_name);
nouveau_dsm_priv.optimus_detected = true;
+   nouveau_dsm_priv.optimus_flags_detected = has_optimus_flags;
ret = true;
} else if (vga_count == 2 && has_mux && guid_valid) {
nouveau_dsm_priv.dhandle = dhandle;
@@ -320,8 +327,9 @@ void nouveau_switcheroo_optimus_dsm(void)
if (!nouveau_dsm_priv.optimus_detected)
return;

-   nouveau_optimus_dsm(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_OPTIMUS_FLAGS,
-   0x3, );
+   if (nouveau_dsm_priv.optimus_flags_detected)
+   nouveau_optimus_dsm(nouveau_dsm_priv.dhandle, 
NOUVEAU_DSM_OPTIMUS_FLAGS,
+   0x3, );

nouveau_optimus_dsm(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_OPTIMUS_CAPS,
NOUVEAU_DSM_OPTIMUS_SET_POWERDOWN, );
-- 
2.9.0

[PATCH v3 2/4] drm/nouveau/acpi: return supported DSM functions

[Peter Wu]

Return the set of supported functions to the caller. No functional
changes.

Reviewed-by: Hans de Goede 
Signed-off-by: Peter Wu 
---
 drivers/gpu/drm/nouveau/nouveau_acpi.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c 
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 886a67c..572ac30 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -107,7 +107,7 @@ static int nouveau_optimus_dsm(acpi_handle handle, int 
func, int arg, uint32_t *
  * requirements on the fourth parameter, so a private implementation
  * instead of using acpi_check_dsm().
  */
-static int nouveau_check_optimus_dsm(acpi_handle handle)
+static int nouveau_dsm_get_optimus_functions(acpi_handle handle)
 {
int result;

@@ -122,7 +122,9 @@ static int nouveau_check_optimus_dsm(acpi_handle handle)
 * ACPI Spec v4 9.14.1: if bit 0 is zero, no function is supported.
 * If the n-th bit is enabled, function n is supported
 */
-   return result & 1 && result & (1 << NOUVEAU_DSM_OPTIMUS_CAPS);
+   if (result & 1 && result & (1 << NOUVEAU_DSM_OPTIMUS_CAPS))
+   return result;
+   return 0;
 }

 static int nouveau_dsm(acpi_handle handle, int func, int arg)
@@ -214,7 +216,7 @@ static void nouveau_dsm_pci_probe(struct pci_dev *pdev, 
acpi_handle *dhandle_out
 {
acpi_handle dhandle;
bool supports_mux;
-   bool supports_opt;
+   int optimus_funcs;

dhandle = ACPI_HANDLE(>dev);
if (!dhandle)
@@ -225,17 +227,17 @@ static void nouveau_dsm_pci_probe(struct pci_dev *pdev, 
acpi_handle *dhandle_out

supports_mux = acpi_check_dsm(dhandle, nouveau_dsm_muid, 0x0102,
  1 << NOUVEAU_DSM_POWER);
-   supports_opt = nouveau_check_optimus_dsm(dhandle);
+   optimus_funcs = nouveau_dsm_get_optimus_functions(dhandle);

/* Does not look like a Nvidia device. */
-   if (!supports_mux && !supports_opt)
+   if (!supports_mux && !optimus_funcs)
return;

*dhandle_out = dhandle;
*has_mux = supports_mux;
-   *has_opt = supports_opt;
+   *has_opt = !!optimus_funcs;

-   if (supports_opt) {
+   if (optimus_funcs) {
uint32_t result;
nouveau_optimus_dsm(dhandle, NOUVEAU_DSM_OPTIMUS_CAPS, 0,
);
-- 
2.9.0

[PATCH v3 1/4] drm/nouveau/acpi: ensure matching ACPI handle and supported functions

[Peter Wu]

Ensure that the returned set of supported DSM functions (MUX, Optimus)
match the ACPI handle that is set in nouveau_dsm_pci_probe.

As there are no machines with a MUX function on just one PCI device and
an Optimus on another, there should not be a functional impact. This
change however makes this implicit assumption more obvious.

Convert int to bool and rename has_dsm to has_mux while at it. Let the
caller set nouveau_dsm_priv.dhandle as needed.

 v2: pass dhandle to the caller.

Reviewed-by: Hans de Goede 
Signed-off-by: Peter Wu 
---
 drivers/gpu/drm/nouveau/nouveau_acpi.c | 58 +++---
 1 file changed, 26 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c 
b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index db76b94..886a67c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -57,9 +57,6 @@ bool nouveau_is_v1_dsm(void) {
return nouveau_dsm_priv.dsm_detected;
 }

-#define NOUVEAU_DSM_HAS_MUX 0x1
-#define NOUVEAU_DSM_HAS_OPT 0x2
-
 #ifdef CONFIG_VGA_SWITCHEROO
 static const char nouveau_dsm_muid[] = {
0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4D,
@@ -212,26 +209,33 @@ static const struct vga_switcheroo_handler 
nouveau_dsm_handler = {
.get_client_id = nouveau_dsm_get_client_id,
 };

-static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
+static void nouveau_dsm_pci_probe(struct pci_dev *pdev, acpi_handle 
*dhandle_out,
+ bool *has_mux, bool *has_opt)
 {
acpi_handle dhandle;
-   int retval = 0;
+   bool supports_mux;
+   bool supports_opt;

dhandle = ACPI_HANDLE(>dev);
if (!dhandle)
-   return false;
+   return;

if (!acpi_has_method(dhandle, "_DSM"))
-   return false;
+   return;

-   if (acpi_check_dsm(dhandle, nouveau_dsm_muid, 0x0102,
-  1 << NOUVEAU_DSM_POWER))
-   retval |= NOUVEAU_DSM_HAS_MUX;
+   supports_mux = acpi_check_dsm(dhandle, nouveau_dsm_muid, 0x0102,
+ 1 << NOUVEAU_DSM_POWER);
+   supports_opt = nouveau_check_optimus_dsm(dhandle);

-   if (nouveau_check_optimus_dsm(dhandle))
-   retval |= NOUVEAU_DSM_HAS_OPT;
+   /* Does not look like a Nvidia device. */
+   if (!supports_mux && !supports_opt)
+   return;

-   if (retval & NOUVEAU_DSM_HAS_OPT) {
+   *dhandle_out = dhandle;
+   *has_mux = supports_mux;
+   *has_opt = supports_opt;
+
+   if (supports_opt) {
uint32_t result;
nouveau_optimus_dsm(dhandle, NOUVEAU_DSM_OPTIMUS_CAPS, 0,
);
@@ -240,10 +244,6 @@ static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
 (result & OPTIMUS_DYNAMIC_PWR_CAP) ? "dynamic power, " 
: "",
 (result & OPTIMUS_HDA_CODEC_MASK) ? "hda bios codec 
supported" : "");
}
-   if (retval)
-   nouveau_dsm_priv.dhandle = dhandle;
-
-   return retval;
 }

 static bool nouveau_dsm_detect(void)
@@ -251,11 +251,11 @@ static bool nouveau_dsm_detect(void)
char acpi_method_name[255] = { 0 };
struct acpi_buffer buffer = {sizeof(acpi_method_name), 
acpi_method_name};
struct pci_dev *pdev = NULL;
-   int has_dsm = 0;
-   int has_optimus = 0;
+   acpi_handle dhandle = NULL;
+   bool has_mux = false;
+   bool has_optimus = false;
int vga_count = 0;
bool guid_valid;
-   int retval;
bool ret = false;

/* lookup the MXM GUID */
@@ -268,32 +268,26 @@ static bool nouveau_dsm_detect(void)
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != 
NULL) {
vga_count++;

-   retval = nouveau_dsm_pci_probe(pdev);
-   if (retval & NOUVEAU_DSM_HAS_MUX)
-   has_dsm |= 1;
-   if (retval & NOUVEAU_DSM_HAS_OPT)
-   has_optimus = 1;
+   nouveau_dsm_pci_probe(pdev, , _mux, _optimus);
}

while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pdev)) != NULL) 
{
vga_count++;

-   retval = nouveau_dsm_pci_probe(pdev);
-   if (retval & NOUVEAU_DSM_HAS_MUX)
-   has_dsm |= 1;
-   if (retval & NOUVEAU_DSM_HAS_OPT)
-   has_optimus = 1;
+   nouveau_dsm_pci_probe(pdev, , _mux, _optimus);
}

/* find the optimus DSM or the old v1 DSM */
-   if (has_optimus == 1) {
+   if (has_optimus) {
+   nouveau_dsm_priv.dhandle = dhandle;
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME,
);
printk(KERN_INFO "VGA switcheroo: detected Optimus DSM method 
%s handle\n",
acpi_method_name);

[PATCH v3 0/4] nouveau RPM fixes for Optimus (final)

[Peter Wu]

Hi,

Here are two patches to fix an issue reported on kernel bugzilla (infinite loop
due to unchecked function) and a more important fix to fix hanging Optimus
machines when runtime PM is enabled (with pm/pci patches).

These are the final patches targeting v4.8. Changes compared to v2[1]:
collected R-b from Hans and Mika and fixed a minor comment style issue.

I recommend it to be merged before the pci/pm patches[2], otherwise there is a
window where newer Nvidia Optimus laptops might fail to runtime resume and/or
lock up.  Once the pci/pm branch is merged I will propose another patch to
improve reliability[3].

Known issue with patch 4: when a Nvidia HDMI audio function is present, the
bridge will not suspend and hence the Nvidia card will still be powered. Fixing
this properly will require more work[4], until then you can kill the audio
device and make runtime PM work properly:

echo 1 > /sys/bus/pci/devices/:01:00.1/remove

Kind regards,
Peter

 [1]: https://lists.freedesktop.org/archives/nouveau/2016-July/025519.html
 [2]: https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/?h=pci/pm
 [3]: http://www.spinics.net/lists/linux-pci/msg52601.html
 [4]: https://lists.freedesktop.org/archives/dri-devel/2016-July/112759.html

Peter Wu (4):
  drm/nouveau/acpi: ensure matching ACPI handle and supported functions
  drm/nouveau/acpi: return supported DSM functions
  drm/nouveau/acpi: check for function 0x1B before using it
  drm/nouveau/acpi: fix lockup with PCIe runtime PM

 drivers/gpu/drm/nouveau/nouveau_acpi.c | 105 +
 1 file changed, 68 insertions(+), 37 deletions(-)

-- 
2.9.0

[Patch V2] intel: Export pooled EU and min no. of eus in a pool.

[Yang Rong]

Update kernel interface with new I915_GETPARAM ioctl entries for
pooled EU and min no. of eus in a pool. Add a wrapping function
for each parameter. Userspace drivers need these values when decide
the thread count. This kernel enabled pooled eu by default for BXT
and for fused down 2x6 parts it is advised to turn it off.

But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled and the no. of eus in a pool is different,
So userspace need to know min no. of eus in a pool.

V2: use return value as the query results.
ret < 0 when error, ret = 0 when not support, and ret > 0 indicate
query results.(Chris)

Signed-off-by: Yang Rong 
---
 include/drm/i915_drm.h   |  2 ++
 intel/intel_bufmgr.h |  3 +++
 intel/intel_bufmgr_gem.c | 32 
 3 files changed, 37 insertions(+)

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index c4ce6b2..eb611a7 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -357,6 +357,8 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_GPU_RESET35
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
 #define I915_PARAM_HAS_EXEC_SOFTPIN 37
+#define I915_PARAM_HAS_POOLED_EU 38
+#define I915_PARAM_MIN_EU_IN_POOL39

 typedef struct drm_i915_getparam {
__s32 param;
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index a1abbcd..96a4d9d 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -273,6 +273,9 @@ int drm_intel_get_reset_stats(drm_intel_context *ctx,
 int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
 int drm_intel_get_eu_total(int fd, unsigned int *eu_total);

+int drm_intel_get_pooled_eu(int fd);
+int drm_intel_get_min_eu_in_pool(int fd);
+
 /** @{ Compatibility defines to keep old code building despite the symbol 
rename
  * from dri_* to drm_intel_*
  */
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 0a4012b..4d9899d 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3237,6 +3237,38 @@ drm_intel_get_eu_total(int fd, unsigned int *eu_total)
return 0;
 }

+int
+drm_intel_get_pooled_eu(int fd)
+{
+   drm_i915_getparam_t gp;
+   int ret;
+
+   memclear(gp);
+   gp.param = I915_PARAM_HAS_POOLED_EU;
+   gp.value = 
+   ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, );
+   if (ret)
+   return -errno;
+
+   return ret;
+}
+
+int
+drm_intel_get_min_eu_in_pool(int fd)
+{
+   drm_i915_getparam_t gp;
+   int ret;
+
+   memclear(gp);
+   gp.param = I915_PARAM_MIN_EU_IN_POOL;
+   gp.value = 
+   ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, );
+   if (ret)
+   return -errno;
+
+   return ret;
+}
+
 /**
  * Annotate the given bo for use in aub dumping.
  *
-- 
2.1.4

[PATCH 12/16] gpu: ipu-v3: Fix CSI0 blur in NTSC format

[Philipp Zabel]

Am Mittwoch, den 13.07.2016, 16:02 -0700 schrieb Steve Longerbeam:
> On 07/10/2016 09:33 AM, Steve Longerbeam wrote:
> >
> >
> > On 07/08/2016 10:34 AM, Philipp Zabel wrote:
> >> Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> >>> From: Suresh Dhandapani 
> >>>
> >>> This patch will change the register IPU_CSI0_CCIR_CODE_2 value from
> >>> 0x40596 to 0x405A6. The change is related to the Start of field 1
> >>> first blanking line command bit[5-3] for NTSC format only. This
> >>> change is dependent with ADV chip where the NEWAVMODE is set to 0
> >>> in register 0x31. Setting NEWAVMODE to "0" in ADV means "EAV/SAV
> >>> codes generated to suit analog devices encoders".
> >>>
> >>> Signed-off-by: Suresh Dhandapani 
> >>> ---
> >>>   drivers/gpu/ipu-v3/ipu-csi.c | 2 +-
> >>>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
> >>> index 0eac28c..ec81958 100644
> >>> --- a/drivers/gpu/ipu-v3/ipu-csi.c
> >>> +++ b/drivers/gpu/ipu-v3/ipu-csi.c
> >>> @@ -422,7 +422,7 @@ int ipu_csi_init_interface(struct ipu_csi *csi,
> >>> ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
> >>> CSI_CCIR_CODE_1);
> >>> -ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
> >>> +ipu_csi_write(csi, 0x405A6, CSI_CCIR_CODE_2);
> >>>   ipu_csi_write(csi, 0xFF, CSI_CCIR_CODE_3);
> >>>   } else {
> >>>   dev_err(csi->ipu->dev,
> >> This looks like a very hardware specific hack? I'll at least have to
> >> test if that also works with other analog decoders.
> >
> > Hi Philipp,
> >
> > Yes it's a hack, but it has always been a hack (hardcoded values). And the
> > reason is simple, nobody AFAIK (including me) understands how to program
> > these CSI_CCIR_CODE registers, the description in the reference manual is
> > complete gibberish.
> 
> Hi Philipp, Ian over at linux-media helped me to understand these registers a
> little better, although there are still mysteries given the poor 
> documentation.
> You should have been copied on that linux-media thread.
> 
> >
> > The reason we made this change is that, in discussions with Analog Devices,
> > they recommended setting NEWAVMODE, which changes the positions of
> > the AV codes sent by the ADV7180 on the bt.656 bus. It took Suresh at least
> > a full day of reverse engineering (Suresh correct me if I am wrong) to hit
> > on the correct values in these registers to regain stable video after 
> > switching
> > the ADV7180 to NEWAVMODE.
> 
> So this NEWAVMODE is somehow breaking from the BT.656 standard, which
> necessitated the change to CSI_CCIR_CODE_2. So NEWAVMODE if enabled in
> the ADV7180 will break other capture backends that are expecting standard
> BT.656 SAV/EAV codes. So NEWAVMODE should not be used and I will remove
> this patch in the next version.

Ok. To use that mode, first a new v4l2 mbus type and corresponding DT
bindings would have to be added.

regards
Philipp

[PATCH 09/16] gpu: ipu-v3: Add ipu_ic_set_src()

[Steve Longerbeam]

On 07/15/2016 05:45 AM, Philipp Zabel wrote:
> Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
>> +int ipu_ic_set_src(struct ipu_ic *ic, int csi_id, bool vdi)
>> +{
>> +struct ipu_ic_priv *priv = ic->priv;
>> +
>> +ipu_set_ic_src_mux(priv->ipu, csi_id, vdi);
>   ipu_set_ic_src_mux(ic->priv->ipu, csi_id, vdi);
> would be shorter.

Again this function isn't needed any longer. I will remove this
patch in next version.

Steve

[PATCH v5 2/2] drm/fsl-dcu: add support for drm bridge

[Meng Yi]

The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.

Signed-off-by: Meng Yi 
---
Changes since V1:
-no change
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index ba1edb1..cc19e1c 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -180,16 +180,26 @@ err_cleanup:
 static int fsl_dcu_attach_endpoint(struct fsl_dcu_drm_device *fsl_dev,
const struct of_endpoint *ep)
 {
+   struct drm_bridge *bridge;
struct device_node *np;

np = of_graph_get_remote_port_parent(ep->local_node);

fsl_dev->connector.panel = of_drm_find_panel(np);
-   of_node_put(np);
-   if (fsl_dev->connector.panel)
+   if (fsl_dev->connector.panel) {
+   of_node_put(np);
return fsl_dcu_attach_panel(fsl_dev, fsl_dev->connector.panel);
+   }
+
+   bridge = of_drm_find_bridge(np);
+   of_node_put(np);
+   if (!bridge)
+   return -ENODEV;
+
+   fsl_dev->encoder.bridge = bridge;
+   bridge->encoder = _dev->encoder;

-   return -ENODEV;
+   return drm_bridge_attach(fsl_dev->drm, bridge);
 }

 int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev)
-- 
2.1.0.27.g96db324

[PATCH v5 1/2] drm/fsl-dcu: rework codes to support of_graph dt binding for panel

[Meng Yi]

This patch rework the output code to add of_graph dt binding support
for panel device and also keeps the backward compatibility

Signed-off-by: Meng Yi 
---
Changes in V5:
-remove unused variable 'ret'
Changes in V4:
-simplify return value statements
-merge corresponding documentation to this patch
Changes in V3:
-simplify return value statements
Changes in V2:
-fix some coding style issue
-add fsl_dev->connector.panel check
-use fsl_dev->np and drop fsl_dev->dev->of_node
-return 'ret' when fsl_dcu_attach_panel failed
---
 .../devicetree/bindings/display/fsl,dcu.txt|  9 ++-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c  |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h   |  3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c  | 68 +++---
 4 files changed, 57 insertions(+), 25 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt 
b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ae55cde..63ec2a6 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -12,7 +12,7 @@ Required properties:
 - clock-names: Should be "dcu" and "pix"
See ../clocks/clock-bindings.txt for details.
 - big-endian   Boolean property, LS1021A DCU registers are big-endian.
-- fsl,panel:   The phandle to panel node.
+- port Video port for the panel output

 Optional properties:
 - fsl,tcon:The phandle to the timing controller node.
@@ -24,6 +24,11 @@ dcu: dcu at 2ce {
clocks = <_clk 0>, <_clk 0>;
clock-names = "dcu", "pix";
big-endian;
-   fsl,panel = <>;
fsl,tcon = <>;
+
+   port {
+   dcu_out: endpoint {
+   remote-endpoint = <_out>;
+};
+   };
 };
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
index a6e4cd5..d9d6cc1 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
@@ -43,7 +43,7 @@ int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device 
*fsl_dev)
if (ret)
goto err;

-   ret = fsl_dcu_drm_connector_create(fsl_dev, _dev->encoder);
+   ret = fsl_dcu_create_outputs(fsl_dev);
if (ret)
goto err;

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
index 7093109..5a7b88e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
@@ -25,9 +25,8 @@ to_fsl_dcu_connector(struct drm_connector *con)
 : NULL;
 }

-int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
-struct drm_encoder *encoder);
 int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
   struct drm_crtc *crtc);
+int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev);

 #endif /* __FSL_DCU_DRM_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 0b0989e..ba1edb1 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -10,6 +10,7 @@
  */

 #include 
+#include 

 #include 
 #include 
@@ -132,12 +133,12 @@ static const struct drm_connector_helper_funcs 
connector_helper_funcs = {
.mode_valid = fsl_dcu_drm_connector_mode_valid,
 };

-int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
-struct drm_encoder *encoder)
+static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
+struct drm_panel *panel)
 {
+   struct drm_encoder *encoder = _dev->encoder;
struct drm_connector *connector = _dev->connector.base;
struct drm_mode_config *mode_config = _dev->drm->mode_config;
-   struct device_node *panel_node;
int ret;

fsl_dev->connector.encoder = encoder;
@@ -161,21 +162,7 @@ int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device 
*fsl_dev,
  mode_config->dpms_property,
  DRM_MODE_DPMS_OFF);

-   panel_node = of_parse_phandle(fsl_dev->np, "fsl,panel", 0);
-   if (!panel_node) {
-   dev_err(fsl_dev->dev, "fsl,panel property not found\n");
-   ret = -ENODEV;
-   goto err_sysfs;
-   }
-
-   fsl_dev->connector.panel = of_drm_find_panel(panel_node);
-   if (!fsl_dev->connector.panel) {
-   ret = -EPROBE_DEFER;
-   goto err_panel;
-   }
-   of_node_put(panel_node);
-
-   ret = drm_panel_attach(fsl_dev->connector.panel, connector);
+   ret = drm_panel_attach(panel, connector);
if (ret) {
dev_err(fsl_dev->dev, "failed to attach panel\n");
goto 

[Nouveau] [PATCH v3] drm/nouveau/fb/nv50: set DMA mask before mapping scratch page

[Alexandre Courbot]

On Fri, Jul 8, 2016 at 1:59 AM, Ard Biesheuvel
 wrote:
> The 100c08 scratch page is mapped using dma_map_page() before the TTM
> layer has had a chance to set the DMA mask. This means we are still
> running with the default of 32 when this code executes, and this causes
> problems for platforms with no memory below 4 GB (such as AMD Seattle)
>
> So move the dma_map_page() to the .init hook, and set the streaming DMA
> mask based on the MMU subdev parameters before performing the call.
>
> Signed-off-by: Ard Biesheuvel 
> ---
> I am sure there is a much better way to address this, but this fixes the
> problem I get on AMD Seattle with a GeForce 210 PCIe card:
>
>nouveau :02:00.0: enabling device ( -> 0003)
>nouveau :02:00.0: NVIDIA GT218 (0a8280b1)
>nouveau :02:00.0: bios: version 70.18.a6.00.00
>nouveau :02:00.0: fb ctor failed, -14
>nouveau: probe of :02:00.0 failed with error -14
>
> v2: replace incorrect comparison of dma_addr_t type var against NULL
> v3: rework code to get rid of DMA_ERROR_CODE references, which is not
> defined on all architectures
>
>  drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 40 ++--
>  1 file changed, 29 insertions(+), 11 deletions(-)

I think the same problem exists in fb/gf100.c, would be nice to fix it
there as well.

I have faced similar issues on Tegra before. I wonder whether this
could not be addressed the same way I did, i.e. by setting a
temporary, fail-safe DMA mask in nvkm_device_pci_new()? That would
allow all subdevs to map pages to the device safely in their init.
With your solution, each subdev in that scenario needs to set a DMA
mask to be safe.

Not sure whether that's practical as I suppose you want to make the
DMA mask larger than 32 bits?

If you absolutely need to do this in the device, can we move the DMA
mask setting logic in nouveau_ttm into its own function and call it
from the FB driver to make sure the mask is correctly set? Maybe this
could even be made a MMU function and called during MMU ctor or init
(in the latter case we would also need to reorder MMU init to make it
happen before FB and INSTMEM).

[PATCH 08/16] gpu: ipu-v3: Add ipu_csi_set_src()

[Philipp Zabel]

Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> Adds ipu_csi_set_src() which is just a wrapper around
> ipu_set_csi_src_mux().
> 
> Signed-off-by: Steve Longerbeam 
> ---
>  drivers/gpu/ipu-v3/ipu-csi.c | 8 
>  include/video/imx-ipu-v3.h   | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
> index 06631ac..336dc06 100644
> --- a/drivers/gpu/ipu-v3/ipu-csi.c
> +++ b/drivers/gpu/ipu-v3/ipu-csi.c
> @@ -609,6 +609,14 @@ int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
>  }
>  EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
>  
> +int ipu_csi_set_src(struct ipu_csi *csi, u32 vc, bool select_mipi_csi2)

vc is unused.

> +{
> + ipu_set_csi_src_mux(csi->ipu, csi->id, select_mipi_csi2);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(ipu_csi_set_src);
> +

Couldn't you just replace ipu_set_csi_src_mux?

regards
Philipp

[PATCH 06/16] gpu: ipu-v3: Add ipu_set_vdi_src_mux()

[Philipp Zabel]

Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> Adds ipu_set_vdi_src_mux() that selects the VDIC input
> (from CSI or memory).
> 
> Signed-off-by: Steve Longerbeam 
> ---
>  drivers/gpu/ipu-v3/ipu-common.c | 20 
>  include/video/imx-ipu-v3.h  |  1 +
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
> index 6d1676e..374100e 100644
> --- a/drivers/gpu/ipu-v3/ipu-common.c
> +++ b/drivers/gpu/ipu-v3/ipu-common.c
> @@ -730,6 +730,26 @@ void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, 
> bool vdi)
>  }
>  EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
>  
> +/*
> + * Set the source for the VDIC. Selects either from CSI[01] or memory.
> + */
> +void ipu_set_vdi_src_mux(struct ipu_soc *ipu, bool csi)
> +{
> + unsigned long flags;
> + u32 val;
> +
> + spin_lock_irqsave(>lock, flags);
> +
> + val = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
> + val &= ~(0x3 << 28);
> + if (csi)
> + val |= (0x01 << 28);

This doesn't set a bus mux, or does it? As I understand it, this
configures the FSU to trigger the VDIC conversion from the CSI direct
channel sync signals (IC channel CB7). As such I believe this belongs
together with the other channel linking code, maybe even in ipu-fsu.c.

Also, some #defines would be nice, for example:

#define FS_VDI_SRC_SEL_MASK (0x3 << 28)
#define FS_VDI_SRC_SEL_OFFSET   28
#define FS_VDI_SRC_SEL_CSI_DIRECT   0x1
#define FS_VDI_SRC_SEL_VDOA 0x2

regards
Philipp

[PATCH 21/21] drm/nouveau: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Nouveau DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/nouveau/Kconfig | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index 5ab13e7..2922a82 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -3,13 +3,7 @@ config DRM_NOUVEAU
depends on DRM && PCI
 select FW_LOADER
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_TTM
-   select FB_CFB_FILLRECT
-   select FB_CFB_COPYAREA
-   select FB_CFB_IMAGEBLIT
-   select FB
-   select FRAMEBUFFER_CONSOLE if !EXPERT
select FB_BACKLIGHT if DRM_NOUVEAU_BACKLIGHT
select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && INPUT
select X86_PLATFORM_DEVICES if ACPI && X86
-- 
2.7.3

[PATCH 20/21] drm/arm: make fbdev support really optional

[Tobias Jakobi]

Currently enabling ARM HDLCD DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/arm/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/arm/Kconfig b/drivers/gpu/drm/arm/Kconfig
index eaed454..ff402500 100644
--- a/drivers/gpu/drm/arm/Kconfig
+++ b/drivers/gpu/drm/arm/Kconfig
@@ -9,7 +9,6 @@ config DRM_HDLCD
depends on COMMON_CLK
select DRM_ARM
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_KMS_CMA_HELPER
help
  Choose this option if you have an ARM High Definition Colour LCD
-- 
2.7.3

[PATCH 19/21] drm/ast: make fbdev support really optional

[Tobias Jakobi]

Currently enabling AST Server DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/ast/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/ast/Kconfig b/drivers/gpu/drm/ast/Kconfig
index 8a784c4..15f6ce7 100644
--- a/drivers/gpu/drm/ast/Kconfig
+++ b/drivers/gpu/drm/ast/Kconfig
@@ -2,11 +2,7 @@ config DRM_AST
tristate "AST server chips"
depends on DRM && PCI
select DRM_TTM
-   select FB_SYS_COPYAREA
-   select FB_SYS_FILLRECT
-   select FB_SYS_IMAGEBLIT
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_TTM
help
 Say yes for experimental AST GPU driver. Do not enable
-- 
2.7.3

[PATCH 18/21] drm/virtio: make fbdev support really optional

[Tobias Jakobi]

Currently enabling VirtIO DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/virtio/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/virtio/Kconfig b/drivers/gpu/drm/virtio/Kconfig
index 9983ead..e1afc3d 100644
--- a/drivers/gpu/drm/virtio/Kconfig
+++ b/drivers/gpu/drm/virtio/Kconfig
@@ -1,11 +1,7 @@
 config DRM_VIRTIO_GPU
tristate "Virtio GPU driver"
depends on DRM && VIRTIO
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
 select DRM_KMS_HELPER
-select DRM_KMS_FB_HELPER
 select DRM_TTM
help
   This is the virtual GPU driver for virtio.  It can be used with
-- 
2.7.3

[PATCH 17/21] drm/atmel-hlcdc: make fbdev support really optional

[Tobias Jakobi]

Currently enabling ATMEL HLCDC DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/atmel-hlcdc/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/atmel-hlcdc/Kconfig 
b/drivers/gpu/drm/atmel-hlcdc/Kconfig
index 99b4f06..32bcc4b 100644
--- a/drivers/gpu/drm/atmel-hlcdc/Kconfig
+++ b/drivers/gpu/drm/atmel-hlcdc/Kconfig
@@ -3,7 +3,6 @@ config DRM_ATMEL_HLCDC
depends on DRM && OF && COMMON_CLK && MFD_ATMEL_HLCDC && ARM
select DRM_GEM_CMA_HELPER
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_KMS_CMA_HELPER
select DRM_PANEL
help
-- 
2.7.3

[PATCH 16/21] drm/udl: make fbdev support really optional

[Tobias Jakobi]

Currently enabling USB DisplayLink DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/udl/Kconfig | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/udl/Kconfig b/drivers/gpu/drm/udl/Kconfig
index 613ab06..1616ec4 100644
--- a/drivers/gpu/drm/udl/Kconfig
+++ b/drivers/gpu/drm/udl/Kconfig
@@ -4,12 +4,7 @@ config DRM_UDL
depends on USB_SUPPORT
depends on USB_ARCH_HAS_HCD
select USB
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
-   select FB_DEFERRED_IO
select DRM_KMS_HELPER
-select DRM_KMS_FB_HELPER
help
  This is a KMS driver for the USB displaylink video adapters.
   Say M/Y to add support for these devices via drm/kms interfaces.
-- 
2.7.3

[PATCH 15/21] drm/vmwgfx: make fbdev support really optional

[Tobias Jakobi]

Currently enabling VMware Virtual DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/vmwgfx/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/Kconfig b/drivers/gpu/drm/vmwgfx/Kconfig
index b49445d..e57ce65 100644
--- a/drivers/gpu/drm/vmwgfx/Kconfig
+++ b/drivers/gpu/drm/vmwgfx/Kconfig
@@ -1,10 +1,6 @@
 config DRM_VMWGFX
tristate "DRM driver for VMware Virtual GPU"
depends on DRM && PCI && X86
-   select FB_DEFERRED_IO
-   select FB_CFB_FILLRECT
-   select FB_CFB_COPYAREA
-   select FB_CFB_IMAGEBLIT
select DRM_TTM
# Only needed for the transitional use of drm_crtc_init - can be removed
# again once vmwgfx sets up the primary plane itself.
-- 
2.7.3

[PATCH 14/21] drm/bochs: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Bochs DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/bochs/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/bochs/Kconfig b/drivers/gpu/drm/bochs/Kconfig
index 5f8b0c2..f739763 100644
--- a/drivers/gpu/drm/bochs/Kconfig
+++ b/drivers/gpu/drm/bochs/Kconfig
@@ -2,10 +2,6 @@ config DRM_BOCHS
tristate "DRM Support for bochs dispi vga interface (qemu stdvga)"
depends on DRM && PCI
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
select DRM_TTM
help
  Choose this option for qemu.
-- 
2.7.3

[PATCH 13/21] drm/fsl-dcu: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Freescale DCU DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/fsl-dcu/Kconfig | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/Kconfig b/drivers/gpu/drm/fsl-dcu/Kconfig
index b9c714d..14a72c4 100644
--- a/drivers/gpu/drm/fsl-dcu/Kconfig
+++ b/drivers/gpu/drm/fsl-dcu/Kconfig
@@ -5,12 +5,7 @@ config DRM_FSL_DCU
select BACKLIGHT_LCD_SUPPORT
select DRM_KMS_HELPER
select DRM_KMS_CMA_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_PANEL
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
-   select FB_SYS_FOPS
select REGMAP_MMIO
select VIDEOMODE_HELPERS
help
-- 
2.7.3

[PATCH 12/21] drm/tilcdc: make fbdev support really optional

[Tobias Jakobi]

Currently enabling TI LCDC DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/tilcdc/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index f60a1ec..28fed7e 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -2,7 +2,6 @@ config DRM_TILCDC
tristate "DRM Support for TI LCDC Display Controller"
depends on DRM && OF && ARM
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
select VIDEOMODE_HELPERS
-- 
2.7.3

[PATCH 11/21] drm/rcar-du: make fbdev support really optional

[Tobias Jakobi]

Currently enabling R-Car DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/rcar-du/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index 7fc3ca5..4c2fd05 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -6,7 +6,6 @@ config DRM_RCAR_DU
select DRM_KMS_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
-   select DRM_KMS_FB_HELPER
select VIDEOMODE_HELPERS
help
  Choose this option if you have an R-Car chipset.
-- 
2.7.3

[PATCH 10/21] drm/gma500: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Intel GMA DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/gma500/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig
index 17f928e..8906d67 100644
--- a/drivers/gpu/drm/gma500/Kconfig
+++ b/drivers/gpu/drm/gma500/Kconfig
@@ -1,11 +1,7 @@
 config DRM_GMA500
tristate "Intel GMA5/600 KMS Framebuffer"
depends on DRM && PCI && X86
-   select FB_CFB_COPYAREA
-   select FB_CFB_FILLRECT
-   select FB_CFB_IMAGEBLIT
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_TTM
# GMA500 depends on ACPI_VIDEO when ACPI is enabled, just like i915
select ACPI_VIDEO if ACPI
-- 
2.7.3

[PATCH 09/21] drm/rockchip: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Rockchip DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/rockchip/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index d30bdc3..6f0ef56 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -3,11 +3,7 @@ config DRM_ROCKCHIP
depends on DRM && ROCKCHIP_IOMMU
depends on RESET_CONTROLLER
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_PANEL
-   select FB_CFB_FILLRECT
-   select FB_CFB_COPYAREA
-   select FB_CFB_IMAGEBLIT
select VIDEOMODE_HELPERS
help
  Choose this option if you have a Rockchip soc chipset.
-- 
2.7.3

[PATCH 08/21] drm/shmobile: make fbdev support really optional

[Tobias Jakobi]

Currently enabling SH Mobile DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/shmobile/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/shmobile/Kconfig b/drivers/gpu/drm/shmobile/Kconfig
index 8d17d00..c987c82 100644
--- a/drivers/gpu/drm/shmobile/Kconfig
+++ b/drivers/gpu/drm/shmobile/Kconfig
@@ -6,7 +6,6 @@ config DRM_SHMOBILE
select BACKLIGHT_CLASS_DEVICE
select BACKLIGHT_LCD_SUPPORT
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
help
-- 
2.7.3

[PATCH 07/21] drm/imx: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Freescale i.MX DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/imx/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index a1844b5..f2c9ae8 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -1,7 +1,6 @@
 config DRM_IMX
tristate "DRM Support for Freescale i.MX"
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select VIDEOMODE_HELPERS
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
-- 
2.7.3

[PATCH 06/21] drm/qxl: make fbdev support really optional

[Tobias Jakobi]

Currently enabling QXL DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/qxl/Kconfig | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/qxl/Kconfig b/drivers/gpu/drm/qxl/Kconfig
index 38c2bb7..da45b11 100644
--- a/drivers/gpu/drm/qxl/Kconfig
+++ b/drivers/gpu/drm/qxl/Kconfig
@@ -1,12 +1,7 @@
 config DRM_QXL
tristate "QXL virtual GPU"
depends on DRM && PCI
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
-   select FB_DEFERRED_IO
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_TTM
select CRC32
help
-- 
2.7.3

[PATCH 05/21] drm/cirrus: make fbdev support really optional

[Tobias Jakobi]

Currently enabling QEMU Cirrus DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/cirrus/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/cirrus/Kconfig b/drivers/gpu/drm/cirrus/Kconfig
index 9864559..04b3c16 100644
--- a/drivers/gpu/drm/cirrus/Kconfig
+++ b/drivers/gpu/drm/cirrus/Kconfig
@@ -1,11 +1,7 @@
 config DRM_CIRRUS_QEMU
tristate "Cirrus driver for QEMU emulated device"
depends on DRM && PCI
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_TTM
help
 This is a KMS driver for emulated cirrus device in qemu.
-- 
2.7.3

[PATCH 04/21] drm/mgag200: make fbdev support really optional

[Tobias Jakobi]

Currently enabling MGA G200 DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/mgag200/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/mgag200/Kconfig b/drivers/gpu/drm/mgag200/Kconfig
index 3a1c5fb..520e5e6 100644
--- a/drivers/gpu/drm/mgag200/Kconfig
+++ b/drivers/gpu/drm/mgag200/Kconfig
@@ -1,11 +1,7 @@
 config DRM_MGAG200
tristate "Kernel modesetting driver for MGA G200 server engines"
depends on DRM && PCI
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_TTM
help
 This is a KMS driver for the MGA G200 server chips, it
-- 
2.7.3

[PATCH 03/21] drm/omap: make fbdev support really optional

[Tobias Jakobi]

Currently enabling OMAP DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/omapdrm/Kconfig | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/Kconfig b/drivers/gpu/drm/omapdrm/Kconfig
index 336ad4d..556f81f 100644
--- a/drivers/gpu/drm/omapdrm/Kconfig
+++ b/drivers/gpu/drm/omapdrm/Kconfig
@@ -4,11 +4,6 @@ config DRM_OMAP
depends on ARCH_OMAP2PLUS || ARCH_MULTIPLATFORM
select OMAP2_DSS
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
-   select FB_SYS_FILLRECT
-   select FB_SYS_COPYAREA
-   select FB_SYS_IMAGEBLIT
-   select FB_SYS_FOPS
default n
help
  DRM display driver for OMAP2/3/4 based boards.
-- 
2.7.3

[PATCH 02/21] drm/armada: make fbdev support really optional

[Tobias Jakobi]

Currently enabling Marvell Armada DRM support automatically pulls
in fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/armada/Kconfig | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/armada/Kconfig b/drivers/gpu/drm/armada/Kconfig
index eb773e9..15f3ecf 100644
--- a/drivers/gpu/drm/armada/Kconfig
+++ b/drivers/gpu/drm/armada/Kconfig
@@ -1,11 +1,7 @@
 config DRM_ARMADA
tristate "DRM support for Marvell Armada SoCs"
depends on DRM && HAVE_CLK && ARM
-   select FB_CFB_FILLRECT
-   select FB_CFB_COPYAREA
-   select FB_CFB_IMAGEBLIT
select DRM_KMS_HELPER
-   select DRM_KMS_FB_HELPER
help
  Support the "LCD" controllers found on the Marvell Armada 510
  devices.  There are two controllers on the device, each controller
-- 
2.7.3

[PATCH 01/21] drm/arc: make fbdev support really optional

[Tobias Jakobi]

Currently enabling ARC DRM support automatically pulls in
fbdev dependency. However this dep is unnecessary since
DRM core already handles this for us (DRM_FBDEV_EMULATION).

Signed-off-by: Tobias Jakobi 
---
 drivers/gpu/drm/arc/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/arc/Kconfig b/drivers/gpu/drm/arc/Kconfig
index f9a13b6..f47d88b 100644
--- a/drivers/gpu/drm/arc/Kconfig
+++ b/drivers/gpu/drm/arc/Kconfig
@@ -2,7 +2,6 @@ config DRM_ARCPGU
tristate "ARC PGU"
depends on DRM && OF
select DRM_KMS_CMA_HELPER
-   select DRM_KMS_FB_HELPER
select DRM_KMS_HELPER
help
  Choose this option if you have an ARC PGU controller.
-- 
2.7.3

[PATCH 00/21] drm: make fbdev support really optional

[Tobias Jakobi]

Hello,

as request by Daniel here 
(http://www.spinics.net/lists/dri-devel/msg112592.html) I went ahead and also 
cleaned up the other Kconfig files. I have mostly compile tested the changes on 
an ARMv7 system (COMPILE_TEST).

With best wishes,
Tobias


Tobias Jakobi (21):
  drm/arc: make fbdev support really optional
  drm/armada: make fbdev support really optional
  drm/omap: make fbdev support really optional
  drm/mgag200: make fbdev support really optional
  drm/cirrus: make fbdev support really optional
  drm/qxl: make fbdev support really optional
  drm/imx: make fbdev support really optional
  drm/shmobile: make fbdev support really optional
  drm/rockchip: make fbdev support really optional
  drm/gma500: make fbdev support really optional
  drm/rcar-du: make fbdev support really optional
  drm/tilcdc: make fbdev support really optional
  drm/fsl-dcu: make fbdev support really optional
  drm/bochs: make fbdev support really optional
  drm/vmwgfx: make fbdev support really optional
  drm/udl: make fbdev support really optional
  drm/atmel-hlcdc: make fbdev support really optional
  drm/virtio: make fbdev support really optional
  drm/ast: make fbdev support really optional
  drm/arm: make fbdev support really optional
  drm/nouveau: make fbdev support really optional

 drivers/gpu/drm/arc/Kconfig | 1 -
 drivers/gpu/drm/arm/Kconfig | 1 -
 drivers/gpu/drm/armada/Kconfig  | 4 
 drivers/gpu/drm/ast/Kconfig | 4 
 drivers/gpu/drm/atmel-hlcdc/Kconfig | 1 -
 drivers/gpu/drm/bochs/Kconfig   | 4 
 drivers/gpu/drm/cirrus/Kconfig  | 4 
 drivers/gpu/drm/fsl-dcu/Kconfig | 5 -
 drivers/gpu/drm/gma500/Kconfig  | 4 
 drivers/gpu/drm/imx/Kconfig | 1 -
 drivers/gpu/drm/mgag200/Kconfig | 4 
 drivers/gpu/drm/nouveau/Kconfig | 6 --
 drivers/gpu/drm/omapdrm/Kconfig | 5 -
 drivers/gpu/drm/qxl/Kconfig | 5 -
 drivers/gpu/drm/rcar-du/Kconfig | 1 -
 drivers/gpu/drm/rockchip/Kconfig| 4 
 drivers/gpu/drm/shmobile/Kconfig| 1 -
 drivers/gpu/drm/tilcdc/Kconfig  | 1 -
 drivers/gpu/drm/udl/Kconfig | 5 -
 drivers/gpu/drm/virtio/Kconfig  | 4 
 drivers/gpu/drm/vmwgfx/Kconfig  | 4 
 21 files changed, 69 deletions(-)

-- 
2.7.3

[PATCH 09/16] gpu: ipu-v3: Add ipu_ic_set_src()

[Philipp Zabel]

Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> Adds ipu_ic_set_src() which is just aa wrapper around
> ipu_set_ic_src_mux().
> 
> Signed-off-by: Steve Longerbeam 
> ---
>  drivers/gpu/ipu-v3/ipu-ic.c | 10 ++
>  include/video/imx-ipu-v3.h  |  1 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-ic.c b/drivers/gpu/ipu-v3/ipu-ic.c
> index 1dcb96c..f306a9c 100644
> --- a/drivers/gpu/ipu-v3/ipu-ic.c
> +++ b/drivers/gpu/ipu-v3/ipu-ic.c
> @@ -629,6 +629,16 @@ unlock:
>  }
>  EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init);
>  
> +int ipu_ic_set_src(struct ipu_ic *ic, int csi_id, bool vdi)
> +{
> + struct ipu_ic_priv *priv = ic->priv;
> +
> + ipu_set_ic_src_mux(priv->ipu, csi_id, vdi);

ipu_set_ic_src_mux(ic->priv->ipu, csi_id, vdi);
would be shorter.

regards
Philipp

[PATCH 04/16] gpu: ipu-v3: Add ipu_get_num()

[Philipp Zabel]

Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> Adds of-alias id to ipu_soc and retrieve with ipu_get_num().
> 
> Signed-off-by: Steve Longerbeam 

This looks good to me, the necessary DT aliases are already in mainline
since commit 41beef39cdc8 ("ARM: dts: imx6qdl: add IPU aliases").

regards
Philipp

[PATCH 07/16] gpu: ipu-v3: Add VDI input IDMAC channels

[Philipp Zabel]

Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> Adds the VDIC field input IDMAC channels. These channels
> transfer fields F(n-1), F(n), and F(N+1) from memory to
> the VDIC (channels 8, 9, 10 respectively).
> 
> Signed-off-by: Steve Longerbeam 
> ---
>  include/video/imx-ipu-v3.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
> index 586979e..2302fc5 100644
> --- a/include/video/imx-ipu-v3.h
> +++ b/include/video/imx-ipu-v3.h
> @@ -107,6 +107,9 @@ enum ipu_channel_irq {
>  #define IPUV3_CHANNEL_CSI22
>  #define IPUV3_CHANNEL_CSI33
>  #define IPUV3_CHANNEL_VDI_MEM_IC_VF   5
> +#define IPUV3_CHANNEL_MEM_VDI_P   8
> +#define IPUV3_CHANNEL_MEM_VDI 9
> +#define IPUV3_CHANNEL_MEM_VDI_N  10

I would prefer the names to be just a bit more descriptive:

#define IPUV3_CHANNEL_MEM_VDI_PREV   8
#define IPUV3_CHANNEL_MEM_VDI_CUR9
#define IPUV3_CHANNEL_MEM_VDI_NEXT  10

The reference manual states that the purposes of these channels are
"Previous field", "Current field", and "Next field" input to the VDIC,
respectively.

regards
Philipp

[PATCH 02/16] gpu: ipu-cpmem: Add ipu_cpmem_set_uv_offset()

[Philipp Zabel]

Am Mittwoch, den 13.07.2016, 15:54 -0700 schrieb Steve Longerbeam:
> Hi Philipp,
> 
> On 07/08/2016 10:34 AM, Philipp Zabel wrote:
> > Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
> >> Adds ipu_cpmem_set_uv_offset(), to set planar U/V offsets.
> >>
> >> Signed-off-by: Steve Longerbeam 
> >> ---
> >>  drivers/gpu/ipu-v3/ipu-cpmem.c | 7 +++
> >>  include/video/imx-ipu-v3.h | 1 +
> >>  2 files changed, 8 insertions(+)
> >>
> >> diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c 
> >> b/drivers/gpu/ipu-v3/ipu-cpmem.c
> >> index 6494a4d..a36c35e 100644
> >> --- a/drivers/gpu/ipu-v3/ipu-cpmem.c
> >> +++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
> >> @@ -253,6 +253,13 @@ void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, 
> >> int bufnum, dma_addr_t buf)
> >>  }
> >>  EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
> >>  
> >> +void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 
> >> v_off)
> >> +{
> >> +  ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
> >> +  ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
> >> +}
> >> +EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
> >> +
> > I'd prefer to avoid too much duplication in the API. Is there a reason
> > you can't use ipu_cpmem_set_yuv_planar_full?
> 
> I could, but it would be cumbersome. ipu_cpmem_set_uv_offset() is being
> called when kicking off a new tile conversion, and the stride length would
> have to be calculated all over again if I were to use 
> ipu_cpmem_set_yuv_planar_ful().
> When kicking off a new tile conversion, the stride doesn't change, only the
> tile's buffer address, and U/V offsets for planar, need to be updated.

Ok. We'll have to change tile width and height as well, but the stride
indeed is constant.

regards
Philipp

[PATCH 08/16] gpu: ipu-v3: Add ipu_csi_set_src()

[Steve Longerbeam]

On 07/15/2016 05:49 AM, Philipp Zabel wrote:
> Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
>
>> +{
>> +ipu_set_csi_src_mux(csi->ipu, csi->id, select_mipi_csi2);
>> +
>> +return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(ipu_csi_set_src);
>> +
> Couldn't you just replace ipu_set_csi_src_mux?

Yeah. I guess I created this as a matter of code convenience,
but not worth exporting another function. I will remove this patch
in next version.

Steve

[PATCH] drm/amdgpu: Disable RPM helpers while reprobing connectors on resume

[Alex Deucher]

On Fri, Jul 8, 2016 at 11:37 AM, Lyude  wrote:
> Just about all of amdgpu's connector probing functions try to acquire
> runtime PM refs. If we try to do this in the context of
> amdgpu_resume_kms by calling drm_helper_hpd_irq_event(), we end up
> deadlocking the system.
>
> Since we're guaranteed to be holding the spinlock for RPM in
> amdgpu_resume_kms, and we already know the GPU is in working order, we
> need to prevent the RPM helpers from trying to run during the initial
> connector reprobe on resume.
>
> There's a couple of solutions I've explored for fixing this, but this
> one by far seems to be the simplest and most reliable (plus I'm pretty
> sure that's what disable_depth is there for anyway).
>
> Reproduction recipe:
>   - Get any laptop dual GPUs using PRIME
>   - Make sure runtime PM is enabled for amdgpu
>   - Boot the machine
>   - If the machine managed to boot without hanging, switch out of X to
> another VT. This should definitely cause X to hang infinitely.
>
> Cc: stable at vger.kernel.org
> Signed-off-by: Lyude 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 6e92008..46c1fee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1841,7 +1841,19 @@ int amdgpu_resume_kms(struct drm_device *dev, bool 
> resume, bool fbcon)
> }
>
> drm_kms_helper_poll_enable(dev);
> +
> +   /*
> +* Most of the connector probing functions try to acquire runtime pm
> +* refs to ensure that the GPU is powered on when connector polling is
> +* performed. Since we're calling this from a runtime PM callback,
> +* trying to acquire rpm refs will cause us to deadlock.
> +*
> +* Since we're guaranteed to be holding the rpm lock, it's safe to
> +* temporarily disable the rpm helpers so this doesn't deadlock us.
> +*/
> +   dev->dev->power.disable_depth++;
> drm_helper_hpd_irq_event(dev);
> +   dev->dev->power.disable_depth--;
>
> if (fbcon) {
> amdgpu_fbdev_set_suspend(adev, 0);
> --
> 2.7.4
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH v4 2/2] drm/fsl-dcu: add support for drm bridge

[Meng Yi]

The current output code only supports connection to drm panels.
Add code to support drm bridge, to support connections to
external connectors.

Signed-off-by: Meng Yi 
---
Changes since V1:
-no change
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index ef34436..56f6991 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -180,17 +180,27 @@ err_cleanup:
 static int fsl_dcu_attach_endpoint(struct fsl_dcu_drm_device *fsl_dev,
const struct of_endpoint *ep)
 {
+   struct drm_bridge *bridge;
struct device_node *np;
int ret;

np = of_graph_get_remote_port_parent(ep->local_node);

fsl_dev->connector.panel = of_drm_find_panel(np);
-   of_node_put(np);
-   if (fsl_dev->connector.panel)
+   if (fsl_dev->connector.panel) {
+   of_node_put(np);
return fsl_dcu_attach_panel(fsl_dev, fsl_dev->connector.panel);
+   }
+
+   bridge = of_drm_find_bridge(np);
+   of_node_put(np);
+   if (!bridge)
+   return -ENODEV;
+
+   fsl_dev->encoder.bridge = bridge;
+   bridge->encoder = _dev->encoder;

-   return -ENODEV;
+   return drm_bridge_attach(fsl_dev->drm, bridge);
 }

 int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev)
-- 
2.1.0.27.g96db324

[PATCH v4 1/2] drm/fsl-dcu: rework codes to support of_graph dt binding for panel

[Meng Yi]

This patch rework the output code to add of_graph dt binding support
for panel device and also keeps the backward compatibility

Signed-off-by: Meng Yi 
---
Changes in V4:
-simplify return value statements
-merge corresponding documentation to this patch
Changes in V3:
-simplify return value statements
Changes in V2:
-fix some coding style issue
-add fsl_dev->connector.panel check
-use fsl_dev->np and drop fsl_dev->dev->of_node
-return 'ret' when fsl_dcu_attach_panel failed
---
 .../devicetree/bindings/display/fsl,dcu.txt|  9 ++-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c  |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h   |  3 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c  | 69 +++---
 4 files changed, 58 insertions(+), 25 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt 
b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index ae55cde..63ec2a6 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -12,7 +12,7 @@ Required properties:
 - clock-names: Should be "dcu" and "pix"
See ../clocks/clock-bindings.txt for details.
 - big-endian   Boolean property, LS1021A DCU registers are big-endian.
-- fsl,panel:   The phandle to panel node.
+- port Video port for the panel output

 Optional properties:
 - fsl,tcon:The phandle to the timing controller node.
@@ -24,6 +24,11 @@ dcu: dcu at 2ce {
clocks = <_clk 0>, <_clk 0>;
clock-names = "dcu", "pix";
big-endian;
-   fsl,panel = <>;
fsl,tcon = <>;
+
+   port {
+   dcu_out: endpoint {
+   remote-endpoint = <_out>;
+};
+   };
 };
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
index a6e4cd5..d9d6cc1 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
@@ -43,7 +43,7 @@ int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device 
*fsl_dev)
if (ret)
goto err;

-   ret = fsl_dcu_drm_connector_create(fsl_dev, _dev->encoder);
+   ret = fsl_dcu_create_outputs(fsl_dev);
if (ret)
goto err;

diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
index 7093109..5a7b88e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h
@@ -25,9 +25,8 @@ to_fsl_dcu_connector(struct drm_connector *con)
 : NULL;
 }

-int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
-struct drm_encoder *encoder);
 int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
   struct drm_crtc *crtc);
+int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev);

 #endif /* __FSL_DCU_DRM_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index 0b0989e..ef34436 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -10,6 +10,7 @@
  */

 #include 
+#include 

 #include 
 #include 
@@ -132,12 +133,12 @@ static const struct drm_connector_helper_funcs 
connector_helper_funcs = {
.mode_valid = fsl_dcu_drm_connector_mode_valid,
 };

-int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device *fsl_dev,
-struct drm_encoder *encoder)
+static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
+struct drm_panel *panel)
 {
+   struct drm_encoder *encoder = _dev->encoder;
struct drm_connector *connector = _dev->connector.base;
struct drm_mode_config *mode_config = _dev->drm->mode_config;
-   struct device_node *panel_node;
int ret;

fsl_dev->connector.encoder = encoder;
@@ -161,21 +162,7 @@ int fsl_dcu_drm_connector_create(struct fsl_dcu_drm_device 
*fsl_dev,
  mode_config->dpms_property,
  DRM_MODE_DPMS_OFF);

-   panel_node = of_parse_phandle(fsl_dev->np, "fsl,panel", 0);
-   if (!panel_node) {
-   dev_err(fsl_dev->dev, "fsl,panel property not found\n");
-   ret = -ENODEV;
-   goto err_sysfs;
-   }
-
-   fsl_dev->connector.panel = of_drm_find_panel(panel_node);
-   if (!fsl_dev->connector.panel) {
-   ret = -EPROBE_DEFER;
-   goto err_panel;
-   }
-   of_node_put(panel_node);
-
-   ret = drm_panel_attach(fsl_dev->connector.panel, connector);
+   ret = drm_panel_attach(panel, connector);
if (ret) {
dev_err(fsl_dev->dev, "failed to attach panel\n");
goto err_sysfs;
@@ -183,11 +170,53 @@ int 

[PATCH 07/16] gpu: ipu-v3: Add VDI input IDMAC channels

[Steve Longerbeam]

On 07/15/2016 05:45 AM, Philipp Zabel wrote:
> Am Donnerstag, den 07.07.2016, 16:03 -0700 schrieb Steve Longerbeam:
>> Adds the VDIC field input IDMAC channels. These channels
>> transfer fields F(n-1), F(n), and F(N+1) from memory to
>> the VDIC (channels 8, 9, 10 respectively).
>>
>> Signed-off-by: Steve Longerbeam 
>> ---
>>   include/video/imx-ipu-v3.h | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
>> index 586979e..2302fc5 100644
>> --- a/include/video/imx-ipu-v3.h
>> +++ b/include/video/imx-ipu-v3.h
>> @@ -107,6 +107,9 @@ enum ipu_channel_irq {
>>   #define IPUV3_CHANNEL_CSI2  2
>>   #define IPUV3_CHANNEL_CSI3  3
>>   #define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
>> +#define IPUV3_CHANNEL_MEM_VDI_P  8
>> +#define IPUV3_CHANNEL_MEM_VDI9
>> +#define IPUV3_CHANNEL_MEM_VDI_N 10
> I would prefer the names to be just a bit more descriptive:
>
> #define IPUV3_CHANNEL_MEM_VDI_PREV 8
> #define IPUV3_CHANNEL_MEM_VDI_CUR  9
> #define IPUV3_CHANNEL_MEM_VDI_NEXT10
>
> The reference manual states that the purposes of these channels are
> "Previous field", "Current field", and "Next field" input to the VDIC,
> respectively.

right. Ok I will make that change in next version.

Steve