[Bug 101294] radeonsi minecraft forge splash freeze since 17.1

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101294

Bug ID: 101294
   Summary: radeonsi minecraft forge splash freeze since 17.1
   Product: Mesa
   Version: 17.1
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel@lists.freedesktop.org
  Reporter: tobi291...@gmail.com
QA Contact: dri-devel@lists.freedesktop.org

Launching Minecraft with Forge installed (vanilla is fine, only happens with
the splash screen enabled) often causes a glSwapBuffers to never return and
spin on a single cpu core.

The freeze seems to always occur right after the texture atlas was created (can
be seen in log) and similarly on the same step on the splash itself, so it is
possible that this is some interaction between the splash rendering and loading
resources.

The rest of the system continues to run fine and running SIGKILL is enough to
stop the process (Other OpenGL-based applications continue function as
expected).

Running on Arch Linux, with Mesa 17.1.0, OpenJDK 8.u121-1 with an AMD Radeon
RX480 (8 GB) and a custom compiled Linux 4.11.3 kernel (Based linux-zen package
with ACS override).

This has happened on older kernel versions as well and the exact Minecraft and
Forge versions do not seem to matter (beside that it is at least Minecraft 1.7,
which is when that splash screen got added).

I have also observed a very similar freeze (spinning on single core, no
system-wide effects) with QupZilla (Qt 5.8, WebEngine), however this is very
rare and I could not get any specific info on it. No other programs seem
affected.

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Re: [PATCH v2 1/2] drm/bridge: Add Cadence DSI driver

[Archit Taneja]

On 6/2/2017 5:34 PM, Boris Brezillon wrote:

Add a driver for Cadence DPI -> DSI bridge.

Signed-off-by: Boris Brezillon 
---
Changes in v2:
- rebase on v4.12-rc1 and adapt to driver to the drm_bridge API changes
- return the correct error when devm_clk_get(sysclk) fails
- add missing depends on OF and select DRM_PANEL in the Kconfig entry
---
  drivers/gpu/drm/bridge/Kconfig|9 +
  drivers/gpu/drm/bridge/Makefile   |1 +
  drivers/gpu/drm/bridge/cdns-dsi.c | 1077 +
  3 files changed, 1087 insertions(+)
  create mode 100644 drivers/gpu/drm/bridge/cdns-dsi.c

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index f6968d3b4b41..7d24b0e11634 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -17,6 +17,15 @@ config DRM_ANALOGIX_ANX78XX
  the HDMI output of an application processor to MyDP
  or DisplayPort.
  
+config DRM_CDNS_DSI

+   tristate "Cadence DPI/DSI bridge"
+   select DRM_KMS_HELPER
+   select DRM_MIPI_DSI
+   select DRM_PANEL
+   depends on OF
+   help
+ Support Cadence DPI to DSI bridge.
+
  config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 3fe2226ee2f2..73a3e32a8005 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,6 +1,7 @@
  ccflags-y := -Iinclude/drm
  
  obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o

+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
  obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o
  obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o
  obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += 
megachips-stdp-ge-b850v3-fw.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c 
b/drivers/gpu/drm/bridge/cdns-dsi.c
new file mode 100644
index ..70a4b91c80ee
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-dsi.c
@@ -0,0 +1,1077 @@
+/*
+ * Copyright: 2017 Cadence Design Systems, Inc.
+ *
+ * Author: Boris Brezillon 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define MCTL_MAIN_DATA_CTL 0x4
+#define DIS_DYN_CLK_CTLBIT(30)
+#define IF_INTERLACED_EN(x)BIT(26 + (x))
+#define TE_MIPI_POLLING_EN BIT(25)
+#define TE_HW_POLLING_EN   BIT(24)
+#define DISP_EOT_GEN   BIT(18)
+#define HOST_EOT_GEN   BIT(17)
+#define DISP_GEN_CHECKSUM  BIT(16)
+#define DISP_GEN_ECC   BIT(15)
+#define BTA_EN BIT(14)
+#define READ_ENBIT(13)
+#define REG_TE_EN  BIT(12)
+#define IF_TE_EN(x)BIT(8 + (x))
+#define TBG_SELBIT(7)
+#define TVG_SELBIT(6)
+#define VID_EN BIT(5)
+#define IF_VID_SELECT(x)   ((x) << 2)
+#define IF_VID_SELECT_MASK GENMASK(4, 2)
+#define IF_VID_MODEBIT(1)
+#define LINK_ENBIT(0)
+
+#define MCTL_MAIN_PHY_CTL  0x8
+#define CLK_FORCE_STOP BIT(14)
+#define WAIT_BURST_TIME(x) ((x) << 10)
+#define DATA_ULPM_EN(x)BIT(6 + (x))
+#define CLK_ULPM_ENBIT(5)
+#define CLK_CONTINUOUS BIT(4)
+#define DATA_FORCE_STOPBIT(3)
+#define DATA_LANE_EN(x)BIT((x) - 1)
+
+#define MCTL_LANE_STS  0x10
+#define LANE_STATE_START   0
+#define LANE_STATE_IDLE1
+#define LANE_STATE_WRITE   2
+#define LANE_STATE_ULPM3
+#define LANE_STATE_READ4
+#define DATA_LANE_STATE(l, val)\
+   (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
+#define CLK_LANE_STATE_HS  2
+#define CLK_LANE_STATE(val)((val) & GENMASK(1, 0))
+
+#define MCTL_DPHY_TIMEOUT1 0x14
+#define CLK_DIV(x) (x)
+#define HSTX_TIMEOUT(x)((x) << 4)
+
+#define MCTL_DPHY_TIMEOUT2 0x18
+#define LPRX_TIMEOUT(x)  

Re: [PATCH v2 2/2] dt-bindings: drm/bridge: Document Cadence DSI bridge bindings

[Archit Taneja]

Hi,

On 06/02/2017 05:34 PM, Boris Brezillon wrote:

Document the bindings used for the Cadence DSI bridge.

Signed-off-by: Boris Brezillon 
---
 .../bindings/display/bridge/cdns,dsi.txt   | 55 ++
 1 file changed, 55 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt

diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
new file mode 100644
index ..770c5c5b1e93
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
@@ -0,0 +1,55 @@
+Cadence DSI bridge
+==
+
+The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.


Is this a separate chip, or an IP integrated into SoCs? If it's the 
latter, I don't think DPI on the its input side is the right term to 
use. Maybe RGB would be more appropriate here.



+
+Required properties:
+- compatible: should be set to "cdns,dsi".


Would it be better to take a dw-hdmi like approach here? I.e, the
binding should be specific to the SoC that integrates this DSI
bridge?


+- reg: physical base address and length of the controller's registers.
+- interrupts: interrupt line connected to the DSI bridge.
+- clocks: DSI bridge clocks.
+- clock-names: must contain "pclk" and "sysclk".
+- phys: phandle link to the MIPI D-PHY controller.
+- phy-names: must contain "dphy".
+- #address-cells: must be set to 1.
+- #size-cells: must be set to 0.
+
+Required subnodes:
+- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
+  Currently contains a single input port at address 0 representing the DPI
+  input. Other ports will be added later to support the SDI inputs.
+  Port 0 should be connected to a DPI encoder output.


The output of the DSI bridge may be another bridge, which could be i2c
controlled. In that case, it won't be a child of the DSI bridge. For
such scenarios, we might want to define an output port for the bridge.

Thanks,
Archit


+- one subnode per DSI device connected on the DSI bus. Each DSI device should
+  contain a reg property encoding its address on the bus.
+
+Example:
+
+   dsi0: dsi@fd0c {
+   compatible = "cdns,dsi";
+   reg = <0x0 0xfd0c 0x0 0x1000>;
+   clocks = <&pclk>, <&sysclk>;
+   clock-names = "pclk", "hclk";
+   interrupts = <1>;
+   phys = <&dphy1>;
+   phy-names = "dphy";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi0_dpi_input: endpoint {
+   remote-endpoint = <&xxx_dpi_output>;
+   };
+   };
+   };
+
+   panel: dsi-dev@0 {
+   compatible = "";
+   reg = <0>;
+   };
+   };
+



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[Bug 101290] Radeon R9 390X regression - No output (CVT) or corruption (CVT-R) at 4096x2160@60Hz over DisplayPort

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101290

Bug ID: 101290
   Summary: Radeon R9 390X regression - No output (CVT) or
corruption (CVT-R) at 4096x2160@60Hz over DisplayPort
   Product: DRI
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: major
  Priority: medium
 Component: DRM/Radeon
  Assignee: dri-devel@lists.freedesktop.org
  Reporter: freedesk...@nuclearsunshine.com

I had thought I had filed this bug a long time ago on here, but I can't find
it...

Graphics card: Radeon R9 390X (Saphhire 11241-04-20G)
Display: LG 31MU97 (via DisplayPort)

With Linux 4.4.x, 4096 x 2160 @ 60 Hz progressive output was working with
standard CVT timing.

With Linux 4.5.x onwards, standard CVT timing at that resolution fails (no
signal) with the following dmesg output:

kernel: [drm:radeon_dp_link_train [radeon]] *ERROR* channel eq failed
kernel: [drm:radeon_dp_link_train [radeon]] *ERROR* channel eq failed: 5 tries

CVT-R timing results in output, but with a flickering/corrupted full-height
band down the right hand side (it approximates the intended output, but pixels
seem be to be corrupt in single-pixel horizontal bands and/or flicker in
horizontal single-pixel bands) It could be complete coincidence, but the width
of the corrupt band seems to be the difference in width vs. 3840x2160, i.e.
aobut 256 pixels. With this timing there are no messages in dmesg.

There's a downstream Fedora bug report here:
https://bugzilla.redhat.com/show_bug.cgi?id=1353341

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[Bug 98145] X modesetting problem on dell laptop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98145

--- Comment #7 from Klaus Kusche  ---
(In reply to Henri Kemppainen from comment #5)
> Created attachment 131597 [details] [review]
> disable gtf modes

Patch works perfectly:

* The beamers are now auto-configuring the correct mode on startup,
without any manual intervention.

* When setting mode 1024x768 manually, it works almost immediately
and chooses the correct frequency.

* xrandr --verbose only shows modes the hardware is actually able to sync to.

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Re: [PATCH v3 1/6] drm/stm: ltdc: Add panel-bridge support

[kbuild test robot]

Hi Philippe,

[auto build test ERROR on drm/drm-next]
[also build test ERROR on next-20170602]
[cannot apply to v4.12-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Philippe-CORNU/STM32-DSI-HOST/20170603-231124
base:   git://people.freedesktop.org/~airlied/linux.git drm-next
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/stm/ltdc.c: In function 'ltdc_load':
>> drivers/gpu/drm/stm/ltdc.c:953:12: error: implicit declaration of function 
>> 'drm_panel_bridge_add' [-Werror=implicit-function-declaration]
  bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
   ^~~~
>> drivers/gpu/drm/stm/ltdc.c:953:10: warning: assignment makes pointer from 
>> integer without a cast [-Wint-conversion]
  bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DPI);
 ^
>> drivers/gpu/drm/stm/ltdc.c:993:2: error: implicit declaration of function 
>> 'drm_panel_bridge_remove' [-Werror=implicit-function-declaration]
 drm_panel_bridge_remove(bridge);
 ^~~
   cc1: some warnings being treated as errors

vim +/drm_panel_bridge_add +953 drivers/gpu/drm/stm/ltdc.c

   947  return ret;
   948  }
   949  
   950  DRM_INFO("ltdc hw version 0x%08x - ready\n", 
ldev->caps.hw_version);
   951  
   952  if (panel) {
 > 953  bridge = drm_panel_bridge_add(panel, 
 > DRM_MODE_CONNECTOR_DPI);
   954  if (IS_ERR(bridge)) {
   955  DRM_ERROR("Failed to create panel-bridge\n");
   956  return PTR_ERR(bridge);
   957  }
   958  }
   959  
   960  ldev->bridge = bridge;
   961  
   962  ret = ltdc_encoder_init(ddev);
   963  if (ret) {
   964  DRM_ERROR("Failed to init encoder\n");
   965  goto err;
   966  }
   967  
   968  crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
   969  if (!crtc) {
   970  DRM_ERROR("Failed to allocate crtc\n");
   971  ret = -ENOMEM;
   972  goto err;
   973  }
   974  
   975  ret = ltdc_crtc_init(ddev, crtc);
   976  if (ret) {
   977  DRM_ERROR("Failed to init crtc\n");
   978  goto err;
   979  }
   980  
   981  ret = drm_vblank_init(ddev, NB_CRTC);
   982  if (ret) {
   983  DRM_ERROR("Failed calling drm_vblank_init()\n");
   984  goto err;
   985  }
   986  
   987  /* Allow usage of vblank without having to call drm_irq_install 
*/
   988  ddev->irq_enabled = 1;
   989  
   990  return 0;
   991  
   992  err:
 > 993  drm_panel_bridge_remove(bridge);
   994  
   995  clk_disable_unprepare(ldev->pixel_clk);
   996  

---
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https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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[PATCH v3 5/6] dt-bindings: display: stm32: Add DSI host driver

[Philippe CORNU]

This patch adds documentation of device tree bindings for the STM32
DSI host driver based on the Synopsys DW MIPI DSI bridge driver.
---
 .../devicetree/bindings/display/st,stm32-ltdc.txt  | 83 +-
 1 file changed, 82 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt 
b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 90a8459..4cd32bd 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -12,8 +12,39 @@
   Required nodes:
 - Video port for RGB output.
 
-Example:
+* STMicroelectronics STM32 dsi specific extensions to Synopsys DesignWare MIPI
+  DSI host controller
 
+The STMicroelectronics STM32 dsi driver uses the Synopsys DesignWare MIPI
+DSI host controller driver (related documentation in [5]).
+
+Required properties:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "st,stm32-dsi".
+- reg: Memory mapped base address and length of the DWC MIPI DSI registers.
+- clocks: References to all the clocks specified in the clock-names property
+  as specified in [1].
+- clock-names:
+  - peripheral clock string name, must be "pclk".
+  - phy pll reference clock string name, must be "ref".
+- resets: References to all the resets specified in the reset-names property
+  as specified in [2].
+- reset-names: string reset name, must be "apb".
+
+Required nodes:
+- dsi input port node: connected to the ltdc rgb output port, see [3] & [4].
+- panel or bridge node: see [6].
+
+Note: You can find more documentation
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/graph.txt
+[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+Example 1: RGB panel
 / {
...
soc {
@@ -33,3 +64,53 @@ Example:
};
};
 };
+
+Example 2: DSI panel
+
+/ {
+   ...
+   soc {
+   ...
+   ltdc: display-controller@40016800 {
+   compatible = "st,stm32-ltdc";
+   reg = <0x40016800 0x200>;
+   interrupts = <88>, <89>;
+   resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+   clocks = <&rcc 1 CLK_LCD>;
+   clock-names = "lcd";
+
+   port {
+   ltdc_out_dsi: endpoint {
+   remote-endpoint = <&dsi_in>;
+   };
+   };
+   };
+
+
+   dsi: dsi@40016c00 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "st,stm32-dsi";
+   reg = <0x40016c00 0x800>;
+   clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+   clock-names = "ref", "pclk";
+   resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+   reset-names = "apb";
+
+   port {
+   dsi_in: endpoint {
+   remote-endpoint = <;
+   };
+   };
+
+   panel-dsi@0 {
+   reg = <0>; /* dsi virtual channel (0..3) */
+   compatible = ...;
+   enable-gpios = ...;
+
+   };
+
+   };
+
+   };
+};
-- 
1.9.1

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[PATCH v11 3/3] drm/i915: Add option to support dynamic backlight via DPCD

[Puthikorn Voravootivat]

This patch adds option to enable dynamic backlight for eDP
panel that supports this feature via DPCD register and
set minimum / maximum brightness to 0% and 100% of the
normal brightness.

Change-Id: I52f04b814bb4cd9df570ab59094ae974b9baec5b
Signed-off-by: Puthikorn Voravootivat 
---
 drivers/gpu/drm/i915/i915_params.c|  5 +
 drivers/gpu/drm/i915/i915_params.h|  3 ++-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 26 ++
 3 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 3758ae1f11b4..d84042ddf1fc 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -65,6 +65,7 @@ struct i915_params i915 __read_mostly = {
.inject_load_failure = 0,
.enable_dpcd_backlight = -1,
.enable_gvt = false,
+   .enable_dbc = true,
 };
 
 module_param_named(modeset, i915.modeset, int, 0400);
@@ -254,3 +255,7 @@ MODULE_PARM_DESC(enable_dpcd_backlight,
 module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
 MODULE_PARM_DESC(enable_gvt,
"Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
+
+module_param_named_unsafe(enable_dbc, i915.enable_dbc, bool, 0600);
+MODULE_PARM_DESC(enable_dbc,
+   "Enable support for dynamic backlight control (default:true)");
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 643dfaf41c1f..99f68d853c18 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -67,7 +67,8 @@
func(bool, verbose_state_checks); \
func(bool, nuclear_pageflip); \
func(bool, enable_dp_mst); \
-   func(bool, enable_gvt)
+   func(bool, enable_gvt); \
+   func(bool, enable_dbc)
 
 #define MEMBER(T, member) T member
 struct i915_params {
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index b73b3d431a82..b2f4cc975a3e 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -172,6 +172,24 @@ static bool intel_dp_aux_set_pwm_freq(struct 
intel_connector *connector)
return true;
 }
 
+/*
+* Set minimum / maximum dynamic brightness percentage. This value is expressed
+* as the percentage of normal brightness in 5% increments.
+*/
+static bool
+intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp,
+  u32 min, u32 max)
+{
+   u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5) };
+
+   if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET,
+ dbc, sizeof(dbc)) < 0) {
+   DRM_DEBUG_KMS("Failed to write aux DBC brightness level\n");
+   return false;
+   }
+   return true;
+}
+
 static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
@@ -205,6 +223,14 @@ static void intel_dp_aux_enable_backlight(struct 
intel_connector *connector)
if (intel_dp_aux_set_pwm_freq(connector))
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
 
+   if (i915.enable_dbc &&
+   (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) {
+   if(intel_dp_aux_set_dynamic_backlight_percent(intel_dp, 0, 
100)) {
+   new_dpcd_buf |= DP_EDP_DYNAMIC_BACKLIGHT_ENABLE;
+   DRM_DEBUG_KMS("Enable dynamic brightness.\n");
+   }
+   }
+
if (new_dpcd_buf != dpcd_buf) {
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
-- 
2.13.0.506.g27d5fe0cd-goog

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exynos drm build failure due to cec_* symbols

[Andreas Färber]

Hello,

We're observing the following build failure with v4.12-rc3, latest
linux.git and linux-next.git:

[ 9825s]   LD  vmlinux.o
[ 9904s]   MODPOST vmlinux.o
[ 9915s] drivers/built-in.o: In function `hdmi_get_modes':
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:866:
undefined reference to `cec_notifier_set_phys_addr_from_edid'
[ 9915s] drivers/built-in.o: In function `hdmi_remove':
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:1923:
undefined reference to `cec_notifier_set_phys_addr'
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:1927:
undefined reference to `cec_notifier_put'
[ 9915s] drivers/built-in.o: In function `hdmi_probe':
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:1889:
undefined reference to `cec_notifier_get'
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:1904:
undefined reference to `cec_notifier_put'
[ 9915s] drivers/built-in.o: In function `hdmi_disable':
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:1509:
undefined reference to `cec_notifier_set_phys_addr'
[ 9915s] drivers/built-in.o: In function `hdmi_detect':
[ 9915s]
/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/linux-obj/../drivers/gpu/drm/exynos/exynos_hdmi.c:827:
undefined reference to `cec_notifier_set_phys_addr'
[ 9931s] make[2]: ***
[/home/abuild/rpmbuild/BUILD/kernel-vanilla-4.12.rc3.51.ga374846/linux-4.12-rc3-51-ga374846/Makefile:997:
vmlinux] Error 1
[ 9931s] make[1]: *** [Makefile:152: sub-make] Error 2
[ 9931s] make: *** [Makefile:24: __sub-make] Error 2

My guess is the symbols used by the exynos drm module are not exported:

cec_notifier_set_phys_addr_from_edid
cec_notifier_set_phys_addr
cec_notifier_put
cec_notifier_get

Can you please look into fixing this?

Configs for reproducing are available here:

v4.12-rc3:
http://kernel.opensuse.org/cgit/kernel-source/tree/config/armv7hl/default
http://kernel.opensuse.org/cgit/kernel-source/tree/config/armv7hl/lpae

linux.git:
http://kernel.opensuse.org/cgit/kernel-source/tree/config/armv7hl/vanilla?h=vanilla

linux-next.git:
http://kernel.opensuse.org/cgit/kernel-source/tree/config/armv7hl/vanilla?h=linux-next

Thanks,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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Re: [RFC 0/1] drm: Add Grain Media GM12U320 kms driver

[Marco Diego Aurélio Mesquita]

Hi Emil!

On Fri, Jun 2, 2017 at 1:14 PM, Emil Velikov  wrote:
> As Daniel mentioned in the earlier thread, factoring out things can be
> done as a follow-up.
> On the other hand, I _think_ that the blocker for this driver that
> it's not doing atomic mode setting.
>

I've been looking on other small drivers to see how complicated would
it be to use the simple pipe framework. Both mxsfb and tinydrm do
atomic mode setting. It looks like some changes would be needed like
using the cma allocator and calling other specific functions tu do
atomic mode setting.

Can you point to a simple patch that implements one of these "conversions"?
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Re: [PATCH 10/19] drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision

[Chen-Yu Tsai]

On Sat, Jun 3, 2017 at 3:30 AM, Maxime Ripard
 wrote:
> On Fri, Jun 02, 2017 at 06:10:15PM +0800, Chen-Yu Tsai wrote:
>> The DDC parent clock on the A31 SoC is also conveniently named
>> "hdmi-ddc", which results in a name collision when the hdmi driver
>> registers its internal DDC divider clock.
>>
>> Rename the internal clock to "hdmi-ddc-divider".
>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
>> b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
>> index e1071838f487..9a6b6243e977 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
>> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
>> @@ -125,7 +125,7 @@ static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, 
>> struct clk *parent,
>>   if (!ddc)
>>   return -ENOMEM;
>>
>> - init.name = "hdmi-ddc";
>> + init.name = "hdmi-ddc-divider";
>
> Can't we rename the CCU clock instead? Having the clock called
> hdmi-ddc being the actual clock output on the DDC bus feels more
> natural.

Do you have any suggestions? The manual labels the conflicting one
in the CCU as "HDMI_DDC"...

ChenYu
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Re: [Intel-gfx] [PATCH v10 2/3] drm/i915: Add option to support dynamic backlight via DPCD

[Pandiyan, Dhinakaran]

On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> This patch adds option to enable dynamic backlight for eDP
> panel that supports this feature via DPCD register and
> set minimum / maximum brightness to 0% and 100% of the
> normal brightness.
> 
> Signed-off-by: Puthikorn Voravootivat 
> ---
>  drivers/gpu/drm/i915/i915_params.c|  5 
>  drivers/gpu/drm/i915/i915_params.h|  3 +-
>  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 42 
> ++-
>  3 files changed, 41 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_params.c 
> b/drivers/gpu/drm/i915/i915_params.c
> index 3758ae1f11b4..ce033d58134e 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -65,6 +65,7 @@ struct i915_params i915 __read_mostly = {
>   .inject_load_failure = 0,
>   .enable_dpcd_backlight = -1,
>   .enable_gvt = false,
> + .enable_dbc = false,
>  };
>  
>  module_param_named(modeset, i915.modeset, int, 0400);
> @@ -254,3 +255,7 @@ MODULE_PARM_DESC(enable_dpcd_backlight,
>  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
>  MODULE_PARM_DESC(enable_gvt,
>   "Enable support for Intel GVT-g graphics virtualization host 
> support(default:false)");
> +
> +module_param_named_unsafe(enable_dbc, i915.enable_dbc, bool, 0600);
> +MODULE_PARM_DESC(enable_dbc,
> + "Enable support for dynamic backlight control (default:false)");
> diff --git a/drivers/gpu/drm/i915/i915_params.h 
> b/drivers/gpu/drm/i915/i915_params.h
> index ac02efce6e22..2de3e2850b54 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -67,7 +67,8 @@
>   func(bool, nuclear_pageflip); \
>   func(bool, enable_dp_mst); \
>   func(int, enable_dpcd_backlight); \
> - func(bool, enable_gvt)
> + func(bool, enable_gvt); \
> + func(bool, enable_dbc)
>  
>  #define MEMBER(T, member) T member
>  struct i915_params {
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index c89aae804659..f55af41ce3bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -100,11 +100,26 @@ intel_dp_aux_set_backlight(struct intel_connector 
> *connector, u32 level)
>   }
>  }
>  
> +/*
> + * Set minimum / maximum dynamic brightness percentage. This value is 
> expressed
> + * as the percentage of normal brightness in 5% increments.
> + */
> +static void
> +intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp,
> +u32 min, u32 max)
> +{
> + u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5) };
> +
> + if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET,
> +   dbc, sizeof(dbc)) < 0) {
> + DRM_DEBUG_KMS("Failed to write aux DBC brightness level\n");
> + }
> +}
> +
>  static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
>  {
>   struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
> - uint8_t dpcd_buf = 0;
> - uint8_t edp_backlight_mode = 0;
> + uint8_t dpcd_buf, new_dpcd_buf, edp_backlight_mode;
>  
>   if (drm_dp_dpcd_readb(&intel_dp->aux,
>   DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
> @@ -113,18 +128,15 @@ static void intel_dp_aux_enable_backlight(struct 
> intel_connector *connector)
>   return;
>   }
>  
> + new_dpcd_buf = dpcd_buf;
>   edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
>  
>   switch (edp_backlight_mode) {
>   case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
>   case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
>   case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
> - dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> - dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf) < 0) {
> - DRM_DEBUG_KMS("Failed to write aux backlight mode\n");
> - }
> + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
>   break;
>  
>   /* Do nothing when it is already DPCD mode */
> @@ -133,6 +145,20 @@ static void intel_dp_aux_enable_backlight(struct 
> intel_connector *connector)
>   break;
>   }
>  
> + if (i915.enable_dbc &&
> + (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) {
> + new_dpcd_buf |= DP_EDP_DYNAMIC_BACKLIGHT_ENABLE;
> + intel_dp_aux_set_dynamic_backlight_percent(intel_dp, 0, 100);
> + DRM_DEBUG_KMS("Enable dynamic brightness.\n");
> + }
> +


Just curious, does DBC require DP AUX brightness control? 


-DK

> + if (new_dpc

Re: [Intel-gfx] [PATCH v10 1/3] drm/i915: Add heuristic to determine better way to adjust brightness

[Pandiyan, Dhinakaran]

On Fri, 2017-06-02 at 17:42 +, Pandiyan, Dhinakaran wrote:

Somehow the CC's got removed in my previous reply, adding them back. See
one additional comment below.


> On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > Add heuristic to decide that AUX or PWM pin should use for
> > backlight brightness adjustment and modify i915 param description
> > to have auto, force disable, and force enable.
> > 
> > The heuristic to determine that using AUX pin is better than using
> > PWM pin is that the panel support any of the feature list here.
> > - Regional backlight brightness adjustment
> > - Backlight PWM frequency set
> > - More than 8 bits resolution of brightness level
> > - Backlight enablement via AUX and not by BL_ENABLE pin
> > 
> > Signed-off-by: Puthikorn Voravootivat 
> > ---
> >  drivers/gpu/drm/i915/i915_params.c|  7 +--
> >  drivers/gpu/drm/i915/i915_params.h|  2 +-
> >  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 64 
> > +--
> >  3 files changed, 66 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_params.c 
> > b/drivers/gpu/drm/i915/i915_params.c
> > index b6a7e363d076..3758ae1f11b4 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -63,7 +63,7 @@ struct i915_params i915 __read_mostly = {
> > .huc_firmware_path = NULL,
> > .enable_dp_mst = true,
> > .inject_load_failure = 0,
> > -   .enable_dpcd_backlight = false,
> > +   .enable_dpcd_backlight = -1,
> > .enable_gvt = false,
> >  };
> >  
> > @@ -246,9 +246,10 @@ MODULE_PARM_DESC(enable_dp_mst,
> >  module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, 
> > uint, 0400);
> >  MODULE_PARM_DESC(inject_load_failure,
> > "Force an error after a number of failure check points (0:disabled 
> > (default), N:force failure at the Nth failure check point)");
> > -module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, 
> > bool, 0600);
> > +module_param_named_unsafe(enable_dpcd_backlight, 
> > i915.enable_dpcd_backlight, int, 0600);
> >  MODULE_PARM_DESC(enable_dpcd_backlight,
> > -   "Enable support for DPCD backlight control (default:false)");
> > +   "Enable support for DPCD backlight control "
> > +   "(-1:auto (default), 0:force disable, 1:force enabled if supported");
> >  
> >  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
> >  MODULE_PARM_DESC(enable_gvt,
> > diff --git a/drivers/gpu/drm/i915/i915_params.h 
> > b/drivers/gpu/drm/i915/i915_params.h
> > index 34148cc8637c..ac02efce6e22 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -66,7 +66,7 @@
> > func(bool, verbose_state_checks); \
> > func(bool, nuclear_pageflip); \
> > func(bool, enable_dp_mst); \
> > -   func(bool, enable_dpcd_backlight); \
> > +   func(int, enable_dpcd_backlight); \


Please move this above the bools, see comment in code that's a few lines
above.

-DK

> > func(bool, enable_gvt)
> >  
> >  #define MEMBER(T, member) T member
> > diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
> > b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > index a0995c00fc84..c89aae804659 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > @@ -43,6 +43,9 @@ static void set_aux_backlight_enable(struct intel_dp 
> > *intel_dp, bool enable)
> > else
> > reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> >  
> > +   /* TODO: If the panel also support enabling backlight via BL_ENABLE pin,
> > +* the backlight will be enabled again in _intel_edp_backlight_on()
> > +*/
> 
> Unrelated hunk, please remove. This should have been included in one of
> the previous patches.
> 
> > if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
> >reg_val) != 1) {
> > DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> > @@ -168,15 +171,66 @@ intel_dp_aux_display_control_capable(struct 
> > intel_connector *connector)
> > /* Check the  eDP Display control capabilities registers to determine if
> >  * the panel can support backlight control over the aux channel
> >  */
> > -   if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> > -   (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
> > -   !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) 
> > {
> > +   if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
> > +   (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
> > DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
> > return true;
> > }
> > return false;
> >  }
> >  
> > +/*
> > + * Heuristic function whether we should use AUX for backlight adjustment 
> > or not.
> > + *
> > + * We should use AUX for backlight brightness adjustment i

[PATCH v3 6/6] drm/stm: Add STM32 DSI host driver

[Philippe CORNU]

Add the STM32 DSI host driver that uses the Synopsys DesignWare
MIPI DSI DRM bridge.

Signed-off-by: Philippe CORNU 
---
 drivers/gpu/drm/stm/Kconfig   |   8 +
 drivers/gpu/drm/stm/Makefile  |   2 +
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 353 ++
 3 files changed, 363 insertions(+)
 create mode 100644 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c

diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
index 4b88223..4c0d670 100644
--- a/drivers/gpu/drm/stm/Kconfig
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -14,3 +14,11 @@ config DRM_STM
  STMicroelectronics STM32 MCUs.
  To compile this driver as a module, choose M here: the module
  will be called stm-drm.
+
+config DRM_STM_DSI
+   tristate "STMicroelectronics specific extensions for Synopsys MIPI DSI"
+   depends on DRM_STM
+   select DRM_MIPI_DSI
+   select DRM_DW_MIPI_DSI
+   help
+ Choose this option for MIPI DSI support on STMicroelectronics SoC.
diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
index a09ecf4..d883adc 100644
--- a/drivers/gpu/drm/stm/Makefile
+++ b/drivers/gpu/drm/stm/Makefile
@@ -2,4 +2,6 @@ stm-drm-y := \
drv.o \
ltdc.o
 
+obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o
+
 obj-$(CONFIG_DRM_STM) += stm-drm.o
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
new file mode 100644
index 000..8dedc5c
--- /dev/null
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu 
+ *  Yannick Fertre 
+ *
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* DSI wrapper register & bit definitions */
+/* Note: registers are named as in the Reference Manual */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define SLEEP_US   1000
+#define TIMEOUT_US 20
+
+struct dw_mipi_dsi_stm {
+   void __iomem *base;
+   struct clk *pllref_clk;
+};
+
+static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
+{
+   writel_relaxed(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
+{
+   return readl_relaxed(dsi->base + reg);
+}
+
+static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
+{
+   dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
+}
+
+static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
+{
+   dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
+}
+
+static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
+  u32 mask, u32 val)
+{
+   dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
+}
+
+static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
+{
+   switch (fmt) {
+   case MIPI_DSI_FMT_RGB888:
+   return DSI_RGB888;
+   case MIPI_DSI_FMT_RGB666:
+   return DSI_RGB666_CONF2;
+   case MIPI_DSI_FMT_RGB666_PACKED:
+   return DSI_RGB666_CONF1;
+   case MIPI_DSI_FMT_RGB565:
+   retur

[PATCH v11 2/3] drm/i915: Add heuristic to determine better way to adjust brightness

[Puthikorn Voravootivat]

Add heuristic to decide that AUX or PWM pin should use for
backlight brightness adjustment and modify i915 param description
to have auto, force disable, and force enable.

The heuristic to determine that using AUX pin is better than using
PWM pin is that the panel support any of the feature list here.
- Regional backlight brightness adjustment
- Backlight PWM frequency set
- More than 8 bits resolution of brightness level
- Backlight enablement via AUX and not by BL_ENABLE pin

Change-Id: If8376b09fbf83398c40037a04ddba1035c6b71fc
Signed-off-by: Puthikorn Voravootivat 
---
 drivers/gpu/drm/i915/i915_params.c|  7 +--
 drivers/gpu/drm/i915/i915_params.h|  2 +-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 61 +--
 3 files changed, 63 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e363d076..3758ae1f11b4 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -63,7 +63,7 @@ struct i915_params i915 __read_mostly = {
.huc_firmware_path = NULL,
.enable_dp_mst = true,
.inject_load_failure = 0,
-   .enable_dpcd_backlight = false,
+   .enable_dpcd_backlight = -1,
.enable_gvt = false,
 };
 
@@ -246,9 +246,10 @@ MODULE_PARM_DESC(enable_dp_mst,
 module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 
0400);
 MODULE_PARM_DESC(inject_load_failure,
"Force an error after a number of failure check points (0:disabled 
(default), N:force failure at the Nth failure check point)");
-module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
0600);
+module_param_named_unsafe(enable_dpcd_backlight, i915.enable_dpcd_backlight, 
int, 0600);
 MODULE_PARM_DESC(enable_dpcd_backlight,
-   "Enable support for DPCD backlight control (default:false)");
+   "Enable support for DPCD backlight control "
+   "(-1:auto (default), 0:force disable, 1:force enabled if supported");
 
 module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
 MODULE_PARM_DESC(enable_gvt,
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 34148cc8637c..643dfaf41c1f 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -52,6 +52,7 @@
func(int, mmio_debug); \
func(int, edp_vswing); \
func(unsigned int, inject_load_failure); \
+   func(int, enable_dpcd_backlight); \
/* leave bools at the end to not create holes */ \
func(bool, alpha_support); \
func(bool, enable_cmd_parser); \
@@ -66,7 +67,6 @@
func(bool, verbose_state_checks); \
func(bool, nuclear_pageflip); \
func(bool, enable_dp_mst); \
-   func(bool, enable_dpcd_backlight); \
func(bool, enable_gvt)
 
 #define MEMBER(T, member) T member
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index 6c64e1f75c4e..b73b3d431a82 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -250,15 +250,66 @@ intel_dp_aux_display_control_capable(struct 
intel_connector *connector)
/* Check the  eDP Display control capabilities registers to determine if
 * the panel can support backlight control over the aux channel
 */
-   if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
-   (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
-   !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) 
{
+   if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
+   (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
return true;
}
return false;
 }
 
+/*
+ * Heuristic function whether we should use AUX for backlight adjustment or 
not.
+ *
+ * We should use AUX for backlight brightness adjustment if panel doesn't this
+ * via PWM pin or using AUX is better than using PWM pin.
+ *
+ * The heuristic to determine that using AUX pin is better than using PWM pin 
is
+ * that the panel support any of the feature list here.
+ * - Regional backlight brightness adjustment
+ * - Backlight PWM frequency set
+ * - More than 8 bits resolution of brightness level
+ * - Backlight enablement via AUX and not by BL_ENABLE pin
+ *
+ * If all above are not true, assume that using PWM pin is better.
+ */
+static bool
+intel_dp_aux_display_control_heuristic(struct intel_connector *connector)
+{
+   struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+   uint8_t reg_val;
+
+   /* Panel doesn't support adjusting backlight brightness via PWN pin */
+   if (!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))
+   return true;
+
+   /

[PATCH v3 1/6] drm/stm: ltdc: Add panel-bridge support

[Philippe CORNU]

Add the panel-bridge support for both panels & bridges (used by DSI host &
HDMI/LVDS bridges).

Signed-off-by: Philippe CORNU 
---
 drivers/gpu/drm/stm/Kconfig |   2 +-
 drivers/gpu/drm/stm/ltdc.c  | 208 +++-
 drivers/gpu/drm/stm/ltdc.h  |   2 +-
 3 files changed, 35 insertions(+), 177 deletions(-)

diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
index 2c4817f..4b88223 100644
--- a/drivers/gpu/drm/stm/Kconfig
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -4,7 +4,7 @@ config DRM_STM
select DRM_KMS_HELPER
select DRM_GEM_CMA_HELPER
select DRM_KMS_CMA_HELPER
-   select DRM_PANEL
+   select DRM_PANEL_BRIDGE
select VIDEOMODE_HELPERS
select FB_PROVIDE_GET_FB_UNMAPPED_AREA
default y
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 700cc08..a962a09 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -21,7 +21,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 #include 
@@ -269,11 +269,6 @@ static inline struct ltdc_device *encoder_to_ltdc(struct 
drm_encoder *enc)
return (struct ltdc_device *)enc->dev->dev_private;
 }
 
-static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
-{
-   return (struct ltdc_device *)con->dev->dev_private;
-}
-
 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 {
enum ltdc_pix_fmt pf;
@@ -813,130 +808,37 @@ static int ltdc_crtc_init(struct drm_device *ddev, 
struct drm_crtc *crtc)
  * DRM_ENCODER
  */
 
-static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
-{
-   struct ltdc_device *ldev = encoder_to_ltdc(encoder);
-
-   DRM_DEBUG_DRIVER("\n");
-
-   drm_panel_prepare(ldev->panel);
-   drm_panel_enable(ldev->panel);
-}
-
-static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
-{
-   struct ltdc_device *ldev = encoder_to_ltdc(encoder);
-
-   DRM_DEBUG_DRIVER("\n");
-
-   drm_panel_disable(ldev->panel);
-   drm_panel_unprepare(ldev->panel);
-}
-
-static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
-   .enable = ltdc_rgb_encoder_enable,
-   .disable = ltdc_rgb_encoder_disable,
-};
-
-static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
+static const struct drm_encoder_funcs ltdc_encoder_funcs = {
.destroy = drm_encoder_cleanup,
 };
 
-static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
+static int ltdc_encoder_init(struct drm_device *ddev)
 {
+   struct ltdc_device *ldev = ddev->dev_private;
struct drm_encoder *encoder;
+   int ret;
 
encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
if (!encoder)
-   return NULL;
+   return -ENOMEM;
 
encoder->possible_crtcs = CRTC_MASK;
encoder->possible_clones = 0; /* No cloning support */
 
-   drm_encoder_init(ddev, encoder, base.id);
-
-   return encoder;
-}
-
-/*
- * DRM_CONNECTOR
- */
-
-static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
-{
-   struct drm_device *ddev = connector->dev;
-   struct ltdc_device *ldev = ddev->dev_private;
-   int ret = 0;
-
-   DRM_DEBUG_DRIVER("\n");
-
-   if (ldev->panel)
-   ret = drm_panel_get_modes(ldev->panel);
-
-   return ret < 0 ? 0 : ret;
-}
-
-static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
-   .get_modes = ltdc_rgb_connector_get_modes,
-};
-
-static enum drm_connector_status
-ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
-{
-   struct ltdc_device *ldev = connector_to_ltdc(connector);
-
-   return ldev->panel ? connector_status_connected :
-  connector_status_disconnected;
-}
-
-static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
-{
-   DRM_DEBUG_DRIVER("\n");
-
-   drm_connector_unregister(connector);
-   drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
-   .dpms = drm_atomic_helper_connector_dpms,
-   .fill_modes = drm_helper_probe_single_connector_modes,
-   .detect = ltdc_rgb_connector_detect,
-   .destroy = ltdc_rgb_connector_destroy,
-   .reset = drm_atomic_helper_connector_reset,
-   .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-   .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
-{
-   struct drm_connector *connector;
-   int err;
-
-   connector = devm_kzalloc(ddev->dev, sizeof(*connect

[PATCH v3 6/6] dt-bindings: net: btusb: DT fix s/interrupt-name/interrupt-names/

[Geert Uytterhoeven]

Fixes: fd913ef7ce619467 ("Bluetooth: btusb: Add out-of-band wakeup support")
Signed-off-by: Geert Uytterhoeven 
---
v3:
  - New.
---
 Documentation/devicetree/bindings/net/btusb.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/btusb.txt 
b/Documentation/devicetree/bindings/net/btusb.txt
index 01fa2d4188d4a900..18dd9c386be094db 100644
--- a/Documentation/devicetree/bindings/net/btusb.txt
+++ b/Documentation/devicetree/bindings/net/btusb.txt
@@ -37,7 +37,7 @@ Following example uses irq pin number 3 of gpio0 for out of 
band wake-on-bt:
compatible = "usb1286,204e";
reg = <1>;
interrupt-parent = <&gpio0>;
-   interrupt-name = "wakeup";
+   interrupt-names = "wakeup";
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 };
 };
-- 
2.7.4

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[PATCH 06/19] dt-bindings: display: sun4i: Add binding for A31 HDMI controller

[Chen-Yu Tsai]

The HDMI controller in the A31 SoC is slightly different from the
earlier version. In addition to the TMDS clock and DDC controls,
this version now takes a second DDC clock input.

Add a compatible string for it, and add the DDC clock input to the
list of clocks required.

Signed-off-by: Chen-Yu Tsai 
---
 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index b83e6018041d..d23e7cad19d0 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -23,14 +23,17 @@ CEC. It is one end of the pipeline.
 Required properties:
   - compatible: value must be one of:
 * allwinner,sun5i-a10s-hdmi
+* allwinner,sun6i-a31-hdmi
   - reg: base address and size of memory-mapped region
   - interrupts: interrupt associated to this IP
   - clocks: phandles to the clocks feeding the HDMI encoder
 * ahb: the HDMI interface clock
 * mod: the HDMI module clock
+* ddc: the HDMI ddc clock (A31 only)
 * pll-0: the first video PLL
 * pll-1: the second video PLL
   - clock-names: the clock names mentioned above
+  - resets: phandle to the reset control for the HDMI encoder (A31 only)
   - dmas: phandles to the DMA channels used by the HDMI encoder
 * ddc-tx: The channel for DDC transmission
 * ddc-rx: The channel for DDC reception
-- 
2.11.0

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[PATCH v3 2/6] dt-bindings: display: Add Synopsys DW MIPI DSI DRM bridge driver

[Philippe CORNU]

This patch adds documentation of device tree bindings for the
Synopsys DesignWare MIPI DSI host DRM bridge driver.

Signed-off-by: Philippe CORNU 
---
 .../bindings/display/bridge/dw_mipi_dsi.txt| 30 ++
 1 file changed, 30 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..1d7c438
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,30 @@
+Synopsys DesignWare MIPI DSI host controller
+
+
+This document defines device tree properties for the Synopsys DesignWare MIPI
+DSI host controller. It doesn't constitue a device tree binding specification
+by itself but is meant to be referenced by platform-specific device tree
+bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each property is required or optional.
+
+- reg: Memory mapped base address and length of the DWC MIPI DSI
+  registers. (mandatory)
+
+- clocks: References to all the clocks specified in the clock-names property
+  as specified in [1]. (mandatory)
+
+- clock-names: "pclk" is peripheral clock for either AHB and APB. (mandatory)
+
+- resets: References to all the resets specified in the reset-names property
+  as specified in [2]. (optional)
+
+- reset-names: string reset name, must be "apb" if used. (optional)
+
+- panel or bridge node: see [3]. (mandatory)
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
-- 
1.9.1

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[PATCH v3 4/6] powerpc: dts: acadia: DT fix s/#interrupts-parent/#interrupt-parent/

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
Acked-by: Rob Herring 
---
v3:
  - No changes,

v2:
  - Add Acked-by.
---
 arch/powerpc/boot/dts/acadia.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/boot/dts/acadia.dts b/arch/powerpc/boot/dts/acadia.dts
index 57291f61ffe7021a..86266159521edac2 100644
--- a/arch/powerpc/boot/dts/acadia.dts
+++ b/arch/powerpc/boot/dts/acadia.dts
@@ -183,7 +183,7 @@
usb@ef603000 {
compatible = "ohci-be";
reg = <0xef603000 0x80>;
-   interrupts-parent = <&UIC0>;
+   interrupt-parent = <&UIC0>;
interrupts = <0xd 0x4 0xe 0x4>;
};
 
-- 
2.7.4

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[PATCH v2 2/3] drm/omap: displays: connector-hdmi: Support for hot plug detection

[Peter Ujfalusi]

If the hpd_gpio is valid, use interrupt handler to react to HPD changes.
In case the hpd_gpio is not valid, try to enable hpd detection on the
encoder if it supports it.

Signed-off-by: Peter Ujfalusi 
---
 drivers/gpu/drm/omapdrm/displays/connector-hdmi.c | 104 ++
 1 file changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c 
b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
index 1ef130641bae..332cda0c323f 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -38,6 +39,10 @@ static const struct videomode hdmic_default_vm = {
 struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
+   void (*hpd_cb)(void *cb_data, enum drm_connector_status status);
+   void *hpd_cb_data;
+   bool hpd_enabled;
+   struct mutex hpd_lock;
 
struct device *dev;
 
@@ -168,6 +173,70 @@ static bool hdmic_detect(struct omap_dss_device *dssdev)
return in->ops.hdmi->detect(in);
 }
 
+static int hdmic_register_hpd_cb(struct omap_dss_device *dssdev,
+void (*cb)(void *cb_data,
+   enum drm_connector_status status),
+void *cb_data)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+   struct omap_dss_device *in = ddata->in;
+
+   if (gpio_is_valid(ddata->hpd_gpio)) {
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_cb = cb;
+   ddata->hpd_cb_data = cb_data;
+   mutex_unlock(&ddata->hpd_lock);
+   return 0;
+   } else if (in->ops.hdmi->register_hpd_cb) {
+   return in->ops.hdmi->register_hpd_cb(in, cb, cb_data);
+   }
+
+   return -ENOTSUPP;
+}
+
+static void hdmic_unregister_hpd_cb(struct omap_dss_device *dssdev)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+   struct omap_dss_device *in = ddata->in;
+
+   if (gpio_is_valid(ddata->hpd_gpio)) {
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_cb = NULL;
+   ddata->hpd_cb_data = NULL;
+   mutex_unlock(&ddata->hpd_lock);
+   } else if (in->ops.hdmi->unregister_hpd_cb) {
+   in->ops.hdmi->unregister_hpd_cb(in);
+   }
+}
+
+static void hdmic_enable_hpd(struct omap_dss_device *dssdev)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+   struct omap_dss_device *in = ddata->in;
+
+   if (gpio_is_valid(ddata->hpd_gpio)) {
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_enabled = true;
+   mutex_unlock(&ddata->hpd_lock);
+   } else if (in->ops.hdmi->enable_hpd) {
+   in->ops.hdmi->enable_hpd(in);
+   }
+}
+
+static void hdmic_disable_hpd(struct omap_dss_device *dssdev)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+   struct omap_dss_device *in = ddata->in;
+
+   if (gpio_is_valid(ddata->hpd_gpio)) {
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_enabled = false;
+   mutex_unlock(&ddata->hpd_lock);
+   } else if (in->ops.hdmi->disable_hpd) {
+   in->ops.hdmi->disable_hpd(in);
+   }
+}
+
 static int hdmic_set_hdmi_mode(struct omap_dss_device *dssdev, bool hdmi_mode)
 {
struct panel_drv_data *ddata = to_panel_data(dssdev);
@@ -200,10 +269,34 @@ static struct omap_dss_driver hdmic_driver = {
 
.read_edid  = hdmic_read_edid,
.detect = hdmic_detect,
+   .register_hpd_cb= hdmic_register_hpd_cb,
+   .unregister_hpd_cb  = hdmic_unregister_hpd_cb,
+   .enable_hpd = hdmic_enable_hpd,
+   .disable_hpd= hdmic_disable_hpd,
.set_hdmi_mode  = hdmic_set_hdmi_mode,
.set_hdmi_infoframe = hdmic_set_infoframe,
 };
 
+static irqreturn_t hdmic_hpd_isr(int irq, void *data)
+{
+   struct panel_drv_data *ddata = data;
+
+   mutex_lock(&ddata->hpd_lock);
+   if (ddata->hpd_enabled && ddata->hpd_cb) {
+   enum drm_connector_status status;
+
+   if (hdmic_detect(&ddata->dssdev))
+   status = connector_status_connected;
+   else
+   status = connector_status_disconnected;
+
+   ddata->hpd_cb(ddata->hpd_cb_data, status);
+   }
+   mutex_unlock(&ddata->hpd_lock);
+
+   return IRQ_HANDLED;
+}
+
 static int hdmic_probe_of(struct platform_device *pdev)
 {
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
@@ -249,11 +342,22 @@ static int hdmic_probe(struct platform_device *pdev)
if (r)
return r;
 
+   mutex_init(&ddata->hpd_lock);
+
if (gpio_is_valid(ddata->hpd_gpio)) {
 

[PATCH v2 3/3] drm/omap: displays: encoder-tpd12s015: Support for hot plug detection

[Peter Ujfalusi]

Use interrupt handler for hpd GPIO to react to HPD changes.

Signed-off-by: Peter Ujfalusi 
---
 .../gpu/drm/omapdrm/displays/encoder-tpd12s015.c   | 81 ++
 1 file changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c 
b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
index 58276a48112e..a9e9d667c55e 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
@@ -15,12 +15,17 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "../dss/omapdss.h"
 
 struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
+   void (*hpd_cb)(void *cb_data, enum drm_connector_status status);
+   void *hpd_cb_data;
+   bool hpd_enabled;
+   struct mutex hpd_lock;
 
struct gpio_desc *ct_cp_hpd_gpio;
struct gpio_desc *ls_oe_gpio;
@@ -162,6 +167,49 @@ static bool tpd_detect(struct omap_dss_device *dssdev)
return gpiod_get_value_cansleep(ddata->hpd_gpio);
 }
 
+static int tpd_register_hpd_cb(struct omap_dss_device *dssdev,
+  void (*cb)(void *cb_data,
+ enum drm_connector_status status),
+  void *cb_data)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_cb = cb;
+   ddata->hpd_cb_data = cb_data;
+   mutex_unlock(&ddata->hpd_lock);
+
+   return 0;
+}
+
+static void tpd_unregister_hpd_cb(struct omap_dss_device *dssdev)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_cb = NULL;
+   ddata->hpd_cb_data = NULL;
+   mutex_unlock(&ddata->hpd_lock);
+}
+
+static void tpd_enable_hpd(struct omap_dss_device *dssdev)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_enabled = true;
+   mutex_unlock(&ddata->hpd_lock);
+}
+
+static void tpd_disable_hpd(struct omap_dss_device *dssdev)
+{
+   struct panel_drv_data *ddata = to_panel_data(dssdev);
+
+   mutex_lock(&ddata->hpd_lock);
+   ddata->hpd_enabled = false;
+   mutex_unlock(&ddata->hpd_lock);
+}
+
 static int tpd_set_infoframe(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi)
 {
@@ -193,10 +241,34 @@ static const struct omapdss_hdmi_ops tpd_hdmi_ops = {
 
.read_edid  = tpd_read_edid,
.detect = tpd_detect,
+   .register_hpd_cb= tpd_register_hpd_cb,
+   .unregister_hpd_cb  = tpd_unregister_hpd_cb,
+   .enable_hpd = tpd_enable_hpd,
+   .disable_hpd= tpd_disable_hpd,
.set_infoframe  = tpd_set_infoframe,
.set_hdmi_mode  = tpd_set_hdmi_mode,
 };
 
+static irqreturn_t tpd_hpd_isr(int irq, void *data)
+{
+   struct panel_drv_data *ddata = data;
+
+   mutex_lock(&ddata->hpd_lock);
+   if (ddata->hpd_enabled && ddata->hpd_cb) {
+   enum drm_connector_status status;
+
+   if (tpd_detect(&ddata->dssdev))
+   status = connector_status_connected;
+   else
+   status = connector_status_disconnected;
+
+   ddata->hpd_cb(ddata->hpd_cb_data, status);
+   }
+   mutex_unlock(&ddata->hpd_lock);
+
+   return IRQ_HANDLED;
+}
+
 static int tpd_probe_of(struct platform_device *pdev)
 {
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
@@ -261,6 +333,15 @@ static int tpd_probe(struct platform_device *pdev)
 
ddata->hpd_gpio = gpio;
 
+   mutex_init(&ddata->hpd_lock);
+
+   r = devm_request_threaded_irq(&pdev->dev, gpiod_to_irq(ddata->hpd_gpio),
+   NULL, tpd_hpd_isr,
+   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+   "tpd12s015 hpd", ddata);
+   if (r)
+   goto err_gpio;
+
dssdev = &ddata->dssdev;
dssdev->ops.hdmi = &tpd_hdmi_ops;
dssdev->dev = &pdev->dev;
-- 
2.13.0

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[PATCH 07/19] drm/sun4i: hdmi: Support different variants of the TMDS clock

[Chen-Yu Tsai]

On the A31, the HDMI TMDS clock has a different value offset for the
divider.

This patch adds support for custom offsets to the TMDS clock.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 26 +++---
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5692e41833ae..3c304e1fbe3b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -18,6 +18,8 @@
 struct sun4i_tmds {
struct clk_hw   hw;
struct sun4i_hdmi   *hdmi;
+
+   u8  div_offset;
 };
 
 static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
@@ -28,6 +30,7 @@ static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
 
 static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
 unsigned long parent_rate,
+u8 div_offset,
 u8 *div,
 bool *half)
 {
@@ -35,7 +38,7 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long 
rate,
u8 best_m = 0, m;
bool is_double;
 
-   for (m = 1; m < 16; m++) {
+   for (m = div_offset ?: 1; m < (16 + div_offset); m++) {
u8 d;
 
for (d = 1; d < 3; d++) {
@@ -67,7 +70,8 @@ static unsigned long sun4i_tmds_calc_divider(unsigned long 
rate,
 static int sun4i_tmds_determine_rate(struct clk_hw *hw,
 struct clk_rate_request *req)
 {
-   struct clk_hw *parent;
+   struct sun4i_tmds *tmds = hw_to_tmds(hw);
+   struct clk_hw *parent = NULL;
unsigned long best_parent = 0;
unsigned long rate = req->rate;
int best_div = 1, best_half = 1;
@@ -85,7 +89,8 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
continue;
 
for (i = 1; i < 3; i++) {
-   for (j = 1; j < 16; j++) {
+   for (j = tmds->div_offset ?: 1;
+j < (16 + tmds->div_offset); j++) {
unsigned long ideal = rate * i * j;
unsigned long rounded;
 
@@ -129,7 +134,7 @@ static unsigned long sun4i_tmds_recalc_rate(struct clk_hw 
*hw,
parent_rate /= 2;
 
reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
-   reg = (reg >> 4) & 0xf;
+   reg = ((reg >> 4) & 0xf) + tmds->div_offset;
if (!reg)
reg = 1;
 
@@ -144,7 +149,8 @@ static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned 
long rate,
u32 reg;
u8 div;
 
-   sun4i_tmds_calc_divider(rate, parent_rate, &div, &half);
+   sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset,
+   &div, &half);
 
reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
@@ -154,7 +160,7 @@ static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned 
long rate,
 
reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
-   writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div),
+   writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
   tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
 
return 0;
@@ -195,7 +201,7 @@ static const struct clk_ops sun4i_tmds_ops = {
.set_parent = sun4i_tmds_set_parent,
 };
 
-int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
+static int _sun4i_tmds_create(struct sun4i_hdmi *hdmi, u8 div_offset)
 {
struct clk_init_data init;
struct sun4i_tmds *tmds;
@@ -221,6 +227,7 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 
tmds->hdmi = hdmi;
tmds->hw.init = &init;
+   tmds->div_offset = div_offset;
 
hdmi->tmds_clk = devm_clk_register(hdmi->dev, &tmds->hw);
if (IS_ERR(hdmi->tmds_clk))
@@ -228,3 +235,8 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 
return 0;
 }
+
+int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
+{
+   return _sun4i_tmds_create(hdmi, 0);
+}
-- 
2.11.0

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Re: iMac 10,1 with Ubuntu 16.04: black screen after suspend

[Florian Echtler]

On 02.06.2017 17:12, Alex Deucher wrote:
> On Fri, Jun 2, 2017 at 3:35 AM, Florian Echtler  wrote:
>>
>> [  166.853787] [drm:radeon_dp_link_train_cr] clock recovery at voltage 0
>> pre-emphasis 0
>> [  166.853788] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>> [  166.855953] [drm:radeon_dp_link_train_ce] channel eq at voltage 0 
>> pre-emphasis 0
> 
> Yes, the link training appears to complete fine.  I guess it's
> something to do with the proprietary mux or backlight controls.

OK, so back to square... well, not one, but definitely back to the registers
(SMC and GPU).

As mentioned, the diff for the GPU registers before/after suspend is huge,
there's 117 register values that have changed. I assume that most of them are
actually internal frame pointers, but which ones? I tried to find some of that
information in drivers/gpu/drm/radeon/, but quickly got lost :-/

Regarding the SMC, there's actually only one key that consistently seems to have
a different value whether the display is on or off:

--- blank   2017-05-05 08:40:53.694565045 +0200
+++ non_blank   2017-05-05 08:40:53.702565066 +0200
@@ -143,7 +143,7 @@
   MSWR  [ui8 ]  0 (bytes 00)
   MVBO  [hex_]  (bytes ff ff)
   MVDC  [bin_]  (bytes 00)
-  MVDS  [bin_]  (bytes 08)
+  MVDS  [bin_]  (bytes 0a)
   MVE1  [si8 ]  (bytes 0d)
   MVE5  [si8 ]  (bytes 0b)
   MVHR  [flag]  (bytes 01)

However, even with my modified SmcDumpKeys.c which I can use to enable TDM, I
cannot write to that key. Since other MV__ keys control the display, too, it
would make sense that that is related to the display state, but it seems to be a
read-only key :-/

Running out of ideas again... any suggestions?

Best, Florian
-- 
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Re: [PATCH v6 5/5] drm/amdgpu: resize VRAM BAR for CPU access v2

[Bjorn Helgaas]

On Fri, Jun 02, 2017 at 11:32:21AM +0200, Christian König wrote:
> Hi Bjorn,
> 
> sorry for not responding earlier and thanks for picking this thread
> up again.
> 
> Am 01.06.2017 um 22:14 schrieb Bjorn Helgaas:
> >[+cc ADMGPU, DRM folks]
> >
> >On Tue, May 09, 2017 at 06:49:07PM +0200, Christian König wrote:
> >>[SNIP]
> >>+/**
> >>+ * amdgpu_resize_bar0 - try to resize BAR0
> >>+ *
> >>+ * @adev: amdgpu_device pointer
> >>+ *
> >>+ * Try to resize BAR0 to make all VRAM CPU accessible.
> >>+ */
> >>+void amdgpu_resize_bar0(struct amdgpu_device *adev)
> >>+{
> >>+   u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
> >>+   u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) -1;
> >>+   u16 cmd;
> >>+   int r;
> >>+
> >>+   /* Free the doorbell mapping, it most likely needs to move as well */
> >>+   amdgpu_doorbell_fini(adev);
> >>+   pci_release_resource(adev->pdev, 2);
> >>+
> >>+   /* Disable memory decoding while we change the BAR addresses and size */
> >>+   pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
> >>+   pci_write_config_word(adev->pdev, PCI_COMMAND,
> >>+ cmd & ~PCI_COMMAND_MEMORY);
> >>+
> >>+   r = pci_resize_resource(adev->pdev, 0, rbar_size);
> >>+   if (r == -ENOSPC)
> >>+   DRM_INFO("Not enough PCI address space for a large BAR.");
> >>+   else if (r && r != -ENOTSUPP)
> >>+   DRM_ERROR("Problem resizing BAR0 (%d).", r);
> >>+
> >>+   pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
> >>+
> >>+   /* When the doorbell BAR isn't available we have no chance of
> >>+* using the device.
> >>+*/
> >>+   BUG_ON(amdgpu_doorbell_init(adev));
> >This amdgpu_doorbell_fini()/amdgpu_doorbell_init() thing doesn't look
> >right.  amdgpu_device_init() only calls amdgpu_doorbell_init() for
> >"adev->asic_type >= CHIP_BONAIRE", but we call it unconditionally
> >here.
> >
> >This is the call graph:
> >
> >   amdgpu_device_init
> > adev->rmmio_base = pci_resource_start(adev->pdev, 5)   # 2 for < BONAIRE
> > adev->rmmio = ioremap(adev->rmmio_base, ...)
> > DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base)
> > if (adev->asic_type >= CHIP_BONAIRE) {
> >   amdgpu_doorbell_init
> > adev->doorbell.base = pci_resource_start(adev->pdev, 2)
> > adev->doorbell.ptr = ioremap(adev->doorbell.base, ...)
> > }
> > amdgpu_init
> >   gmc_v7_0_sw_init  # gmc_v7_0_ip_funcs.sw_init
> > gmc_v7_0_mc_init
> >   + amdgpu_resize_bar0
> >   +   amdgpu_doorbell_fini
> >   +   pci_release_resource(adev->pdev, 2)
> >   +   pci_resize_resource(adev->pdev, 0, size)
> >   +   amdgpu_doorbell_init
> >   adev->mc.aper_base = pci_resource_start(adev->pdev, 0)
> >
> >If "asic_type < CHIP_BONAIRE", we ioremapped BAR 2 in
> >amdgpu_device_init(), then we released the resource here and never
> >updated the ioremap.
> 
> The first hardware with a resizeable BAR I could find is a Tonga,
> and that is even a generation later than Bonaire.
> 
> So we are never going to call this code on earlier hardware generations.

The problem with that is that it's impossible for a code reader to
verify that.  So adding a check is ugly but I think makes it more
readable.

> But I think I will just move the asic_type check into the function
> to be absolute sure.
> 
> > From the PCI core perspective, it would be much cleaner to do the BAR
> >resize before the driver calls pci_enable_device().  If that could be
> >done, there would be no need for this sort of shutdown/reinit stuff
> >and we wouldn't have to worry about issues like these.  The amdgpu
> >init path is pretty complicated, so I don't know whether this is
> >possible.
> 
> I completely agree on this and it is actually the approach I tried first.
> 
> There are just two problems with this approach:
> 1. When the amdgpu driver is loaded there can already be the VGA
> console, Vesa or EFI driver active for the device and displaying the
> splash screen.
> 
> When we resize and most likely relocate the BAR while those drivers
> are active it will certainly cause problems.
> 
> What amdgpu does before trying to resize the BAR is kicking out
> other driver and making sure it has exclusive access to the
> hardware.

I don't understand the problem here yet.  If you need to enable the
device, then disable it, resize, and re-enable it, that's fine.

The important thing I'm looking for is that the resize happens before
a pci_enable_device(), because pci_enable_device() is the sync point
where the PCI core enables resources and makes them available to the
driver.  Drivers know that they can't look at the resources before
that point.  There's a little bit of text about this in [1].

> 2. Without taking a look at the registers you don't know how much
> memory there actually is on the board.
> 
> We could always resize it to the maximum supported, but that would
> mean we could easily waste 128GB of address space while the h

Re: [PATCH 4/4] drm/bridge: dw-hdmi: add cec driver

[Russell King - ARM Linux]

On Fri, Jun 02, 2017 at 11:28:08AM +0200, Hans Verkuil wrote:
> The 'signal_free_time' argument of adap_transmit will have the recommended
> signal free time. You can test against the CEC_SIGNAL_FREE_TIME_* defines
> from media/cec.h. You probably saw this already, but just in case you missed
> this...

Yes, it's a recent addition to the CEC core, which I've added support
for, but it doesn't make too much sense until the retrying stuff is
sorted out.

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[PATCH 13/19] drm/sun4i: hdmi: Add support for controller hardware variants

[Chen-Yu Tsai]

The HDMI controller found in earlier Allwinner SoCs have slight
differences:

  - Need different initial values for the PLL related registers

  - Different behavior of the DDC and TMDS clocks

  - Different register layout for the DDC portion

  - Separate DDC parent clock on the A31

  - Explicit reset control

The clock variants are supported within their implementations,
which only expose a create function for each variant.

The different layout of the DDC registers necessitates a separate
version of struct drm_connector_helper_funcs.

A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   |   2 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |   8 +++
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 114 ++---
 3 files changed, 100 insertions(+), 24 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 4d6078fca9ac..e48186985a51 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -610,7 +610,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", 
lcd_ch1_parents,
 
 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
 
-static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
+static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x154, BIT(31), 0);
 
 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
 "pll-ddr" };
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index c39c2a245339..c63d0bd95963 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -155,6 +155,8 @@ enum sun4i_hdmi_pkt_type {
SUN4I_HDMI_PKT_END = 15,
 };
 
+struct sun4i_hdmi_variant;
+
 struct sun4i_hdmi {
struct drm_connectorconnector;
struct drm_encoder  encoder;
@@ -162,9 +164,13 @@ struct sun4i_hdmi {
 
void __iomem*base;
 
+   /* Reset control */
+   struct reset_control*reset;
+
/* Parent clocks */
struct clk  *bus_clk;
struct clk  *mod_clk;
+   struct clk  *ddc_parent_clk;
struct clk  *pll0_clk;
struct clk  *pll1_clk;
 
@@ -175,6 +181,8 @@ struct sun4i_hdmi {
struct sun4i_drv*drv;
 
boolhdmi_monitor;
+
+   const struct sun4i_hdmi_variant *variant;
 };
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 457614073501..9ded40aaed32 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -20,8 +20,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 #include "sun4i_backend.h"
 #include "sun4i_crtc.h"
@@ -315,6 +317,56 @@ static const struct drm_connector_funcs 
sun4i_hdmi_connector_funcs = {
.atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
 };
 
+struct sun4i_hdmi_variant {
+   const struct drm_connector_helper_funcs *connector_helpers;
+   int (*ddc_create)(struct sun4i_hdmi *hdmi, struct clk *clk);
+   int (*tmds_create)(struct sun4i_hdmi *hdmi);
+   bool has_ddc_parent_clk;
+   bool has_reset_control;
+
+   u32 pad_ctrl0_init_val;
+   u32 pad_ctrl1_init_val;
+   u32 pll_ctrl_init_val;
+};
+
+#define SUN4I_HDMI_PAD_CTRL1_MASK  (GENMASK(24, 7) | GENMASK(5, 0))
+#define SUN4I_HDMI_PLL_CTRL_MASK   (GENMASK(31, 8) | GENMASK(3, 0))
+
+static const struct sun4i_hdmi_variant sun5i_variant = {
+   .connector_helpers  = &sun4i_hdmi_connector_helper_funcs,
+   .ddc_create = sun4i_ddc_create,
+   .tmds_create= sun4i_tmds_create,
+   .has_ddc_parent_clk = false,
+   .has_reset_control  = false,
+   .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
+ SUN4I_HDMI_PAD_CTRL0_CKEN |
+ SUN4I_HDMI_PAD_CTRL0_PWENG |
+ SUN4I_HDMI_PAD_CTRL0_PWEND |
+ SUN4I_HDMI_PAD_CTRL0_PWENC |
+ SUN4I_HDMI_PAD_CTRL0_LDODEN |
+ SUN4I_HDMI_PAD_CTRL0_LDOCEN |
+ SUN4I_HDMI_PAD_CTRL0_BIASEN,
+   .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
+ SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
+ SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
+ SUN4I_HDMI_PAD_CTRL1_REG_DEN |
+  

[PATCH v3 3/6] drm/bridge/synopsys: Add MIPI DSI host controller bridge

[Philippe CORNU]

Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: Philippe CORNU 
---
 drivers/gpu/drm/bridge/synopsys/Kconfig   |9 +
 drivers/gpu/drm/bridge/synopsys/Makefile  |2 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 1022 +
 include/drm/bridge/dw_mipi_dsi.h  |   42 +
 4 files changed, 1075 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
 create mode 100644 include/drm/bridge/dw_mipi_dsi.h

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 40d2827..d7fbdff 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -21,3 +21,12 @@ config DRM_DW_HDMI_I2S_AUDIO
help
  Support the I2S Audio interface which is part of the Synopsys
  Designware HDMI block.
+
+config DRM_DW_MIPI_DSI
+   tristate "Synopsys DesignWare MIPI DSI host controller bridge"
+   select DRM_KMS_HELPER
+   select DRM_MIPI_DSI
+   select DRM_PANEL
+   help
+ Choose this if you want to use the Synopsys DesignWare MIPI DSI host
+ controller bridge.
diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile 
b/drivers/gpu/drm/bridge/synopsys/Makefile
index 17aa7a6..5f57d36 100644
--- a/drivers/gpu/drm/bridge/synopsys/Makefile
+++ b/drivers/gpu/drm/bridge/synopsys/Makefile
@@ -3,3 +3,5 @@
 obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
+
+obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
new file mode 100644
index 000..6b25629
--- /dev/null
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -0,0 +1,1022 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Modified by Philippe Cornu 
+ * This generic Synopsys Designware MIPI DSI host driver is based on the
+ * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DSI_VERSION0x00
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_CLKMGR_CFG 0x08
+#define TO_CLK_DIVIDSION(div)  (((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVIDSION(div)  (((div) & 0xff) << 0)
+
+#define DSI_DPI_VCID   0x0c
+#define DPI_VID(vid)   (((vid) & 0x3) << 0)
+
+#define DSI_DPI_COLOR_CODING   0x10
+#define EN18_LOOSELY   BIT(8)
+#define DPI_COLOR_CODING_16BIT_1   0x0
+#define DPI_COLOR_CODING_16BIT_2   0x1
+#define DPI_COLOR_CODING_16BIT_3   0x2
+#define DPI_COLOR_CODING_18BIT_1   0x3
+#define DPI_COLOR_CODING_18BIT_2   0x4
+#define DPI_COLOR_CODING_24BIT 0x5
+
+#define DSI_DPI_CFG_POL0x14
+#define COLORM_ACTIVE_LOW  BIT(4)
+#define SHUTD_ACTIVE_LOW   BIT(3)
+#define HSYNC_ACTIVE_LOW   BIT(2)
+#define VSYNC_ACTIVE_LOW   BIT(1)
+#define DATAEN_ACTIVE_LOW  BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM 0x18
+#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
+
+#define DSI_DBI_CFG0x20
+#define DSI_DBI_CMDSIZE0x28
+
+#define DSI_PCKHDL_CFG 0x2c
+#define EN_CRC_RX  BIT(4)
+#define EN_ECC_RX  BIT(3)
+#define EN_BTA BIT(2)
+#define EN_EOTP_RX BIT(1)
+#define EN_EOTP_TX BIT(0)
+
+#define DSI_MODE_CFG   0x34
+#define ENABLE_VIDEO_MODE  0
+#define ENABLE_CMD_MODEBIT(0)
+
+#define DSI_VID_MODE_CFG   0x38
+#define FRAME_BTA_ACK  BIT(14)
+#define ENABLE_LOW_POWER   (0x3f << 8)
+#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
+#define VID_MODE_TYPE_BURST0x2
+#define VID_MODE_TYPE_MASK 0x3
+
+#define DSI_VID_PKT_SIZE   0x3c
+#define VID_PKT_SIZE(p)(((p) & 0x3fff) << 0)
+#define VID_PKT_MAX_SIZE

[PATCH 08/19] drm/sun4i: hdmi: Support the TMDS clock in the A31's HDMI controller

[Chen-Yu Tsai]

The A31's HDMI controller's TMDS clock is slightly different.
There is an offset of 1 between the divider value and the actual
value programmed into the registers.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h  | 1 +
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 2f2f2ff1ea63..3a4987ab8da8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -153,5 +153,6 @@ struct sun4i_hdmi {
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
 int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
+int sun6i_tmds_create(struct sun4i_hdmi *hdmi);
 
 #endif /* _SUN4I_HDMI_H_ */
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 3c304e1fbe3b..6f25c7bd887e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -240,3 +240,10 @@ int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
 {
return _sun4i_tmds_create(hdmi, 0);
 }
+
+/* sun6i variant has a different value offset for the divider */
+
+int sun6i_tmds_create(struct sun4i_hdmi *hdmi)
+{
+   return _sun4i_tmds_create(hdmi, 1);
+}
-- 
2.11.0

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[PATCH 03/19] drm/sun4i: tcon: Add support for demuxing TCON output on A31

[Chen-Yu Tsai]

On systems with 2 TCONs such as the A31, it is possible to demux the
output of the TCONs to one encoder.

Add support for this for the A31.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 61 ++
 1 file changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..21bd7fab7aaa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -14,9 +14,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
@@ -109,11 +112,69 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, 
bool enable)
 }
 EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
 
+static struct sun4i_tcon *sun4i_get_first_tcon(struct drm_device *drm)
+{
+   struct sun4i_drv *drv = drm->dev_private;
+   struct sun4i_tcon *tcon;
+
+   list_for_each_entry(tcon, &drv->tcon_list, list)
+   if (tcon->id == 0)
+   return tcon;
+
+   dev_warn(drm->dev,
+"TCON0 not found, display output muxing may not work\n");
+
+   return tcon;
+}
+
+static int _sun6i_tcon_set_mux(struct drm_encoder *encoder)
+{
+   struct sun4i_tcon *tcon = sun4i_get_first_tcon(encoder->dev);
+   int tcon_id = drm_crtc_to_sun4i_crtc(encoder->crtc)->tcon->id;
+   u32 shift;
+
+   DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s (TCON %d)\n",
+encoder->name, encoder->crtc->name, tcon_id);
+
+   /* Only 2 TCONs */
+   if (tcon_id >= 2)
+   return -EINVAL;
+
+   switch (encoder->encoder_type) {
+   case DRM_MODE_ENCODER_TMDS:
+   /* HDMI */
+   shift = 8;
+   break;
+   case DRM_MODE_ENCODER_DSI:
+   /* No MIPI DSI on A31s */
+   if (of_device_is_compatible(tcon->dev->of_node,
+   "allwinner,sun6i-a31s-tcon"))
+   return -EINVAL;
+   shift = 0;
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   regmap_update_bits(tcon->regs, SUN4I_TCON_MUX_CTRL_REG,
+  0x3 << shift, tcon_id << shift);
+
+   return 0;
+}
+
 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
struct drm_encoder *encoder)
 {
+   /* Get the device node of the display engine */
+   struct device_node *node = encoder->dev->dev->of_node;
u32 val;
 
+   if (of_device_is_compatible(node, "allwinner,sun6i-a31-display-engine") 
||
+   of_device_is_compatible(node, 
"allwinner,sun6i-a31s-display-engine")) {
+   _sun6i_tcon_set_mux(encoder);
+   return;
+   }
+
if (!tcon->quirks->has_unknown_mux)
return;
 
-- 
2.11.0

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[PATCH v3 0/6] STM32 DSI HOST

[Philippe CORNU]

Version 3:
- stm/ltdc: Use panel-bridge (-170 lines), thanks to comments of Eric Anholt,
  Boris Brezillon, Archit Taneja & Andrzej Hajda.
- Synopsys dsi: Add dw_mipi_dsi.h (forgotten in v2), thanks to comments of
  Neil Armstrong.
- Synopsys dsi/dw-mipi-dsi.c: add dw_mipi_dsi_dphy_init() &
  dw_mipi_dsi_dphy_enable() to better manage DW phy-dedicated regs, remove
  dw_mipi_dsi_mode enum, remove stm32 patch for lpm, remove pllref (manage in
  the vendor phy) thanks to comments of Archit Taneja. Add mode_flags to phy
  parameters to better adjust lane mbps according to dsi burst and non burst
  modes todos in caps.
- stm/dw_mipi_dsi-stm.c: Add pllref management.
- dt-bindings/display/stm: Split dt-bindings patch in two (parent node
  removal/ dsi), add required nodes (port & panel/bridge), updates thanks to
  comments of Rob Herring.
- dt-bindings/display/Synopsys dsi: remove port as part of the vendor
  documentation, add panel/bridge node, update dt-bindings thanks to comments
  of Rob Herring.
- Add more people from Hisilicon & Rockchip.

Version 2:
- Add a generic Synopsys DesignWare MIPI DSI bridge driver following
  comments from Neil Armstrong & Archit Taneja.
- Use drm_of_find_panel_or_bridge() thanks to Eric Anholt comments
- Update dt-bindings thanks to Rob Herring comments

Version 1:
- Initial commit

The purpose of this set of patches is to add the mipi dsi host driver
to the stm32 family.

This mipi dsi host driver is based on the Rockchip version of the
Synopsys Designware mipi dsi driver (rockchip/dw-mipi-dsi.c)
modified for the stm32 family:
- replace Rockchip digital & phy specific extensions with stm32's ones.
- add a bridge

Philippe CORNU (6):
  drm/stm: ltdc: Add panel-bridge support
  dt-bindings: display: Add Synopsys DW MIPI DSI DRM bridge driver
  drm/bridge/synopsys: Add MIPI DSI host controller bridge
  dt-bindings: display: stm32: remove st-display-subsystem parent node
requirement
  dt-bindings: display: stm32: Add DSI host driver
  drm/stm: Add STM32 DSI host driver

 .../bindings/display/bridge/dw_mipi_dsi.txt|   30 +
 .../devicetree/bindings/display/st,stm32-ltdc.txt  |   84 +-
 drivers/gpu/drm/bridge/synopsys/Kconfig|9 +
 drivers/gpu/drm/bridge/synopsys/Makefile   |2 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c  | 1022 
 drivers/gpu/drm/stm/Kconfig|   10 +-
 drivers/gpu/drm/stm/Makefile   |2 +
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c  |  353 +++
 drivers/gpu/drm/stm/ltdc.c |  208 +---
 drivers/gpu/drm/stm/ltdc.h |2 +-
 include/drm/bridge/dw_mipi_dsi.h   |   42 +
 11 files changed, 1585 insertions(+), 179 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
 create mode 100644 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
 create mode 100644 include/drm/bridge/dw_mipi_dsi.h

-- 
1.9.1

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[PATCH v3 4/6] dt-bindings: display: stm32: remove st-display-subsystem parent node requirement

[Philippe CORNU]

There is no need anymore to have a "st-display-subsystem" parent node
in the device tree for the ltdc.

Signed-off-by: Philippe CORNU 
---
 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt 
b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
index 8e14769..90a8459 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -1,7 +1,6 @@
 * STMicroelectronics STM32 lcd-tft display controller
 
 - ltdc: lcd-tft display controller host
-  must be a sub-node of st-display-subsystem
   Required properties:
   - compatible: "st,stm32-ltdc"
   - reg: Physical base address of the IP registers and length of memory mapped 
region.
-- 
1.9.1

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[PATCH 17/19] ARM: sun6i: a31: Enable HDMI support on the A31 Hummingbird

[Chen-Yu Tsai]

The A31 Humminbird has an HDMI connector wired to the HDMI pins
on the SoC. Enable HDMI support for this board.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts 
b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 9ecb5f0b3f83..19e382a11297 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -62,6 +62,17 @@
stdout-path = "serial0:115200n8";
};
 
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
+
vga-connector {
compatible = "vga-connector";
 
@@ -162,6 +173,16 @@
};
 };
 
+&hdmi {
+   status = "okay";
+};
+
+&hdmi_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <&hdmi_con_in>;
+   };
+};
+
 &i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
-- 
2.11.0

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[PATCH 12/19] drm/sun4i: hdmi: Support the DDC clock in the A31's HDMI controller

[Chen-Yu Tsai]

On the A31, the HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.

This patch adds support for this variant.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |  1 +
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 08c514672fd3..c39c2a245339 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -178,6 +178,7 @@ struct sun4i_hdmi {
 };
 
 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
+int sun6i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
 int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
 int sun6i_tmds_create(struct sun4i_hdmi *hdmi);
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index 9a6b6243e977..b1395e7b242c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -151,3 +151,14 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
*parent)
 {
return _sun4i_ddc_create(hdmi, parent, &sun4i_variant);
 }
+
+static const struct sun4i_ddc_variant sun6i_variant = {
+   .reg_offset = SUN6I_HDMI_DDC_CLK_REG,
+   .pre_divider= 1,
+   .m_offset   = 2,
+};
+
+int sun6i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
+{
+   return _sun4i_ddc_create(hdmi, parent, &sun6i_variant);
+}
-- 
2.11.0

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[PATCH 01/19] drm/sun4i: call drm_vblank_init with correct number of crtcs

[Chen-Yu Tsai]

If we want to have vblank on both pipelines at the same time, we need
to call drm_vblank_init with num_crtcs = 2.

Instead, since the crtc init calls correctly set mode_config.num_crtc,
we can move the drm_vblank_init call to after the crtc init code is
called, which is the component bind part. Then we can just pass
mode_config.num_crtc in.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index f19100c91c2b..ed75a779ae4b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -100,11 +100,6 @@ static int sun4i_drv_bind(struct device *dev)
goto free_drm;
}
 
-   /* drm_vblank_init calls kcalloc, which can fail */
-   ret = drm_vblank_init(drm, 1);
-   if (ret)
-   goto free_mem_region;
-
drm_mode_config_init(drm);
 
ret = component_bind_all(drm->dev, drm);
@@ -113,6 +108,11 @@ static int sun4i_drv_bind(struct device *dev)
goto cleanup_mode_config;
}
 
+   /* drm_vblank_init calls kcalloc, which can fail */
+   ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
+   if (ret)
+   goto free_mem_region;
+
drm->irq_enabled = true;
 
/* Remove early framebuffers (ie. simplefb) */
-- 
2.11.0

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[PATCH 10/19] drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision

[Chen-Yu Tsai]

The DDC parent clock on the A31 SoC is also conveniently named
"hdmi-ddc", which results in a name collision when the hdmi driver
registers its internal DDC divider clock.

Rename the internal clock to "hdmi-ddc-divider".

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index e1071838f487..9a6b6243e977 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -125,7 +125,7 @@ static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, 
struct clk *parent,
if (!ddc)
return -ENOMEM;
 
-   init.name = "hdmi-ddc";
+   init.name = "hdmi-ddc-divider";
init.ops = &sun4i_ddc_ops;
init.parent_names = &parent_name;
init.num_parents = 1;
-- 
2.11.0

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[PATCH 14/19] drm/sun4i: hdmi: Add support for A31's HDMI controller

[Chen-Yu Tsai]

The HDMI controller found in the A31 SoCs is slightly different
from the one already supported, which is found in the A10s:

  - Need different initial values for the PLL related registers

  - Different behavior of the DDC and TMDS clocks

  - Different register layout for the DDC portion

  - Separate DDC parent clock

This patch adds support for it.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |   3 +
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 141 +
 2 files changed, 144 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index c63d0bd95963..2589bc92be59 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -56,10 +56,13 @@
 #define SUN4I_HDMI_PAD_CTRL0_TXEN  BIT(23)
 
 #define SUN4I_HDMI_PAD_CTRL1_REG   0x204
+#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN   BIT(24) /* set on A31 */
 #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT   BIT(23)
 #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22)
 #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT   BIT(20)
 #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19)
+#define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18)
+#define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17)
 #define SUN4I_HDMI_PAD_CTRL1_REG_DEN   BIT(15)
 #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14)
 #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)(((n) & 7) << 10)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 9ded40aaed32..e9abf93eb41c 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -293,6 +293,109 @@ static const struct drm_connector_helper_funcs 
sun4i_hdmi_connector_helper_funcs
.get_modes  = sun4i_hdmi_get_modes,
 };
 
+static int sun6i_hdmi_read_sub_block(struct sun4i_hdmi *hdmi,
+unsigned int blk, unsigned int offset,
+u8 *buf, unsigned int count)
+{
+   unsigned long reg;
+   int i;
+
+   reg = readl(hdmi->base + SUN6I_HDMI_DDC_FIFO_CTRL_REG);
+   writel(reg | SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR,
+  hdmi->base + SUN6I_HDMI_DDC_FIFO_CTRL_REG);
+   writel(SUN6I_HDMI_DDC_ADDR_SEGMENT(offset >> 8) |
+  SUN6I_HDMI_DDC_ADDR_EDDC(DDC_SEGMENT_ADDR << 1) |
+  SUN6I_HDMI_DDC_ADDR_OFFSET(offset) |
+  SUN6I_HDMI_DDC_ADDR_SLAVE(DDC_ADDR),
+  hdmi->base + SUN6I_HDMI_DDC_ADDR_REG);
+
+   writel(SUN6I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ |
+  SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count),
+  hdmi->base + SUN6I_HDMI_DDC_CMD_REG);
+
+   reg = readl(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
+   writel(reg | SUN6I_HDMI_DDC_CTRL_START_CMD,
+  hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
+
+   if (readl_poll_timeout(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG, reg,
+  !(reg & SUN6I_HDMI_DDC_CTRL_START_CMD),
+  100, 10))
+   return -EIO;
+
+   for (i = 0; i < count; i++)
+   buf[i] = readb(hdmi->base + SUN6I_HDMI_DDC_FIFO_DATA_REG);
+
+   return 0;
+}
+
+static int sun6i_hdmi_read_edid_block(void *data, u8 *buf, unsigned int blk,
+ size_t length)
+{
+   struct sun4i_hdmi *hdmi = data;
+   int retry = 2, i;
+
+   do {
+   for (i = 0; i < length; i += SUN4I_HDMI_DDC_FIFO_SIZE) {
+   unsigned char offset = blk * EDID_LENGTH + i;
+   unsigned int count = min((unsigned 
int)SUN4I_HDMI_DDC_FIFO_SIZE,
+length - i);
+   int ret;
+
+   ret = sun6i_hdmi_read_sub_block(hdmi, blk, offset,
+   buf + i, count);
+   if (ret)
+   return ret;
+   }
+   } while (!drm_edid_block_valid(buf, blk, true, NULL) && (retry--));
+
+   return 0;
+}
+
+static int sun6i_hdmi_get_modes(struct drm_connector *connector)
+{
+   struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
+   u32 reg;
+   struct edid *edid;
+   int ret;
+
+   clk_set_rate(hdmi->ddc_clk, 10);
+   clk_prepare_enable(hdmi->ddc_clk);
+
+   /* Reset i2c controller */
+   writel(SUN6I_HDMI_DDC_CTRL_ENABLE | SUN6I_HDMI_DDC_CTRL_RESET |
+  SUN6I_HDMI_DDC_CTRL_SDA_ENABLE |
+  SUN6I_HDMI_DDC_CTRL_SCL_ENABLE,
+  hdmi->base + SUN6I_HDMI_DDC_CTRL_REG);
+   if (readl_poll_timeout(hdmi->base + SUN6I_HDMI_DDC_CTRL_REG, reg,
+  !(reg & SUN6I_HDMI_DDC_CTRL_RESET),
+  100, 2000)) {
+   dev_err(hdmi->dev, "DDC reset timeout: %08x\n", reg);
+   clk_disable_unprepare(hdm

[PATCH v3 3/6] dt: booting-without-of: DT fix s/#interrupt-cell/#interrupt-cells/

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
Acked-by: Rob Herring 
---
v3:
  - No changes,

v2:
  - Add Acked-by.
---
 Documentation/devicetree/booting-without-of.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/booting-without-of.txt 
b/Documentation/devicetree/booting-without-of.txt
index 280d283304bb82d8..f35d3adacb987f7d 100644
--- a/Documentation/devicetree/booting-without-of.txt
+++ b/Documentation/devicetree/booting-without-of.txt
@@ -1309,7 +1309,7 @@ number and level/sense information. All interrupt 
children in an
 OpenPIC interrupt domain use 2 cells per interrupt in their interrupts
 property.
 
-The PCI bus binding specifies a #interrupt-cell value of 1 to encode
+The PCI bus binding specifies a #interrupt-cells value of 1 to encode
 which interrupt pin (INTA,INTB,INTC,INTD) is used.
 
 2) interrupt-parent property
-- 
2.7.4

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[PATCH v3 5/6] dt-bindings: display: amlogic: DT fix s/resets-names/reset-names/

[Geert Uytterhoeven]

Fixes: 8cceda5349377e30 ("dt-bindings: Add bindings for the Amlogic Meson 
dw-hdmi extension")
Signed-off-by: Geert Uytterhoeven 
---
v3:
  - New.
---
 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt 
b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
index 7f040edc16fe6325..a65c890e3170f875 100644
--- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
@@ -43,7 +43,7 @@ Required properties:
   and the Amlogic Meson venci clocks as described in
   Documentation/devicetree/bindings/clock/clock-bindings.txt,
   the clocks are soc specific, the clock-names should be "iahb", "isfr", 
"venci"
-- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
+- resets, reset-names: must have the phandles to the HDMI apb, glue and phy
   resets as described in :
   Documentation/devicetree/bindings/reset/reset.txt,
   the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
-- 
2.7.4

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[PATCH 05/19] drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent

[Chen-Yu Tsai]

On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.

Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 51 -
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
index 5cf2527bffc8..5692e41833ae 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
@@ -71,7 +71,7 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
unsigned long best_parent = 0;
unsigned long rate = req->rate;
int best_div = 1, best_half = 1;
-   int i, j;
+   int i, j, p;
 
/*
 * We only consider PLL3, since the TCON is very likely to be
@@ -79,32 +79,37 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
 * clock, so we should not need to do anything.
 */
 
-   parent = clk_hw_get_parent_by_index(hw, 0);
-   if (!parent)
-   return -EINVAL;
-
-   for (i = 1; i < 3; i++) {
-   for (j = 1; j < 16; j++) {
-   unsigned long ideal = rate * i * j;
-   unsigned long rounded;
-
-   rounded = clk_hw_round_rate(parent, ideal);
-
-   if (rounded == ideal) {
-   best_parent = rounded;
-   best_half = i;
-   best_div = j;
-   goto out;
-   }
-
-   if (abs(rate - rounded / i) <
-   abs(rate - best_parent / best_div)) {
-   best_parent = rounded;
-   best_div = i;
+   for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
+   parent = clk_hw_get_parent_by_index(hw, p);
+   if (!parent)
+   continue;
+
+   for (i = 1; i < 3; i++) {
+   for (j = 1; j < 16; j++) {
+   unsigned long ideal = rate * i * j;
+   unsigned long rounded;
+
+   rounded = clk_hw_round_rate(parent, ideal);
+
+   if (rounded == ideal) {
+   best_parent = rounded;
+   best_half = i;
+   best_div = j;
+   goto out;
+   }
+
+   if (abs(rate - rounded / i) <
+   abs(rate - best_parent / best_div)) {
+   best_parent = rounded;
+   best_div = i;
+   }
}
}
}
 
+   if (!parent)
+   return -EINVAL;
+
 out:
req->rate = best_parent / best_half / best_div;
req->best_parent_rate = best_parent;
-- 
2.11.0

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[PATCH v11 1/3] drm/i915: Set PWM divider to match desired frequency in vbt

[Puthikorn Voravootivat]

Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to have
as many bits as possible for PWM duty cyle for granularity of
brightness adjustment while the frequency divisor is still
within 25% of the desired value.

Change-Id: I96221608e1288ffc03a0fd9c4a658809acda4aca
Signed-off-by: Puthikorn Voravootivat 
---
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 98 ---
 1 file changed, 90 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index a0995c00fc84..6c64e1f75c4e 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -97,11 +97,85 @@ intel_dp_aux_set_backlight(struct intel_connector 
*connector, u32 level)
}
 }
 
+/*
+ * Set PWM Frequency divider to match desired frequency in vbt.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
+static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
+{
+   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+   struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+   int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+   u8 pn, pn_min, pn_max;
+
+   /* Find desired value of (F x P)
+* Note that, if F x P is out of supported range, the maximum value or
+* minimum value will applied automatically. So no need to check that.
+*/
+   freq = dev_priv->vbt.backlight.pwm_freq_hz;
+   DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
+   if (!freq) {
+   DRM_DEBUG_KMS("Use panel default backlight frequency\n");
+   return false;
+   }
+
+   fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
+
+   /* Use highest possible value of Pn for more granularity of brightness
+* adjustment while satifying the conditions below.
+* - Pn is in the range of Pn_min and Pn_max
+* - F is in the range of 1 and 255
+* - FxP is within 25% of desired value.
+*   Note: 25% is arbitrary value and may need some tweak.
+*/
+   if (drm_dp_dpcd_readb(&intel_dp->aux,
+  DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
+   DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
+   return false;
+   }
+   if (drm_dp_dpcd_readb(&intel_dp->aux,
+  DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
+   DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
+   return false;
+   }
+   pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+   pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+   fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+   fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+   if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+   DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
+   return false;
+   }
+
+   for (pn = pn_max; pn >= pn_min; pn--) {
+   f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+   fxp_actual = f << pn;
+   if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+   break;
+   }
+
+   if (drm_dp_dpcd_writeb(&intel_dp->aux,
+  DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+   DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
+   return false;
+   }
+   if (drm_dp_dpcd_writeb(&intel_dp->aux,
+  DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
+   DRM_DEBUG_KMS("Failed to write aux backlight freq\n");
+   return false;
+   }
+   return true;
+}
+
 static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
 {
struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
-   uint8_t dpcd_buf = 0;
-   uint8_t edp_backlight_mode = 0;
+   uint8_t dpcd_buf, new_dpcd_buf, edp_backlight_mode;
 
if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
@@ -110,18 +184,15 @@ static void intel_dp_aux_enable_backlight(struct 
intel_connector *connector)
return;
}
 
+   new_dpcd_buf = dpcd_buf;
edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
 
switch (edp_backlight_mode) {
case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
- 

Re: [Intel-gfx] [PATCH v10 1/3] drm/i915: Add heuristic to determine better way to adjust brightness

[Pandiyan, Dhinakaran]

On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> Add heuristic to decide that AUX or PWM pin should use for
> backlight brightness adjustment and modify i915 param description
> to have auto, force disable, and force enable.
> 
> The heuristic to determine that using AUX pin is better than using
> PWM pin is that the panel support any of the feature list here.
> - Regional backlight brightness adjustment
> - Backlight PWM frequency set
> - More than 8 bits resolution of brightness level
> - Backlight enablement via AUX and not by BL_ENABLE pin
> 
> Signed-off-by: Puthikorn Voravootivat 
> ---
>  drivers/gpu/drm/i915/i915_params.c|  7 +--
>  drivers/gpu/drm/i915/i915_params.h|  2 +-
>  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 64 
> +--
>  3 files changed, 66 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_params.c 
> b/drivers/gpu/drm/i915/i915_params.c
> index b6a7e363d076..3758ae1f11b4 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -63,7 +63,7 @@ struct i915_params i915 __read_mostly = {
>   .huc_firmware_path = NULL,
>   .enable_dp_mst = true,
>   .inject_load_failure = 0,
> - .enable_dpcd_backlight = false,
> + .enable_dpcd_backlight = -1,
>   .enable_gvt = false,
>  };
>  
> @@ -246,9 +246,10 @@ MODULE_PARM_DESC(enable_dp_mst,
>  module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, 
> uint, 0400);
>  MODULE_PARM_DESC(inject_load_failure,
>   "Force an error after a number of failure check points (0:disabled 
> (default), N:force failure at the Nth failure check point)");
> -module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 
> 0600);
> +module_param_named_unsafe(enable_dpcd_backlight, i915.enable_dpcd_backlight, 
> int, 0600);
>  MODULE_PARM_DESC(enable_dpcd_backlight,
> - "Enable support for DPCD backlight control (default:false)");
> + "Enable support for DPCD backlight control "
> + "(-1:auto (default), 0:force disable, 1:force enabled if supported");
>  
>  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
>  MODULE_PARM_DESC(enable_gvt,
> diff --git a/drivers/gpu/drm/i915/i915_params.h 
> b/drivers/gpu/drm/i915/i915_params.h
> index 34148cc8637c..ac02efce6e22 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -66,7 +66,7 @@
>   func(bool, verbose_state_checks); \
>   func(bool, nuclear_pageflip); \
>   func(bool, enable_dp_mst); \
> - func(bool, enable_dpcd_backlight); \
> + func(int, enable_dpcd_backlight); \
>   func(bool, enable_gvt)
>  
>  #define MEMBER(T, member) T member
> diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c 
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> index a0995c00fc84..c89aae804659 100644
> --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> @@ -43,6 +43,9 @@ static void set_aux_backlight_enable(struct intel_dp 
> *intel_dp, bool enable)
>   else
>   reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
>  
> + /* TODO: If the panel also support enabling backlight via BL_ENABLE pin,
> +  * the backlight will be enabled again in _intel_edp_backlight_on()
> +  */

Unrelated hunk, please remove. This should have been included in one of
the previous patches.

>   if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
>  reg_val) != 1) {
>   DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> @@ -168,15 +171,66 @@ intel_dp_aux_display_control_capable(struct 
> intel_connector *connector)
>   /* Check the  eDP Display control capabilities registers to determine if
>* the panel can support backlight control over the aux channel
>*/
> - if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
> - !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) 
> {
> + if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
> + (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
>   DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
>   return true;
>   }
>   return false;
>  }
>  
> +/*
> + * Heuristic function whether we should use AUX for backlight adjustment or 
> not.
> + *
> + * We should use AUX for backlight brightness adjustment if panel doesn't 
> this
> + * via PWM pin or using AUX is better than using PWM pin.
> + *
> + * The heuristic to determine that using AUX pin is better than using PWM 
> pin is
> + * that the panel support any of the feature list here.
> + * - Regional backlight brightness adjustment
> + * - Backlight PWM frequency set
> + * - More than 8 bits resolution of brightness level
> + * - Backlight ena

[PATCH v2 1/3] drm/omap: Support for HDMI hot plug detection

[Peter Ujfalusi]

The HPD signal can be used for detecting HDMI cable plug and unplug event
without the need for polling the status of the line.
This will speed up detecting such event because we do not need to wait for
the next poll event to notice the state change.

Signed-off-by: Peter Ujfalusi 
---
 drivers/gpu/drm/omapdrm/dss/omapdss.h| 17 +++
 drivers/gpu/drm/omapdrm/omap_connector.c | 37 +++-
 drivers/gpu/drm/omapdrm/omap_drv.c   | 29 +
 3 files changed, 82 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h 
b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index b19dae1fd6c5..1f01669eb610 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define DISPC_IRQ_FRAMEDONE(1 << 0)
 #define DISPC_IRQ_VSYNC(1 << 1)
@@ -555,6 +556,14 @@ struct omapdss_hdmi_ops {
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
bool (*detect)(struct omap_dss_device *dssdev);
 
+   int (*register_hpd_cb)(struct omap_dss_device *dssdev,
+  void (*cb)(void *cb_data,
+ enum drm_connector_status status),
+  void *cb_data);
+   void (*unregister_hpd_cb)(struct omap_dss_device *dssdev);
+   void (*enable_hpd)(struct omap_dss_device *dssdev);
+   void (*disable_hpd)(struct omap_dss_device *dssdev);
+
int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
int (*set_infoframe)(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi);
@@ -761,6 +770,14 @@ struct omap_dss_driver {
int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
bool (*detect)(struct omap_dss_device *dssdev);
 
+   int (*register_hpd_cb)(struct omap_dss_device *dssdev,
+  void (*cb)(void *cb_data,
+ enum drm_connector_status status),
+  void *cb_data);
+   void (*unregister_hpd_cb)(struct omap_dss_device *dssdev);
+   void (*enable_hpd)(struct omap_dss_device *dssdev);
+   void (*disable_hpd)(struct omap_dss_device *dssdev);
+
int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi);
diff --git a/drivers/gpu/drm/omapdrm/omap_connector.c 
b/drivers/gpu/drm/omapdrm/omap_connector.c
index c24b6b783e9a..613945c23377 100644
--- a/drivers/gpu/drm/omapdrm/omap_connector.c
+++ b/drivers/gpu/drm/omapdrm/omap_connector.c
@@ -35,6 +35,23 @@ struct omap_connector {
bool hdmi_mode;
 };
 
+static void omap_connector_hpd_cb(void *cb_data,
+ enum drm_connector_status status)
+{
+   struct omap_connector *omap_connector = cb_data;
+   struct drm_connector *connector = &omap_connector->base;
+   struct drm_device *dev = connector->dev;
+   enum drm_connector_status old_status;
+
+   mutex_lock(&dev->mode_config.mutex);
+   old_status = connector->status;
+   connector->status = status;
+   mutex_unlock(&dev->mode_config.mutex);
+
+   if (old_status != status)
+   drm_kms_helper_hotplug_event(dev);
+}
+
 bool omap_connector_get_hdmi_mode(struct drm_connector *connector)
 {
struct omap_connector *omap_connector = to_omap_connector(connector);
@@ -75,6 +92,10 @@ static void omap_connector_destroy(struct drm_connector 
*connector)
struct omap_dss_device *dssdev = omap_connector->dssdev;
 
DBG("%s", omap_connector->dssdev->name);
+   if (connector->polled == DRM_CONNECTOR_POLL_HPD &&
+   dssdev->driver->unregister_hpd_cb) {
+   dssdev->driver->unregister_hpd_cb(dssdev);
+   }
drm_connector_unregister(connector);
drm_connector_cleanup(connector);
kfree(omap_connector);
@@ -216,6 +237,7 @@ struct drm_connector *omap_connector_init(struct drm_device 
*dev,
 {
struct drm_connector *connector = NULL;
struct omap_connector *omap_connector;
+   bool hpd_supported = false;
 
DBG("%s", dssdev->name);
 
@@ -233,7 +255,20 @@ struct drm_connector *omap_connector_init(struct 
drm_device *dev,
connector_type);
drm_connector_helper_add(connector, &omap_connector_helper_funcs);
 
-   if (dssdev->driver->detect)
+   if (dssdev->driver->register_hpd_cb) {
+   int ret = dssdev->driver->register_hpd_cb(dssdev,
+ omap_connector_hpd_cb,
+ omap_connector);
+   if (!ret)
+   hpd_supported = true;
+   else if (ret != 

[PATCH v3 1/6] arm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
Acked-by: Rob Herring 
Acked-by: Chanho Min 
---
v3:
  - Add Acked-by,

v2:
  - Add Acked-by,
  - Rebased.
---
 arch/arm64/boot/dts/lg/lg1312.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi 
b/arch/arm64/boot/dts/lg/lg1312.dtsi
index fbafa24cd5335b90..647606a83c517448 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -123,7 +123,7 @@
amba {
#address-cells = <2>;
#size-cells = <1>;
-   #interrupts-cells = <3>;
+   #interrupt-cells = <3>;
 
compatible = "simple-bus";
interrupt-parent = <&gic>;
-- 
2.7.4

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[PATCH v3 0/6] DT: Fix spelling of standard properties

[Geert Uytterhoeven]

Hi all,

This patch series fixes misspellings of various standard DT properties
in DT binding documentation, DTS files, and examples.
While most of these are harmless, some of them may cause hard-to-debug
failures.

Changes compared to v3:
  - Drop patches that have been applied already,
  - Add Acked-by,
  - Add new patches 5 and 6.

Changes compared to v2:
  - Drop patches that have been applied already,
  - Add Rob Herring's Acked-by,
  - Split off "[PATCH v2 4/6] ASoC: davinci-mcbsp: DT fix
s/interrupts-names/interrupt-names/" from the unrelated "[PATCH 06/14]
dmaengine: bcm2835: DT spelling s/interrupts-names/interrupt-names/",
  - Add new patch "[PATCH v2 3/6] arm64: dts: lg1313: DT fix
s/#interrupts-cells/#interrupt-cells/".

Please apply where appropriate.

Thanks!

P.S. I used the following to detect misspellings:


words="(address|clock|cooling|dma|gpio|index|interrupt|msi|nvmem|phy|phys|power-domain|pwm|reset|size|sleep|sound-dai|thermal-sensor)"

git grep -Ew "${words}s-names"
git grep -E "[^-]\<${words}-name\>[^-]"
git grep -Ew "#${words}s-cells" # false positive phys-cells
git grep -E "#${words}-cell\>[^-]"

git grep -w adress-cells
git grep -Ew "interrupts-(map|parent)"

Geert Uytterhoeven (6):
  arm64: dts: lg1312: DT fix s/#interrupts-cells/#interrupt-cells/
  arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/
  dt: booting-without-of: DT fix s/#interrupt-cell/#interrupt-cells/
  powerpc: dts: acadia: DT fix s/#interrupts-parent/#interrupt-parent/
  dt-bindings: display: amlogic: DT fix s/resets-names/reset-names/
  dt-bindings: net: btusb: DT fix s/interrupt-name/interrupt-names/

 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt | 2 +-
 Documentation/devicetree/bindings/net/btusb.txt | 2 +-
 Documentation/devicetree/booting-without-of.txt | 2 +-
 arch/arm64/boot/dts/lg/lg1312.dtsi  | 2 +-
 arch/arm64/boot/dts/lg/lg1313.dtsi  | 2 +-
 arch/powerpc/boot/dts/acadia.dts| 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH v3 2/6] arm64: dts: lg1313: DT fix s/#interrupts-cells/#interrupt-cells/

[Geert Uytterhoeven]

Signed-off-by: Geert Uytterhoeven 
Acked-by: Chanho Min 
---
v3:
  - Add Acked-by,

v2:
  - New.
---
 arch/arm64/boot/dts/lg/lg1313.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi 
b/arch/arm64/boot/dts/lg/lg1313.dtsi
index e703e1149c757082..abb2162228e82d39 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -123,7 +123,7 @@
amba {
#address-cells = <2>;
#size-cells = <1>;
-   #interrupts-cells = <3>;
+   #interrupt-cells = <3>;
 
compatible = "simple-bus";
interrupt-parent = <&gic>;
-- 
2.7.4

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[PATCH 11/19] drm/sun4i: hdmi: Add A31 specific DDC register definitions

[Chen-Yu Tsai]

The DDC block for the HDMI controller is different on the A31.

This patch adds the register definitions.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi.h | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
index 3a4987ab8da8..08c514672fd3 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -124,6 +124,32 @@
 
 #define SUN4I_HDMI_DDC_FIFO_SIZE   16
 
+/* A31 specific */
+#define SUN6I_HDMI_DDC_CTRL_REG0x500
+#define SUN6I_HDMI_DDC_CTRL_RESET  BIT(31)
+#define SUN6I_HDMI_DDC_CTRL_START_CMD  BIT(27)
+#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6)
+#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4)
+#define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0)
+
+#define SUN6I_HDMI_DDC_CMD_REG 0x508
+#define SUN6I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ  6
+#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count)   ((count) << 16)
+
+#define SUN6I_HDMI_DDC_ADDR_REG0x50c
+#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg)   (((seg) & 0xff) << 24)
+#define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
+#define SUN6I_HDMI_DDC_ADDR_OFFSET(off)(((off) & 0xff) << 8)
+#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr)(((addr) & 0xff) << 1)
+
+#define SUN6I_HDMI_DDC_FIFO_CTRL_REG   0x518
+#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15)
+
+#define SUN6I_HDMI_DDC_CLK_REG 0x520
+/* DDC CLK bit fields are the same, but the formula is not */
+
+#define SUN6I_HDMI_DDC_FIFO_DATA_REG   0x580
+
 enum sun4i_hdmi_pkt_type {
SUN4I_HDMI_PKT_AVI = 2,
SUN4I_HDMI_PKT_END = 15,
-- 
2.11.0

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[PATCH 04/19] drm/sun4i: hdmi: Disable clks in bind function error path and unbind function

[Chen-Yu Tsai]

The HDMI driver enables the bus and mod clocks in the bind function, but
does not disable them if it then bails our due to any errors. Neither
does it disable the clocks in the unbind function.

Fix this by adding a proper error path to the bind function, and
clk_disable_unprepare calls to the unbind function.

Also rename the err_cleanup_connector label to err_cleanup_encoder,
since it is the encoder that gets cleaned up.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 25 +
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index d3398f6250ef..457614073501 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -350,26 +350,29 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
hdmi->mod_clk = devm_clk_get(dev, "mod");
if (IS_ERR(hdmi->mod_clk)) {
dev_err(dev, "Couldn't get the HDMI mod clock\n");
-   return PTR_ERR(hdmi->mod_clk);
+   ret = PTR_ERR(hdmi->mod_clk);
+   goto err_disable_bus_clk;
}
clk_prepare_enable(hdmi->mod_clk);
 
hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
if (IS_ERR(hdmi->pll0_clk)) {
dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
-   return PTR_ERR(hdmi->pll0_clk);
+   ret = PTR_ERR(hdmi->pll0_clk);
+   goto err_disable_mod_clk;
}
 
hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
if (IS_ERR(hdmi->pll1_clk)) {
dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
-   return PTR_ERR(hdmi->pll1_clk);
+   ret = PTR_ERR(hdmi->pll1_clk);
+   goto err_disable_mod_clk;
}
 
ret = sun4i_tmds_create(hdmi);
if (ret) {
dev_err(dev, "Couldn't create the TMDS clock\n");
-   return ret;
+   goto err_disable_mod_clk;
}
 
writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
@@ -410,7 +413,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
ret = sun4i_ddc_create(hdmi, hdmi->tmds_clk);
if (ret) {
dev_err(dev, "Couldn't create the DDC clock\n");
-   return ret;
+   goto err_disable_mod_clk;
}
 
drm_encoder_helper_add(&hdmi->encoder,
@@ -428,7 +431,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
  dev->of_node);
if (!hdmi->encoder.possible_crtcs)
-   return -EPROBE_DEFER;
+   goto err_disable_mod_clk;
 
drm_connector_helper_add(&hdmi->connector,
 &sun4i_hdmi_connector_helper_funcs);
@@ -438,7 +441,7 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
if (ret) {
dev_err(dev,
"Couldn't initialise the HDMI connector\n");
-   goto err_cleanup_connector;
+   goto err_cleanup_encoder;
}
 
/* There is no HPD interrupt, so we need to poll the controller */
@@ -449,8 +452,12 @@ static int sun4i_hdmi_bind(struct device *dev, struct 
device *master,
 
return 0;
 
-err_cleanup_connector:
+err_cleanup_encoder:
drm_encoder_cleanup(&hdmi->encoder);
+err_disable_mod_clk:
+   clk_disable_unprepare(hdmi->mod_clk);
+err_disable_bus_clk:
+   clk_disable_unprepare(hdmi->bus_clk);
return ret;
 }
 
@@ -461,6 +468,8 @@ static void sun4i_hdmi_unbind(struct device *dev, struct 
device *master,
 
drm_connector_cleanup(&hdmi->connector);
drm_encoder_cleanup(&hdmi->encoder);
+   clk_disable_unprepare(hdmi->mod_clk);
+   clk_disable_unprepare(hdmi->bus_clk);
 }
 
 static const struct component_ops sun4i_hdmi_ops = {
-- 
2.11.0

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Re: [Intel-gfx] [PATCH v10 2/3] drm/i915: Add option to support dynamic backlight via DPCD

[Puthikorn Voravootivat]

On Fri, Jun 2, 2017 at 11:25 AM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:

> On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > This patch adds option to enable dynamic backlight for eDP
> > panel that supports this feature via DPCD register and
> > set minimum / maximum brightness to 0% and 100% of the
> > normal brightness.
> >
> > Signed-off-by: Puthikorn Voravootivat 
> > ---
> >  drivers/gpu/drm/i915/i915_params.c|  5 
> >  drivers/gpu/drm/i915/i915_params.h|  3 +-
> >  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 42
> ++-
> >  3 files changed, 41 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> > index 3758ae1f11b4..ce033d58134e 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -65,6 +65,7 @@ struct i915_params i915 __read_mostly = {
> >   .inject_load_failure = 0,
> >   .enable_dpcd_backlight = -1,
> >   .enable_gvt = false,
> > + .enable_dbc = false,
> >  };
> >
> >  module_param_named(modeset, i915.modeset, int, 0400);
> > @@ -254,3 +255,7 @@ MODULE_PARM_DESC(enable_dpcd_backlight,
> >  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
> >  MODULE_PARM_DESC(enable_gvt,
> >   "Enable support for Intel GVT-g graphics virtualization host
> support(default:false)");
> > +
> > +module_param_named_unsafe(enable_dbc, i915.enable_dbc, bool, 0600);
> > +MODULE_PARM_DESC(enable_dbc,
> > + "Enable support for dynamic backlight control (default:false)");
> > diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> > index ac02efce6e22..2de3e2850b54 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -67,7 +67,8 @@
> >   func(bool, nuclear_pageflip); \
> >   func(bool, enable_dp_mst); \
> >   func(int, enable_dpcd_backlight); \
> > - func(bool, enable_gvt)
> > + func(bool, enable_gvt); \
> > + func(bool, enable_dbc)
> >
> >  #define MEMBER(T, member) T member
> >  struct i915_params {
> > diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > index c89aae804659..f55af41ce3bd 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > @@ -100,11 +100,26 @@ intel_dp_aux_set_backlight(struct intel_connector
> *connector, u32 level)
> >   }
> >  }
> >
> > +/*
> > + * Set minimum / maximum dynamic brightness percentage. This value is
> expressed
> > + * as the percentage of normal brightness in 5% increments.
> > + */
> > +static void
> > +intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp,
> > +u32 min, u32 max)
> > +{
> > + u8 dbc[] = { DIV_ROUND_CLOSEST(min, 5), DIV_ROUND_CLOSEST(max, 5)
> };
> > +
> > + if (drm_dp_dpcd_write(&intel_dp->aux,
> DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET,
> > +   dbc, sizeof(dbc)) < 0) {
> > + DRM_DEBUG_KMS("Failed to write aux DBC brightness
> level\n");
> > + }
> > +}
> > +
> >  static void intel_dp_aux_enable_backlight(struct intel_connector
> *connector)
> >  {
> >   struct intel_dp *intel_dp = enc_to_intel_dp(&connector->
> encoder->base);
> > - uint8_t dpcd_buf = 0;
> > - uint8_t edp_backlight_mode = 0;
> > + uint8_t dpcd_buf, new_dpcd_buf, edp_backlight_mode;
> >
> >   if (drm_dp_dpcd_readb(&intel_dp->aux,
> >   DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) !=
> 1) {
> > @@ -113,18 +128,15 @@ static void intel_dp_aux_enable_backlight(struct
> intel_connector *connector)
> >   return;
> >   }
> >
> > + new_dpcd_buf = dpcd_buf;
> >   edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_
> MASK;
> >
> >   switch (edp_backlight_mode) {
> >   case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
> >   case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
> >   case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
> > - dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> > - dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> > - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> > - DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf) <
> 0) {
> > - DRM_DEBUG_KMS("Failed to write aux backlight
> mode\n");
> > - }
> > + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> > + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> >   break;
> >
> >   /* Do nothing when it is already DPCD mode */
> > @@ -133,6 +145,20 @@ static void intel_dp_aux_enable_backlight(struct
> intel_connector *connector)
> >   break;
> >   }
> >
> > + if (i915.enable_dbc &&
> > + (intel_dp->edp_dpcd[2] & DP_EDP_DYNAMIC_BACKLIGHT_CAP)) {
> >

[PATCH 09/19] drm/sun4i: hdmi: Support different variants of the DDC clock

[Chen-Yu Tsai]

On the A31, the HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.

This patch adds support for different variants of the DDC clock.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 42 --
 1 file changed, 34 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
index 4692e8c345ed..e1071838f487 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
@@ -15,9 +15,16 @@
 #include "sun4i_tcon.h"
 #include "sun4i_hdmi.h"
 
+struct sun4i_ddc_variant {
+   u32 reg_offset;
+   u8  pre_divider;
+   u8  m_offset;
+};
+
 struct sun4i_ddc {
struct clk_hw   hw;
struct sun4i_hdmi   *hdmi;
+   const struct sun4i_ddc_variant  *variant;
 };
 
 static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
@@ -27,6 +34,7 @@ static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
 
 static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
unsigned long parent_rate,
+   const struct sun4i_ddc_variant 
*variant,
u8 *m, u8 *n)
 {
unsigned long best_rate = 0;
@@ -36,7 +44,8 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long 
rate,
for (_n = 0; _n < 8; _n++) {
unsigned long tmp_rate;
 
-   tmp_rate = (((parent_rate / 2) / 10) >> _n) / (_m + 1);
+   tmp_rate = (((parent_rate / variant->pre_divider) /
+10) >> _n) / (_m + variant->m_offset);
 
if (tmp_rate > rate)
continue;
@@ -60,7 +69,9 @@ static unsigned long sun4i_ddc_calc_divider(unsigned long 
rate,
 static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
 unsigned long *prate)
 {
-   return sun4i_ddc_calc_divider(rate, *prate, NULL, NULL);
+   struct sun4i_ddc *ddc = hw_to_ddc(hw);
+
+   return sun4i_ddc_calc_divider(rate, *prate, ddc->variant, NULL, NULL);
 }
 
 static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
@@ -70,11 +81,12 @@ static unsigned long sun4i_ddc_recalc_rate(struct clk_hw 
*hw,
u32 reg;
u8 m, n;
 
-   reg = readl(ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
-   m = (reg >> 3) & 0x7;
+   reg = readl(ddc->hdmi->base + ddc->variant->reg_offset);
+   m = (reg >> 3) & 0xf;
n = reg & 0x7;
 
-   return (((parent_rate / 2) / 10) >> n) / (m + 1);
+   return (((parent_rate / ddc->variant->pre_divider) / 10) >> n) /
+  (m + ddc->variant->m_offset);
 }
 
 static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -83,10 +95,11 @@ static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned 
long rate,
struct sun4i_ddc *ddc = hw_to_ddc(hw);
u8 div_m, div_n;
 
-   sun4i_ddc_calc_divider(rate, parent_rate, &div_m, &div_n);
+   sun4i_ddc_calc_divider(rate, parent_rate, ddc->variant,
+  &div_m, &div_n);
 
writel(SUN4I_HDMI_DDC_CLK_M(div_m) | SUN4I_HDMI_DDC_CLK_N(div_n),
-  ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
+  ddc->hdmi->base + ddc->variant->reg_offset);
 
return 0;
 }
@@ -97,7 +110,8 @@ static const struct clk_ops sun4i_ddc_ops = {
.set_rate   = sun4i_ddc_set_rate,
 };
 
-int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
+static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent,
+const struct sun4i_ddc_variant *variant)
 {
struct clk_init_data init;
struct sun4i_ddc *ddc;
@@ -117,6 +131,7 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
*parent)
init.num_parents = 1;
 
ddc->hdmi = hdmi;
+   ddc->variant = variant;
ddc->hw.init = &init;
 
hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);
@@ -125,3 +140,14 @@ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk 
*parent)
 
return 0;
 }
+
+static const struct sun4i_ddc_variant sun4i_variant = {
+   .reg_offset = SUN4I_HDMI_DDC_CLK_REG,
+   .pre_divider= 2,
+   .m_offset   = 1,
+};
+
+int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
+{
+   return _sun4i_ddc_create(hdmi, parent, &sun4i_variant);
+}
-- 
2.11.0

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[PATCH v11 0/3] Enhancement to intel_dp_aux_backlight driver

[Puthikorn Voravootivat]

This patch set contain 3 patches. Another 6 patches in previous version
was already merged in v7 and v9.
- First patch sets the PWM freqency to match data in panel vbt.
- Next patch adds heuristic to determine whether we should use AUX
  or PWM pin to adjust panel backlight brightness.
- Last patch adds support for dynamic brightness.

Change log:
v11:
- Reorder patches in v10 to make the last patch come first
- Fix nits

v10:
- Add heuristic in patch #1
- Add _unsafe mod option in patch #1, #2
- handle frequency set error in patch #3

v9:
- Fix nits in v8

v8:
- Drop 4 patches that was already merged
- Move DP_EDP_BACKLIGHT_AUX_ENABLE_CAP check to patch #2 to avoid
  behavior change if only apply patch #1
- Add TODO to warn about enable backlight twice in patch #2
- Use DIV_ROUND_CLOSEST instead of just "/" in patch #5
- Fix bug calculate pn in patch #5
- Clarify commit  message / code comment in patch #5

v7:
- Add check in intel_dp_pwm_pin_display_control_capable in patch #4
- Add option in patch #6 to enable DPCD or not
- Change definition in patch #8 and implementation in #9 to use Khz
- Fix compiler warning from build bot in patch #9

v6:
- Address review from Dhinakaran
- Make PWM frequency to have highest value of Pn that make the
  frequency still within 25% of desired frequency.

v5:
- Split first patch in v4 to 3 patches
- Bump priority for "Correctly enable backlight brightness adjustment via DPCD"
- Make logic clearer for the case that both PWM pin and AUX are supported
- Add more log when write to register fail
- Add log when enable DBC

v4:
- Rebase / minor typo fix.

v3:
- Add new implementation of PWM frequency patch

v2:
- Drop PWM frequency patch
- Address suggestion from Jani Nikula

Puthikorn Voravootivat (3):
  drm/i915: Set PWM divider to match desired frequency in vbt
  drm/i915: Add heuristic to determine better way to adjust brightness
  drm/i915: Add option to support dynamic backlight via DPCD

 drivers/gpu/drm/i915/i915_params.c|  12 +-
 drivers/gpu/drm/i915/i915_params.h|   5 +-
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 185 --
 3 files changed, 186 insertions(+), 16 deletions(-)

-- 
2.13.0.506.g27d5fe0cd-goog

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[PATCH 00/19] drm/sun4i: hdmi: Support HDMI controller on A31

[Chen-Yu Tsai]

Hi everyone,

This series adds support for the HDMI controller found on Allwinner
A31/A31s SoCs. It builds upon Maxime's work that added support for
the HDMI controller on the Allwinner A10s SoC.

The HDMI controllers in the older generation Allwinner SoCs is very
similar. The A10/A10s/A20 all have the same hardware block, with the
A10 having slightly different initial configuration values. The A31's
variant splits out the DDC parent clock, has different formulas for
the DDC and TMDS clocks, and a different register layout for the DDC
block. Also, it does not expose the CEC pins outside of the SoC, which
is unfortunate.

The first 2 patches allow the sun4i-drm driver to work correctly with
2 display pipelines.

Patch 3 adds support for the TCON demuxing feature on the A31. This is
needed if the user wants to output through HDMI from the second display
pipeline.

Patch 4 adds proper error path cleanup to the HDMI driver.

Patch 5 allows the HDMI TMDS clock to use the second PLL as its parent,
in case the first PLL is driving an incompatible dot clock.

Patch 6 adds the A31 HDMI controller variant to the device tree binding.

Patch 7 adds support for different variants of the TMDS clock, with the
different being an offset value for the divider.

Patch 8 adds support for the A31's TMDS clock variant.

Patch 9 adds support for different variants of the DDC clock, with the
differences being a different register offset, different divider offset,
different pre-divider, and different clock parent.

Patch 10 renames the HDMI block's DDC clock, so that it doesn't conflict
with the A31's SoC level HDMI DDC clock.

Patch 11 adds defines for the A31 specific DDC register offsets.

Patch 12 adds support for the A31's DDC clock variant.

Patch 13 adds support for different variants of the HDMI controller
hardware, with the differences mentioned in the beginning of this
letter.

Patch 14 adds support for the A31's HDMI controller variant.

Patch 15 exports the 2x outputs of the two video PLLs. These feed the
TMDS clock directly.

Patch 16 adds a device node for the HDMI controller on the A31.

Patches 17~19 enable HDMI video output on three boards that I have.


Patches 13 & 14 are somewhat complicated. If the DDC block were factored
out into a proper I2C controller, it might be cleaner. Other than that
this series should be quite straightforward.

I also had simultaneous output on both display pipelines on the SinA31s,
one with an LCD panel and the other using HDMI. After boot, both screens
showed a proper console. The HDMI screen had higher resolution, so the
console was limited to the upper left corner.


Regards
ChenYu

Chen-Yu Tsai (19):
  drm/sun4i: call drm_vblank_init with correct number of crtcs
  drm/sun4i: add components in two passes with encoders added in second
pass
  drm/sun4i: tcon: Add support for demuxing TCON output on A31
  drm/sun4i: hdmi: Disable clks in bind function error path and unbind
function
  drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent
  dt-bindings: display: sun4i: Add binding for A31 HDMI controller
  drm/sun4i: hdmi: Support different variants of the TMDS clock
  drm/sun4i: hdmi: Support the TMDS clock in the A31's HDMI controller
  drm/sun4i: hdmi: Support different variants of the DDC clock
  drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision
  drm/sun4i: hdmi: Add A31 specific DDC register definitions
  drm/sun4i: hdmi: Support the DDC clock in the A31's HDMI controller
  drm/sun4i: hdmi: Add support for controller hardware variants
  drm/sun4i: hdmi: Add support for A31's HDMI controller
  clk: sunxi-ng: sun6i: Export video PLLs
  ARM: sun6i: a31: Add device node for HDMI controller
  ARM: sun6i: a31: Enable HDMI support on the A31 Hummingbird
  ARM: sun6i: a31s: Enable HDMI display output on the Sinlinx SinA31s
  ARM: sun6i: a31s: Enable HDMI display output on the MSI Primo81 tablet

 .../bindings/display/sunxi/sun4i-drm.txt   |   3 +
 arch/arm/boot/dts/sun6i-a31-hummingbird.dts|  21 ++
 arch/arm/boot/dts/sun6i-a31.dtsi   |  55 
 arch/arm/boot/dts/sun6i-a31s-primo81.dts   |  25 ++
 arch/arm/boot/dts/sun6i-a31s-sina31s.dts   |  25 ++
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   |   2 +-
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   8 +-
 drivers/gpu/drm/sun4i/sun4i_drv.c  |  34 ++-
 drivers/gpu/drm/sun4i/sun4i_hdmi.h |  39 +++
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c |  55 +++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 280 ++---
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c|  82 +++---
 drivers/gpu/drm/sun4i/sun4i_tcon.c |  61 +
 include/dt-bindings/clock/sun6i-a31-ccu.h  |   4 +
 14 files changed, 613 insertions(+), 81 deletions(-)

-- 
2.11.0

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[PATCH 15/19] clk: sunxi-ng: sun6i: Export video PLLs

[Chen-Yu Tsai]

The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.

Export them so they can be referenced in the device tree.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h  | 8 ++--
 include/dt-bindings/clock/sun6i-a31-ccu.h | 4 
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
index 4e434011e9e7..27e6ad4133ab 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
@@ -27,7 +27,9 @@
 #define CLK_PLL_AUDIO_4X   4
 #define CLK_PLL_AUDIO_8X   5
 #define CLK_PLL_VIDEO0 6
-#define CLK_PLL_VIDEO0_2X  7
+
+/* The PLL_VIDEO0_2X clock is exported */
+
 #define CLK_PLL_VE 8
 #define CLK_PLL_DDR9
 
@@ -35,7 +37,9 @@
 
 #define CLK_PLL_PERIPH_2X  11
 #define CLK_PLL_VIDEO1 12
-#define CLK_PLL_VIDEO1_2X  13
+
+/* The PLL_VIDEO1_2X clock is exported */
+
 #define CLK_PLL_GPU14
 #define CLK_PLL_MIPI   15
 #define CLK_PLL9   16
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h 
b/include/dt-bindings/clock/sun6i-a31-ccu.h
index 4482530fb6f5..c5d13340184a 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -43,8 +43,12 @@
 #ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
 #define _DT_BINDINGS_CLK_SUN6I_A31_H_
 
+#define CLK_PLL_VIDEO0_2X  7
+
 #define CLK_PLL_PERIPH 10
 
+#define CLK_PLL_VIDEO1_2X  13
+
 #define CLK_CPU18
 
 #define CLK_AHB1_MIPIDSI   23
-- 
2.11.0

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Re: [PATCH v2 3/5] drm/bridge/synopsys: Add MIPI DSI host controller bridge

[Philippe CORNU]

On 05/25/2017 01:23 PM, Archit Taneja wrote:
> Hi Philippe,
> 
> Thanks a lot for creating a bridge driver for this.
> 
> Copying some Hisilicon and Rockchip folks so that they can consider adapting 
> to this.
> 
> Some comments below.
Hi Archit,
and many thanks for your great comments.

> 
> On 05/19/2017 08:50 PM, Philippe CORNU wrote:
>> Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
>> Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>>
>> Signed-off-by: Philippe CORNU 
>> ---
>>   drivers/gpu/drm/bridge/synopsys/Kconfig   |9 +
>>   drivers/gpu/drm/bridge/synopsys/Makefile  |2 +
>>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 1024 
>> +
>>   3 files changed, 1035 insertions(+)
>>   create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>
>> diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
>> b/drivers/gpu/drm/bridge/synopsys/Kconfig
>> index 40d2827..d7fbdff 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
>> +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
>> @@ -21,3 +21,12 @@ config DRM_DW_HDMI_I2S_AUDIO
>>  help
>>Support the I2S Audio interface which is part of the Synopsys
>>Designware HDMI block.
>> +
>> +config DRM_DW_MIPI_DSI
>> +tristate "Synopsys DesignWare MIPI DSI host controller bridge"
>> +select DRM_KMS_HELPER
>> +select DRM_MIPI_DSI
>> +select DRM_PANEL
>> +help
>> +  Choose this if you want to use the Synopsys DesignWare MIPI DSI host
>> +  controller bridge.
>> diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile 
>> b/drivers/gpu/drm/bridge/synopsys/Makefile
>> index 17aa7a6..5f57d36 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/Makefile
>> +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
>> @@ -3,3 +3,5 @@
>>   obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>>   obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>> +
>> +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> new file mode 100644
>> index 000..041f564
>> --- /dev/null
>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> @@ -0,0 +1,1024 @@
>> +/*
>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * Modified by Philippe Cornu 
>> + * This generic Synopsys Designware MIPI DSI host driver is based on the
>> + * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define DSI_VERSION 0x00
>> +#define DSI_PWR_UP  0x04
>> +#define RESET   0
>> +#define POWERUP BIT(0)
>> +
>> +#define DSI_CLKMGR_CFG  0x08
>> +#define TO_CLK_DIVIDSION(div)   (((div) & 0xff) << 8)
>> +#define TX_ESC_CLK_DIVIDSION(div)   (((div) & 0xff) << 0)
>> +
>> +#define DSI_DPI_VCID0x0c
>> +#define DPI_VID(vid)(((vid) & 0x3) << 0)
>> +
>> +#define DSI_DPI_COLOR_CODING0x10
>> +#define EN18_LOOSELYBIT(8)
>> +#define DPI_COLOR_CODING_16BIT_10x0
>> +#define DPI_COLOR_CODING_16BIT_20x1
>> +#define DPI_COLOR_CODING_16BIT_30x2
>> +#define DPI_COLOR_CODING_18BIT_10x3
>> +#define DPI_COLOR_CODING_18BIT_20x4
>> +#define DPI_COLOR_CODING_24BIT  0x5
>> +
>> +#define DSI_DPI_CFG_POL 0x14
>> +#define COLORM_ACTIVE_LOW   BIT(4)
>> +#define SHUTD_ACTIVE_LOWBIT(3)
>> +#define HSYNC_ACTIVE_LOWBIT(2)
>> +#define VSYNC_ACTIVE_LOWBIT(1)
>> +#define DATAEN_ACTIVE_LOW   BIT(0)
>> +
>> +#define DSI_DPI_LP_CMD_TIM  0x18
>> +#define OUTVACT_LPCMD_TIME(p)   (((p) & 0xff) << 16)
>> +#define INVACT_LPCMD_TIME(p)((p) & 0xff)
>> +
>> +#define DSI_DBI_CFG 0x20
>> +#define DSI_DBI_CMDSIZE 0x28
>> +
>> +#define DSI_PCKHDL_CFG  0x2c
>> +#define EN_CRC_RX   BIT(4)
>> +#define EN_ECC_RX   BIT(3)
>> +#define EN_BTA  BIT(2)
>> +#define EN_EOTP_RX  BIT(1)
>> +#define EN_EOTP_TX  BIT(0)
>> +
>> +#define DSI_MODE_CFG0x34
>> +#define ENABLE_VIDEO_MODE   0
>> +#define ENABLE_CMD_MODE

Re: [Intel-gfx] [PATCH v10 1/3] drm/i915: Add heuristic to determine better way to adjust brightness

[Puthikorn Voravootivat]

On Fri, Jun 2, 2017 at 10:56 AM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:

> On Fri, 2017-06-02 at 17:42 +, Pandiyan, Dhinakaran wrote:
>
> Somehow the CC's got removed in my previous reply, adding them back. See
> one additional comment below.
>
>
> > On Fri, 2017-05-26 at 18:42 -0700, Puthikorn Voravootivat wrote:
> > > Add heuristic to decide that AUX or PWM pin should use for
> > > backlight brightness adjustment and modify i915 param description
> > > to have auto, force disable, and force enable.
> > >
> > > The heuristic to determine that using AUX pin is better than using
> > > PWM pin is that the panel support any of the feature list here.
> > > - Regional backlight brightness adjustment
> > > - Backlight PWM frequency set
> > > - More than 8 bits resolution of brightness level
> > > - Backlight enablement via AUX and not by BL_ENABLE pin
> > >
> > > Signed-off-by: Puthikorn Voravootivat 
> > > ---
> > >  drivers/gpu/drm/i915/i915_params.c|  7 +--
> > >  drivers/gpu/drm/i915/i915_params.h|  2 +-
> > >  drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 64
> +--
> > >  3 files changed, 66 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> > > index b6a7e363d076..3758ae1f11b4 100644
> > > --- a/drivers/gpu/drm/i915/i915_params.c
> > > +++ b/drivers/gpu/drm/i915/i915_params.c
> > > @@ -63,7 +63,7 @@ struct i915_params i915 __read_mostly = {
> > > .huc_firmware_path = NULL,
> > > .enable_dp_mst = true,
> > > .inject_load_failure = 0,
> > > -   .enable_dpcd_backlight = false,
> > > +   .enable_dpcd_backlight = -1,
> > > .enable_gvt = false,
> > >  };
> > >
> > > @@ -246,9 +246,10 @@ MODULE_PARM_DESC(enable_dp_mst,
> > >  module_param_named_unsafe(inject_load_failure,
> i915.inject_load_failure, uint, 0400);
> > >  MODULE_PARM_DESC(inject_load_failure,
> > > "Force an error after a number of failure check points (0:disabled
> (default), N:force failure at the Nth failure check point)");
> > > -module_param_named(enable_dpcd_backlight,
> i915.enable_dpcd_backlight, bool, 0600);
> > > +module_param_named_unsafe(enable_dpcd_backlight,
> i915.enable_dpcd_backlight, int, 0600);
> > >  MODULE_PARM_DESC(enable_dpcd_backlight,
> > > -   "Enable support for DPCD backlight control (default:false)");
> > > +   "Enable support for DPCD backlight control "
> > > +   "(-1:auto (default), 0:force disable, 1:force enabled if
> supported");
> > >
> > >  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
> > >  MODULE_PARM_DESC(enable_gvt,
> > > diff --git a/drivers/gpu/drm/i915/i915_params.h
> b/drivers/gpu/drm/i915/i915_params.h
> > > index 34148cc8637c..ac02efce6e22 100644
> > > --- a/drivers/gpu/drm/i915/i915_params.h
> > > +++ b/drivers/gpu/drm/i915/i915_params.h
> > > @@ -66,7 +66,7 @@
> > > func(bool, verbose_state_checks); \
> > > func(bool, nuclear_pageflip); \
> > > func(bool, enable_dp_mst); \
> > > -   func(bool, enable_dpcd_backlight); \
> > > +   func(int, enable_dpcd_backlight); \
>
>
> Please move this above the bools, see comment in code that's a few lines
> above.
>
> Will do


> -DK
>
> > > func(bool, enable_gvt)
> > >
> > >  #define MEMBER(T, member) T member
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > index a0995c00fc84..c89aae804659 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > @@ -43,6 +43,9 @@ static void set_aux_backlight_enable(struct
> intel_dp *intel_dp, bool enable)
> > > else
> > > reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> > >
> > > +   /* TODO: If the panel also support enabling backlight via
> BL_ENABLE pin,
> > > +* the backlight will be enabled again in _intel_edp_backlight_on()
> > > +*/
> >
> > Unrelated hunk, please remove. This should have been included in one of
> > the previous patches.
>
Removed


> >
> > > if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_
> REGISTER,
> > >reg_val) != 1) {
> > > DRM_DEBUG_KMS("Failed to %s aux backlight\n",
> > > @@ -168,15 +171,66 @@ intel_dp_aux_display_control_capable(struct
> intel_connector *connector)
> > > /* Check the  eDP Display control capabilities registers to
> determine if
> > >  * the panel can support backlight control over the aux channel
> > >  */
> > > -   if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP
> &&
> > > -   (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
> &&
> > > -   !(intel_dp->edp_dpcd[2] & 
> > > DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))
> {
> > > +   if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP)
> &&
> > > +   (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP))
> {
> > > DRM_DEBUG

[PATCH v2 0/3] drm/omap: Support for hotplug detection

[Peter Ujfalusi]

Hi,

Changes since v1:
- proper locking within omap_connector_hpd_cb()
- include the correct linux/mutex.h in omap_connector and tpd driver.

this series will add support for HPD in omapdrm. Instead of polling for HPD
changes we can use interrupts to be notified of HPD change, thus we can react to
events faster.

The series is based on top of 4.12-rc3

Regards,
Peter
---
Peter Ujfalusi (3):
  drm/omap: Support for HDMI hot plug detection
  drm/omap: displays: connector-hdmi: Support for hot plug detection
  drm/omap: displays: encoder-tpd12s015: Support for hot plug detection

 drivers/gpu/drm/omapdrm/displays/connector-hdmi.c  | 104 +
 .../gpu/drm/omapdrm/displays/encoder-tpd12s015.c   |  81 
 drivers/gpu/drm/omapdrm/dss/omapdss.h  |  17 
 drivers/gpu/drm/omapdrm/omap_connector.c   |  37 +++-
 drivers/gpu/drm/omapdrm/omap_drv.c |  29 ++
 5 files changed, 267 insertions(+), 1 deletion(-)

-- 
2.13.0

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[PATCH 16/19] ARM: sun6i: a31: Add device node for HDMI controller

[Chen-Yu Tsai]

Now that we support the HDMI controller on the A31 SoC, we can add it
to the device tree.

This adds a device node for the HDMI controller, and the of_graph nodes
connecting it to the 2 TCONs.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 55 
 1 file changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index d0cede5aaeb5..36bfb6ad6578 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -284,6 +284,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+   tcon0_out_hdmi: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<&hdmi_in_tcon0>;
+   allwinner,tcon-channel = <1>;
+   };
};
};
};
@@ -321,6 +327,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+   tcon1_out_hdmi: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<&hdmi_in_tcon1>;
+   allwinner,tcon-channel = <1>;
+   };
};
};
};
@@ -401,6 +413,49 @@
#size-cells = <0>;
};
 
+   hdmi: hdmi@01c16000 {
+   compatible = "allwinner,sun6i-a31-hdmi";
+   reg = <0x01c16000 0x1000>;
+   interrupts = ;
+   clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
+<&ccu CLK_HDMI_DDC>,
+<&ccu CLK_PLL_VIDEO0_2X>,
+<&ccu CLK_PLL_VIDEO1_2X>;
+   clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
+   resets = <&ccu RST_AHB1_HDMI>;
+   reset-names = "ahb";
+   dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+   dmas = <&dma 13>, <&dma 13>, <&dma 14>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   hdmi_in: port@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0>;
+
+   hdmi_in_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<&tcon0_out_hdmi>;
+   };
+
+   hdmi_in_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<&tcon1_out_hdmi>;
+   };
+   };
+
+   hdmi_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+   };
+   };
+   };
+
usb_otg: usb@01c19000 {
compatible = "allwinner,sun6i-a31-musb";
reg = <0x01c19000 0x0400>;
-- 
2.11.0

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[PATCH 19/19] ARM: sun6i: a31s: Enable HDMI display output on the MSI Primo81 tablet

[Chen-Yu Tsai]

The MSI Primo81 tablet has a micro HDMI connector at the bottom.
This is connected to the SoCs HDMI output.

Enable the display pipeline and the HDMI output.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31s-primo81.dts | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts 
b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index f3712753fa42..26154b2f87a3 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -52,17 +52,42 @@
 / {
model = "MSI Primo81 tablet";
compatible = "msi,primo81", "allwinner,sun6i-a31s";
+
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "c";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
 };
 
 &cpu0 {
cpu-supply = <®_dcdc3>;
 };
 
+&de {
+   status = "okay";
+};
+
 &ehci0 {
/* rtl8188etv wifi is connected here */
status = "okay";
 };
 
+&hdmi {
+   status = "okay";
+};
+
+&hdmi_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <&hdmi_con_in>;
+   };
+};
+
 &i2c0 {
/* pull-ups and device VDDIO use AXP221 DLDO3 */
pinctrl-names = "default";
-- 
2.11.0

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[PATCH 18/19] ARM: sun6i: a31s: Enable HDMI display output on the Sinlinx SinA31s

[Chen-Yu Tsai]

The Sinlinx SinA31s has an HDMI connector wired to the HDMI pins
from the SoC.

Enable the display pipeline and the HDMI output.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts 
b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index b3d98222bd81..298476485bb4 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -53,6 +53,17 @@
stdout-path = "serial0:115200n8";
};
 
+   hdmi-connector {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con_in: endpoint {
+   remote-endpoint = <&hdmi_out_con>;
+   };
+   };
+   };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -90,6 +101,10 @@
status = "okay";
 };
 
+&de {
+   status = "okay";
+};
+
 &ehci0 {
/* USB 2.0 4 port hub IC */
status = "okay";
@@ -112,6 +127,16 @@
};
 };
 
+&hdmi {
+   status = "okay";
+};
+
+&hdmi_out {
+   hdmi_out_con: endpoint {
+   remote-endpoint = <&hdmi_con_in>;
+   };
+};
+
 &ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
-- 
2.11.0

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[PATCH 02/19] drm/sun4i: add components in two passes with encoders added in second pass

[Chen-Yu Tsai]

The encoder drivers use drm_of_find_possible_crtcs to get upstream
crtcs from the device tree using of_graph. For the results to be
correct, encoders must be probed/bound after _all_ crtcs have been
created. The existing code uses a depth first recursive traversal
of the of_graph, which means the encoders downstream of the TCON
get add right after the first TCON. The second TCON or CRTC will
never be properly associated with encoders connected to it.

Other platforms, such as Rockchip, deal with this by probing all
crtcs first, then all subsequent components. This is easy to do
since the crtcs correspond to just one device node, and are the
first nodes in the pipeline.

However with Allwinner SoCs, the function of the CRTC is split between
the display backend (DE 1.0) or mixer (DE 2.0), which does scan-out
and compositing, and the TCON, which generating the display timing
signals. Further complicating the process, there may be a Dynamic Range
Controller between the backend and the TCON. Also, the backend is
preceded by the frontend, with a Display Enhancement Unit possibly
in between.

One solution would be, instead of a depth first traversal of the
component of_graph, we do a breadth first traversal, so that components
at the same depth are grouped together. This however requires us to
implement extra code for a queue structure that is only used here.

Instead, since we can identify TCON device nodes, and since the
component system can gracefully deal with duplicate entries, we can add
components in two passes, using the existing recursive depth code. The
first pass stops right after the TCON is added. The second pass will
re-add all components up to the TCON, but these will be skipped since
they will have already been bound with the entries from the first pass.
The encoders added in the second pass will be the last entries in the
list.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 24 
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c 
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index ed75a779ae4b..bc13dcf06783 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -198,7 +198,8 @@ static int compare_of(struct device *dev, void *data)
 
 static int sun4i_drv_add_endpoints(struct device *dev,
   struct component_match **match,
-  struct device_node *node)
+  struct device_node *node,
+  bool add_encoders)
 {
struct device_node *port, *ep, *remote;
int count = 0;
@@ -227,13 +228,16 @@ static int sun4i_drv_add_endpoints(struct device *dev,
count++;
}
 
+   /* Skip downstream encoders during the first pass */
+   if (sun4i_drv_node_is_tcon(node) && !add_encoders)
+   return count;
+
/* Inputs are listed first, then outputs */
port = of_graph_get_port_by_id(node, 1);
if (!port) {
DRM_DEBUG_DRIVER("No output to bind\n");
return count;
}
-
for_each_available_child_of_node(port, ep) {
remote = of_graph_get_remote_port_parent(ep);
if (!remote) {
@@ -262,7 +266,8 @@ static int sun4i_drv_add_endpoints(struct device *dev,
}
 
/* Walk down our tree */
-   count += sun4i_drv_add_endpoints(dev, match, remote);
+   count += sun4i_drv_add_endpoints(dev, match, remote,
+add_encoders);
 
of_node_put(remote);
}
@@ -283,8 +288,19 @@ static int sun4i_drv_probe(struct platform_device *pdev)
if (!pipeline)
break;
 
+   sun4i_drv_add_endpoints(&pdev->dev, &match, pipeline, false);
+   of_node_put(pipeline);
+   }
+
+   for (i = 0;; i++) {
+   struct device_node *pipeline = of_parse_phandle(np,
+   
"allwinner,pipelines",
+   i);
+   if (!pipeline)
+   break;
+
count += sun4i_drv_add_endpoints(&pdev->dev, &match,
-   pipeline);
+pipeline, true);
of_node_put(pipeline);
 
DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n",
-- 
2.11.0

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Kernel panic on nouveau during boot on NVIDIA NV118 (GM108)

[Chris Chiu]

We are working with new desktop that have the NVIDIA NV118
chipset.

During boot, the display becomes unusable at the point where the
nouveau driver loads. We have reproduced on 4.8, 4.11 and linux
master (4.12-rc3).

Dmesg log is attached.

Is this a known issue? Anything we can do to help?

Thanks


Bristol195i_dmesg.log
Description: Binary data
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Re: [PATCH 4/4] drm/bridge: dw-hdmi: add cec driver

[Russell King - ARM Linux]

On Fri, Jun 02, 2017 at 06:02:28AM +0100, Jose Abreu wrote:
> You should check that CEC is: not in standy, acknowledges
> broadcast messages, signal free time is 5bit period, and not lost
> arbitration, which basically means CEC_CTRL must be 0x2 and
> IH_CEC_STAT0 must not have ARB_LOST set.

If ARB_LOST is set, that will trigger an interrupt, and the interrupt
handler will clear the bit.  So all the time that the interrupt handler
is present, ARB_LOST should be clear whenever we try to send a message.

When we enable the CEC interface, we zero the CEC_CTRL register, which
takes the controller out of standby, and initialises the command
register.

Bits 2:1 select the signal free time, and there's no requirement
specified to require them to be set to '01' before writing the
message - in fact, it's legal for them to be set to other values,
particularly when retrying, which is something I've missed.

 2-1 Frame Type bit
  FRAME_TYP
 00Signal Free Time = 3-bit periods. Previous
   attempt to send frame is unsuccessful.
 01Signal Free Time = 5-bit periods. New initiator
   wants to send a frame.
 10Signal Free Time = 7-bit periods. Present
   initiator wants to send another frame
   immediately after its previous frame. (spec
   CEC 9.1)
 11Illegal value. If software write this value,
   hardware will set the value to the default 2'b01.

Clearly from that, there are times when we want to transmit a message
without a 5-bit signal free time period, particularly when we're
retrying or wanting to send another frame, so I don't believe that
there's a requirement for the control register to always be set to
0x02.  I suspect that where that value is coming from is an application
note describing how to send a brand new message each time, and not
covering the other cases.

It could be that we need to set the frame type before loading the
message - that I'll buy, but not that it must always be set to 0x02.

Provided that the standby and BC_NACK bits are both cleared should
be sufficient.

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Re: [PATCH 4/4] drm/bridge: dw-hdmi: add cec driver

[Russell King - ARM Linux]

On Thu, Jun 01, 2017 at 10:31:10AM +0200, Hans Verkuil wrote:
> This will change. Patches to fix the config handling are pending for 4.12.
> 
> Here you can see the pending patches:
> https://git.linuxtv.org/hverkuil/media_tree.git/log/?h=drm-cec
> 
> The patches from 'cec-notifier.h: handle unreachable CONFIG_CEC_CORE' to
> 'cec: drop MEDIA_CEC_DEBUG' should all be merged in 4.12.

Hi Hans,

I'll wait until these have hit mainline before generating another
patch series.  Do you have any idea when that might happen?

Thanks.

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Re: [PATCH 4/4] drm/bridge: dw-hdmi: add cec driver

[Russell King - ARM Linux]

On Fri, Jun 02, 2017 at 11:06:24AM +0200, Hans Verkuil wrote:
> On 06/02/17 08:43, Jose Abreu wrote:
> > Hi Hans,
> > 
> > 
> > On 02-06-2017 07:31, Hans Verkuil wrote:
> >> On 06/01/2017 03:47 PM, Neil Armstrong wrote:
> >>> On 05/30/2017 04:23 PM, Russell King wrote:
>  Add a CEC driver for the dw-hdmi hardware.
> 
>  Signed-off-by: Russell King 
>  ---
>    drivers/gpu/drm/bridge/synopsys/Kconfig   |   8 +
>    drivers/gpu/drm/bridge/synopsys/Makefile  |   1 +
>    drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 320
>  ++
>    drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.h |  19 ++
>    drivers/gpu/drm/bridge/synopsys/dw-hdmi.c |  40 +++-
>    5 files changed, 387 insertions(+), 1 deletion(-)
>    create mode 100644
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
>    create mode 100644
>  drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.h
> 
>  diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig
>  b/drivers/gpu/drm/bridge/synopsys/Kconfig
>  index 40d2827a6d19..bd30a0a07272 100644
>  --- a/drivers/gpu/drm/bridge/synopsys/Kconfig
>  +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
>  @@ -21,3 +21,11 @@ config DRM_DW_HDMI_I2S_AUDIO
>    help
>  Support the I2S Audio interface which is part of the
>  Synopsys
>  Designware HDMI block.
>  +
>  +config DRM_DW_HDMI_CEC
>  +tristate "Synopsis Designware CEC interface"
>  +depends on DRM_DW_HDMI && MEDIA_CEC_SUPPORT
>  +select MEDIA_CEC_NOTIFIER
>  +help
>  +  Support the CE interface which is part of the Synopsis
>  +  Designware HDMI block.
>  diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile
>  b/drivers/gpu/drm/bridge/synopsys/Makefile
>  index 17aa7a65b57e..6fe415903668 100644
>  --- a/drivers/gpu/drm/bridge/synopsys/Makefile
>  +++ b/drivers/gpu/drm/bridge/synopsys/Makefile
>  @@ -3,3 +3,4 @@
>    obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>    obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>    obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o
>  +obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
>  diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
>  b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
>  new file mode 100644
>  index ..761ef5ae687d
>  --- /dev/null
>  +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
>  @@ -0,0 +1,320 @@
>  +/*
>  + * Designware HDMI CEC driver
>  + *
>  + * Copyright (C) 2015-2017 Russell King.
>  + *
>  + * This program is free software; you can redistribute it
>  and/or modify
>  + * it under the terms of the GNU General Public License
>  version 2 as
>  + * published by the Free Software Foundation.
>  + */
>  +#include 
>  +#include 
>  +#include 
>  +#include 
>  +#include 
>  +#include 
>  +
>  +#include 
>  +
>  +#include 
>  +#include 
>  +
>  +#include "dw-hdmi-cec.h"
>  +
>  +enum {
>  +HDMI_IH_CEC_STAT0= 0x0106,
>  +HDMI_IH_MUTE_CEC_STAT0= 0x0186,
>  +
>  +HDMI_CEC_CTRL= 0x7d00,
>  +CEC_CTRL_START= BIT(0),
>  +CEC_CTRL_NORMAL= 1 << 1,
>  +
>  +HDMI_CEC_STAT= 0x7d01,
>  +CEC_STAT_DONE= BIT(0),
>  +CEC_STAT_EOM= BIT(1),
>  +CEC_STAT_NACK= BIT(2),
>  +CEC_STAT_ARBLOST= BIT(3),
>  +CEC_STAT_ERROR_INIT= BIT(4),
>  +CEC_STAT_ERROR_FOLL= BIT(5),
>  +CEC_STAT_WAKEUP= BIT(6),
> >>
> >> I hadn't realized until Jose Abreu's latest reply, but you need
> >> to check the
> >> ARBLOST status and set the TX state to CEC_TX_STATUS_ARB_LOST.
> >>
> >> I think CEC_STAT_ERROR_FOLL might equal
> >> CEC_TX_STATUS_LOW_DRIVE, but without
> >> documentation I can't be sure.
> >>
> >> My experience is that this low drive condition tends to be
> >> poorly reported by
> >> hardware. Either that or poorly documented. This is why I added a
> >> CEC_TX_STATUS_ERROR status as a catch-all error status when it
> >> is unclear from
> >> the hardware/documentation what error occurred.
> >>
> >> Jose, do you know which status bit is used to report a follower
> >> pulling the
> >> CEC line low for a long time (approx. 3.6 ms) to signal a CEC
> >> error?
> > 
> > Bit 5 for follower error, bit 4 for initiator error.
> 
> I gathered that from the define names :-)
> 
> But what does it mean? What sort of error is reported here?

I think the problem is that no one really knows, the documentation is
quite poor:

 5   An error is notified by a follower. Abnormal logic data
 ERROR_FOLL  bit error (for follower).
 4   An error is detected on cec line (for initiator only).
 ERROR_INIT

It is so vague that you can read anything into tha

Re: nouveau "eDP-1: EDID is invalid" regression after 4.11 with HP ZBook 15 G3

[Tommi Rantala]

2017-05-15 8:20 GMT+03:00 Tommi Rantala :
> 2017-05-15 3:03 GMT+03:00 Ben Skeggs :
>> On 05/15/2017 01:10 AM, Tommi Rantala wrote:
>>>
>>> Hi,
>>
>> Hey Tommi,
>>
>> Thanks for bisecting this.  It's rather unexpected that you should be seeing
>> problems here, but, the commit makes sense for it at least.
>>
>> Are you able to get me new kernel logs of both before and after this patch
>> with "log_buf_len=8M drm.debug=0x14
>> nouveau.debug=disp=trace,i2c=trace,bios=trace" please?
>
> Hi Ben,
>
> Before:
> https://www.dropbox.com/s/b2namqtqvzv5ppp/trace.4.10.0-tr-10409-g5c68d91?dl=1
>
> After:
> https://www.dropbox.com/s/9url8qdo15959fy/trace.4.10.0-tr-10410-gdf8dc97?dl=1

Hi, any comments to this?

-Tommi

> -Tommi
>
>> Thanks,
>> Ben.
>>
>>
>>>
>>> Bisected this to:
>>>
>>> commit df8dc97cd17269474344d73cc02739532c468d04
>>> Author: Ben Skeggs 
>>> Date:   Wed Mar 1 09:42:04 2017 +1000
>>>
>>> drm/nouveau/kms/nv50: use drm core i2c-over-aux algorithm
>>>
>>> I'm not entirely sure NVKM needs to support this now, but I haven't
>>> removed it as of yet just in case it's needed from DEVINIT scripts
>>> where DRM isn't available.
>>>
>>> Signed-off-by: Ben Skeggs 
>>>
>>>
>>> dmesg after boot with drm.debug enabled:
>>>
>>> v4.10-10409-g5c68d91 (still works):
>>> http://termbin.com/b0is
>>>
>>> v4.10-10410-gdf8dc97 (failure):
>>> http://termbin.com/j6lq
>>>
>>>
>>> Tommi
>>>
>>>
>>> 2017-05-10 11:24 GMT+03:00 Tommi Rantala :

 Hi,

 The HP ZBook 15 G3 laptop builtin display (eDP-1) does not work
 correctly with v4.11-11413-g2868b25.

 When booting the laptop, the resolution seems to be limited to
 1024x768, and gnome-session segfaults.

 Up to 4.11 the display works just fine in 1920x1080 mode.

 I'm seeing this in the kernel logs:

 nouveau :01:00.0: eDP-1: EDID is invalid:
  [00] BAD  00 ff ff ff ff ff ff 00 ff ff ff ff ff ff ff ff
  [00] BAD  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
  [00] BAD  ff ff ff ff ff ff ff ff ff ff ff ff ff 84 53 54
  [00] BAD  66 69 50 55 57 66 74 49 48 ff ff ff ff ff ff ff
  [00] BAD  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
  [00] BAD  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
  [00] BAD  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
  [00] BAD  ff ff ff ff ff ff ff ff ff ff ff 00 00 ff 00 ff
 nouveau :01:00.0: DRM: DDC responded, but no EDID for eDP-1
 [drm] Cannot find any crtc or sizes - going 1024x768


 $ lspci | grep NVIDIA
 01:00.0 VGA compatible controller: NVIDIA Corporation GM107GLM [Quadro
 M2000M] (rev a2)

 Any ideas, or should I bisect?

 4.11 dmesg & xrandr output:
 https://pastebin.com/raw/P9LGP7e1

 4.11-11413-g2868b25 dmesg:
 https://pastebin.com/raw/QBT9mMua

 -Tommi
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[Bug 194761] amdgpu driver breaks on Oland (SI)

[bugzilla-daemon]

https://bugzilla.kernel.org/show_bug.cgi?id=194761

--- Comment #38 from Marek Olšák (mar...@gmail.com) ---
The second possible fix is a bug fix by itself (not just for this issue), seems
like an important fix affecting Mesa, and may change the outcome of the first
fix. (which we are still uncertain of)

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[Bug 194761] amdgpu driver breaks on Oland (SI)

[bugzilla-daemon]

https://bugzilla.kernel.org/show_bug.cgi?id=194761

--- Comment #37 from Jean Delvare (jdelv...@suse.de) ---
Alex, is the fix in comment #35 possibly related to this bug, or you just
happened to find it while reading the code?

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[Bug 194761] amdgpu driver breaks on Oland (SI)

[bugzilla-daemon]

https://bugzilla.kernel.org/show_bug.cgi?id=194761

--- Comment #36 from Jean Delvare (jdelv...@suse.de) ---
The patch in comment #33 is what I came up with (see comment #26) and it works
OK for me. Note that the second part of the patch isn't needed though, the
added condition will always be tree if you reach it.

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Re: [PATCH] vc4_bo.c: always set bo->resv

[Hans Verkuil]

On 06/02/2017 11:48 PM, Eric Anholt wrote:

Hans Verkuil  writes:


The bo->resv pointer could be NULL, leading to kernel oopses like the one below.
It looks like .fb_probe -> drm_fbdev_cma_create() -> drm_gem_cma_create() would
end up not initializing resv, because we're doing that in vc4_bo_create(), not
vc4_create_object().

This patch ensures that bo->resv is always set in vc4_create_object
ensuring that it is never NULL.

Thanks to Eric Anholt for pointing to the correct solution.


Folks that know dma-buf better: Will having two reservations around for
the lifetime of the BO in the case of CMA dma-buf imports be a bad
thing?  I'm assuming reservations are cheap, given that we're
unconditionally allocating them per BO for un-shared BOs already.


Signed-off-by: Hans Verkuil 
---
   drivers/gpu/drm/vc4/vc4_bo.c | 12 
   1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index 80b2f9e55c5c..2231ee76cd8d 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -91,8 +91,7 @@ static void vc4_bo_destroy(struct vc4_bo *bo)
vc4->bo_stats.num_allocated--;
vc4->bo_stats.size_allocated -= obj->size;

-   if (bo->resv == &bo->_resv)
-   reservation_object_fini(bo->resv);
+   reservation_object_fini(bo->resv);


This one would need to be "reservation_object_fini(&bo->_resv);" -- we
need to free the reservation that we created (and left unused in the
case of an import), not the one that was imported from someone else.


Of course, fixed. I'll wait a bit to see if anyone replies to your query
above, and will post a v2 some time next week.

Regards,

Hans




drm_gem_cma_free_object(obj);
   }
@@ -212,6 +211,8 @@ struct drm_gem_object *vc4_create_object(struct drm_device 
*dev, size_t size)
vc4->bo_stats.num_allocated++;
vc4->bo_stats.size_allocated += size;
mutex_unlock(&vc4->bo_lock);
+   bo->resv = &bo->_resv;
+   reservation_object_init(bo->resv);

return &bo->base.base;
   }
@@ -250,12 +251,7 @@ struct vc4_bo *vc4_bo_create(struct drm_device *dev, 
size_t unaligned_size,
return ERR_PTR(-ENOMEM);
}
}
-   bo = to_vc4_bo(&cma_obj->base);
-
-   bo->resv = &bo->_resv;
-   reservation_object_init(bo->resv);
-
-   return bo;
+   return to_vc4_bo(&cma_obj->base);
   }

   int vc4_dumb_create(struct drm_file *file_priv,
--
2.11.0


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