[Bug 110701] GPU faults in in Unigine Valley 1.0
https://bugs.freedesktop.org/show_bug.cgi?id=110701 Christian Widmer changed: What|Removed |Added CC||cwid...@umbrox.de --- Comment #7 from Christian Widmer --- (In reply to Yury Zhuravlev from comment #6) > 78e35df52aa2f7d770f929a0866a0faa89c261a9 radeonsi: update buffer descriptors > in all contexts after buffer invalidation That is the commit I identified in comment #1 as being responsible for my issues. I would not be surprised if reverting that one makes your faults disappear as well. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 105251] [Vega10] GPU lockup on boot: VMC page fault
https://bugs.freedesktop.org/show_bug.cgi?id=105251 --- Comment #66 from CheatCodesOfLife --- I jumped ship to nvidia months ago so this doesn't help me, but for you guys following this thread, the Cemu developers managed to fix this issue on their end. If you install the latest public release of Cemu, all games will work with Vega + mesa under wine. Since there are non-cemu cases in here, I won't close the issue (someone else can if appropriate). I'm unsubscribing from this now. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 107612] [Vega10] Hard Lock [gfxhub] VMC page fault when opening Mario Kart 8 in Cemu under wine
https://bugs.freedesktop.org/show_bug.cgi?id=107612 CheatCodesOfLife changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #6 from CheatCodesOfLife --- I jumpped ship to nvidia months ago so this doesn't help me, but for you guys following this thread, the Cemu developers managed to fix this issue. If you install the latest public release of Cemu, it will work with Vega + mesa under wine. The latest mesa build also fixes the BOTW texture problem. So latest Cemu + latest mesa works perfectly with Vega cards now. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 104206] [drm:construct [amdgpu]] *ERROR* construct: Invalid Connector ObjectID from Adapter Service for connector index:2!
https://bugs.freedesktop.org/show_bug.cgi?id=104206 alex.bradata...@yahoo.it changed: What|Removed |Added CC||alex.bradata...@yahoo.it --- Comment #24 from alex.bradata...@yahoo.it --- Created attachment 144298 --> https://bugs.freedesktop.org/attachment.cgi?id=144298&action=edit dmesg from vivobook x505za Added the dmesg from boot of a Asus Vivobook X505ZA with a Ryzen 2500U with Vega 8 mobile graphics running Arch Linux kernel version 5.1.2. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: etnaviv: avoid DMA API warning when importing buffers
On Sat, May 18, 2019 at 06:04:42PM -0300, Fabio Estevam wrote: > Hi Russell, > > On Sat, May 18, 2019 at 2:51 PM Russell King - ARM Linux admin > wrote: > > > > Ping. > > This patch is present in Lucas' pull request: > https://lists.freedesktop.org/archives/etnaviv/2019-May/002490.html I'm wondering why it didn't make 5.1 since it's a regression. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: etnaviv: avoid DMA API warning when importing buffers
Hi Russell, On Sat, May 18, 2019 at 2:51 PM Russell King - ARM Linux admin wrote: > > Ping. This patch is present in Lucas' pull request: https://lists.freedesktop.org/archives/etnaviv/2019-May/002490.html ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110704] BLACK SCREEN RADEON RX570 fail to initialise GPU passtrough all linux in Hypervisor PROXMOX
https://bugs.freedesktop.org/show_bug.cgi?id=110704 Bas Nieuwenhuizen changed: What|Removed |Added QA Contact|mesa-dev@lists.freedesktop. | |org | Product|Mesa|DRI Component|Drivers/Vulkan/radeon |DRM/AMDgpu Assignee|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop |org |.org -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: etnaviv: avoid DMA API warning when importing buffers
Ping.
On Mon, Feb 25, 2019 at 10:54:23AM +, Russell King - ARM Linux admin wrote:
> On Mon, Feb 25, 2019 at 10:51:30AM +, Russell King wrote:
> > During boot, I get this kernel warning:
> >
> > WARNING: CPU: 0 PID: 19001 at kernel/dma/debug.c:1301
> > debug_dma_map_sg+0x284/0x3dc
> > etnaviv etnaviv: DMA-API: mapping sg segment longer than device claims to
> > support [len=3145728] [max=65536]
> > Modules linked in: ip6t_REJECT nf_reject_ipv6 ip6t_rpfilter xt_tcpudp
> > ipt_REJECT nf_reject_ipv4 xt_conntrack ip_set nfnetlink ebtable_broute
> > ebtable_nat ip6table_raw ip6table_nat nf_nat_ipv6 ip6table_mangle
> > iptable_raw iptable_nat nf_nat_ipv4 nf_nat nf_conntrack nf_defrag_ipv4
> > nf_defrag_ipv6 libcrc32c iptable_mangle ebtable_filter ebtables
> > ip6table_filter ip6_tables iptable_filter caam_jr error snd_soc_imx_spdif
> > imx_thermal snd_soc_imx_audmux nvmem_imx_ocotp snd_soc_sgtl5000
> > caam imx_sdma virt_dma coda rc_cec v4l2_mem2mem snd_soc_fsl_ssi
> > snd_soc_fsl_spdif imx_vdoa imx_pcm_dma videobuf2_dma_contig etnaviv
> > dw_hdmi_cec gpu_sched dw_hdmi_ahb_audio imx6q_cpufreq nfsd sch_fq_codel
> > ip_tables x_tables
> > CPU: 0 PID: 19001 Comm: Xorg Not tainted 4.20.0+ #307
> > Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> > [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
> > [] (show_stack) from [] (dump_stack+0x9c/0xd4)
> > [] (dump_stack) from [] (__warn+0xf8/0x124)
> > [] (__warn) from [] (warn_slowpath_fmt+0x38/0x48)
> > [] (warn_slowpath_fmt) from []
> > (debug_dma_map_sg+0x284/0x3dc)
> > [] (debug_dma_map_sg) from []
> > (drm_gem_map_dma_buf+0xc4/0x13c)
> > [] (drm_gem_map_dma_buf) from []
> > (dma_buf_map_attachment+0x38/0x5c)
> > [] (dma_buf_map_attachment) from []
> > (drm_gem_prime_import_dev+0x74/0x104)
> > [] (drm_gem_prime_import_dev) from []
> > (drm_gem_prime_fd_to_handle+0x84/0x17c)
> > [] (drm_gem_prime_fd_to_handle) from []
> > (drm_prime_fd_to_handle_ioctl+0x38/0x4c)
> > [] (drm_prime_fd_to_handle_ioctl) from []
> > (drm_ioctl_kernel+0x90/0xc8)
> > [] (drm_ioctl_kernel) from [] (drm_ioctl+0x1e0/0x3b0)
> > [] (drm_ioctl) from [] (do_vfs_ioctl+0x90/0xa48)
> > [] (do_vfs_ioctl) from [] (ksys_ioctl+0x34/0x60)
> > [] (ksys_ioctl) from [] (ret_fast_syscall+0x0/0x28)
> > Exception stack(0xd81a9fa8 to 0xd81a9ff0)
> > 9fa0: b6c69c88 bec613f8 0009 c00c642e bec613f8
> > b86c4600
> > 9fc0: b6c69c88 bec613f8 c00c642e 0036 012762e0 01276348 0300
> > 012d91f8
> > 9fe0: b6989f18 bec613dc b697185c b667be5c
> > irq event stamp: 47905
> > hardirqs last enabled at (47913): [] console_unlock+0x46c/0x680
> > hardirqs last disabled at (47922): [] console_unlock+0xb8/0x680
> > softirqs last enabled at (47754): [] __do_softirq+0x344/0x540
> > softirqs last disabled at (47701): [] irq_exit+0x124/0x144
> > ---[ end trace af477747acbcc642 ]---
> >
> > The reason is the contiguous buffer exceeds the default maximum segment
> > size of 64K as specified by dma_get_max_seg_size() in
> > linux/dma-mapping.h. Fix this by providing our own segment size, which
> > is set to 2GiB to cover the window found in MMUv1 GPUs.
> >
> > Signed-off-by: Russell King
>
> Fixes: 78c47830a5cb ("dma-debug: check scatterlist segments")
>
> not really that there's a problem with that commit, but it is where the
> warning was introduced.
>
> > ---
> > Patch against v4.20.
> >
> > drivers/gpu/drm/etnaviv/etnaviv_drv.c | 4
> > drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 +
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> > b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> > index 4713885012ab..e414f284f424 100644
> > --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> > +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
> > @@ -527,6 +527,9 @@ static int etnaviv_bind(struct device *dev)
> > }
> > drm->dev_private = priv;
> >
> > + dev->dma_parms = &priv->dma_parms;
> > + dma_set_max_seg_size(dev, SZ_2G);
> > +
> > mutex_init(&priv->gem_lock);
> > INIT_LIST_HEAD(&priv->gem_list);
> > priv->num_gpus = 0;
> > @@ -564,6 +567,7 @@ static void etnaviv_unbind(struct device *dev)
> >
> > component_unbind_all(dev, drm);
> >
> > + dev->dma_parms = NULL;
> > drm->dev_private = NULL;
> > kfree(priv);
> >
> > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> > b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> > index 8d02d1b7dcf5..b2930d1fe97c 100644
> > --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> > +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> > @@ -43,6 +43,7 @@ struct etnaviv_file_private {
> >
> > struct etnaviv_drm_private {
> > int num_gpus;
> > + struct device_dma_parameters dma_parms;
> > struct etnaviv_gpu *gpu[ETNA_MAX_PIPES];
> >
> > /* list of GEM objects: */
> > --
> > 2.7.4
> >
> >
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
> Accord
Re: [PATCH] drm: rcar-du: writeback: include interface header
Hi Sergei, On Sat, May 18, 2019 at 11:42:28AM +0300, Sergei Shtylyov wrote: > Hello! > > On 18.05.2019 0:20, Kieran Bingham wrote: > > > The new writeback feature is exports functions so that they can > ^^ not needed? Good catch. I'll fix it in my branch. > > integrate into the rcar_du_kms module. > > > > The interface functions are defined in the rcar_du_writeback header, but > > it is not included in the object file itself leading to compiler > > warnings for missing prototypes. > > > > Include the header as appropriate. > > > > Signed-off-by: Kieran Bingham > [...] > > MBR, Sergei -- Regards, Laurent Pinchart
Re: [PATCH v5 1/6] drm: panfrost: add optional bus_clock
Hi,
On Sat, 18 May 2019 at 00:17, Rob Herring wrote:
>
> On Fri, May 17, 2019 at 5:08 PM Clément Péron wrote:
> >
> > Hi Rob,
> >
> > On Fri, 17 May 2019 at 22:07, Rob Herring wrote:
> > >
> > > On Fri, May 17, 2019 at 1:47 PM Clément Péron
> > > wrote:
> > > >
> > > > Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.
> > > >
> > > > Add an optional bus_clock at the init of the panfrost driver.
> > > >
> > > > Signed-off-by: Clément Péron
> > > > ---
> > > > drivers/gpu/drm/panfrost/panfrost_device.c | 25 +-
> > > > drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> > > > 2 files changed, 25 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > index 3b2bced1b015..8da6e612d384 100644
> > > > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > @@ -44,7 +44,8 @@ static int panfrost_clk_init(struct panfrost_device
> > > > *pfdev)
> > > >
> > > > pfdev->clock = devm_clk_get(pfdev->dev, NULL);
> > > > if (IS_ERR(pfdev->clock)) {
> > > > - dev_err(pfdev->dev, "get clock failed %ld\n",
> > > > PTR_ERR(pfdev->clock));
> > > > + dev_err(pfdev->dev, "get clock failed %ld\n",
> > > > + PTR_ERR(pfdev->clock));
> > >
> > > Please drop this whitespace change.
> >
> > Sorry, I thought it was only a mistake here, I will drop it.
> > Why are they so many lines over 80 characters?
>
> I'd guess most are prints and/or just slightly over.
>
> > Is there a specific coding style to follow ?
>
> Yes, but generally the 80 character thing is more a guidance. Not
> having unrelated changes in a single commit is more of a hard rule.
Ok, thanks for the clarification.
Clément
>
> Rob
[Bug 110671] Regression: DP outputs out of sync on dual-DP tiled 5k screen
https://bugs.freedesktop.org/show_bug.cgi?id=110671 Denys changed: What|Removed |Added See Also||https://bugs.freedesktop.or ||g/show_bug.cgi?id=105651 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 105651] Vega64 doesn't output properly onto dell up2715k at 5120x2880
https://bugs.freedesktop.org/show_bug.cgi?id=105651 Denys changed: What|Removed |Added See Also||https://bugs.freedesktop.or ||g/show_bug.cgi?id=110671 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110671] Regression: DP outputs out of sync on dual-DP tiled 5k screen
https://bugs.freedesktop.org/show_bug.cgi?id=110671 --- Comment #5 from Denys --- Have same issue on Vega FE + Dell UP2715K. Also it may be related to this bug: https://bugs.freedesktop.org/show_bug.cgi?id=105651 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110701] GPU faults in in Unigine Valley 1.0
https://bugs.freedesktop.org/show_bug.cgi?id=110701 --- Comment #6 from Yury Zhuravlev --- Ok, currently I know bug somewhere in this 3 commits f3ae455eb08e8d718b828eb42f2529437916179b radeonsi: compute culling - flush CS to remove write references to buffers 0f1b070bad34c46c4bcc6c679fa533bf6b4b79e5 radeonsi: remove old_va parameter from si_rebind_buffer by remembering offsets 78e35df52aa2f7d770f929a0866a0faa89c261a9 radeonsi: update buffer descriptors in all contexts after buffer invalidation I will test more. Looks like some commit after current makes this bug more reproducible. Before it also exists but not so often. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[v4 2/5] drm/mediatek: dpi dual edge support
DPI sample the data both rising and falling edge.
It can reduce half data io pins.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 22e68a100e7b..ccef3ac1c560 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -117,6 +117,7 @@ struct mtk_dpi_conf {
unsigned int (*cal_factor)(int clock);
u32 reg_h_fre_con;
bool edge_sel_en;
+ bool dual_edge;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -353,6 +354,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi
*dpi)
mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
}
+static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
+{
+ mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
+DDR_EN | DDR_4PHASE);
+ mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
+}
+
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)
{
@@ -444,7 +452,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor;
- clk_set_rate(dpi->pixel_clk, vm.pixelclock);
+ clk_set_rate(dpi->pixel_clk,
+vm.pixelclock * (dpi->conf->dual_edge ? 2 : 1));
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
@@ -509,6 +518,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_color_format(dpi, dpi->color_format);
mtk_dpi_config_2n_h_fre(dpi);
mtk_dpi_config_disable_edge(dpi);
+ if (dpi->conf->dual_edge)
+ mtk_dpi_enable_dual_edge(dpi);
mtk_dpi_sw_reset(dpi, false);
return 0;
--
2.21.0
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[v4 5/5] drm/mediatek: add mt8183 support dpi pins control
Some DPI pins(Hsync Vsync DE ... ) keep high voltage and will cause
leakage current. So set dpi pin as gpio and pull low when dpi off.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 0c4ba0a2be27..565892a3e1ba 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -719,6 +719,7 @@ static const struct mtk_dpi_conf mt8183_conf = {
.cal_factor = mt8183_calculate_factor,
.reg_h_fre_con = 0xe0,
.dual_edge = true,
+ .dpi_pin_ctrl = true,
};
static int mtk_dpi_probe(struct platform_device *pdev)
--
2.21.0
[v4 4/5] drm/mediatek: control dpi pins dpi or gpio mode in on or off
Pull dpi pins low when dpi has nothing to display. Aovid leakage
current from some dpi pins (Hsync Vsync DE ... ).
Some chips have dpi pins, but there are some chip don't have pins.
So this function is controlled by chips driver data.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 35 +-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 77e6e0f99188..0c4ba0a2be27 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -17,10 +17,12 @@
#include
#include
#include
-#include
#include
#include
+#include
#include
+#include
+#include
#include
#include
#include
@@ -79,6 +81,9 @@ struct mtk_dpi {
enum mtk_dpi_out_yc_map yc_map;
enum mtk_dpi_out_bit_num bit_num;
enum mtk_dpi_out_channel_swap channel_swap;
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pins_default;
+ struct pinctrl_state *pins_dpi;
int refcount;
};
@@ -118,6 +123,7 @@ struct mtk_dpi_conf {
u32 reg_h_fre_con;
bool edge_sel_en;
bool dual_edge;
+ bool dpi_pin_ctrl;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -392,6 +398,9 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
if (--dpi->refcount != 0)
return;
+ if (dpi->conf->dpi_pin_ctrl)
+ pinctrl_select_state(dpi->pinctrl, dpi->pins_default);
+
mtk_dpi_disable(dpi);
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
@@ -416,6 +425,9 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_pixel;
}
+ if (dpi->conf->dpi_pin_ctrl)
+ pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
+
mtk_dpi_enable(dpi);
return 0;
@@ -724,6 +736,27 @@ static int mtk_dpi_probe(struct platform_device *pdev)
dpi->dev = dev;
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
+ if (dpi->conf->dpi_pin_ctrl) {
+ dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(dpi->pinctrl)) {
+ dev_err(&pdev->dev, "Cannot find pinctrl!\n");
+ return PTR_ERR(dpi->pinctrl);
+ }
+
+ dpi->pins_default = pinctrl_lookup_state(dpi->pinctrl,
+"default");
+ if (IS_ERR(dpi->pins_default)) {
+ dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
+ return PTR_ERR(dpi->pins_default);
+ }
+
+ dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "dpimode");
+ if (IS_ERR(dpi->pins_dpi)) {
+ dev_err(&pdev->dev, "Cannot find pinctrl dpimode!\n");
+ return PTR_ERR(dpi->pins_dpi);
+ }
+ }
+
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dpi->regs = devm_ioremap_resource(dev, mem);
if (IS_ERR(dpi->regs)) {
--
2.21.0
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[v4 3/5] drm/mediatek: add mt8183 dpi dual edge support
Add mt8183 dual edge support.
DPI sample the data both rising and falling edge.
It can reduce half data io pins.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index ccef3ac1c560..77e6e0f99188 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -682,6 +682,16 @@ static unsigned int mt2701_calculate_factor(int clock)
return 2;
}
+static unsigned int mt8183_calculate_factor(int clock)
+{
+ if (clock <= 27000)
+ return 8;
+ else if (clock <= 167000)
+ return 4;
+ else
+ return 2;
+}
+
static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
@@ -693,6 +703,12 @@ static const struct mtk_dpi_conf mt2701_conf = {
.edge_sel_en = true,
};
+static const struct mtk_dpi_conf mt8183_conf = {
+ .cal_factor = mt8183_calculate_factor,
+ .reg_h_fre_con = 0xe0,
+ .dual_edge = true,
+};
+
static int mtk_dpi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -788,6 +804,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8173-dpi",
.data = &mt8173_conf,
},
+ { .compatible = "mediatek,mt8183-dpi",
+ .data = &mt8183_conf,
+ },
{ },
};
--
2.21.0
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[v4 1/5] dt-bindings: display: mediatek: update dpi supported chips
Add decriptions about supported chips, including MT2701 & MT8173 & mt8183 Signed-off-by: Jitao Shi Reviewed-by: Rob Herring --- .../devicetree/bindings/display/mediatek/mediatek,dpi.txt| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index b6a7e7397b8b..58914cf681b8 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -7,6 +7,7 @@ output bus. Required properties: - compatible: "mediatek,-dpi" + the supported chips are mt2701 , mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[v4 0/5] Support dpi for mt8183
Changes since v3: - add dpi pin mode control when dpi on or off. - update dpi dual edge comment. Changes since v2: - update dt-bindings document for mt8183 dpi. - separate dual edge modfication as independent patch. Jitao Shi (5): dt-bindings: display: mediatek: update dpi supported chips drm/mediatek: dpi dual edge support drm/mediatek: add mt8183 dpi dual edge support drm/mediatek: control dpi pins dpi or gpio mode in on or off drm/mediatek: add mt8183 support dpi pins control .../display/mediatek/mediatek,dpi.txt | 1 + drivers/gpu/drm/mediatek/mtk_dpi.c| 68 ++- 2 files changed, 67 insertions(+), 2 deletions(-) -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm: rcar-du: writeback: include interface header
Hello! On 18.05.2019 0:20, Kieran Bingham wrote: The new writeback feature is exports functions so that they can ^^ not needed? integrate into the rcar_du_kms module. The interface functions are defined in the rcar_du_writeback header, but it is not included in the object file itself leading to compiler warnings for missing prototypes. Include the header as appropriate. Signed-off-by: Kieran Bingham [...] MBR, Sergei ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[v3 0/3] Support mipitx on mt8183
Changes since v2: - update Acked-by: Rob Herring - update mt8183 max bit rate support Changes since v1: - update dt-bindings document for mt8183 mipitx. - remove mtk_mipitx_clk_get_ops and assign clk_ops in probe. - fix the lincence - remove txdiv1 from mtk_mipi_tx_pll_prepare Jitao Shi (3): dt-bindings: display: mediatek: update dsi supported chips drm/mediatek: separate mipi_tx to different file drm/mediatek: add mipi_tx driver for mt8183 .../display/mediatek/mediatek,dsi.txt | 2 +- drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 344 ++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 50 +++ drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++ drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 160 6 files changed, 527 insertions(+), 320 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[v3 3/3] drm/mediatek: add mipi_tx driver for mt8183
This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 160 ++
4 files changed, 164 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
mtk_dsi.o \
mtk_mipi_tx.o \
mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
mtk_dpi.o
obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 46bc02cfe85c..66b3c2efe013 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -182,6 +182,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
.data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
.data = &mt8173_mipitx_data },
+ { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
};
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 660726924992..3fd24563952e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -45,5 +45,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
extern const struct mtk_mipitx_data mt2701_mipitx_data;
extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..00652ca5c0c8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN BIT(0)
+#define RG_DSI_ANA_CK_SEL BIT(1)
+#define RG_DSI_PHY_CK_SEL BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN BIT(6)
+#define RG_DSI_BG_CORE_EN BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
+{
+ struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ unsigned int txdiv, txdiv0;
+ u64 pcw;
+ int ret;
+
+ dev_dbg(mipi_tx->dev, "prepare: %u bps\n", mipi_tx->data_rate);
+
+ if (mipi_tx->data_rate >= 20) {
+ txdiv = 1;
+ txdiv0 = 0;
+ } else if (mipi_tx->data_rate >= 10) {
+ txdiv = 2;
+ txdiv0 = 1;
+ } else if (mipi_tx->data_rate >= 5) {
+ txdiv = 4;
+ txdiv0 = 2;
+ } else if (mipi_tx->data_rate > 25000) {
+ txdiv = 8;
+ txdiv0 = 3;
+ } else if (mipi_tx->data_rate >= 12500) {
+ txdiv = 16;
+ txdiv0 = 4;
+ } else {
+ return -EINVAL;
+ }
+
+ ret = clk_prepare_enable(mipi_tx->ref_clk);
+ if (ret < 0) {
+ dev_err(mipi_tx->dev,
+ "can't prepare and enable mipi_tx ref_clk %d\n", ret);
+ return ret;
+ }
+
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+ mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ usleep_range(30, 100);
+ mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR,
[v3 1/3] dt-bindings: display: mediatek: update dsi supported chips
Update device tree binding documentation for the dsi for Mediatek MT8183 SoCs. Signed-off-by: Jitao Shi Acked-by: Rob Herring --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index fadf327c7cdf..bb3dcd2d8571 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[v3 2/3] drm/mediatek: separate mipi_tx to different file
Different IC has different mipi_tx setting of dsi. This patch separates the mipi_tx hardware relate part for mt8173. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 342 ++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 49 +++ drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++ 4 files changed, 362 insertions(+), 319 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 82ae49c64221..2c8de1f5a5ee 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -12,6 +12,7 @@ mediatek-drm-y := mtk_disp_color.o \ mtk_drm_plane.o \ mtk_dsi.o \ mtk_mipi_tx.o \ + mtk_mt8173_mipi_tx.o \ mtk_dpi.o obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index 90e913108950..46bc02cfe85c 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -11,292 +11,39 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include -#include -#include - -#define MIPITX_DSI_CON 0x00 -#define RG_DSI_LDOCORE_EN BIT(0) -#define RG_DSI_CKG_LDOOUT_EN BIT(1) -#define RG_DSI_BCLK_SEL(3 << 2) -#define RG_DSI_LD_IDX_SEL (7 << 4) -#define RG_DSI_PHYCLK_SEL (2 << 8) -#define RG_DSI_DSICLK_FREQ_SEL BIT(10) -#define RG_DSI_LPTX_CLMP_ENBIT(11) - -#define MIPITX_DSI_CLOCK_LANE 0x04 -#define MIPITX_DSI_DATA_LANE0 0x08 -#define MIPITX_DSI_DATA_LANE1 0x0c -#define MIPITX_DSI_DATA_LANE2 0x10 -#define MIPITX_DSI_DATA_LANE3 0x14 -#define RG_DSI_LNTx_LDOOUT_EN BIT(0) -#define RG_DSI_LNTx_CKLANE_EN BIT(1) -#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2) -#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3) -#define RG_DSI_LNTx_LPTX_IMINUSBIT(4) -#define RG_DSI_LNTx_LPCD_IPLUS BIT(5) -#define RG_DSI_LNTx_LPCD_IMINUSBIT(6) -#define RG_DSI_LNTx_RT_CODE(0xf << 8) - -#define MIPITX_DSI_TOP_CON 0x40 -#define RG_DSI_LNT_INTR_EN BIT(0) -#define RG_DSI_LNT_HS_BIAS_EN BIT(1) -#define RG_DSI_LNT_IMP_CAL_EN BIT(2) -#define RG_DSI_LNT_TESTMODE_EN BIT(3) -#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4) -#define RG_DSI_LNT_AIO_SEL (7 << 8) -#define RG_DSI_PAD_TIE_LOW_EN BIT(11) -#define RG_DSI_DEBUG_INPUT_EN BIT(12) -#define RG_DSI_PRESERVE(7 << 13) - -#define MIPITX_DSI_BG_CON 0x44 -#define RG_DSI_BG_CORE_EN BIT(0) -#define RG_DSI_BG_CKEN BIT(1) -#define RG_DSI_BG_DIV (0x3 << 2) -#define RG_DSI_BG_FAST_CHARGE BIT(4) -#define RG_DSI_VOUT_MSK(0x3 << 5) -#define RG_DSI_V12_SEL (7 << 5) -#define RG_DSI_V10_SEL (7 << 8) -#define RG_DSI_V072_SEL(7 << 11) -#define RG_DSI_V04_SEL (7 << 14) -#define RG_DSI_V032_SEL(7 << 17) -#define RG_DSI_V02_SEL (7 << 20) -#define RG_DSI_BG_R1_TRIM (0xf << 24) -#define RG_DSI_BG_R2_TRIM (0xf << 28) - -#define MIPITX_DSI_PLL_CON00x50 -#define RG_DSI_MPPLL_PLL_ENBIT(0) -#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1) -#define RG_DSI_MPPLL_PREDIV(3 << 1) -#define RG_DSI_MPPLL_TXDIV0(3 << 3) -#define RG_DSI_MPPLL_TXDIV1(3 << 5) -#define RG_DSI_MPPLL_POSDIV(7 << 7) -#define RG_DSI_MPPLL_MONVC_EN BIT(10) -#define RG_DSI_MPPLL_MONREF_EN BIT(11) -#define RG_DSI_MPPLL_VOD_ENBIT(12) - -#define MIPITX_DSI_PLL_CON10x54 -#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0) -#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1) -#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2) -#define RG_DSI_MPPLL_SDM_SSC_PRD (0x << 16) - -#define MIPITX_DSI_PLL_CON20x58 - -#define MIPITX_DSI_PLL_TOP 0x64 -#define RG_DSI_MPPLL_PRESERVE (0xff << 8) - -#define MIPITX_DSI_PLL_PWR 0x68 -#define RG_DSI_MPPLL_SDM_PWR_ONBIT(0) -#define RG_DSI_MPPLL_SDM_ISO_ENBIT(1) -#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8) - -#define MIPITX_DSI_SW_CTRL 0x80 -#define SW_CTRL_EN BIT(0) - -#define MIPITX_DSI_SW_CTRL_CON00x84 -#define SW_LNTC_LPTX_PRE_OEBIT(0) -#define SW_LNTC_LPTX_OEBIT(1) -#define SW_LNTC_LPTX_P BIT(2) -#define SW_LNTC_LPTX_N
Re: [v2 3/3] drm/mediatek: add mipi_tx driver for mt8183
On Mon, 2019-05-06 at 17:17 +0800, CK Hu wrote:
> Hi, Jitao:
>
> On Tue, 2019-04-16 at 13:42 +0800, Jitao Shi wrote:
> > This patch add mt8183 mipi_tx driver.
> > And also support other chips that use the same binding and driver.
> >
> > Signed-off-by: Jitao Shi
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 2 +
> > drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
> > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 154 ++
> > 4 files changed, 158 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
> >
>
> [snip]
>
> > +
> > +static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
> > +{
> > + struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
> > + unsigned int txdiv, txdiv0;
> > + u64 pcw;
> > + int ret;
> > +
> > + dev_dbg(mipi_tx->dev, "prepare: %u bps\n", mipi_tx->data_rate);
> > +
> > + if (mipi_tx->data_rate >= 20) {
> > + txdiv = 1;
> > + txdiv0 = 0;
> > + } else if (mipi_tx->data_rate >= 10) {
> > + txdiv = 2;
> > + txdiv0 = 1;
> > + } else if (mipi_tx->data_rate >= 5) {
> > + txdiv = 4;
> > + txdiv0 = 2;
> > + } else if (mipi_tx->data_rate > 25000) {
> > + txdiv = 8;
> > + txdiv0 = 3;
> > + } else if (mipi_tx->data_rate >= 12500) {
> > + txdiv = 16;
> > + txdiv0 = 4;
> > + } else {
> > + return -EINVAL;
> > + }
> > +
> > + ret = clk_prepare_enable(mipi_tx->ref_clk);
> > + if (ret < 0) {
> > + dev_err(mipi_tx->dev,
> > + "can't prepare and enable mipi_tx ref_clk %d\n", ret);
> > + return ret;
> > + }
>
> You enable the parent clock when prepare this clock here, this behavior
> looks strange. I think the flow should be:
>
> 1. Parent clock prepare
> 2. This clock prepare
> 3. Parent clock enable
> 4. This clock enable
>
> Maybe you should implement 'enable callback' so that parent clock would
> be already enabled.
>
> One question is, mipi_tx_pll is used by dsi driver, but I does not see
> dsi prepare_enable() mipi_tx_pll, how does this work?
>
> Regards,
> CK
>
The mipi_tx can be accessed after clk_prepare_enable(mipi_tx->ref_clk);
So place the clk_prepare_enable(mipi_tx->ref_clk) before accessing
mipitx.
mipi_tx_pll is enable by mtk_mipi_tx_power_on() in mtk_mip_tx.c.
clk_prepare_enable(mipi_tx->pll) will enable mipi_tx_pll.
Beset Regards
Jitao
> > +
> > + mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
> > +
> > + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
> > + usleep_range(30, 100);
> > + mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
> > + pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 2600);
> > + writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
> > + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
> > + txdiv0 << 8);
> > + usleep_range(1000, 2000);
> > + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
> > +
> > + return 0;
> > +}
> > +
> > +static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
> > +{
> > + struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
> > +
> > + dev_dbg(mipi_tx->dev, "unprepare\n");
> > +
> > + mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
> > +
> > + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
> > + mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
> > + clk_disable_unprepare(mipi_tx->ref_clk);
> > +}
> > +
>
>
