[PATCH v3 3/3] drm/simpledrm: Add [AX]RGB2101010 formats
This is the format used by the bootloader framebuffer on Apple ARM64
platforms.
Reviewed-by: Thomas Zimmermann
Signed-off-by: Hector Martin
---
drivers/gpu/drm/tiny/simpledrm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tiny/simpledrm.c b/drivers/gpu/drm/tiny/simpledrm.c
index 2f15b9aa..b977f5c94562 100644
--- a/drivers/gpu/drm/tiny/simpledrm.c
+++ b/drivers/gpu/drm/tiny/simpledrm.c
@@ -571,8 +571,8 @@ static const uint32_t simpledrm_default_formats[] = {
//DRM_FORMAT_XRGB1555,
//DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB888,
- //DRM_FORMAT_XRGB2101010,
- //DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_ARGB2101010,
};
static const uint64_t simpledrm_format_modifiers[] = {
--
2.33.0
[PATCH v3 2/3] drm/format-helper: Add drm_fb_xrgb8888_to_xrgb2101010_toio()
Add XRGB emulation support for devices that can only do XRGB2101010.
This is chiefly useful for simpledrm on Apple devices where the
bootloader-provided framebuffer is 10-bit.
Signed-off-by: Hector Martin
---
drivers/gpu/drm/drm_format_helper.c | 64 +
include/drm/drm_format_helper.h | 3 ++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/drm_format_helper.c
b/drivers/gpu/drm/drm_format_helper.c
index dbe3e830096e..0f28dd2bdd72 100644
--- a/drivers/gpu/drm/drm_format_helper.c
+++ b/drivers/gpu/drm/drm_format_helper.c
@@ -409,6 +409,61 @@ void drm_fb_xrgb_to_rgb888_toio(void __iomem *dst,
unsigned int dst_pitch,
}
EXPORT_SYMBOL(drm_fb_xrgb_to_rgb888_toio);
+static void drm_fb_xrgb_to_xrgb2101010_line(u32 *dbuf, const u32 *sbuf,
+ unsigned int pixels)
+{
+ unsigned int x;
+ u32 val32;
+
+ for (x = 0; x < pixels; x++) {
+ val32 = ((sbuf[x] & 0x00FF) << 2) |
+ ((sbuf[x] & 0xFF00) << 4) |
+ ((sbuf[x] & 0x00FF) << 6);
+ *dbuf++ = val32 | ((val32 >> 8) & 0x00300C03);
+ }
+}
+
+/**
+ * drm_fb_xrgb_to_xrgb2101010_toio - Convert XRGB to XRGB2101010 clip
+ * buffer
+ * @dst: XRGB2101010 destination buffer (iomem)
+ * @dst_pitch: Number of bytes between two consecutive scanlines within dst
+ * @vaddr: XRGB source buffer
+ * @fb: DRM framebuffer
+ * @clip: Clip rectangle area to copy
+ *
+ * Drivers can use this function for XRGB2101010 devices that don't natively
+ * support XRGB.
+ */
+void drm_fb_xrgb_to_xrgb2101010_toio(void __iomem *dst,
+unsigned int dst_pitch, const void
*vaddr,
+const struct drm_framebuffer *fb,
+const struct drm_rect *clip)
+{
+ size_t linepixels = clip->x2 - clip->x1;
+ size_t dst_len = linepixels * sizeof(u32);
+ unsigned int y, lines = clip->y2 - clip->y1;
+ void *dbuf;
+
+ if (!dst_pitch)
+ dst_pitch = dst_len;
+
+ dbuf = kmalloc(dst_len, GFP_KERNEL);
+ if (!dbuf)
+ return;
+
+ vaddr += clip_offset(clip, fb->pitches[0], sizeof(u32));
+ for (y = 0; y < lines; y++) {
+ drm_fb_xrgb_to_xrgb2101010_line(dbuf, vaddr, linepixels);
+ memcpy_toio(dst, dbuf, dst_len);
+ vaddr += fb->pitches[0];
+ dst += dst_pitch;
+ }
+
+ kfree(dbuf);
+}
+EXPORT_SYMBOL(drm_fb_xrgb_to_xrgb2101010_toio);
+
/**
* drm_fb_xrgb_to_gray8 - Convert XRGB to grayscale
* @dst: 8-bit grayscale destination buffer
@@ -500,6 +555,10 @@ int drm_fb_blit_toio(void __iomem *dst, unsigned int
dst_pitch, uint32_t dst_for
fb_format = DRM_FORMAT_XRGB;
if (dst_format == DRM_FORMAT_ARGB)
dst_format = DRM_FORMAT_XRGB;
+ if (fb_format == DRM_FORMAT_ARGB2101010)
+ fb_format = DRM_FORMAT_XRGB2101010;
+ if (dst_format == DRM_FORMAT_ARGB2101010)
+ dst_format = DRM_FORMAT_XRGB2101010;
if (dst_format == fb_format) {
drm_fb_memcpy_toio(dst, dst_pitch, vmap, fb, clip);
@@ -515,6 +574,11 @@ int drm_fb_blit_toio(void __iomem *dst, unsigned int
dst_pitch, uint32_t dst_for
drm_fb_xrgb_to_rgb888_toio(dst, dst_pitch, vmap,
fb, clip);
return 0;
}
+ } else if (dst_format == DRM_FORMAT_XRGB2101010) {
+ if (fb_format == DRM_FORMAT_XRGB) {
+ drm_fb_xrgb_to_xrgb2101010_toio(dst, dst_pitch,
vmap, fb, clip);
+ return 0;
+ }
}
return -EINVAL;
diff --git a/include/drm/drm_format_helper.h b/include/drm/drm_format_helper.h
index 97e4c3223af3..b30ed5de0a33 100644
--- a/include/drm/drm_format_helper.h
+++ b/include/drm/drm_format_helper.h
@@ -33,6 +33,9 @@ void drm_fb_xrgb_to_rgb888(void *dst, unsigned int
dst_pitch, const void *sr
void drm_fb_xrgb_to_rgb888_toio(void __iomem *dst, unsigned int dst_pitch,
const void *vaddr, const struct
drm_framebuffer *fb,
const struct drm_rect *clip);
+void drm_fb_xrgb_to_xrgb2101010_toio(void __iomem *dst, unsigned int
dst_pitch,
+const void *vaddr, const struct
drm_framebuffer *fb,
+const struct drm_rect *clip);
void drm_fb_xrgb_to_gray8(void *dst, unsigned int dst_pitch, const void
*vaddr,
const struct drm_framebuffer *fb, const struct
drm_rect *clip);
--
2.33.0
[PATCH v3 1/3] of: Move simple-framebuffer device handling from simplefb to of
This code is required for both simplefb and simpledrm, so let's move it
into the OF core instead of having it as an ad-hoc initcall in the
drivers.
Acked-by: Thomas Zimmermann
Signed-off-by: Hector Martin
---
drivers/of/platform.c | 4
drivers/video/fbdev/simplefb.c | 21 +
2 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index b3faf89744aa..793350028906 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -540,6 +540,10 @@ static int __init of_platform_default_populate_init(void)
of_node_put(node);
}
+ node = of_get_compatible_child(of_chosen, "simple-framebuffer");
+ of_platform_device_create(node, NULL, NULL);
+ of_node_put(node);
+
/* Populate everything else. */
of_platform_default_populate(NULL, NULL, NULL);
diff --git a/drivers/video/fbdev/simplefb.c b/drivers/video/fbdev/simplefb.c
index b63074fd892e..57541887188b 100644
--- a/drivers/video/fbdev/simplefb.c
+++ b/drivers/video/fbdev/simplefb.c
@@ -541,26 +541,7 @@ static struct platform_driver simplefb_driver = {
.remove = simplefb_remove,
};
-static int __init simplefb_init(void)
-{
- int ret;
- struct device_node *np;
-
- ret = platform_driver_register(_driver);
- if (ret)
- return ret;
-
- if (IS_ENABLED(CONFIG_OF_ADDRESS) && of_chosen) {
- for_each_child_of_node(of_chosen, np) {
- if (of_device_is_compatible(np, "simple-framebuffer"))
- of_platform_device_create(np, NULL, NULL);
- }
- }
-
- return 0;
-}
-
-fs_initcall(simplefb_init);
+module_platform_driver(simplefb_driver);
MODULE_AUTHOR("Stephen Warren ");
MODULE_DESCRIPTION("Simple framebuffer driver");
--
2.33.0
[PATCH v3 0/3] drm/simpledrm: Apple M1 / DT platform support fixes
Hi DRM folks, This short series makes simpledrm work on Apple M1 (including Pro/Max) platforms the way simplefb already does, by adding XRGB2101010 support and making it bind to framebuffers in /chosen the same way simplefb does. This avoids breaking the bootloader-provided framebuffer console when simpledrm is selected to replace simplefb, as these FBs always seem to be 10-bit (at least when a real screen is attached). Changes since v2: - Made 10-bit conversion code fill the LSBs - Added ARGB2101010 to supported formats list - Simplified OF core code per review feedback Hector Martin (3): of: Move simple-framebuffer device handling from simplefb to of drm/format-helper: Add drm_fb_xrgb_to_xrgb2101010_toio() drm/simpledrm: Add [AX]RGB2101010 formats drivers/gpu/drm/drm_format_helper.c | 64 + drivers/gpu/drm/tiny/simpledrm.c| 4 +- drivers/of/platform.c | 4 ++ drivers/video/fbdev/simplefb.c | 21 +- include/drm/drm_format_helper.h | 3 ++ 5 files changed, 74 insertions(+), 22 deletions(-) -- 2.33.0
Re: [syzbot] WARNING in drm_wait_one_vblank
syzbot has found a reproducer for the following issue on: HEAD commit:6f513529296f Merge tag 'for-5.16-rc4-tag' of git://git.ker.. git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=16499fc5b0 kernel config: https://syzkaller.appspot.com/x/.config?x=221ffc09e39ebbd1 dashboard link: https://syzkaller.appspot.com/bug?extid=6f7fe2dbc479dca0ed17 compiler: gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2 syz repro: https://syzkaller.appspot.com/x/repro.syz?x=17ab646db0 C reproducer: https://syzkaller.appspot.com/x/repro.c?x=17767fc5b0 IMPORTANT: if you fix the issue, please add the following tag to the commit: Reported-by: syzbot+6f7fe2dbc479dca0e...@syzkaller.appspotmail.com platform vkms: vblank wait timed out on crtc 0 WARNING: CPU: 1 PID: 3708 at drivers/gpu/drm/drm_vblank.c:1269 drm_wait_one_vblank+0x2bc/0x500 drivers/gpu/drm/drm_vblank.c:1269 Modules linked in: CPU: 1 PID: 3708 Comm: syz-executor955 Not tainted 5.16.0-rc4-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 RIP: 0010:drm_wait_one_vblank+0x2bc/0x500 drivers/gpu/drm/drm_vblank.c:1269 Code: 85 f6 0f 84 a3 01 00 00 e8 11 4c 1a fd 4c 89 ef e8 f9 34 13 00 44 89 e1 4c 89 f2 48 c7 c7 40 7d 1a 8a 48 89 c6 e8 7f 61 a3 04 <0f> 0b e9 87 fe ff ff e8 e8 4b 1a fd 31 ff 4c 89 ee e8 6e 4e 1a fd RSP: 0018:c9000298fb40 EFLAGS: 00010282 RAX: RBX: 0596 RCX: RDX: 8880766f3a00 RSI: 815f1e08 RDI: f52000531f5a RBP: 8881469f4000 R08: R09: R10: 815ebbae R11: R12: R13: 888146e02010 R14: 888146cc7500 R15: 888146e10030 FS: 572d9300() GS:8880b9d0() knlGS: CS: 0010 DS: ES: CR0: 80050033 CR2: 7fa33cdb0290 CR3: 79034000 CR4: 003506e0 DR0: DR1: DR2: DR3: DR6: fffe0ff0 DR7: 0400 Call Trace: drm_fb_helper_ioctl+0x159/0x1a0 drivers/gpu/drm/drm_fb_helper.c:1197 do_fb_ioctl+0x1d5/0x690 drivers/video/fbdev/core/fbmem.c:1175 fb_ioctl+0xe7/0x150 drivers/video/fbdev/core/fbmem.c:1189 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:874 [inline] __se_sys_ioctl fs/ioctl.c:860 [inline] __x64_sys_ioctl+0x193/0x200 fs/ioctl.c:860 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7fa33cd3c1c9 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 b1 14 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48 RSP: 002b:7ffc7e8b9d98 EFLAGS: 0246 ORIG_RAX: 0010 RAX: ffda RBX: 000f4240 RCX: 7fa33cd3c1c9 RDX: RSI: 40044620 RDI: 0004 RBP: R08: R09: R10: R11: 0246 R12: 00016e91 R13: 7ffc7e8b9dac R14: 7ffc7e8b9dd0 R15: 7ffc7e8b9dc0
[PATCH v2 2/2] dt-bindings: convert Rockchip DW MIPI DSI binding to YAML format
Convert into YAML format into format, which can be validated.
Changes:
- drop panel from example
Signed-off-by: David Heidelberg
---
v2:
- rename patch
- drop possibility for only one compatible string
- add patch for adding compatible to the PX30 dtsi
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 93 -
.../rockchip/rockchip,dw-mipi-dsi.yaml| 194 ++
2 files changed, 194 insertions(+), 93 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
create mode 100644
Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
deleted file mode 100644
index 39792f051d2d..
---
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-Rockchip specific extensions to the Synopsys Designware MIPI DSI
-
-
-Required properties:
-- #address-cells: Should be <1>.
-- #size-cells: Should be <0>.
-- compatible: one of
- "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
- "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
- "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
-- reg: Represent the physical address range of the controller.
-- interrupts: Represent the controller's interrupt to the CPU(s).
-- clocks, clock-names: Phandles to the controller's pll reference
- clock(ref) when using an internal dphy and APB clock(pclk).
- For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
- are required. As described in [1].
-- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
-- ports: contain a port node with endpoint definitions as defined in [2].
- For vopb,set the reg = <0> and set the reg = <1> for vopl.
-- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
-- video port 1 for either a panel or subsequent encoder
-
-Optional properties:
-- phys: from general PHY binding: the phandle for the PHY device.
-- phy-names: Should be "dphy" if phys references an external phy.
-- #phy-cells: Defined when used as ISP phy, should be 0.
-- power-domains: a phandle to mipi dsi power domain node.
-- resets: list of phandle + reset specifier pairs, as described in [3].
-- reset-names: string reset name, must be "apb".
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/media/video-interfaces.txt
-[3] Documentation/devicetree/bindings/reset/reset.txt
-
-Example:
- mipi_dsi: mipi@ff96 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
- reg = <0xff96 0x4000>;
- interrupts = ;
- clocks = < SCLK_MIPI_24M>, < PCLK_MIPI_DSI0>;
- clock-names = "ref", "pclk";
- resets = < SRST_MIPIDSI0>;
- reset-names = "apb";
- rockchip,grf = <>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in: port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_in_vopb: endpoint@0 {
- reg = <0>;
- remote-endpoint = <_out_mipi>;
- };
- mipi_in_vopl: endpoint@1 {
- reg = <1>;
- remote-endpoint = <_out_mipi>;
- };
- };
-
- mipi_out: port@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mipi_out_panel: endpoint {
- remote-endpoint = <_in_mipi>;
- };
- };
- };
-
- panel {
- compatible ="boe,tv080wum-nl0";
- reg = <0>;
-
- enable-gpios = < 3 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <_en>;
- backlight = <>;
-
- port {
- panel_in_mipi: endpoint {
- remote-endpoint = <_out_panel>;
- };
- };
- };
- };
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
[PATCH 2/2] drm/imx/dcss: select DRM_KMS_HELPER
DCSS can not be built without the DRM_KMS_HELPERs being available. Select this symbol to disallow this invalid configuration. Signed-off-by: Lucas Stach --- drivers/gpu/drm/imx/dcss/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/imx/dcss/Kconfig b/drivers/gpu/drm/imx/dcss/Kconfig index 2b17a964ff05..4c2158dc5540 100644 --- a/drivers/gpu/drm/imx/dcss/Kconfig +++ b/drivers/gpu/drm/imx/dcss/Kconfig @@ -1,6 +1,7 @@ config DRM_IMX_DCSS tristate "i.MX8MQ DCSS" select IMX_IRQSTEER + select DRM_KMS_HELPER select DRM_KMS_CMA_HELPER select VIDEOMODE_HELPERS depends on DRM && ARCH_MXC && ARM64 -- 2.31.1
[PATCH 1/2] drm/imx/dcss: add missing drm_bridge.h include
This has been pulled in via some other include before, which is no longer true. Signed-off-by: Lucas Stach --- drivers/gpu/drm/imx/dcss/dcss-kms.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c b/drivers/gpu/drm/imx/dcss/dcss-kms.c index 9b84df34a6a1..96a9517021fe 100644 --- a/drivers/gpu/drm/imx/dcss/dcss-kms.c +++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include -- 2.31.1
Re: [PATCH v2 2/2] drm/msm/dpu: Fix timeout issues on command mode panels
On 2021-12-12 00:49:09, Dmitry Baryshkov wrote: > On Sun, 12 Dec 2021 at 00:35, Marijn Suijten > wrote: > > [..] > > On this note, does it perhaps make more sense to call the "internal" > > _dpu_encoder_phys_cmd_wait_for_idle function directly, instead of going > > through the "public" dpu_encoder_phys_cmd_wait_for_tx_complete which > > seems solely intended to handle the wait_for_tx_complete callback? > > Either one would work. The main difference is the error message. Do > you want to see it here if the wait times out or not? I prefer calling _dpu_encoder_phys_cmd_wait_for_idle directly and optionally adding our own error message. IIRC DRM_ERROR prints source information such as the function this originated from, and that makes it impossible to distinguish between the wait_for_tx_complete callback or the invocation through dpu_encoder_phys_cmd_wait_for_commit_done anyway. - Marijn
Re: [PATCH v2 2/2] drm/msm/dpu: Fix timeout issues on command mode panels
On Sun, 12 Dec 2021 at 00:35, Marijn Suijten wrote: > > On 2021-12-09 18:02:40, AngeloGioacchino Del Regno wrote: > > Il 02/10/21 00:33, Dmitry Baryshkov ha scritto: > > > On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote: > > >> [..] > > > I've compared this with the MDP5 driver, where we always wait for PP_DONE > > > interrupt. Would it be enough to always wait for it (= always call > > > dpu_encoder_phys_cmd_wait_for_tx_complete())? > > > > > > > Jokes apart, yes it would make sense to do that, it's something that works > > at least... but we should verify that such a thing doesn't break new > > platforms > > (like sm8150 and newer). > > On sm6125 (keeping in mind that we're on llvmpipe, will bring up the GPU > later) none of this hurts the display: > > - Without this patch, so only checking for wait_for_ctl_start; > - With this patch, checking for idle if it was already started; > - With this patch altered to only ever call wait_for_tx_complete (wait > for idle), in place of wait_for_ctl_start. > > Working in the sense that glxgears, which actually reports a framerate > of approx 170 despite being on llvmpipe on an SoC that is still in > snail-mode, seems to update (commit) the panel smoothly on every > occasion. > > On this note, does it perhaps make more sense to call the "internal" > _dpu_encoder_phys_cmd_wait_for_idle function directly, instead of going > through the "public" dpu_encoder_phys_cmd_wait_for_tx_complete which > seems solely intended to handle the wait_for_tx_complete callback? Either one would work. The main difference is the error message. Do you want to see it here if the wait times out or not? -- With best wishes Dmitry
[PATCH v2 1/3] dt-bindings: sharp, lq101r1sx01: Add compatible for LQ101R1SX03
From: Anton Bambura LQ101R1SX03 is compatible with LQ101R1SX01 from software perspective, document it. The LQ101R1SX03 is a newer revision of LQ101R1SX01, it has minor differences in hardware pins in comparison to the older version. The newer version of the panel can be found on Android tablets, like ASUS TF701T. Signed-off-by: Anton Bambura Signed-off-by: Dmitry Osipenko --- .../bindings/display/panel/sharp,lq101r1sx01.yaml | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml b/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml index a679d3647dbd..9ec0e8aae4c6 100644 --- a/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml +++ b/Documentation/devicetree/bindings/display/panel/sharp,lq101r1sx01.yaml @@ -30,7 +30,12 @@ allOf: properties: compatible: -const: sharp,lq101r1sx01 +oneOf: + - items: + - const: sharp,lq101r1sx03 + - const: sharp,lq101r1sx01 + - items: + - const: sharp,lq101r1sx01 reg: true power-supply: true -- 2.33.1
[PATCH v2 3/3] drm/panel: simple: Add support for HannStar HSD101PWW2 panel
From: Svyatoslav Ryhel
Add definition of the HannStar HSD101PWW2 Rev0-A00/A01 LCD
SuperIPS+ HD panel.
Signed-off-by: Svyatoslav Ryhel
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index dde033066f3d..f86378ff32a5 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1927,6 +1927,31 @@ static const struct panel_desc hannstar_hsd100pxn1 = {
.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
+static const struct display_timing hannstar_hsd101pww2_timing = {
+ .pixelclock = { 6430, 7110, 8200 },
+ .hactive = { 1280, 1280, 1280 },
+ .hfront_porch = { 1, 1, 10 },
+ .hback_porch = { 1, 1, 10 },
+ .hsync_len = { 58, 158, 661 },
+ .vactive = { 800, 800, 800 },
+ .vfront_porch = { 1, 1, 10 },
+ .vback_porch = { 1, 1, 10 },
+ .vsync_len = { 1, 21, 203 },
+ .flags = DISPLAY_FLAGS_DE_HIGH,
+};
+
+static const struct panel_desc hannstar_hsd101pww2 = {
+ .timings = _hsd101pww2_timing,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 217,
+ .height = 136,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
.clock = 3,
.hdisplay = 800,
@@ -3775,6 +3800,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "hannstar,hsd100pxn1",
.data = _hsd100pxn1,
+ }, {
+ .compatible = "hannstar,hsd101pww2",
+ .data = _hsd101pww2,
}, {
.compatible = "hit,tx23d38vm0caa",
.data = _tx23d38vm0caa
--
2.33.1
[PATCH v2 2/3] dt-bindings: display: simple: Add HannStar HSD101PWW2
From: Svyatoslav Ryhel Add HannStar HSD101PWW2 10.1" WXGA (1280x800) TFT-LCD LVDS panel to the list of compatibles. Acked-by: Rob Herring Signed-off-by: Svyatoslav Ryhel Signed-off-by: Dmitry Osipenko --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index f3c9395d23b6..ecb9a79c2e78 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -156,6 +156,8 @@ properties: - hannstar,hsd070pww1 # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel - hannstar,hsd100pxn1 +# HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel + - hannstar,hsd101pww2 # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel - hit,tx23d38vm0caa # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel -- 2.33.1
[PATCH v2 0/3] Support Sharp LQ101R1SX03 and HannStar HSD101PWW2 panels
This series adds support for Sharp LQ101R1SX03 and HannStar HSD101PWW2 display panels that are used by Asus Transformer tablets, which we're planning to support since 5.17 kernel. Changelog: v2: - Added ack from Rob Herring to the HSD101PWW2 binding. - Updated LQ101R1SX01 binding, like it was suggested by Rob Herring, making LQ101R1SX03 directly compatible with the LQ101R1SX01. Such that ["sharp,lq101r1sx03", "sharp,lq101r1sx01"] could be used in DT. This removes need to update panel driver with the new compatible. - Improved commit message of the LQ101R1SX03 patch. - Added my s-o-b to all patches. Anton Bambura (1): dt-bindings: sharp,lq101r1sx01: Add compatible for LQ101R1SX03 Svyatoslav Ryhel (2): dt-bindings: display: simple: Add HannStar HSD101PWW2 drm/panel: simple: Add support for HannStar HSD101PWW2 panel .../bindings/display/panel/panel-simple.yaml | 2 ++ .../display/panel/sharp,lq101r1sx01.yaml | 7 - drivers/gpu/drm/panel/panel-simple.c | 28 +++ 3 files changed, 36 insertions(+), 1 deletion(-) -- 2.33.1
Re: [PATCH v2 2/2] drm/msm/dpu: Fix timeout issues on command mode panels
On 2021-12-09 18:02:40, AngeloGioacchino Del Regno wrote: > Il 02/10/21 00:33, Dmitry Baryshkov ha scritto: > > On 11/09/2021 19:39, AngeloGioacchino Del Regno wrote: > >> [..] > > I've compared this with the MDP5 driver, where we always wait for PP_DONE > > interrupt. Would it be enough to always wait for it (= always call > > dpu_encoder_phys_cmd_wait_for_tx_complete())? > > > > Jokes apart, yes it would make sense to do that, it's something that works > at least... but we should verify that such a thing doesn't break new platforms > (like sm8150 and newer). On sm6125 (keeping in mind that we're on llvmpipe, will bring up the GPU later) none of this hurts the display: - Without this patch, so only checking for wait_for_ctl_start; - With this patch, checking for idle if it was already started; - With this patch altered to only ever call wait_for_tx_complete (wait for idle), in place of wait_for_ctl_start. Working in the sense that glxgears, which actually reports a framerate of approx 170 despite being on llvmpipe on an SoC that is still in snail-mode, seems to update (commit) the panel smoothly on every occasion. On this note, does it perhaps make more sense to call the "internal" _dpu_encoder_phys_cmd_wait_for_idle function directly, instead of going through the "public" dpu_encoder_phys_cmd_wait_for_tx_complete which seems solely intended to handle the wait_for_tx_complete callback? - Marijn
[PATCH 7/7] drm/i915/guc: Selftest for stealing of guc ids
Testing the stealing of guc ids is hard from user space as we have 64k
guc_ids. Add a selftest, which artificially reduces the number of guc
ids, and forces a steal. Description of test below.
The test creates a spinner which is used to block all subsequent
submissions until it completes. Next, a loop creates a context and a NOP
request each iteration until the guc_ids are exhausted (request creation
returns -EAGAIN). The spinner is ended, unblocking all requests created
in the loop. At this point all guc_ids are exhausted but are available
to steal. Try to create another request which should successfully steal
a guc_id. Wait on last request to complete, idle GPU, verify a guc_id
was stolen via a counter, and exit the test. Test also artificially
reduces the number of guc_ids so the test runs in a timely manner.
v2:
(John Harrison)
- s/stole/stolen
- Fix some wording in test description
- Rework indexing into context array
- Add test description to commit message
- Fix typo in commit message
(Checkpatch)
- s/guc/(guc) in NUMBER_MULTI_LRC_GUC_ID
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 12 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 +-
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 173 ++
3 files changed, 196 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 1cb46098030d..f9240d4baa69 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -94,6 +94,11 @@ struct intel_guc {
* @guc_ids: used to allocate new guc_ids, single-lrc
*/
struct ida guc_ids;
+ /**
+* @num_guc_ids: Number of guc_ids, selftest feature to be able
+* to reduce this number while testing.
+*/
+ int num_guc_ids;
/**
* @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc
*/
@@ -202,6 +207,13 @@ struct intel_guc {
*/
struct delayed_work work;
} timestamp;
+
+#ifdef CONFIG_DRM_I915_SELFTEST
+ /**
+* @number_guc_id_stolen: The number of guc_ids that have been stolen
+*/
+ int number_guc_id_stolen;
+#endif
};
static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 96fcf869e3ff..99414b49ca6d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -145,7 +145,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
* use should be low and 1/16 should be sufficient. Minimum of 32 guc_ids for
* multi-lrc.
*/
-#define NUMBER_MULTI_LRC_GUC_ID(GUC_MAX_LRC_DESCRIPTORS / 16)
+#define NUMBER_MULTI_LRC_GUC_ID(guc) \
+ ((guc)->submission_state.num_guc_ids / 16)
/*
* Below is a set of functions which control the GuC scheduling state which
@@ -1775,7 +1776,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
destroyed_worker_func);
guc->submission_state.guc_ids_bitmap =
- bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID, GFP_KERNEL);
+ bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
if (!guc->submission_state.guc_ids_bitmap)
return -ENOMEM;
@@ -1869,13 +1870,13 @@ static int new_guc_id(struct intel_guc *guc, struct
intel_context *ce)
if (intel_context_is_parent(ce))
ret =
bitmap_find_free_region(guc->submission_state.guc_ids_bitmap,
- NUMBER_MULTI_LRC_GUC_ID,
+ NUMBER_MULTI_LRC_GUC_ID(guc),
order_base_2(ce->parallel.number_children
+ 1));
else
ret = ida_simple_get(>submission_state.guc_ids,
-NUMBER_MULTI_LRC_GUC_ID,
-GUC_MAX_LRC_DESCRIPTORS,
+NUMBER_MULTI_LRC_GUC_ID(guc),
+guc->submission_state.num_guc_ids,
GFP_KERNEL | __GFP_RETRY_MAYFAIL |
__GFP_NOWARN);
if (unlikely(ret < 0))
@@ -1941,6 +1942,10 @@ static int steal_guc_id(struct intel_guc *guc, struct
intel_context *ce)
set_context_guc_id_invalid(cn);
+#ifdef CONFIG_DRM_I915_SELFTEST
+ guc->number_guc_id_stolen++;
+#endif
+
return 0;
} else {
return -EAGAIN;
@@ -3779,6 +3784,7 @@ static bool __guc_submission_selected(struct intel_guc
*guc)
void intel_guc_submission_init_early(struct
[PATCH 3/7] drm/i915/guc: Remove racey GEM_BUG_ON
A full GT reset can race with the last context put resulting in the
context ref count being zero but the destroyed bit not yet being set.
Remove GEM_BUG_ON in scrub_guc_desc_for_outstanding_g2h that asserts the
destroyed bit must be set in ref count is zero.
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0fb2eeff0262..36c2965db49b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1040,8 +1040,6 @@ static void scrub_guc_desc_for_outstanding_g2h(struct
intel_guc *guc)
spin_unlock(>guc_state.lock);
- GEM_BUG_ON(!do_put && !destroyed);
-
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
if (deregister)
--
2.33.1
[PATCH 6/7] drm/i915/guc: Kick G2H tasklet if no credits
Let's be paranoid and kick the G2H tasklet, which dequeues messages, if
G2H credits are exhausted.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 741be9abab68..aa6dd6415202 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -591,12 +591,19 @@ static inline bool h2g_has_room(struct intel_guc_ct *ct,
u32 len_dw)
static int has_room_nb(struct intel_guc_ct *ct, u32 h2g_dw, u32 g2h_dw)
{
+ bool h2g = h2g_has_room(ct, h2g_dw);
+ bool g2h = g2h_has_room(ct, g2h_dw);
+
lockdep_assert_held(>ctbs.send.lock);
- if (unlikely(!h2g_has_room(ct, h2g_dw) || !g2h_has_room(ct, g2h_dw))) {
+ if (unlikely(!h2g || !g2h)) {
if (ct->stall_time == KTIME_MAX)
ct->stall_time = ktime_get();
+ /* Be paranoid and kick G2H tasklet to free credits */
+ if (!g2h)
+ tasklet_hi_schedule(>receive_tasklet);
+
if (unlikely(ct_deadlocked(ct)))
return -EPIPE;
else
--
2.33.1
[PATCH 5/7] drm/i915/guc: Add extra debug on CT deadlock
Print CT state (H2G + G2H head / tail pointers, credits) on CT deadlock. v2: (John Harrison) - Add units to debug messages Reviewed-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index a0cc34be7b56..741be9abab68 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -523,6 +523,15 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", ktime_ms_delta(ktime_get(), ct->stall_time), send->status, recv->status); + CT_ERROR(ct, "H2G Space: %u (Bytes)\n", +atomic_read(>ctbs.send.space) * 4); + CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); + CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); + CT_ERROR(ct, "G2H Space: %u (Bytes)\n", +atomic_read(>ctbs.recv.space) * 4); + CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); + CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); + ct->ctbs.send.broken = true; } -- 2.33.1
[PATCH 2/7] drm/i915/guc: Only assign guc_id.id when stealing guc_id
Previously assigned whole guc_id structure (list, spin lock) which is
incorrect, only assign the guc_id.id.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost
Reviewed-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9b7b4f4e0d91..0fb2eeff0262 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1935,7 +1935,7 @@ static int steal_guc_id(struct intel_guc *guc, struct
intel_context *ce)
GEM_BUG_ON(intel_context_is_parent(cn));
list_del_init(>guc_id.link);
- ce->guc_id = cn->guc_id;
+ ce->guc_id.id = cn->guc_id.id;
spin_lock(>guc_state.lock);
clr_context_registered(cn);
--
2.33.1
[PATCH 4/7] drm/i915/guc: Don't hog IRQs when destroying contexts
From: John Harrison
While attempting to debug a CT deadlock issue in various CI failures
(most easily reproduced with gem_ctx_create/basic-files), I was seeing
CPU deadlock errors being reported. This were because the context
destroy loop was blocking waiting on H2G space from inside an IRQ
spinlock. There no was deadlock as such, it's just that the H2G queue
was full of context destroy commands and GuC was taking a long time to
process them. However, the kernel was seeing the large amount of time
spent inside the IRQ lock as a dead CPU. Various Bad Things(tm) would
then happen (heartbeat failures, CT deadlock errors, outstanding H2G
WARNs, etc.).
Re-working the loop to only acquire the spinlock around the list
management (which is all it is meant to protect) rather than the
entire destroy operation seems to fix all the above issues.
v2:
(John Harrison)
- Fix typo in comment message
Signed-off-by: John Harrison
Signed-off-by: Matthew Brost
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 ---
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 36c2965db49b..96fcf869e3ff 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2644,7 +2644,6 @@ static inline void guc_lrc_desc_unpin(struct
intel_context *ce)
unsigned long flags;
bool disabled;
- lockdep_assert_held(>submission_state.lock);
GEM_BUG_ON(!intel_gt_pm_is_awake(gt));
GEM_BUG_ON(!lrc_desc_registered(guc, ce->guc_id.id));
GEM_BUG_ON(ce != __get_context(guc, ce->guc_id.id));
@@ -2660,7 +2659,7 @@ static inline void guc_lrc_desc_unpin(struct
intel_context *ce)
}
spin_unlock_irqrestore(>guc_state.lock, flags);
if (unlikely(disabled)) {
- __release_guc_id(guc, ce);
+ release_guc_id(guc, ce);
__guc_context_destroy(ce);
return;
}
@@ -2694,36 +2693,48 @@ static void __guc_context_destroy(struct intel_context
*ce)
static void guc_flush_destroyed_contexts(struct intel_guc *guc)
{
- struct intel_context *ce, *cn;
+ struct intel_context *ce;
unsigned long flags;
GEM_BUG_ON(!submission_disabled(guc) &&
guc_submission_initialized(guc));
- spin_lock_irqsave(>submission_state.lock, flags);
- list_for_each_entry_safe(ce, cn,
->submission_state.destroyed_contexts,
-destroyed_link) {
- list_del_init(>destroyed_link);
- __release_guc_id(guc, ce);
+ while (!list_empty(>submission_state.destroyed_contexts)) {
+ spin_lock_irqsave(>submission_state.lock, flags);
+ ce =
list_first_entry_or_null(>submission_state.destroyed_contexts,
+ struct intel_context,
+ destroyed_link);
+ if (ce)
+ list_del_init(>destroyed_link);
+ spin_unlock_irqrestore(>submission_state.lock, flags);
+
+ if (!ce)
+ break;
+
+ release_guc_id(guc, ce);
__guc_context_destroy(ce);
}
- spin_unlock_irqrestore(>submission_state.lock, flags);
}
static void deregister_destroyed_contexts(struct intel_guc *guc)
{
- struct intel_context *ce, *cn;
+ struct intel_context *ce;
unsigned long flags;
- spin_lock_irqsave(>submission_state.lock, flags);
- list_for_each_entry_safe(ce, cn,
->submission_state.destroyed_contexts,
-destroyed_link) {
- list_del_init(>destroyed_link);
+ while (!list_empty(>submission_state.destroyed_contexts)) {
+ spin_lock_irqsave(>submission_state.lock, flags);
+ ce =
list_first_entry_or_null(>submission_state.destroyed_contexts,
+ struct intel_context,
+ destroyed_link);
+ if (ce)
+ list_del_init(>destroyed_link);
+ spin_unlock_irqrestore(>submission_state.lock, flags);
+
+ if (!ce)
+ break;
+
guc_lrc_desc_unpin(ce);
}
- spin_unlock_irqrestore(>submission_state.lock, flags);
}
static void destroyed_worker_func(struct work_struct *w)
--
2.33.1
[PATCH 1/7] drm/i915/guc: Use correct context lock when callig clr_context_registered
s/ce/cn/ when grabbing guc_state.lock before calling
clr_context_registered.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1f9d4fde421f..9b7b4f4e0d91 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1937,9 +1937,9 @@ static int steal_guc_id(struct intel_guc *guc, struct
intel_context *ce)
list_del_init(>guc_id.link);
ce->guc_id = cn->guc_id;
- spin_lock(>guc_state.lock);
+ spin_lock(>guc_state.lock);
clr_context_registered(cn);
- spin_unlock(>guc_state.lock);
+ spin_unlock(>guc_state.lock);
set_context_guc_id_invalid(cn);
--
2.33.1
[PATCH 0/7] Fix stealing guc_ids + test
Patches 1 & 2 address bugs in stealing of guc_ids and patch 7 tests this path. Patches 4-6 address some issues with the CTs exposed by the selftest in patch 7. Basically if a lot of contexts were all deregistered all at once, the CT channel could deadlock. Patch 3 is a small fix that is already review but just included for CI. v2: Address comments, resend for CI Signed-off-by: Matthew Brost John Harrison (1): drm/i915/guc: Don't hog IRQs when destroying contexts Matthew Brost (6): drm/i915/guc: Use correct context lock when callig clr_context_registered drm/i915/guc: Only assign guc_id.id when stealing guc_id drm/i915/guc: Remove racey GEM_BUG_ON drm/i915/guc: Add extra debug on CT deadlock drm/i915/guc: Kick G2H tasklet if no credits drm/i915/guc: Selftest for stealing of guc ids drivers/gpu/drm/i915/gt/uc/intel_guc.h| 12 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 18 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 --- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 173 ++ 4 files changed, 244 insertions(+), 28 deletions(-) -- 2.33.1
[drm-intel:topic/core-for-CI 16/25] arch/powerpc/platforms/embedded6xx/Kconfig:2:error: recursive dependency detected!
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI head: 4c82fd0506b4cc196a375d1200361fb0c5439acd commit: b3acf17eafd473e6e8f8f7c5ec7040efaaff22b8 [16/25] Revert "drm/i915: Don't select BROKEN" config: powerpc64-randconfig-r015-20211210 compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 097a1cb1d5ebb3a0ec4bcaed8ba3ff6a8e33c00a) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install powerpc64 cross compiling tool for clang build # apt-get install binutils-powerpc-linux-gnu git remote add drm-intel git://anongit.freedesktop.org/drm-intel git fetch --no-tags drm-intel topic/core-for-CI git checkout b3acf17eafd473e6e8f8f7c5ec7040efaaff22b8 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc randconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=powerpc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> arch/powerpc/platforms/embedded6xx/Kconfig:2:error: recursive dependency >> detected! arch/powerpc/platforms/embedded6xx/Kconfig:2: symbol EMBEDDED6xx depends on BROKEN_ON_SMP init/Kconfig:113: symbol BROKEN_ON_SMP depends on BROKEN init/Kconfig:110: symbol BROKEN is selected by DRM_I915_DEBUG drivers/gpu/drm/i915/Kconfig.debug:19: symbol DRM_I915_DEBUG depends on DRM_I915 drivers/gpu/drm/i915/Kconfig:2: symbol DRM_I915 depends on DRM drivers/gpu/drm/Kconfig:8: symbol DRM depends on AGP drivers/char/agp/Kconfig:2: symbol AGP depends on PCI drivers/pci/Kconfig:16: symbol PCI depends on HAVE_PCI drivers/pci/Kconfig:7: symbol HAVE_PCI is selected by FORCE_PCI drivers/pci/Kconfig:11: symbol FORCE_PCI is selected by MVME5100 arch/powerpc/platforms/embedded6xx/Kconfig:51: symbol MVME5100 depends on EMBEDDED6xx For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" vim +2 arch/powerpc/platforms/embedded6xx/Kconfig a35e370cfd2ddf Arnd Bergmann2007-08-30 @2 config EMBEDDED6xx a35e370cfd2ddf Arnd Bergmann2007-08-30 3 bool "Embedded 6xx/7xx/7xxx-based boards" be34fff07c3755 Christophe Leroy 2018-11-17 4 depends on PPC_BOOK3S_32 && BROKEN_ON_SMP 14cf11af6cf608 Paul Mackerras 2005-09-26 5 :: The code at line 2 was first introduced by commit :: a35e370cfd2ddfb5d2f0ceae376ffeda273b357c [POWERPC] Move embedded6xx into multiplatform :: TO: Arnd Bergmann :: CC: Paul Mackerras --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[drm-intel:topic/core-for-CI 16/25] arch/powerpc/platforms/embedded6xx/Kconfig:2:error: recursive dependency detected!
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI head: 4c82fd0506b4cc196a375d1200361fb0c5439acd commit: b3acf17eafd473e6e8f8f7c5ec7040efaaff22b8 [16/25] Revert "drm/i915: Don't select BROKEN" config: powerpc-randconfig-r035-20211210 compiler: powerpc-linux-gcc (GCC) 11.2.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git remote add drm-intel git://anongit.freedesktop.org/drm-intel git fetch --no-tags drm-intel topic/core-for-CI git checkout b3acf17eafd473e6e8f8f7c5ec7040efaaff22b8 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=powerpc randconfig COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=powerpc If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> arch/powerpc/platforms/embedded6xx/Kconfig:2:error: recursive dependency >> detected! arch/powerpc/platforms/embedded6xx/Kconfig:2: symbol EMBEDDED6xx depends on BROKEN_ON_SMP init/Kconfig:113: symbol BROKEN_ON_SMP depends on BROKEN init/Kconfig:110: symbol BROKEN is selected by DRM_I915_DEBUG drivers/gpu/drm/i915/Kconfig.debug:19: symbol DRM_I915_DEBUG depends on DRM_I915 drivers/gpu/drm/i915/Kconfig:2: symbol DRM_I915 depends on DRM drivers/gpu/drm/Kconfig:8: symbol DRM depends on AGP drivers/char/agp/Kconfig:2: symbol AGP depends on PCI drivers/pci/Kconfig:16: symbol PCI depends on HAVE_PCI drivers/pci/Kconfig:7: symbol HAVE_PCI is selected by FORCE_PCI drivers/pci/Kconfig:11: symbol FORCE_PCI is selected by MVME5100 arch/powerpc/platforms/embedded6xx/Kconfig:51: symbol MVME5100 depends on EMBEDDED6xx For a resolution refer to Documentation/kbuild/kconfig-language.rst subsection "Kconfig recursive dependency limitations" vim +2 arch/powerpc/platforms/embedded6xx/Kconfig a35e370cfd2ddf Arnd Bergmann2007-08-30 @2 config EMBEDDED6xx a35e370cfd2ddf Arnd Bergmann2007-08-30 3 bool "Embedded 6xx/7xx/7xxx-based boards" be34fff07c3755 Christophe Leroy 2018-11-17 4 depends on PPC_BOOK3S_32 && BROKEN_ON_SMP 14cf11af6cf608 Paul Mackerras 2005-09-26 5 :: The code at line 2 was first introduced by commit :: a35e370cfd2ddfb5d2f0ceae376ffeda273b357c [POWERPC] Move embedded6xx into multiplatform :: TO: Arnd Bergmann :: CC: Paul Mackerras --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [PATCH 1/2] drm/amd/display: Reduce stack size for dml31_ModeSupportAndSystemConfigurationFull
On 2021-12-09 11:46 a.m., Michel Dänzer wrote:
From: Michel Dänzer
Move code using the Pipe struct to a new helper function.
Works around[0] this warning (resulting in failure to build a RHEL debug
kernel with Werror enabled):
../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c: In
function ‘dml31_ModeSupportAndSystemConfigurationFull’:
../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:5740:1:
warning: the frame size of 2144 bytes is larger than 2048 bytes
[-Wframe-larger-than=]
The culprit seems to be the Pipe struct, so pull the relevant block out
into its own sub-function. (This is porting
a62427ef9b55 "drm/amd/display: Reduce stack size for
dml21_ModeSupportAndSystemConfigurationFull"
from dml31 to dml21)
[0] AFAICT this doesn't actually reduce the total amount of stack which
can be used, just moves some of it from
dml31_ModeSupportAndSystemConfigurationFull to the new helper function,
so the former happens to no longer exceed the limit for a single
function.
Signed-off-by: Michel Dänzer
---
.../dc/dml/dcn31/display_mode_vba_31.c| 185 ++
1 file changed, 99 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 7e937bdcea00..8965f9af9d0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -3949,6 +3949,102 @@ static double TruncToValidBPP(
return BPP_INVALID;
}
+static noinline void CalculatePrefetchSchedulePerPlane(
+ struct display_mode_lib *mode_lib,
+ double HostVMInefficiencyFactor,
+ int i,
+ unsigned j,
+ unsigned k)
+{
+ struct vba_vars_st *v = _lib->vba;
+ Pipe myPipe;
+
+ myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
+ myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
+ myPipe.PixelClock = v->PixelClock[k];
+ myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
+ myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
+ myPipe.ScalerEnabled = v->ScalerEnabled[k];
+ myPipe.SourceScan = v->SourceScan[k];
+ myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
+ myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
+ myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
+ myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
+ myPipe.InterlaceEnable = v->Interlace[k];
+ myPipe.NumberOfCursors = v->NumberOfCursors[k];
+ myPipe.VBlank = v->VTotal[k] - v->VActive[k];
+ myPipe.HTotal = v->HTotal[k];
+ myPipe.DCCEnable = v->DCCEnable[k];
+ myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] ==
dm_odm_combine_mode_4to1
+ || v->ODMCombineEnablePerState[i][k] ==
dm_odm_combine_mode_2to1;
+ myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
+ myPipe.BytePerPixelY = v->BytePerPixelY[k];
+ myPipe.BytePerPixelC = v->BytePerPixelC[k];
+ myPipe.ProgressiveToInterlaceUnitInOPP =
v->ProgressiveToInterlaceUnitInOPP;
+ v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
+ mode_lib,
+ HostVMInefficiencyFactor,
+ ,
+ v->DSCDelayPerState[i][k],
+ v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
+ v->DPPCLKDelaySCL,
+ v->DPPCLKDelaySCLLBOnly,
+ v->DPPCLKDelayCNVCCursor,
+ v->DISPCLKDelaySubtotal,
+ v->SwathWidthYThisState[k] / v->HRatio[k],
+ v->OutputFormat[k],
+ v->MaxInterDCNTileRepeaters,
+ dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
+ v->MaximumVStartup[i][j][k],
+ v->GPUVMMaxPageTableLevels,
+ v->GPUVMEnable,
+ v->HostVMEnable,
+ v->HostVMMaxNonCachedPageTableLevels,
+ v->HostVMMinPageSize,
+ v->DynamicMetadataEnable[k],
+ v->DynamicMetadataVMEnabled,
+ v->DynamicMetadataLinesBeforeActiveRequired[k],
+ v->DynamicMetadataTransmittedBytes[k],
+ v->UrgLatency[i],
+ v->ExtraLatency,
+ v->TimeCalc,
+ v->PDEAndMetaPTEBytesPerFrame[i][j][k],
+ v->MetaRowBytes[i][j][k],
+ v->DPTEBytesPerRow[i][j][k],
+ v->PrefetchLinesY[i][j][k],
+ v->SwathWidthYThisState[k],
+ v->PrefillY[k],
+ v->MaxNumSwY[k],
+ v->PrefetchLinesC[i][j][k],
+ v->SwathWidthCThisState[k],
+ v->PrefillC[k],
+ v->MaxNumSwC[k],
+ v->swath_width_luma_ub_this_state[k],
+ v->swath_width_chroma_ub_this_state[k],
+
Re: [PATCH] dt-bindings: convert power domain node for rockchip DW MIPI DSI
Hi David, Am Montag, 6. Dezember 2021, 22:26:50 CET schrieb David Heidelberg: > Convert into YAML format into format, which can be validated. > > Changes: > - drop panel from example the patch subject is strange, talking about a "power domain node". That needs a fix. Some more things below. > +properties: > + compatible: > +oneOf: > + - items: > + - enum: > + - rockchip,px30-mipi-dsi > + - rockchip,rk3288-mipi-dsi > + - rockchip,rk3399-mipi-dsi > + - const: snps,dw-mipi-dsi > + - items: > + - const: rockchip,px30-mipi-dsi > + - items: > + - const: rockchip,rk3288-mipi-dsi > + - items: > + - const: rockchip,rk3399-mipi-dsi what are these for? I see that px30 uses the dsi without the snps part, but you can also just add a patch adding that second compatible to px30.dtsi I don't think we need to support both ways. > + > + reg: > +maxItems: 1 > + > + interrupts: > +maxItems: 1 > + > + clocks: true > + > + clock-names: true > + > + phys: > +maxItems: 1 > +description: The external PHY make that "Optional external PHY perhaps"? Heiko
Re: [PATCH] drm/nouveau: wait for the exclusive fence after the shared ones v2
On 09.12.21 11:23, Christian König wrote:
Always waiting for the exclusive fence resulted on some performance
regressions. So try to wait for the shared fences first, then the
exclusive fence should always be signaled already.
v2: fix incorrectly placed "(", add some comment why we do this.
Signed-off-by: Christian König
Tested-by: Stefan Fritsch
Please also add a cc for linux-stable, so that this is fixed in 5.15.x
Cheers,
Stefan
---
drivers/gpu/drm/nouveau/nouveau_fence.c | 28 +
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c
b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 05d0b3eb3690..0ae416aa76dc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -353,15 +353,22 @@ nouveau_fence_sync(struct nouveau_bo *nvbo, struct
nouveau_channel *chan, bool e
if (ret)
return ret;
- }
- fobj = dma_resv_shared_list(resv);
- fence = dma_resv_excl_fence(resv);
+ fobj = NULL;
+ } else {
+ fobj = dma_resv_shared_list(resv);
+ }
- if (fence) {
+ /* Waiting for the exclusive fence first causes performance regressions
+* under some circumstances. So manually wait for the shared ones first.
+*/
+ for (i = 0; i < (fobj ? fobj->shared_count : 0) && !ret; ++i) {
struct nouveau_channel *prev = NULL;
bool must_wait = true;
+ fence = rcu_dereference_protected(fobj->shared[i],
+ dma_resv_held(resv));
+
f = nouveau_local_fence(fence, chan->drm);
if (f) {
rcu_read_lock();
@@ -373,20 +380,13 @@ nouveau_fence_sync(struct nouveau_bo *nvbo, struct
nouveau_channel *chan, bool e
if (must_wait)
ret = dma_fence_wait(fence, intr);
-
- return ret;
}
- if (!exclusive || !fobj)
- return ret;
-
- for (i = 0; i < fobj->shared_count && !ret; ++i) {
+ fence = dma_resv_excl_fence(resv);
+ if (fence) {
struct nouveau_channel *prev = NULL;
bool must_wait = true;
- fence = rcu_dereference_protected(fobj->shared[i],
- dma_resv_held(resv));
-
f = nouveau_local_fence(fence, chan->drm);
if (f) {
rcu_read_lock();
@@ -398,6 +398,8 @@ nouveau_fence_sync(struct nouveau_bo *nvbo, struct
nouveau_channel *chan, bool e
if (must_wait)
ret = dma_fence_wait(fence, intr);
+
+ return ret;
}
return ret;
Re: Reuse framebuffer after a kexec (amdgpu / efifb)
On Fri, Dec 10, 2021 at 07:54:34PM -0500, Felix Kuehling wrote: > Do you actually need to restore the exact boot-up mode? If you have the same > framebuffer memory layout (width, height, bpp, stride) the precise display > timing doesn't really matter. So we "just" need to switch to a mode that's > compatible with the efifb framebuffer parameters and point the display > engine at the efifb as the scan-out buffer. That'll probably doable for a normal kexec but in case of a crashdump kexec I don't think it is a good idea to touch the gpu using the driver of the kernel which just crashed ... take care, Gerd
