date:20220422

The i.MX8MP contains two syscon registers which are responsible
for configuring the on-SoC DPI-to-LVDS serializer. Implement a
simple bridge driver for this serializer.

Reviewed-by: Sam Ravnborg 
Signed-off-by: Marek Vasut 
Cc: Laurent Pinchart 
Cc: Lucas Stach 
Cc: Maxime Ripard 
Cc: Peng Fan 
Cc: Robby Cai 
Cc: Robert Foss 
Cc: Sam Ravnborg 
Cc: Thomas Zimmermann 
To: dri-devel@lists.freedesktop.org
--
V2: - Rename syscon to fsl,syscon
V3: - Consistently use MX8MP
- Add sentinel of_device_table
- Add RB from Sam
---
 drivers/gpu/drm/bridge/Kconfig   |   8 +
 drivers/gpu/drm/bridge/Makefile  |   1 +
 drivers/gpu/drm/bridge/nxp-ldb.c | 343 +++
 3 files changed, 352 insertions(+)
 create mode 100644 drivers/gpu/drm/bridge/nxp-ldb.c

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 20f9bc7f4be5..3ea2f2745e33 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -185,6 +185,14 @@ config DRM_NWL_MIPI_DSI
  This enables the Northwest Logic MIPI DSI Host controller as
  for example found on NXP's i.MX8 Processors.
 
+config DRM_NXP_LDB
+   tristate "NXP i.MX8MP LDB bridge"
+   depends on OF
+   select DRM_KMS_HELPER
+   select DRM_PANEL_BRIDGE
+   help
+ Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
+
 config DRM_NXP_PTN3460
tristate "NXP PTN3460 DP/LVDS bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index bdffad2a7ed3..f800b2331d9e 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
 obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o
 obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
 obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += 
megachips-stdp-ge-b850v3-fw.o
+obj-$(CONFIG_DRM_NXP_LDB) += nxp-ldb.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
diff --git a/drivers/gpu/drm/bridge/nxp-ldb.c b/drivers/gpu/drm/bridge/nxp-ldb.c
new file mode 100644
index ..0c8954e0f329
--- /dev/null
+++ b/drivers/gpu/drm/bridge/nxp-ldb.c
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2022 Marek Vasut 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define LDB_CTRL   0x5c
+#define LDB_CTRL_CH0_ENABLEBIT(0)
+#define LDB_CTRL_CH0_DI_SELECT BIT(1)
+#define LDB_CTRL_CH1_ENABLEBIT(2)
+#define LDB_CTRL_CH1_DI_SELECT BIT(3)
+#define LDB_CTRL_SPLIT_MODEBIT(4)
+#define LDB_CTRL_CH0_DATA_WIDTHBIT(5)
+#define LDB_CTRL_CH0_BIT_MAPPING   BIT(6)
+#define LDB_CTRL_CH1_DATA_WIDTHBIT(7)
+#define LDB_CTRL_CH1_BIT_MAPPING   BIT(8)
+#define LDB_CTRL_DI0_VSYNC_POLARITYBIT(9)
+#define LDB_CTRL_DI1_VSYNC_POLARITYBIT(10)
+#define LDB_CTRL_REG_CH0_FIFO_RESETBIT(11)
+#define LDB_CTRL_REG_CH1_FIFO_RESETBIT(12)
+#define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24)
+#define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25)
+
+#define LVDS_CTRL  0x128
+#define LVDS_CTRL_CH0_EN   BIT(0)
+#define LVDS_CTRL_CH1_EN   BIT(1)
+#define LVDS_CTRL_VBG_EN   BIT(2)
+#define LVDS_CTRL_HS_ENBIT(3)
+#define LVDS_CTRL_PRE_EMPH_EN  BIT(4)
+#define LVDS_CTRL_PRE_EMPH_ADJ(n)  (((n) & 0x7) << 5)
+#define LVDS_CTRL_PRE_EMPH_ADJ_MASKGENMASK(7, 5)
+#define LVDS_CTRL_CM_ADJ(n)(((n) & 0x7) << 8)
+#define LVDS_CTRL_CM_ADJ_MASK  GENMASK(10, 8)
+#define LVDS_CTRL_CC_ADJ(n)(((n) & 0x7) << 11)
+#define LVDS_CTRL_CC_ADJ_MASK  GENMASK(13, 11)
+#define LVDS_CTRL_SLEW_ADJ(n)  (((n) & 0x7) << 14)
+#define LVDS_CTRL_SLEW_ADJ_MASKGENMASK(16, 14)
+#define LVDS_CTRL_VBG_ADJ(n)   (((n) & 0x7) << 17)
+#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
+
+struct nxp_ldb {
+   struct device *dev;
+   struct drm_bridge bridge;
+   struct drm_bridge *panel_bridge;
+   struct clk *clk;
+   struct regmap *regmap;
+   bool lvds_dual_link;
+};
+
+static inline struct nxp_ldb *to_nxp_ldb(struct drm_bridge *bridge)
+{
+   return container_of(bridge, struct nxp_ldb, bridge);
+}
+
+static int nxp_ldb_attach(struct drm_bridge *bridge,
+   enum drm_bridge_attach_flags flags)
+{
+   struct nxp_ldb *nxp_ldb = to_nxp_ldb(bridge);
+
+   return

[PATCH v3 1/2] dt-bindings: display: bridge: ldb: Implement simple NXP i.MX8MP LDB bridge

The i.MX8MP contains two syscon registers which are responsible
for configuring the on-SoC DPI-to-LVDS serializer. Add DT binding
which represents this serializer as a bridge.

Acked-by: Sam Ravnborg 
Signed-off-by: Marek Vasut 
Cc: Laurent Pinchart 
Cc: Lucas Stach 
Cc: Maxime Ripard 
Cc: Peng Fan 
Cc: Rob Herring 
Cc: Robby Cai 
Cc: Robert Foss 
Cc: Sam Ravnborg 
Cc: Thomas Zimmermann 
Cc: devicet...@vger.kernel.org
To: dri-devel@lists.freedesktop.org
---
V2: - Consistently use fsl,imx8mp-ldb as compatible
- Drop items: from compatible:
- Replace minItems with maxItems in clocks:
- Drop quotes from clock-names const: ldb
- Rename syscon to fsl,syscon
- Use generic name of ldb-lvds in example
V3: - Add AB from Sam
- Consistently use MX8MP
---
 .../bindings/display/bridge/nxp,ldb.yaml  | 96 +++
 1 file changed, 96 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml 
b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
new file mode 100644
index ..9c1807f2ae43
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/nxp,ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP DPI to LVDS bridge chip
+
+maintainers:
+  - Marek Vasut 
+
+description: |
+  The i.MX8MP contains two syscon registers which are responsible
+  for configuring the on-SoC DPI-to-LVDS serializer. This describes
+  those registers as bridge within the DT.
+
+properties:
+  compatible:
+const: fsl,imx8mp-ldb
+
+  clocks:
+maxItems: 1
+
+  clock-names:
+const: ldb
+
+  fsl,syscon:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: A phandle to media block controller.
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Video port for DPI input.
+
+  port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: Video port for LVDS Channel-A output (panel or bridge).
+
+  port@2:
+$ref: /schemas/graph.yaml#/properties/port
+description: Video port for LVDS Channel-B output (panel or bridge).
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - clocks
+  - fsl,syscon
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+bridge {
+compatible = "fsl,imx8mp-ldb";
+clocks = < IMX8MP_CLK_MEDIA_LDB>;
+clock-names = "ldb";
+fsl,syscon = <_blk_ctrl>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+
+ldb_from_lcdif2: endpoint {
+remote-endpoint = <_to_ldb>;
+};
+};
+
+port@1 {
+reg = <1>;
+
+ldb_lvds_ch0: endpoint {
+remote-endpoint = <_to_lvdsx4panel>;
+};
+};
+
+port@2 {
+reg = <2>;
+
+ldb_lvds_ch1: endpoint {
+};
+};
+};
+};
-- 
2.35.1

Re: [PATCH v2 1/2] dt-bindings: display: bridge: ldb: Implement simple NXP i.MX8M LDB bridge


On 4/22/22 20:26, Sam Ravnborg wrote:

Hi Marek, I read the patch once more.

On Mon, Apr 18, 2022 at 04:51:04PM +0200, Marek Vasut wrote:

The i.MX8MP contains two syscon registers which are responsible


Here it says i.MX8MP


Fixed, this and the bindings.

Re: [PATCH v3 1/4] drm: mxsfb: Wrap FIFO reset and comments into mxsfb_reset_block()


On 4/22/22 20:39, Sam Ravnborg wrote:

On Sun, Apr 17, 2022 at 04:07:57AM +0200, Marek Vasut wrote:

Wrap FIFO reset and comments into mxsfb_reset_block(), this is a clean up.
No functional change.

Reviewed-by: Lucas Stach 
Signed-off-by: Marek Vasut 
Cc: Alexander Stein 
Cc: Laurent Pinchart 
Cc: Lucas Stach 
Cc: Peng Fan 
Cc: Robby Cai 
Cc: Sam Ravnborg 
Cc: Stefan Agner 

Acked-by: Sam Ravnborg 


If that's OK with everyone, I will apply those soon.

Re: [PATCH v9 4/4] drm/msm/dp: Support the eDP modes given by panel

Quoting Sankeerth Billakanti (2022-04-22 02:11:06)
> The eDP controller does not have a reliable way keep panel
> powered on to read the sink capabilities. So, the controller
> driver cannot validate if a mode can be supported by the
> source. We will rely on the panel driver to populate only
> the supported modes for now.
>
> Signed-off-by: Sankeerth Billakanti 
> Reviewed-by: Douglas Anderson 
> ---

Reviewed-by: Stephen Boyd

Re: [PATCH v9 3/4] drm/msm/dp: wait for hpd high before aux transaction

Quoting Sankeerth Billakanti (2022-04-22 02:11:05)
> The source device should ensure the sink is ready before proceeding to
> read the sink capability or perform any aux transactions. The sink
> will indicate its readiness by asserting the HPD line. The controller
> driver needs to wait for the hpd line to be asserted by the sink before
> it performs any aux transactions.
>
> The eDP sink is assumed to be always connected. It needs power from the
> source and its HPD line will be asserted only after the panel is powered
> on. The panel power will be enabled from the panel-edp driver and only
> after that, the hpd line will be asserted.
>
> Whereas for DP, the sink can be hotplugged and unplugged anytime. The hpd
> line gets asserted to indicate the sink is connected and ready. Hence
> there is no need to wait for the hpd line to be asserted for a DP sink.
>
> Signed-off-by: Sankeerth Billakanti 
> Reviewed-by: Douglas Anderson 
> ---

Reviewed-by: Stephen Boyd

[PATCH] drm/amd/display: fix non-kernel-doc comment warnings

2022-04-22 Thread Randy Dunlap

Fix kernel-doc warnings for a comment that should not use
kernel-doc notation:

dmub_psr.c:235: warning: This comment starts with '/**', but isn't a kernel-doc 
comment. Refer Documentation/doc-guide/kernel-doc.rst
 * Set PSR power optimization flags.
dmub_psr.c:235: warning: missing initial short description on line:
 * Set PSR power optimization flags.

Fixes: e5dfcd272722 ("drm/amd/display: dc_link_set_psr_allow_active 
refactoring")
Signed-off-by: Randy Dunlap 
Reported-by: kernel test robot 
Cc: Robin Chen 
Cc: Alex Deucher 
Cc: Anthony Koo 
Cc: amd-...@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Cc: David Airlie 
Cc: Daniel Vetter 
Cc: Harry Wentland 
Cc: Leo Li 
Cc: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -231,7 +231,7 @@ static void dmub_psr_set_level(struct dm
dc_dmub_srv_wait_idle(dc->dmub_srv);
 }
 
-/**
+/*
  * Set PSR power optimization flags.
  */
 static void dmub_psr_set_power_opt(struct dmub_psr *dmub, unsigned int 
power_opt, uint8_t panel_inst)

Re: [PATCH v9 2/4] drm/msm/dp: Support only IRQ_HPD and REPLUG interrupts for eDP

Quoting Sankeerth Billakanti (2022-04-22 02:11:04)
> The panel-edp enables the eDP panel power during probe, get_modes
> and pre-enable. The eDP connect and disconnect interrupts for the eDP/DP
> controller are directly dependent on panel power. As eDP display can be
> assumed as always connected, the controller driver can skip the eDP
> connect and disconnect interrupts. Any disruption in the link status
> will be indicated via the IRQ_HPD interrupts.
>
> So, the eDP controller driver can just enable the IRQ_HPD and replug
> interrupts. The DP controller driver still needs to enable all the
> interrupts.
>
> Signed-off-by: Sankeerth Billakanti 

The sprinkling of if conditions and manual driving of the DP plug/unplug
state machine is pretty convoluted. To make it better the driver needs
an overhaul. Anyway, it looks mostly fine to me except for this replug
interrupt question below. Otherwise

Reviewed-by: Stephen Boyd 

>  int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index 055681a..dea4de9 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -1096,6 +1097,13 @@ static void dp_display_config_hpd(struct 
> dp_display_private *dp)
> dp_display_host_init(dp);
> dp_catalog_ctrl_hpd_config(dp->catalog);
>
> +   /* Enable plug and unplug interrupts only for external DisplayPort */
> +   if (!dp->dp_display.is_edp)
> +   dp_catalog_hpd_config_intr(dp->catalog,
> +   DP_DP_HPD_PLUG_INT_MASK |
> +   DP_DP_HPD_UNPLUG_INT_MASK,
> +   true);
> +

It seems like only the plug and unplug is enabled for DP here. Is replug
enabled for eDP when it shouldn't be?

> /* Enable interrupt first time
>  * we are leaving dp clocks on during disconnect
>  * and never disable interrupt

Re: [PATCH v9 1/4] drm/msm/dp: Add eDP support via aux_bus

Quoting Sankeerth Billakanti (2022-04-22 02:11:03)
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index d7a19d6..055681a 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c

Some nitpicks

Reviewed-by: Stephen Boyd 

> @@ -1508,7 +1509,8 @@ void msm_dp_irq_postinstall(struct msm_dp *dp_display)
>
> dp_hpd_event_setup(dp);
>
> -   dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100);
> +   if (!dp_display->is_edp)
> +   dp_add_event(dp, EV_HPD_INIT_SETUP, 0, 100);

Did it turn out that in fact DP isn't ready still to setup even after
delaying the irq?

>  }
>
>  void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor)
> @@ -1530,6 +1532,65 @@ void msm_dp_debugfs_init(struct msm_dp *dp_display, 
> struct drm_minor *minor)
> }
>  }
>
> +static int dp_display_get_next_bridge(struct msm_dp *dp)
> +{
> +   int rc;
> +   struct dp_display_private *dp_priv;
> +   struct device_node *aux_bus;
> +   struct device *dev;
> +
> +   dp_priv = container_of(dp, struct dp_display_private, dp_display);
> +   dev = _priv->pdev->dev;
> +   aux_bus = of_get_child_by_name(dev->of_node, "aux-bus");
> +
> +   if (aux_bus && dp->is_edp) {
> +   dp_display_host_init(dp_priv);
> +   dp_catalog_ctrl_hpd_config(dp_priv->catalog);
> +   dp_display_host_phy_init(dp_priv);
> +   enable_irq(dp_priv->irq);
> +
> +   /*
> +* The code below assumes that the panel will finish probing
> +* by the time devm_of_dp_aux_populate_ep_devices() returns.
> +* This isn't a great assumption since it will fail if the
> +* panel driver is probed asynchronously but is the best we
> +* can do without a bigger driver reorganization.
> +*/
> +   rc = devm_of_dp_aux_populate_ep_devices(dp_priv->aux);
> +   of_node_put(aux_bus);
> +   if (rc)
> +   goto error;
> +   } else if (dp->is_edp) {
> +   DRM_ERROR("eDP aux_bus not found\n");
> +   return -ENODEV;
> +   }
> +
> +   /*
> +* External bridges are mandatory for eDP interfaces: one has to
> +* provide at least an eDP panel (which gets wrapped into 
> panel-bridge).
> +*
> +* For DisplayPort interfaces external bridges are optional, so
> +* silently ignore an error if one is not present (-ENODEV).
> +*/
> +   rc = dp_parser_find_next_bridge(dp_priv->parser);
> +   if (!dp->is_edp && rc == -ENODEV)
> +   return 0;
> +   else if (rc)

Just an if because there's a return above.

> +   goto error;
> +
> +   dp->next_bridge = dp_priv->parser->next_bridge;

In which case it almost feels like it could be written

if (!dp->is_edp && rc == -ENODEV)
return 0;
if (!rc) {
dp->next_bridge = dp_priv->parser->next_bridge;
return 0;
}
error:
if (dp->is_edp) {

but I'm not worried either way, besides removing the else from the else-if.

> +
> +   return 0;
> +
> +error:
> +   if (dp->is_edp) {
> +   disable_irq(dp_priv->irq);
> +   dp_display_host_phy_exit(dp_priv);
> +   dp_display_host_deinit(dp_priv);
> +   }
> +   return rc;
> +}
> +
>  int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
> struct drm_encoder *encoder)
>  {
> diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h 
> b/drivers/gpu/drm/msm/dp/dp_parser.h
> index d371bae..950416c 100644
> --- a/drivers/gpu/drm/msm/dp/dp_parser.h
> +++ b/drivers/gpu/drm/msm/dp/dp_parser.h
> @@ -125,7 +125,7 @@ struct dp_parser {
> u32 max_dp_lanes;
> struct drm_bridge *next_bridge;
>
> -   int (*parse)(struct dp_parser *parser, int connector_type);
> +   int (*parse)(struct dp_parser *parser);
>  };
>
>  /**
> @@ -141,4 +141,15 @@ struct dp_parser {
>   */
>  struct dp_parser *dp_parser_get(struct platform_device *pdev);
>
> +/**
> + * dp_parser_find_next_bridge() - find an additional bridge to DP
> + *
> + * @parser: dp_parser data from client
> + * return: 0 if able to get the bridge else return an error code

return comes after the description below. Also should be capitalized.
You can check this by compiling with W=1 I believe, or run the
kernel doc format script on the file..

> + *
> + * This function is used to find any additional bridge attached to
> + * the DP controller. The eDP interface requires a panel bridge.

Return: 0 if able to get the bridge, otherwise negative errno for failure

> + */
> +int dp_parser_find_next_bridge(struct dp_parser *parser);
> +

Re: [PATCH] drm/msm/dp: move add fail safe mode to dp_connector_get_mode()





On 4/22/2022 5:07 PM, Dmitry Baryshkov wrote:

On 23/04/2022 02:45, Kuogee Hsieh wrote:

Current DP driver implementation has adding safe mode done at
dp_hpd_plug_handle() which is expected to be executed under event
thread context.

However there is possible circular locking happen (see blow stack trace)
after edp driver call dp_hpd_plug_handle() from dp_bridge_enable() which
is executed under drm_thread context.

To break this circular locking, this patch have safe mode added at
dp_connector_get_mode() which is executed under drm thread context.
Therefore no lock acquired required for >mode_config.mutex while
adding fail safe mode since it has been hold by drm thread already.

==
  WARNING: possible circular locking dependency detected
  5.15.35-lockdep #6 Tainted: G    W
  --
  frecon/429 is trying to acquire lock:
  ff808dc3c4e8 (>mode_config.mutex){+.+.}-{3:3}, at:
dp_panel_add_fail_safe_mode+0x4c/0xa0

  but task is already holding lock:
  ff808dc441e0 (>commit_lock[i]){+.+.}-{3:3}, at: 
lock_crtcs+0xb4/0x124


  which lock already depends on the new lock.

  the existing dependency chain (in reverse order) is:

  -> #3 (>commit_lock[i]){+.+.}-{3:3}:
 __mutex_lock_common+0x174/0x1a64
 mutex_lock_nested+0x98/0xac
 lock_crtcs+0xb4/0x124
 msm_atomic_commit_tail+0x330/0x748
 commit_tail+0x19c/0x278
 drm_atomic_helper_commit+0x1dc/0x1f0
 drm_atomic_commit+0xc0/0xd8
 drm_atomic_helper_set_config+0xb4/0x134
 drm_mode_setcrtc+0x688/0x1248
 drm_ioctl_kernel+0x1e4/0x338
 drm_ioctl+0x3a4/0x684
 __arm64_sys_ioctl+0x118/0x154
 invoke_syscall+0x78/0x224
 el0_svc_common+0x178/0x200
 do_el0_svc+0x94/0x13c
 el0_svc+0x5c/0xec
 el0t_64_sync_handler+0x78/0x108
 el0t_64_sync+0x1a4/0x1a8

  -> #2 (crtc_ww_class_mutex){+.+.}-{3:3}:
 __mutex_lock_common+0x174/0x1a64
 ww_mutex_lock+0xb8/0x278
 modeset_lock+0x304/0x4ac
 drm_modeset_lock+0x4c/0x7c
 drmm_mode_config_init+0x4a8/0xc50
 msm_drm_init+0x274/0xac0
 msm_drm_bind+0x20/0x2c
 try_to_bring_up_master+0x3dc/0x470
 __component_add+0x18c/0x3c0
 component_add+0x1c/0x28
 dp_display_probe+0x954/0xa98
 platform_probe+0x124/0x15c
 really_probe+0x1b0/0x5f8
 __driver_probe_device+0x174/0x20c
 driver_probe_device+0x70/0x134
 __device_attach_driver+0x130/0x1d0
 bus_for_each_drv+0xfc/0x14c
 __device_attach+0x1bc/0x2bc
 device_initial_probe+0x1c/0x28
 bus_probe_device+0x94/0x178
 deferred_probe_work_func+0x1a4/0x1f0
 process_one_work+0x5d4/0x9dc
 worker_thread+0x898/0xccc
 kthread+0x2d4/0x3d4
 ret_from_fork+0x10/0x20

  -> #1 (crtc_ww_class_acquire){+.+.}-{0:0}:
 ww_acquire_init+0x1c4/0x2c8
 drm_modeset_acquire_init+0x44/0xc8
 drm_helper_probe_single_connector_modes+0xb0/0x12dc
 drm_mode_getconnector+0x5dc/0xfe8
 drm_ioctl_kernel+0x1e4/0x338
 drm_ioctl+0x3a4/0x684
 __arm64_sys_ioctl+0x118/0x154
 invoke_syscall+0x78/0x224
 el0_svc_common+0x178/0x200
 do_el0_svc+0x94/0x13c
 el0_svc+0x5c/0xec
 el0t_64_sync_handler+0x78/0x108
 el0t_64_sync+0x1a4/0x1a8

  -> #0 (>mode_config.mutex){+.+.}-{3:3}:
 __lock_acquire+0x2650/0x672c
 lock_acquire+0x1b4/0x4ac
 __mutex_lock_common+0x174/0x1a64
 mutex_lock_nested+0x98/0xac
 dp_panel_add_fail_safe_mode+0x4c/0xa0
 dp_hpd_plug_handle+0x1f0/0x280
 dp_bridge_enable+0x94/0x2b8
 drm_atomic_bridge_chain_enable+0x11c/0x168
 drm_atomic_helper_commit_modeset_enables+0x500/0x740
 msm_atomic_commit_tail+0x3e4/0x748
 commit_tail+0x19c/0x278
 drm_atomic_helper_commit+0x1dc/0x1f0
 drm_atomic_commit+0xc0/0xd8
 drm_atomic_helper_set_config+0xb4/0x134
 drm_mode_setcrtc+0x688/0x1248
 drm_ioctl_kernel+0x1e4/0x338
 drm_ioctl+0x3a4/0x684
 __arm64_sys_ioctl+0x118/0x154
 invoke_syscall+0x78/0x224
 el0_svc_common+0x178/0x200
 do_el0_svc+0x94/0x13c
 el0_svc+0x5c/0xec
 el0t_64_sync_handler+0x78/0x108
 el0t_64_sync+0x1a4/0x1a8

Signed-off-by: Kuogee Hsieh 
---
  drivers/gpu/drm/msm/dp/dp_display.c |  6 --
  drivers/gpu/drm/msm/dp/dp_panel.c   | 23 +--
  2 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c

index 92cd50f..01453db 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -555,12 +555,6 @@ static int dp_hpd_plug_handle(struct 
dp_display_private *dp, u32 data)

Re: [PATCH] drm/msm/dp: move add fail safe mode to dp_connector_get_mode()


On 23/04/2022 02:45, Kuogee Hsieh wrote:

Current DP driver implementation has adding safe mode done at
dp_hpd_plug_handle() which is expected to be executed under event
thread context.

However there is possible circular locking happen (see blow stack trace)
after edp driver call dp_hpd_plug_handle() from dp_bridge_enable() which
is executed under drm_thread context.

To break this circular locking, this patch have safe mode added at
dp_connector_get_mode() which is executed under drm thread context.
Therefore no lock acquired required for >mode_config.mutex while
adding fail safe mode since it has been hold by drm thread already.

==
  WARNING: possible circular locking dependency detected
  5.15.35-lockdep #6 Tainted: GW
  --
  frecon/429 is trying to acquire lock:
  ff808dc3c4e8 (>mode_config.mutex){+.+.}-{3:3}, at:
dp_panel_add_fail_safe_mode+0x4c/0xa0

  but task is already holding lock:
  ff808dc441e0 (>commit_lock[i]){+.+.}-{3:3}, at: lock_crtcs+0xb4/0x124

  which lock already depends on the new lock.

  the existing dependency chain (in reverse order) is:

  -> #3 (>commit_lock[i]){+.+.}-{3:3}:
 __mutex_lock_common+0x174/0x1a64
 mutex_lock_nested+0x98/0xac
 lock_crtcs+0xb4/0x124
 msm_atomic_commit_tail+0x330/0x748
 commit_tail+0x19c/0x278
 drm_atomic_helper_commit+0x1dc/0x1f0
 drm_atomic_commit+0xc0/0xd8
 drm_atomic_helper_set_config+0xb4/0x134
 drm_mode_setcrtc+0x688/0x1248
 drm_ioctl_kernel+0x1e4/0x338
 drm_ioctl+0x3a4/0x684
 __arm64_sys_ioctl+0x118/0x154
 invoke_syscall+0x78/0x224
 el0_svc_common+0x178/0x200
 do_el0_svc+0x94/0x13c
 el0_svc+0x5c/0xec
 el0t_64_sync_handler+0x78/0x108
 el0t_64_sync+0x1a4/0x1a8

  -> #2 (crtc_ww_class_mutex){+.+.}-{3:3}:
 __mutex_lock_common+0x174/0x1a64
 ww_mutex_lock+0xb8/0x278
 modeset_lock+0x304/0x4ac
 drm_modeset_lock+0x4c/0x7c
 drmm_mode_config_init+0x4a8/0xc50
 msm_drm_init+0x274/0xac0
 msm_drm_bind+0x20/0x2c
 try_to_bring_up_master+0x3dc/0x470
 __component_add+0x18c/0x3c0
 component_add+0x1c/0x28
 dp_display_probe+0x954/0xa98
 platform_probe+0x124/0x15c
 really_probe+0x1b0/0x5f8
 __driver_probe_device+0x174/0x20c
 driver_probe_device+0x70/0x134
 __device_attach_driver+0x130/0x1d0
 bus_for_each_drv+0xfc/0x14c
 __device_attach+0x1bc/0x2bc
 device_initial_probe+0x1c/0x28
 bus_probe_device+0x94/0x178
 deferred_probe_work_func+0x1a4/0x1f0
 process_one_work+0x5d4/0x9dc
 worker_thread+0x898/0xccc
 kthread+0x2d4/0x3d4
 ret_from_fork+0x10/0x20

  -> #1 (crtc_ww_class_acquire){+.+.}-{0:0}:
 ww_acquire_init+0x1c4/0x2c8
 drm_modeset_acquire_init+0x44/0xc8
 drm_helper_probe_single_connector_modes+0xb0/0x12dc
 drm_mode_getconnector+0x5dc/0xfe8
 drm_ioctl_kernel+0x1e4/0x338
 drm_ioctl+0x3a4/0x684
 __arm64_sys_ioctl+0x118/0x154
 invoke_syscall+0x78/0x224
 el0_svc_common+0x178/0x200
 do_el0_svc+0x94/0x13c
 el0_svc+0x5c/0xec
 el0t_64_sync_handler+0x78/0x108
 el0t_64_sync+0x1a4/0x1a8

  -> #0 (>mode_config.mutex){+.+.}-{3:3}:
 __lock_acquire+0x2650/0x672c
 lock_acquire+0x1b4/0x4ac
 __mutex_lock_common+0x174/0x1a64
 mutex_lock_nested+0x98/0xac
 dp_panel_add_fail_safe_mode+0x4c/0xa0
 dp_hpd_plug_handle+0x1f0/0x280
 dp_bridge_enable+0x94/0x2b8
 drm_atomic_bridge_chain_enable+0x11c/0x168
 drm_atomic_helper_commit_modeset_enables+0x500/0x740
 msm_atomic_commit_tail+0x3e4/0x748
 commit_tail+0x19c/0x278
 drm_atomic_helper_commit+0x1dc/0x1f0
 drm_atomic_commit+0xc0/0xd8
 drm_atomic_helper_set_config+0xb4/0x134
 drm_mode_setcrtc+0x688/0x1248
 drm_ioctl_kernel+0x1e4/0x338
 drm_ioctl+0x3a4/0x684
 __arm64_sys_ioctl+0x118/0x154
 invoke_syscall+0x78/0x224
 el0_svc_common+0x178/0x200
 do_el0_svc+0x94/0x13c
 el0_svc+0x5c/0xec
 el0t_64_sync_handler+0x78/0x108
 el0t_64_sync+0x1a4/0x1a8

Signed-off-by: Kuogee Hsieh 
---
  drivers/gpu/drm/msm/dp/dp_display.c |  6 --
  drivers/gpu/drm/msm/dp/dp_panel.c   | 23 +--
  2 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index 92cd50f..01453db 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -555,12 +555,6 @@ static int dp_hpd_plug_handle(struct dp_display_private 
*dp, u32 data)
  
  	mutex_unlock(>event_mutex);
  
-	/*

-* add fail safe

Re: [PATCH] drm/msm/dp: move add fail safe mode to dp_connector_get_mode()

Quoting Kuogee Hsieh (2022-04-22 16:45:23)
> Current DP driver implementation has adding safe mode done at
> dp_hpd_plug_handle() which is expected to be executed under event
> thread context.
>
> However there is possible circular locking happen (see blow stack trace)
> after edp driver call dp_hpd_plug_handle() from dp_bridge_enable() which
> is executed under drm_thread context.
>
> To break this circular locking, this patch have safe mode added at
> dp_connector_get_mode() which is executed under drm thread context.
> Therefore no lock acquired required for >mode_config.mutex while
> adding fail safe mode since it has been hold by drm thread already.

Reported-by: Douglas Anderson 
Fixes: 8b2c181e3dcf ("drm/msm/dp: add fail safe mode outside of
event_mutex context")
Reviewed-by: Stephen Boyd

[PATCH] drm/msm/dp: move add fail safe mode to dp_connector_get_mode()

2022-04-22 Thread Kuogee Hsieh

Current DP driver implementation has adding safe mode done at
dp_hpd_plug_handle() which is expected to be executed under event
thread context.

However there is possible circular locking happen (see blow stack trace)
after edp driver call dp_hpd_plug_handle() from dp_bridge_enable() which
is executed under drm_thread context.

To break this circular locking, this patch have safe mode added at
dp_connector_get_mode() which is executed under drm thread context.
Therefore no lock acquired required for >mode_config.mutex while
adding fail safe mode since it has been hold by drm thread already.

==
 WARNING: possible circular locking dependency detected
 5.15.35-lockdep #6 Tainted: GW
 --
 frecon/429 is trying to acquire lock:
 ff808dc3c4e8 (>mode_config.mutex){+.+.}-{3:3}, at:
dp_panel_add_fail_safe_mode+0x4c/0xa0

 but task is already holding lock:
 ff808dc441e0 (>commit_lock[i]){+.+.}-{3:3}, at: lock_crtcs+0xb4/0x124

 which lock already depends on the new lock.

 the existing dependency chain (in reverse order) is:

 -> #3 (>commit_lock[i]){+.+.}-{3:3}:
__mutex_lock_common+0x174/0x1a64
mutex_lock_nested+0x98/0xac
lock_crtcs+0xb4/0x124
msm_atomic_commit_tail+0x330/0x748
commit_tail+0x19c/0x278
drm_atomic_helper_commit+0x1dc/0x1f0
drm_atomic_commit+0xc0/0xd8
drm_atomic_helper_set_config+0xb4/0x134
drm_mode_setcrtc+0x688/0x1248
drm_ioctl_kernel+0x1e4/0x338
drm_ioctl+0x3a4/0x684
__arm64_sys_ioctl+0x118/0x154
invoke_syscall+0x78/0x224
el0_svc_common+0x178/0x200
do_el0_svc+0x94/0x13c
el0_svc+0x5c/0xec
el0t_64_sync_handler+0x78/0x108
el0t_64_sync+0x1a4/0x1a8

 -> #2 (crtc_ww_class_mutex){+.+.}-{3:3}:
__mutex_lock_common+0x174/0x1a64
ww_mutex_lock+0xb8/0x278
modeset_lock+0x304/0x4ac
drm_modeset_lock+0x4c/0x7c
drmm_mode_config_init+0x4a8/0xc50
msm_drm_init+0x274/0xac0
msm_drm_bind+0x20/0x2c
try_to_bring_up_master+0x3dc/0x470
__component_add+0x18c/0x3c0
component_add+0x1c/0x28
dp_display_probe+0x954/0xa98
platform_probe+0x124/0x15c
really_probe+0x1b0/0x5f8
__driver_probe_device+0x174/0x20c
driver_probe_device+0x70/0x134
__device_attach_driver+0x130/0x1d0
bus_for_each_drv+0xfc/0x14c
__device_attach+0x1bc/0x2bc
device_initial_probe+0x1c/0x28
bus_probe_device+0x94/0x178
deferred_probe_work_func+0x1a4/0x1f0
process_one_work+0x5d4/0x9dc
worker_thread+0x898/0xccc
kthread+0x2d4/0x3d4
ret_from_fork+0x10/0x20

 -> #1 (crtc_ww_class_acquire){+.+.}-{0:0}:
ww_acquire_init+0x1c4/0x2c8
drm_modeset_acquire_init+0x44/0xc8
drm_helper_probe_single_connector_modes+0xb0/0x12dc
drm_mode_getconnector+0x5dc/0xfe8
drm_ioctl_kernel+0x1e4/0x338
drm_ioctl+0x3a4/0x684
__arm64_sys_ioctl+0x118/0x154
invoke_syscall+0x78/0x224
el0_svc_common+0x178/0x200
do_el0_svc+0x94/0x13c
el0_svc+0x5c/0xec
el0t_64_sync_handler+0x78/0x108
el0t_64_sync+0x1a4/0x1a8

 -> #0 (>mode_config.mutex){+.+.}-{3:3}:
__lock_acquire+0x2650/0x672c
lock_acquire+0x1b4/0x4ac
__mutex_lock_common+0x174/0x1a64
mutex_lock_nested+0x98/0xac
dp_panel_add_fail_safe_mode+0x4c/0xa0
dp_hpd_plug_handle+0x1f0/0x280
dp_bridge_enable+0x94/0x2b8
drm_atomic_bridge_chain_enable+0x11c/0x168
drm_atomic_helper_commit_modeset_enables+0x500/0x740
msm_atomic_commit_tail+0x3e4/0x748
commit_tail+0x19c/0x278
drm_atomic_helper_commit+0x1dc/0x1f0
drm_atomic_commit+0xc0/0xd8
drm_atomic_helper_set_config+0xb4/0x134
drm_mode_setcrtc+0x688/0x1248
drm_ioctl_kernel+0x1e4/0x338
drm_ioctl+0x3a4/0x684
__arm64_sys_ioctl+0x118/0x154
invoke_syscall+0x78/0x224
el0_svc_common+0x178/0x200
do_el0_svc+0x94/0x13c
el0_svc+0x5c/0xec
el0t_64_sync_handler+0x78/0x108
el0t_64_sync+0x1a4/0x1a8

Signed-off-by: Kuogee Hsieh 
---
 drivers/gpu/drm/msm/dp/dp_display.c |  6 --
 drivers/gpu/drm/msm/dp/dp_panel.c   | 23 +--
 2 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index 92cd50f..01453db 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -555,12 +555,6 @@ static int dp_hpd_plug_handle(struct dp_display_private 
*dp, u32 data)
 
mutex_unlock(>event_mutex);
 
-   /*
-* add fail safe mode outside event_mutex scope
-* to avoid potiential circular lock with drm thread
-*/
-

Re: [PATCH v2 00/48] ARM: PXA multiplatform support

On Sat, Apr 23, 2022 at 12:04:31AM +0200, Arnd Bergmann wrote:
> On Fri, Apr 22, 2022 at 10:55 PM Guenter Roeck  wrote:
> > On 4/22/22 12:16, Arnd Bergmann wrote:
> > > On Fri, Apr 22, 2022 at 7:05 PM Guenter Roeck  wrote:
> > >
> > > Which machine did you hit this on? Is this on hardware or in qemu?
> > >
> > qemu, as always. borzoi, spitz, terrier, tosa, z2, and sx1 fail.
> > Also, I just noticed that the failure is not always the same.
> > z2 fails to boot from initrd, and sx1 fails to boot completely.
> 
> That's a lot of machines failing, I hope at least we got the same bugs more
> than once here.
> 
> For the I/O space, I found now that PXA was not using the standard
> virtual I/O address yet, but instead used a NULL-based offset.
> 
> I'm not entirely happy with this patch, but this is an outline of what
> I think we need to fix that: https://pastebin.com/3nVgQsEw
> This one is probably incomplete, at least it breaks sa1100 for now,
> and it adds a bogus CONFIG_PCI dependency. I'm also not sure
> in what way the last patch in the series triggers it, rather than the
> one that removed mach/io.h.
> 
> I had sx1 booting in qemu at least, with the omap1 multiplatform series only.
> If you have a custom config for this one, make sure you get the right
> DEBUG_LL address.
> 
> > I'll do another round of bisects.
> 

Here is the bisect for the sx1 boot failure.

Guenter

---
# bad: [e7d6987e09a328d4a949701db40ef63fbb970670] Add linux-next specific files 
for 20220422
# good: [b2d229d4ddb17db541098b83524d901257e93845] Linux 5.18-rc3
git bisect start 'HEAD' 'v5.18-rc3'
# bad: [479506a21bd2df998017a00f4fe0ea893039d9d0] Merge branch 'drm-next' of 
git://git.freedesktop.org/git/drm/drm.git
git bisect bad 479506a21bd2df998017a00f4fe0ea893039d9d0
# bad: [84fdc506ff63f3f8eb7feaac87821c39bf1dbdfd] Merge branch 'for-next' of 
git://git.kernel.org/pub/scm/linux/kernel/git/printk/linux.git
git bisect bad 84fdc506ff63f3f8eb7feaac87821c39bf1dbdfd
# bad: [0318e72d28be01b99056a7e66572423682eae2bb] Merge branch 'for-next' of 
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
git bisect bad 0318e72d28be01b99056a7e66572423682eae2bb
# good: [813d98e2e26d3f418d925263a82d72d1454b326e] Merge branch 'zstd-linus' of 
https://github.com/terrelln/linux.git
git bisect good 813d98e2e26d3f418d925263a82d72d1454b326e
# bad: [5e87f91cfe6e938eccb88a992687e2ac52eec2a7] Merge branch 'for-next' of 
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
git bisect bad 5e87f91cfe6e938eccb88a992687e2ac52eec2a7
# bad: [ac4b03d5ad6b887558eb94943f0f2834661dee45] Merge branch 
'pxa-multiplatform-5.18' of 
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc into 
arm/multiplatform-late
git bisect bad ac4b03d5ad6b887558eb94943f0f2834661dee45
# good: [6eab9bfd712f63c0977f2d38a45f321816030707] Merge branch 
'omap1/multiplatform-prep' of 
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc into arm/multiplatform
git bisect good 6eab9bfd712f63c0977f2d38a45f321816030707
# good: [ac571609a9fab9b94bbd8e634ba20e2ab672e32d] input: touchscreen: 
mainstone: sync with zylonite driver
git bisect good ac571609a9fab9b94bbd8e634ba20e2ab672e32d
# good: [77b9aeb6e3cd4de6b320d3a9be5d692594159f9e] ARM: pxa: remove unused 
mach/bitfield.h
git bisect good 77b9aeb6e3cd4de6b320d3a9be5d692594159f9e
# good: [7643a9ca9f8e08f71e15f89dd74863635e981e03] ARM: pxa: convert to 
multiplatform
git bisect good 7643a9ca9f8e08f71e15f89dd74863635e981e03
# good: [bdfb692acfa98c3e8135ab44bc8366636443590a] [MERGED] ASoC: ti: osk5912: 
Make it CCF clk API compatible
git bisect good bdfb692acfa98c3e8135ab44bc8366636443590a
# bad: [b59e8a5fd321fe44bdabd38908b4f899f933cf0f] [TO BE REBASED] ARM: omap1: 
enable multiplatform
git bisect bad b59e8a5fd321fe44bdabd38908b4f899f933cf0f
# good: [4c4467ac74299b14b8cf74406722af8090aa7766] [TO BE REBASED] ARM: OMAP1: 
clock: Convert to CCF
git bisect good 4c4467ac74299b14b8cf74406722af8090aa7766
# first bad commit: [b59e8a5fd321fe44bdabd38908b4f899f933cf0f] [TO BE REBASED] 
ARM: omap1: enable multiplatform

Re: [PATCH v2 00/48] ARM: PXA multiplatform support

On Sat, Apr 23, 2022 at 12:04:31AM +0200, Arnd Bergmann wrote:
> On Fri, Apr 22, 2022 at 10:55 PM Guenter Roeck  wrote:
> > On 4/22/22 12:16, Arnd Bergmann wrote:
> > > On Fri, Apr 22, 2022 at 7:05 PM Guenter Roeck  wrote:
> > >
> > > Which machine did you hit this on? Is this on hardware or in qemu?
> > >
> > qemu, as always. borzoi, spitz, terrier, tosa, z2, and sx1 fail.
> > Also, I just noticed that the failure is not always the same.
> > z2 fails to boot from initrd, and sx1 fails to boot completely.
> 
> That's a lot of machines failing, I hope at least we got the same bugs more
> than once here.
> 
> For the I/O space, I found now that PXA was not using the standard
> virtual I/O address yet, but instead used a NULL-based offset.
> 
> I'm not entirely happy with this patch, but this is an outline of what
> I think we need to fix that: https://pastebin.com/3nVgQsEw
> This one is probably incomplete, at least it breaks sa1100 for now,
> and it adds a bogus CONFIG_PCI dependency. I'm also not sure
> in what way the last patch in the series triggers it, rather than the
> one that removed mach/io.h.
> 
> I had sx1 booting in qemu at least, with the omap1 multiplatform series only.
> If you have a custom config for this one, make sure you get the right
> DEBUG_LL address.
> 
> > I'll do another round of bisects.
> 

So ... z2 bisect points to the same patch, but the error is different.
As mentioned, it does not recognize the initrd. Oddly enough, booting
from initrd works for the other platforms.

The sx1 boot failure seems to be unrelated to your patch series. It boots
fine if built from the tip of your branch, but fails to boot in -next.
That will require a bisect from -next.

Guenter

Re: [PATCH v2 04/17] drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog


Hi Liviu

Thank you for the feedback.

I have fixed the order of copyright years in all the changes in the next 
version.


Thanks

Abhinav

On 4/21/2022 5:16 AM, Liviu Dudau wrote:

On Tue, Apr 19, 2022 at 06:45:56PM -0700, Abhinav Kumar wrote:

Add writeback blocks to the sm8250 DPU hardware catalog. Other
chipsets support writeback too but add it to sm8250 to prototype
the feature so that it can be easily extended to other chipsets.

changes in v2:
- none

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 74 +-
  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 66 ++-
  2 files changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b0a0ef7..bcb5273 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1,5 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.


Hi Abhinav,

Nit: Order should be historical (i.e. QIC copyright comes last). Comment 
applies to
all other copyright years additions.

Best regards,
Liviu


   */
  
  #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__

@@ -120,6 +121,16 @@
  BIT(MDP_AD4_0_INTR) | \
  BIT(MDP_AD4_1_INTR))
  
+#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \

+BIT(DPU_WB_UBWC) | \
+BIT(DPU_WB_YUV_CONFIG) | \
+BIT(DPU_WB_PIPE_ALPHA) | \
+BIT(DPU_WB_XY_ROI_OFFSET) | \
+BIT(DPU_WB_QOS) | \
+BIT(DPU_WB_QOS_8LVL) | \
+BIT(DPU_WB_CDP) | \
+BIT(DPU_WB_INPUT_CTRL))
+
  #define DEFAULT_PIXEL_RAM_SIZE(50 * 1024)
  #define DEFAULT_DPU_LINE_WIDTH2048
  #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
@@ -211,6 +222,40 @@ static const u32 rotation_v2_formats[] = {
/* TODO add formats after validation */
  };
  
+static const uint32_t wb2_formats[] = {

+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_BGR565,
+   DRM_FORMAT_RGB888,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_RGBA,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_RGBX,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ARGB1555,
+   DRM_FORMAT_RGBA5551,
+   DRM_FORMAT_XRGB1555,
+   DRM_FORMAT_RGBX5551,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_RGBA,
+   DRM_FORMAT_RGBX,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_BGR565,
+   DRM_FORMAT_BGR888,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_BGRA,
+   DRM_FORMAT_BGRX,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ABGR1555,
+   DRM_FORMAT_BGRA5551,
+   DRM_FORMAT_XBGR1555,
+   DRM_FORMAT_BGRX5551,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_BGRA,
+   DRM_FORMAT_BGRX,
+   DRM_FORMAT_XBGR,
+};
+
  /*
   * DPU sub blocks config
   */
@@ -448,6 +493,8 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
.reg_off = 0x2C4, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
.reg_off = 0x2BC, .bit_off = 20},
+   .clk_ctrls[DPU_CLK_CTRL_WB2] = {
+   .reg_off = 0x3B8, .bit_off = 24},
},
  };
  
@@ -1235,6 +1282,29 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {

  };
  
  /*

+ * Writeback blocks config
+ */
+#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
+   __xin_id, vbif_id, _reg, _wb_done_bit) \
+   { \
+   .name = _name, .id = _id, \
+   .base = _base, .len = 0x2c8, \
+   .features = _features, \
+   .format_list = wb2_formats, \
+   .num_formats = ARRAY_SIZE(wb2_formats), \
+   .clk_ctrl = _clk_ctrl, \
+   .xin_id = __xin_id, \
+   .vbif_idx = vbif_id, \
+   .maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \
+   .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
+   }
+
+static const struct dpu_wb_cfg sm8250_wb[] = {
+   WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
+   VBIF_RT, MDP_SSPP_TOP0_INTR, 4),
+};
+
+/*
   * VBIF sub blocks config
   */
  /* VBIF QOS remap */
@@ -1832,6 +1902,8 @@ static void

[PATCH v4 19/20] drm/msm/dpu: add wb_idx to existing DRM prints in dpu_encoder

Add wb_idx to existing DRM prints in dpu_encoder and also
print the intf_mode so that its clear that for any INTF_CMD/VID
there will be a valid intf_idx and any INTF_WB_* there will be a
valid wb_idx.

Update the debugfs to add the same information. Here is a sample
output with this change:

root:/sys/kernel/debug/dri/0/encoder31# cat status
intf:1  wb:-1  vsync: 31  underrun: 0mode: INTF_MODE_VIDEO
root:/sys/kernel/debug/dri/0/encoder33# cat status
intf:-1  wb:2  vsync:  7  underrun: 0mode: INTF_MODE_WB_LINE

Also remove DPU_DEBUG_PHYS macros as its unused because the
respective dpu_encoder_phys_* files have their own macros.

changes in v2:
- use switch case instead of if/else-if for get_intf_type

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 52 +
 1 file changed, 24 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 90ef807..6d093cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -38,18 +38,6 @@
 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
 
-#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
-   (p) ? (p)->parent->base.id : -1, \
-   (p) ? (p)->intf_idx - INTF_0 : -1, \
-   (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
-   ##__VA_ARGS__)
-
-#define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
-   (p) ? (p)->parent->base.id : -1, \
-   (p) ? (p)->intf_idx - INTF_0 : -1, \
-   (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
-   ##__VA_ARGS__)
-
 /*
  * Two to anticipate panels that can do cmd/vid dynamic switching
  * plan is to create all possible physical encoder types, and switch between
@@ -263,12 +251,30 @@ static void _dpu_encoder_setup_dither(struct 
dpu_hw_pingpong *hw_pp, unsigned bp
hw_pp->ops.setup_dither(hw_pp, _cfg);
 }
 
+static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
+{
+   switch (intf_mode) {
+   case INTF_MODE_VIDEO:
+   return "INTF_MODE_VIDEO";
+   case INTF_MODE_CMD:
+   return "INTF_MODE_CMD";
+   case INTF_MODE_WB_BLOCK:
+   return "INTF_MODE_WB_BLOCK";
+   case INTF_MODE_WB_LINE:
+   return "INTF_MODE_WB_LINE";
+   default:
+   return "INTF_MODE_UNKNOWN";
+   }
+}
+
 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
 {
-   DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
- DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
- phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
+   DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, 
intr=%d\n",
+   DRMID(phys_enc->parent),
+   dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
+   phys_enc->intf_idx - INTF_0, phys_enc->wb_idx - WB_0,
+   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 
if (phys_enc->parent_ops->handle_frame_done)
phys_enc->parent_ops->handle_frame_done(
@@ -2049,22 +2055,12 @@ static int _dpu_encoder_status_show(struct seq_file *s, 
void *data)
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 
-   seq_printf(s, "intf:%dvsync:%8d underrun:%8d",
-   phys->intf_idx - INTF_0,
+   seq_printf(s, "intf:%d  wb:%d  vsync:%8d underrun:%8d",
+   phys->intf_idx - INTF_0, phys->wb_idx - WB_0,
atomic_read(>vsync_cnt),
atomic_read(>underrun_cnt));
 
-   switch (phys->intf_mode) {
-   case INTF_MODE_VIDEO:
-   seq_puts(s, "mode: video\n");
-   break;
-   case INTF_MODE_CMD:
-   seq_puts(s, "mode: command\n");
-   break;
-   default:
-   seq_puts(s, "mode: ???\n");
-   break;
-   }
+   seq_printf(s, "mode: %s\n", 
dpu_encoder_helper_get_intf_type(phys->intf_mode));
}
mutex_unlock(_enc->enc_lock);
 
-- 
2.7.4

[PATCH v4 18/20] drm/msm/dpu: add writeback blocks to the display snapshot

Add writeback block information while capturing the display
snapshot.

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9a406e1..b18bff8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -945,6 +945,11 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state 
*disp_state, struct msm_k
msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i);
 
+   /* dump WB sub-blocks HW regs info */
+   for (i = 0; i < cat->wb_count; i++)
+   msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
+   dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
+
msm_disp_snapshot_add_block(disp_state, top->hw.length,
dpu_kms->mmio + top->hw.blk_off, "top");
 
-- 
2.7.4

[PATCH v4 17/20] drm/msm/dpu: gracefully handle null fb commits for writeback

kms_writeback test cases also verify with a null fb for the
writeback connector job. In addition there are also other
commit paths which can result in kickoffs without a valid
framebuffer like while closing the fb which results in the
callback to drm_atomic_helper_dirtyfb() which internally
triggers a commit.

Add protection in the dpu driver to ensure that commits for
writeback encoders without a valid fb are gracefully skipped.

changes in v2:
- rename dpu_encoder_has_valid_fb to dpu_encoder_is_valid_for_commit

changes in v3:
- none

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|  9 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 21 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h |  6 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h|  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 12 
 5 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7763558..d65e124 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -869,6 +869,13 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
 
DPU_ATRACE_BEGIN("crtc_commit");
 
+   drm_for_each_encoder_mask(encoder, crtc->dev,
+   crtc->state->encoder_mask) {
+   if (!dpu_encoder_is_valid_for_commit(encoder)) {
+   DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n");
+   goto end;
+   }
+   }
/*
 * Encoder will flush/start now, unless it has a tx pending. If so, it
 * may delay and flush at an irq event (e.g. ppdone)
@@ -891,6 +898,8 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
dpu_encoder_kickoff(encoder);
 
reinit_completion(_crtc->frame_done_comp);
+
+end:
DPU_ATRACE_END("crtc_commit");
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 2d79002..90ef807 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1862,6 +1862,27 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder 
*drm_enc)
dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
 }
 
+bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc)
+{
+   struct dpu_encoder_virt *dpu_enc;
+   unsigned int i;
+   struct dpu_encoder_phys *phys;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+   if (drm_enc->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   phys = dpu_enc->phys_encs[i];
+   if (phys->ops.is_valid_for_commit && 
!phys->ops.is_valid_for_commit(phys)) {
+   DPU_DEBUG("invalid FB not kicking off\n");
+   return false;
+   }
+   }
+   }
+
+   return true;
+}
+
 void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
 {
struct dpu_encoder_virt *dpu_enc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 6ceec1d..781d41c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -196,4 +196,10 @@ void dpu_encoder_prepare_wb_job(struct drm_encoder 
*drm_enc,
 void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
struct drm_writeback_job *job);
 
+/**
+ * dpu_encoder_is_valid_for_commit - check if encode has valid parameters for 
commit.
+ * @drm_enc:Pointer to drm encoder structure
+ */
+bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc);
+
 #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index bed4523..f2af07d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -142,6 +142,7 @@ struct dpu_encoder_phys_ops {
struct drm_writeback_job *job);
void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
struct drm_writeback_job *job);
+   bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 4ab2699..cb5c7da 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -667,6 +667,16 @@ static void dpu_encoder_phys_wb_cleanup_wb_job(struct 
dpu_encoder_phys *phys_enc
wb_enc->wb_conn = NULL;
 }
 
+static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys 
*phys_enc)
+{
+   struct

[PATCH v4 20/20] drm/msm/dpu: add wb_idx to DRM traces in dpu_encoder

Change the DRM traces to include both the intf_mode
and wb_idx similar to the DRM prints in the previous change.

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h   | 26 ++
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6d093cf..3bd1790 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1354,8 +1354,9 @@ static void dpu_encoder_frame_done_callback(
 * suppress frame_done without waiter,
 * likely autorefresh
 */
-   trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
-   event, ready_phys->intf_idx);
+   trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 
event,
+   
dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
+   ready_phys->intf_idx, 
ready_phys->wb_idx);
return;
}
 
@@ -1433,9 +1434,11 @@ static void _dpu_encoder_trigger_flush(struct 
drm_encoder *drm_enc,
if (ctl->ops.get_pending_flush)
ret = ctl->ops.get_pending_flush(ctl);
 
-   trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
-   pending_kickoff_cnt, ctl->idx,
-   extra_flush_bits, ret);
+   trace_dpu_enc_trigger_flush(DRMID(drm_enc),
+   dpu_encoder_helper_get_intf_type(phys->intf_mode),
+   phys->intf_idx, phys->wb_idx,
+   pending_kickoff_cnt, ctl->idx,
+   extra_flush_bits, ret);
 }
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 58b411f..1106d44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -380,20 +380,26 @@ TRACE_EVENT(dpu_enc_rc,
 );
 
 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
-   TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx),
-   TP_ARGS(drm_id, event, intf_idx),
+   TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf 
intf_idx,
+   enum dpu_wb wb_idx),
+   TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx),
TP_STRUCT__entry(
__field(uint32_t,   drm_id  )
__field(u32,event   )
+   __string(   intf_mode_str,  intf_mode   )
__field(enum dpu_intf,  intf_idx)
+   __field(enum dpu_wb,  wb_idx)
),
TP_fast_assign(
__entry->drm_id = drm_id;
__entry->event = event;
+   __assign_str(intf_mode_str, intf_mode);
__entry->intf_idx = intf_idx;
+   __entry->wb_idx = wb_idx;
),
-   TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event,
- __entry->intf_idx)
+   TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", 
__entry->drm_id,
+   __entry->event, __get_str(intf_mode_str),
+   __entry->intf_idx, __entry->wb_idx)
 );
 
 TRACE_EVENT(dpu_enc_frame_done_cb,
@@ -415,14 +421,16 @@ TRACE_EVENT(dpu_enc_frame_done_cb,
 );
 
 TRACE_EVENT(dpu_enc_trigger_flush,
-   TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
+   TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum 
dpu_wb wb_idx,
 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
 u32 pending_flush_ret),
-   TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx,
+   TP_ARGS(drm_id, intf_mode, intf_idx, pending_kickoff_cnt, ctl_idx,
extra_flush_bits, pending_flush_ret),
TP_STRUCT__entry(
__field(uint32_t,   drm_id  )
+   __string(   intf_mode_str,  intf_mode   )
__field(enum dpu_intf,  intf_idx)
+   __field(enum dpu_wb,  wb_idx)
__field(int,pending_kickoff_cnt )
__field(int,ctl_idx )
__field(u32,extra_flush_bits)
@@ -430,15 +438,17 @@ TRACE_EVENT(dpu_enc_trigger_flush,
),
TP_fast_assign(
__entry->drm_id = drm_id;
+   __assign_str(intf_mode_str, intf_mode);
__entry->intf_idx = intf_idx;
+   __entry->wb_idx = wb_idx;
__entry->pending_kickoff_cnt =

[PATCH v4 14/20] drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback

Introduce the dpu_encoder_phys_* for the writeback interface
to handle writeback specific hardware programming.

changes in v4:
- squash the encoder_phys_wb bits from [1]
- since its a trivial change of a previously acked change
  preserving the ack

[1] https://patchwork.freedesktop.org/patch/483099/?series=102964=2

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/Makefile   |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  30 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 751 +
 3 files changed, 782 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index ca779c1..0387f22 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -60,6 +60,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
+   disp/dpu1/dpu_encoder_phys_wb.o \
disp/dpu1/dpu_formats.o \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_ctl.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index a42ed4b..bed4523 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -150,6 +150,7 @@ struct dpu_encoder_phys_ops {
  * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
  * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
  * @INTR_IDX_RDPTR:Readpointer done unterrupt for cmd mode panel
+ * @INTR_IDX_WB_DONE:  Writeback fone interrupt for virtual connector
  */
 enum dpu_intr_idx {
INTR_IDX_VSYNC,
@@ -157,6 +158,7 @@ enum dpu_intr_idx {
INTR_IDX_UNDERRUN,
INTR_IDX_CTL_START,
INTR_IDX_RDPTR,
+   INTR_IDX_WB_DONE,
INTR_IDX_MAX,
 };
 
@@ -226,6 +228,27 @@ static inline int dpu_encoder_phys_inc_pending(struct 
dpu_encoder_phys *phys)
 }
 
 /**
+ * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
+ * mode specific operations
+ * @base:  Baseclass physical encoder structure
+ * @wbirq_refcount: Reference count of writeback interrupt
+ * @wb_done_timeout_cnt: number of wb done irq timeout errors
+ * @wb_cfg:  writeback block config to store fb related details
+ * @wb_conn: backpointer to writeback connector
+ * @wb_job: backpointer to current writeback job
+ * @dest:   dpu buffer layout for current writeback output buffer
+ */
+struct dpu_encoder_phys_wb {
+   struct dpu_encoder_phys base;
+   atomic_t wbirq_refcount;
+   int wb_done_timeout_cnt;
+   struct dpu_hw_wb_cfg wb_cfg;
+   struct drm_writeback_connector *wb_conn;
+   struct drm_writeback_job *wb_job;
+   struct dpu_hw_fmt_layout dest;
+};
+
+/**
  * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle 
command
  * mode specific operations
  * @base:  Baseclass physical encoder structure
@@ -295,6 +318,13 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
struct dpu_enc_phys_init_params *p);
 
 /**
+ * dpu_encoder_phys_wb_init - initialize writeback encoder
+ * @init:  Pointer to init info structure with initialization params
+ */
+struct dpu_encoder_phys *dpu_encoder_phys_wb_init(
+   struct dpu_enc_phys_init_params *p);
+
+/**
  * dpu_encoder_helper_trigger_start - control start helper function
  * This helper function may be optionally specified by physical
  * encoders if they require ctl_start triggering.
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
new file mode 100644
index 000..4ab2699
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -0,0 +1,751 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#define pr_fmt(fmt)"[drm:%s:%d] " fmt, __func__, __LINE__
+
+#include 
+
+#include "dpu_encoder_phys.h"
+#include "dpu_formats.h"
+#include "dpu_hw_top.h"
+#include "dpu_hw_wb.h"
+#include "dpu_hw_lm.h"
+#include "dpu_hw_blk.h"
+#include "dpu_hw_merge3d.h"
+#include "dpu_hw_interrupts.h"
+#include "dpu_core_irq.h"
+#include "dpu_vbif.h"
+#include "dpu_crtc.h"
+#include "disp/msm_disp_snapshot.h"
+
+#define DEFAULT_MAX_WRITEBACK_WIDTH 2048
+
+#define to_dpu_encoder_phys_wb(x) \
+   container_of(x, struct dpu_encoder_phys_wb, base)
+
+/**
+ * dpu_encoder_phys_wb_is_master - report wb always as master encoder
+ */
+static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
+{
+   /* there is only one physical enc for dpu_writeback */
+   return true;
+}
+
+/**
+ * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
+ * @phys_enc:  Pointer

[PATCH v4 10/20] drm/msm/dpu: add an API to reset the encoder related hw blocks

Add an API to reset the encoder related hw blocks to ensure
a proper teardown of the pipeline. At the moment this is being
used only for the writeback encoder but eventually we can start
using this for all interfaces.

changes in v4:
- none

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 85 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  7 ++
 2 files changed, 91 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 4523693..25c7eda 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1,7 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights 
reserved.
  * Copyright (C) 2013 Red Hat
+ * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights 
reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
  * Author: Rob Clark 
  */
 
@@ -22,6 +24,7 @@
 #include "dpu_hw_ctl.h"
 #include "dpu_hw_dspp.h"
 #include "dpu_hw_dsc.h"
+#include "dpu_hw_merge3d.h"
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_crtc.h"
@@ -1838,6 +1841,86 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
DPU_ATRACE_END("encoder_kickoff");
 }
 
+static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
+{
+   struct dpu_hw_mixer_cfg mixer;
+   int i, num_lm;
+   u32 flush_mask = 0;
+   struct dpu_global_state *global_state;
+   struct dpu_hw_blk *hw_lm[2];
+   struct dpu_hw_mixer *hw_mixer[2];
+   struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
+
+   memset(, 0, sizeof(mixer));
+
+   /* reset all mixers for this encoder */
+   if (phys_enc->hw_ctl->ops.clear_all_blendstages)
+   phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
+
+   global_state = dpu_kms_get_existing_global_state(phys_enc->dpu_kms);
+
+   num_lm = dpu_rm_get_assigned_resources(_enc->dpu_kms->rm, 
global_state,
+   phys_enc->parent->base.id, DPU_HW_BLK_LM, hw_lm, 
ARRAY_SIZE(hw_lm));
+
+   for (i = 0; i < num_lm; i++) {
+   hw_mixer[i] = to_dpu_hw_mixer(hw_lm[i]);
+   flush_mask = phys_enc->hw_ctl->ops.get_bitmask_mixer(ctl, 
hw_mixer[i]->idx);
+   if (phys_enc->hw_ctl->ops.update_pending_flush)
+   phys_enc->hw_ctl->ops.update_pending_flush(ctl, 
flush_mask);
+
+   /* clear all blendstages */
+   if (phys_enc->hw_ctl->ops.setup_blendstage)
+   phys_enc->hw_ctl->ops.setup_blendstage(ctl, 
hw_mixer[i]->idx, NULL);
+   }
+}
+
+void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
+{
+   struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
+   struct dpu_hw_intf_cfg intf_cfg = { 0 };
+   int i;
+   struct dpu_encoder_virt *dpu_enc;
+
+   dpu_enc = to_dpu_encoder_virt(phys_enc->parent);
+
+   phys_enc->hw_ctl->ops.reset(ctl);
+
+   dpu_encoder_helper_reset_mixers(phys_enc);
+
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   if (dpu_enc->phys_encs[i] && 
phys_enc->hw_intf->ops.bind_pingpong_blk)
+   phys_enc->hw_intf->ops.bind_pingpong_blk(
+   dpu_enc->phys_encs[i]->hw_intf, false,
+   dpu_enc->phys_encs[i]->hw_pp->idx);
+
+   /* mark INTF flush as pending */
+   if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
+   
phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
+   dpu_enc->phys_encs[i]->hw_intf->idx);
+   }
+
+   /* reset the merge 3D HW block */
+   if (phys_enc->hw_pp->merge_3d) {
+   
phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
+   BLEND_3D_NONE);
+   if (phys_enc->hw_ctl->ops.update_pending_flush_merge_3d)
+   phys_enc->hw_ctl->ops.update_pending_flush_merge_3d(ctl,
+   phys_enc->hw_pp->merge_3d->idx);
+   }
+
+   intf_cfg.stream_sel = 0; /* Don't care value for video mode */
+   intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+   if (phys_enc->hw_pp->merge_3d)
+   intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
+
+   if (ctl->ops.reset_intf_cfg)
+   ctl->ops.reset_intf_cfg(ctl, _cfg);
+
+   ctl->ops.trigger_flush(ctl);
+   ctl->ops.trigger_start(ctl);
+   ctl->ops.clear_pending_flush(ctl);
+}
+
 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc)
 {
struct dpu_encoder_virt *dpu_enc;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

[PATCH v4 12/20] drm/msm/dpu: add encoder operations to prepare/cleanup wb job

add dpu encoder APIs to prepare and cleanup writeback job
for the writeback encoder. These shall be invoked from the
prepare_wb_job/cleanup_wb_job hooks of the drm_writeback
framework.

changes in v3:
- none

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 34 
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h  | 16 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  5 
 3 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d1e92d89..24870eb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -913,6 +913,40 @@ static int dpu_encoder_resource_control(struct drm_encoder 
*drm_enc,
return 0;
 }
 
+void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
+   struct drm_writeback_job *job)
+{
+   struct dpu_encoder_virt *dpu_enc;
+   int i;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+   if (phys->ops.prepare_wb_job)
+   phys->ops.prepare_wb_job(phys, job);
+
+   }
+}
+
+void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
+   struct drm_writeback_job *job)
+{
+   struct dpu_encoder_virt *dpu_enc;
+   int i;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+
+   if (phys->ops.cleanup_wb_job)
+   phys->ops.cleanup_wb_job(phys, job);
+
+   }
+}
+
 static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
 struct drm_crtc_state *crtc_state,
 struct drm_connector_state 
*conn_state)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 2903e65..6ceec1d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -180,4 +180,20 @@ bool dpu_encoder_is_widebus_enabled(const struct 
drm_encoder *drm_enc);
  */
 bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_prepare_wb_job - prepare writeback job for the encoder.
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @job:Pointer to the current drm writeback job
+ */
+void dpu_encoder_prepare_wb_job(struct drm_encoder *drm_enc,
+   struct drm_writeback_job *job);
+
+/**
+ * dpu_encoder_cleanup_wb_job - cleanup writeback job for the encoder.
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @job:Pointer to the current drm writeback job
+ */
+void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc,
+   struct drm_writeback_job *job);
+
 #endif /* __DPU_ENCODER_H__ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index c84b8e8..a42ed4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -7,6 +7,7 @@
 #ifndef __DPU_ENCODER_PHYS_H__
 #define __DPU_ENCODER_PHYS_H__
 
+#include 
 #include 
 
 #include "dpu_kms.h"
@@ -137,6 +138,10 @@ struct dpu_encoder_phys_ops {
void (*restore)(struct dpu_encoder_phys *phys);
int (*get_line_count)(struct dpu_encoder_phys *phys);
int (*get_frame_count)(struct dpu_encoder_phys *phys);
+   void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
+   struct drm_writeback_job *job);
+   void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
+   struct drm_writeback_job *job);
 };
 
 /**
-- 
2.7.4

[PATCH v4 15/20] drm/msm/dpu: add the writeback connector layer

Introduce the dpu_writeback module which serves as the
interface between dpu operations and the drm_writeback.

This module manages the connector related operations for
dpu writeback.

changes in v2:
- start using drm_writeback_connector_init_with_encoder()
- drop unnecessary arguments from dpu_writeback_init()
- rebase on msm-next tip and remove usage of priv->connectors

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/Makefile  |  1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c | 68 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h | 25 ++
 3 files changed, 94 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 0387f22..66395ee 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -80,6 +80,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_plane.o \
disp/dpu1/dpu_rm.o \
disp/dpu1/dpu_vbif.o \
+   disp/dpu1/dpu_writeback.o
 
 msm-$(CONFIG_DRM_MSM_MDSS) += \
msm_mdss.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
new file mode 100644
index 000..526d884
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "dpu_writeback.h"
+
+static int dpu_wb_conn_get_modes(struct drm_connector *connector)
+{
+   struct drm_device *dev = connector->dev;
+
+   return drm_add_modes_noedid(connector, dev->mode_config.max_width,
+   dev->mode_config.max_height);
+}
+
+static const struct drm_connector_funcs dpu_wb_conn_funcs = {
+   .reset = drm_atomic_helper_connector_reset,
+   .fill_modes = drm_helper_probe_single_connector_modes,
+   .destroy = drm_connector_cleanup,
+   .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+   .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int dpu_wb_conn_prepare_job(struct drm_writeback_connector *connector,
+   struct drm_writeback_job *job)
+{
+   if (!job->fb)
+   return 0;
+
+   dpu_encoder_prepare_wb_job(connector->encoder, job);
+
+   return 0;
+}
+
+static void dpu_wb_conn_cleanup_job(struct drm_writeback_connector *connector,
+   struct drm_writeback_job *job)
+{
+   if (!job->fb)
+   return;
+
+   dpu_encoder_cleanup_wb_job(connector->encoder, job);
+}
+
+static const struct drm_connector_helper_funcs dpu_wb_conn_helper_funcs = {
+   .get_modes = dpu_wb_conn_get_modes,
+   .prepare_writeback_job = dpu_wb_conn_prepare_job,
+   .cleanup_writeback_job = dpu_wb_conn_cleanup_job,
+};
+
+int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc,
+   const u32 *format_list, u32 num_formats)
+{
+   struct dpu_wb_connector *dpu_wb_conn;
+   int rc = 0;
+
+   dpu_wb_conn = devm_kzalloc(dev->dev, sizeof(*dpu_wb_conn), GFP_KERNEL);
+
+   drm_connector_helper_add(_wb_conn->base.base, 
_wb_conn_helper_funcs);
+
+   /* DPU initializes the encoder and sets it up completely for writeback
+* cases and hence should use the new API 
drm_writeback_connector_init_with_encoder
+* to initialize the writeback connector
+*/
+   rc = drm_writeback_connector_init_with_encoder(dev, _wb_conn->base, 
enc,
+   _wb_conn_funcs, format_list, num_formats);
+
+   return rc;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h
new file mode 100644
index 000..05aff05
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DPU_WRITEBACK_H
+#define _DPU_WRITEBACK_H
+
+#include 
+#include 
+#include 
+#include 
+
+#include "msm_drv.h"
+#include "dpu_kms.h"
+#include "dpu_encoder_phys.h"
+
+struct dpu_wb_connector {
+   struct drm_writeback_connector base;
+};
+
+int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc,
+   const u32 *format_list, u32 num_formats);
+
+#endif /*_DPU_WRITEBACK_H */
-- 
2.7.4

Re: [PATCH v3 2/2] drm/msm/dp: Implement oob_hotplug_event()


On 23/04/2022 01:32, Bjorn Andersson wrote:

The Qualcomm DisplayPort driver contains traces of the necessary
plumbing to hook up USB HPD, in the form of the dp_hpd module and the
dp_usbpd_cb struct. Use this as basis for implementing the
oob_hotplug_event() callback, by amending the dp_hpd module with the
missing logic.

Overall the solution is similar to what's done downstream, but upstream
all the code to disect the HPD notification lives on the calling side of
drm_connector_oob_hotplug_event().

drm_connector_oob_hotplug_event() performs the lookup of the
drm_connector based on fwnode, hence the need to assign the fwnode in
dp_drm_connector_init().

Signed-off-by: Bjorn Andersson 
---

Changes since v2:
- Rebased patch

  drivers/gpu/drm/msm/dp/dp_display.c |  9 +
  drivers/gpu/drm/msm/dp/dp_display.h |  3 +++
  drivers/gpu/drm/msm/dp/dp_drm.c | 11 +++
  drivers/gpu/drm/msm/dp/dp_hpd.c | 21 +
  drivers/gpu/drm/msm/dp/dp_hpd.h |  5 +
  5 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index a42732b67349..1019f6d8fd03 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -449,6 +449,14 @@ static int dp_display_usbpd_configure_cb(struct device 
*dev)
return dp_display_process_hpd_high(dp);
  }
  
+void dp_display_oob_hotplug_event(struct msm_dp *dp_display,

+ enum drm_connector_hpd_state hpd_state)
+{
+   struct dp_display_private *dp = container_of(dp_display, struct 
dp_display_private, dp_display);
+
+   dp->usbpd->oob_event(dp->usbpd, hpd_state);
+}
+
  static int dp_display_usbpd_disconnect_cb(struct device *dev)
  {
struct dp_display_private *dp = dev_get_dp_display_private(dev);
@@ -1302,6 +1310,7 @@ static int dp_display_probe(struct platform_device *pdev)
dp->pdev = pdev;
dp->name = "drm_dp";
dp->dp_display.connector_type = desc->connector_type;
+   dp->dp_display.dev = >dev;
  
  	rc = dp_init_sub_modules(dp);

if (rc) {
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h 
b/drivers/gpu/drm/msm/dp/dp_display.h
index 7af2b186d2d9..16658270df2c 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -11,6 +11,7 @@
  #include "disp/msm_disp_snapshot.h"
  
  struct msm_dp {

+   struct device *dev;
struct drm_device *drm_dev;
struct device *codec_dev;
struct drm_bridge *bridge;
@@ -40,5 +41,7 @@ bool dp_display_check_video_test(struct msm_dp *dp_display);
  int dp_display_get_test_bpp(struct msm_dp *dp_display);
  void dp_display_signal_audio_start(struct msm_dp *dp_display);
  void dp_display_signal_audio_complete(struct msm_dp *dp_display);
+void dp_display_oob_hotplug_event(struct msm_dp *dp_display,
+ enum drm_connector_hpd_state hpd_state);
  
  #endif /* _DP_DISPLAY_H_ */

diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 80f59cf99089..76904b1601b1 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -123,6 +123,14 @@ static enum drm_mode_status dp_connector_mode_valid(
return dp_display_validate_mode(dp_disp, mode->clock);
  }
  
+static void dp_oob_hotplug_event(struct drm_connector *connector,

+enum drm_connector_hpd_state hpd_state)
+{
+   struct msm_dp *dp_disp = to_dp_connector(connector)->dp_display;
+
+   dp_display_oob_hotplug_event(dp_disp, hpd_state);
+}
+
  static const struct drm_connector_funcs dp_connector_funcs = {
.detect = dp_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
@@ -130,6 +138,7 @@ static const struct drm_connector_funcs dp_connector_funcs 
= {
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+   .oob_hotplug_event = dp_oob_hotplug_event,


We were (are) going to switch dp driver to use drm_bridge_connector (to 
fix support for bridge chains, eDP panels, etc.


So these changes must be ported to drm_bridge_connector (or we must 
abandon/defer the idea of using the bridge_connector).


For the oob_hotplug_event() callback proper support might be as simple 
as calling drm_bridge_connector_hpd_cb().



  };
  
  static const struct drm_connector_helper_funcs dp_connector_helper_funcs = {

@@ -160,6 +169,8 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp 
*dp_display)
if (ret)
return ERR_PTR(ret);
  
+	connector->fwnode = fwnode_handle_get(dev_fwnode(dp_display->dev));

+


This would be much more interesting. Supporting this in a generic way 
might be tricky. But we can still set the fwnode manually from the dp code.



drm_connector_helper_add(connector,

[PATCH v4 16/20] drm/msm/dpu: initialize dpu encoder and connector for writeback

Initialize dpu encoder and connector for writeback if the
target supports it in the catalog.

changes in v2:
- start initialing the encoder for writeback since we
have migrated to using drm_writeback_connector_init_with_encoder()
- instead of checking for WB_2 inside _dpu_kms_initialize_writeback
call it only when its WB_2
- rebase on tip of msm-next and remove usage of priv->encoders

changes in v3:
- none

changes in v4:
- fix copyright years order

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 27 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 61 -
 2 files changed, 80 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 24870eb..2d79002 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2102,7 +2102,7 @@ static void dpu_encoder_early_unregister(struct 
drm_encoder *encoder)
 }
 
 static int dpu_encoder_virt_add_phys_encs(
-   u32 display_caps,
+   struct msm_display_info *disp_info,
struct dpu_encoder_virt *dpu_enc,
struct dpu_enc_phys_init_params *params)
 {
@@ -2121,7 +2121,7 @@ static int dpu_encoder_virt_add_phys_encs(
return -EINVAL;
}
 
-   if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
+   if (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE) {
enc = dpu_encoder_phys_vid_init(params);
 
if (IS_ERR_OR_NULL(enc)) {
@@ -2134,7 +2134,7 @@ static int dpu_encoder_virt_add_phys_encs(
++dpu_enc->num_phys_encs;
}
 
-   if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
+   if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
enc = dpu_encoder_phys_cmd_init(params);
 
if (IS_ERR_OR_NULL(enc)) {
@@ -2147,6 +2147,19 @@ static int dpu_encoder_virt_add_phys_encs(
++dpu_enc->num_phys_encs;
}
 
+   if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) {
+   enc = dpu_encoder_phys_wb_init(params);
+
+   if (IS_ERR_OR_NULL(enc)) {
+   DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n",
+   PTR_ERR(enc));
+   return enc == NULL ? -EINVAL : PTR_ERR(enc);
+   }
+
+   dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc;
+   ++dpu_enc->num_phys_encs;
+   }
+
if (params->split_role == ENC_ROLE_SLAVE)
dpu_enc->cur_slave = enc;
else
@@ -2248,9 +2261,8 @@ static int dpu_encoder_setup_display(struct 
dpu_encoder_virt *dpu_enc,
}
 
if (!ret) {
-   ret = 
dpu_encoder_virt_add_phys_encs(disp_info->capabilities,
-   
 dpu_enc,
-   
 _params);
+   ret = dpu_encoder_virt_add_phys_encs(disp_info,
+   dpu_enc, _params);
if (ret)
DPU_ERROR_ENC(dpu_enc, "failed to add phys 
encs\n");
}
@@ -2367,8 +2379,9 @@ struct drm_encoder *dpu_encoder_init(struct drm_device 
*dev,
if (!dpu_enc)
return ERR_PTR(-ENOMEM);
 
+
rc = drm_encoder_init(dev, _enc->base, _encoder_funcs,
-   drm_enc_mode, NULL);
+ drm_enc_mode, NULL);
if (rc) {
devm_kfree(dev->dev, dpu_enc);
return ERR_PTR(rc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index c683cab..9a406e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1,7 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
+ * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
  * Author: Rob Clark 
  */
 
@@ -15,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "msm_drv.h"
 #include "msm_mmu.h"
@@ -29,6 +32,7 @@
 #include "dpu_kms.h"
 #include "dpu_plane.h"
 #include "dpu_vbif.h"
+#include "dpu_writeback.h"
 
 #define CREATE_TRACE_POINTS
 #include "dpu_trace.h"
@@ -648,6 +652,45 @@ static int _dpu_kms_initialize_displayport(struct 
drm_device *dev,
return 0;
 }
 
+static int _dpu_kms_initialize_writeback(struct drm_device *dev,
+   struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
+

[PATCH v4 11/20] drm/msm/dpu: make changes to dpu_encoder to support virtual encoder

Make changes to dpu_encoder to support virtual encoder needed
to support writeback for dpu.

changes in v4:
- squash dpu_encoder pieces from [1]

[1] https://patchwork.freedesktop.org/patch/483099/?series=102964=2

Signed-off-by: Abhinav Kumar 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 94 +++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  7 ++
 2 files changed, 83 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 25c7eda..d1e92d89 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1013,9 +1013,18 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
phys->hw_intf = dpu_rm_get_intf(_kms->rm, 
phys->intf_idx);
 
-   if (!phys->hw_intf) {
+   if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
+   phys->hw_wb = dpu_rm_get_wb(_kms->rm, phys->wb_idx);
+
+   if (!phys->hw_intf && !phys->hw_wb) {
DPU_ERROR_ENC(dpu_enc,
- "no intf block assigned at idx: %d\n", i);
+ "no intf or wb block assigned at idx: 
%d\n", i);
+   return;
+   }
+
+   if (phys->hw_intf && phys->hw_wb) {
+   DPU_ERROR_ENC(dpu_enc,
+   "invalid phys both intf and wb block at 
idx: %d\n", i);
return;
}
 
@@ -1163,16 +1172,35 @@ static enum dpu_intf dpu_encoder_get_intf(struct 
dpu_mdss_cfg *catalog,
 {
int i = 0;
 
-   for (i = 0; i < catalog->intf_count; i++) {
-   if (catalog->intf[i].type == type
-   && catalog->intf[i].controller_id == controller_id) {
-   return catalog->intf[i].id;
+   if (type != INTF_WB) {
+   for (i = 0; i < catalog->intf_count; i++) {
+   if (catalog->intf[i].type == type
+   && catalog->intf[i].controller_id == 
controller_id) {
+   return catalog->intf[i].id;
+   }
}
}
 
return INTF_MAX;
 }
 
+static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,
+   enum dpu_intf_type type, u32 controller_id)
+{
+   int i = 0;
+
+   if (type != INTF_WB)
+   goto end;
+
+   for (i = 0; i < catalog->wb_count; i++) {
+   if (catalog->wb[i].id == controller_id)
+   return catalog->wb[i].id;
+   }
+
+end:
+   return WB_MAX;
+}
+
 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
struct dpu_encoder_phys *phy_enc)
 {
@@ -1887,16 +1915,32 @@ void dpu_encoder_helper_phys_cleanup(struct 
dpu_encoder_phys *phys_enc)
 
dpu_encoder_helper_reset_mixers(phys_enc);
 
-   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-   if (dpu_enc->phys_encs[i] && 
phys_enc->hw_intf->ops.bind_pingpong_blk)
-   phys_enc->hw_intf->ops.bind_pingpong_blk(
-   dpu_enc->phys_encs[i]->hw_intf, false,
-   dpu_enc->phys_encs[i]->hw_pp->idx);
-
-   /* mark INTF flush as pending */
-   if (phys_enc->hw_ctl->ops.update_pending_flush_intf)
-   
phys_enc->hw_ctl->ops.update_pending_flush_intf(phys_enc->hw_ctl,
-   dpu_enc->phys_encs[i]->hw_intf->idx);
+   /*
+* TODO: move the once-only operation like CTL flush/trigger
+* into dpu_encoder_virt_disable() and all operations which need
+* to be done per phys encoder into the phys_disable() op.
+*/
+   if (phys_enc->hw_wb) {
+   /* disable the PP block */
+   if (phys_enc->hw_wb->ops.bind_pingpong_blk)
+   phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb, 
false,
+   phys_enc->hw_pp->idx);
+
+   /* mark WB flush as pending */
+   if (phys_enc->hw_ctl->ops.update_pending_flush_wb)
+   phys_enc->hw_ctl->ops.update_pending_flush_wb(ctl, 
phys_enc->hw_wb->idx);
+   } else {
+   for (i = 0; i < dpu_enc->num_phys_encs; i++) {
+   if (dpu_enc->phys_encs[i] && 
phys_enc->hw_intf->ops.bind_pingpong_blk)
+   phys_enc->hw_intf->ops.bind_pingpong_blk(
+   dpu_enc->phys_encs[i]->hw_intf, 
false,
+   
dpu_enc->phys_encs[i]->hw_pp->idx);
+
+   /* mark INTF flush as pending */
+

[PATCH v4 13/20] drm/msm/dpu: move _dpu_plane_get_qos_lut to dpu_hw_util file

_dpu_plane_get_qos_lut() is not specific to just dpu_plane.
It can take any fill level and return the LUT matching it.
This can be used even for other modules like dpu_writeback.

Move _dpu_plane_get_qos_lut() to the common dpu_hw_util file
and rename it to _dpu_hw_get_qos_lut().

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 25 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h |  4 
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   | 27 +--
 3 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index aad8511..512316f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -422,3 +422,28 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
 }
+
+/**
+ * _dpu_hw_get_qos_lut - get LUT mapping based on fill level
+ * @tbl:   Pointer to LUT table
+ * @total_fl:  fill level
+ * Return: LUT setting corresponding to the fill level
+ */
+u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
+   u32 total_fl)
+{
+   int i;
+
+   if (!tbl || !tbl->nentry || !tbl->entries)
+   return 0;
+
+   for (i = 0; i < tbl->nentry; i++)
+   if (total_fl <= tbl->entries[i].fl)
+   return tbl->entries[i].lut;
+
+   /* if last fl is zero, use as default */
+   if (!tbl->entries[i-1].fl)
+   return tbl->entries[i-1].lut;
+
+   return 0;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index a200df1..e4a65eb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include "dpu_hw_mdss.h"
+#include "dpu_hw_catalog.h"
 
 #define REG_MASK(n) ((BIT(n)) - 1)
 
@@ -339,4 +340,7 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
u32 csc_reg_off,
const struct dpu_csc_cfg *data, bool csc10);
 
+u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
+   u32 total_fl);
+
 #endif /* _DPU_HW_UTIL_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 08b8c64..9d2f036 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -280,31 +280,6 @@ static int _dpu_plane_calc_fill_level(struct drm_plane 
*plane,
 }
 
 /**
- * _dpu_plane_get_qos_lut - get LUT mapping based on fill level
- * @tbl:   Pointer to LUT table
- * @total_fl:  fill level
- * Return: LUT setting corresponding to the fill level
- */
-static u64 _dpu_plane_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
-   u32 total_fl)
-{
-   int i;
-
-   if (!tbl || !tbl->nentry || !tbl->entries)
-   return 0;
-
-   for (i = 0; i < tbl->nentry; i++)
-   if (total_fl <= tbl->entries[i].fl)
-   return tbl->entries[i].lut;
-
-   /* if last fl is zero, use as default */
-   if (!tbl->entries[i-1].fl)
-   return tbl->entries[i-1].lut;
-
-   return 0;
-}
-
-/**
  * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
  * @plane: Pointer to drm plane
  * @fb:Pointer to framebuffer associated with the 
given plane
@@ -333,7 +308,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
}
 
-   qos_lut = _dpu_plane_get_qos_lut(
+   qos_lut = _dpu_hw_get_qos_lut(
>catalog->perf.qos_lut_tbl[lut_usage], total_fl);
 
trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0,
-- 
2.7.4

[PATCH v4 07/20] drm/msm/dpu: add dpu_hw_wb abstraction for writeback blocks

Add the dpu_hw_wb abstraction to program registers related to the
writeback block. These will be invoked once all the configuration
is set and ready to be programmed to the registers.

changes in v3:
- start using the common struct dpu_hw_cdp_cfg
- leave a comment about DPU non-DPU_WB_QOS_8LVL chipsets

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 279 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 115 
 3 files changed, 395 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
 create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d5ca2e6..ca779c1 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -74,6 +74,7 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_hw_top.o \
disp/dpu1/dpu_hw_util.o \
disp/dpu1/dpu_hw_vbif.o \
+   disp/dpu1/dpu_hw_wb.o \
disp/dpu1/dpu_kms.o \
disp/dpu1/dpu_plane.o \
disp/dpu1/dpu_rm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
new file mode 100644
index 000..be2
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0-only
+ /*
+  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved
+  */
+
+#include "dpu_hw_mdss.h"
+#include "dpu_hwio.h"
+#include "dpu_hw_catalog.h"
+#include "dpu_hw_wb.h"
+#include "dpu_formats.h"
+#include "dpu_kms.h"
+
+#define WB_DST_FORMAT 0x000
+#define WB_DST_OP_MODE0x004
+#define WB_DST_PACK_PATTERN   0x008
+#define WB_DST0_ADDR  0x00C
+#define WB_DST1_ADDR  0x010
+#define WB_DST2_ADDR  0x014
+#define WB_DST3_ADDR  0x018
+#define WB_DST_YSTRIDE0   0x01C
+#define WB_DST_YSTRIDE1   0x020
+#define WB_DST_YSTRIDE1   0x020
+#define WB_DST_DITHER_BITDEPTH0x024
+#define WB_DST_MATRIX_ROW00x030
+#define WB_DST_MATRIX_ROW10x034
+#define WB_DST_MATRIX_ROW20x038
+#define WB_DST_MATRIX_ROW30x03C
+#define WB_DST_WRITE_CONFIG   0x048
+#define WB_ROTATION_DNSCALER  0x050
+#define WB_ROTATOR_PIPE_DOWNSCALER0x054
+#define WB_N16_INIT_PHASE_X_C03   0x060
+#define WB_N16_INIT_PHASE_X_C12   0x064
+#define WB_N16_INIT_PHASE_Y_C03   0x068
+#define WB_N16_INIT_PHASE_Y_C12   0x06C
+#define WB_OUT_SIZE   0x074
+#define WB_ALPHA_X_VALUE  0x078
+#define WB_DANGER_LUT 0x084
+#define WB_SAFE_LUT   0x088
+#define WB_QOS_CTRL   0x090
+#define WB_CREQ_LUT_0 0x098
+#define WB_CREQ_LUT_1 0x09C
+#define WB_UBWC_STATIC_CTRL   0x144
+#define WB_MUX0x150
+#define WB_CROP_CTRL  0x154
+#define WB_CROP_OFFSET0x158
+#define WB_CSC_BASE   0x260
+#define WB_DST_ADDR_SW_STATUS 0x2B0
+#define WB_CDP_CNTL   0x2B4
+#define WB_OUT_IMAGE_SIZE 0x2C0
+#define WB_OUT_XY 0x2C4
+
+/* WB_QOS_CTRL */
+#define WB_QOS_CTRL_DANGER_SAFE_ENBIT(0)
+
+static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb,
+   const struct dpu_mdss_cfg *m, void __iomem *addr,
+   struct dpu_hw_blk_reg_map *b)
+{
+   int i;
+
+   for (i = 0; i < m->wb_count; i++) {
+   if (wb == m->wb[i].id) {
+   b->base_off = addr;
+   b->blk_off = m->wb[i].base;
+   b->length = m->wb[i].len;
+   b->hwversion = m->hwversion;
+   return >wb[i];
+   }
+   }
+   return ERR_PTR(-EINVAL);
+}
+
+static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx,
+   struct dpu_hw_wb_cfg *data)
+{
+   struct dpu_hw_blk_reg_map *c = >hw;
+
+   DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);
+   DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]);
+   DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]);
+   DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]);
+}
+
+static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
+   struct dpu_hw_wb_cfg *data)
+{
+   struct dpu_hw_blk_reg_map *c = >hw;
+   const struct dpu_format *fmt = data->dest.format;

[PATCH v4 04/20] drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog

Add writeback blocks to the sm8250 DPU hardware catalog. Other
chipsets support writeback too but add it to sm8250 to prototype
the feature so that it can be easily extended to other chipsets.

changes in v4:
- fix the copyright year order

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 72 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 66 ++-
 2 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index b0a0ef7..7e3f0f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #define pr_fmt(fmt)"[drm:%s:%d] " fmt, __func__, __LINE__
@@ -120,6 +121,16 @@
  BIT(MDP_AD4_0_INTR) | \
  BIT(MDP_AD4_1_INTR))
 
+#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
+BIT(DPU_WB_UBWC) | \
+BIT(DPU_WB_YUV_CONFIG) | \
+BIT(DPU_WB_PIPE_ALPHA) | \
+BIT(DPU_WB_XY_ROI_OFFSET) | \
+BIT(DPU_WB_QOS) | \
+BIT(DPU_WB_QOS_8LVL) | \
+BIT(DPU_WB_CDP) | \
+BIT(DPU_WB_INPUT_CTRL))
+
 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
 #define DEFAULT_DPU_LINE_WIDTH 2048
 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH  2560
@@ -211,6 +222,40 @@ static const u32 rotation_v2_formats[] = {
/* TODO add formats after validation */
 };
 
+static const uint32_t wb2_formats[] = {
+   DRM_FORMAT_RGB565,
+   DRM_FORMAT_BGR565,
+   DRM_FORMAT_RGB888,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_RGBA,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_RGBX,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ARGB1555,
+   DRM_FORMAT_RGBA5551,
+   DRM_FORMAT_XRGB1555,
+   DRM_FORMAT_RGBX5551,
+   DRM_FORMAT_ARGB,
+   DRM_FORMAT_RGBA,
+   DRM_FORMAT_RGBX,
+   DRM_FORMAT_XRGB,
+   DRM_FORMAT_BGR565,
+   DRM_FORMAT_BGR888,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_BGRA,
+   DRM_FORMAT_BGRX,
+   DRM_FORMAT_XBGR,
+   DRM_FORMAT_ABGR1555,
+   DRM_FORMAT_BGRA5551,
+   DRM_FORMAT_XBGR1555,
+   DRM_FORMAT_BGRX5551,
+   DRM_FORMAT_ABGR,
+   DRM_FORMAT_BGRA,
+   DRM_FORMAT_BGRX,
+   DRM_FORMAT_XBGR,
+};
+
 /*
  * DPU sub blocks config
  */
@@ -448,6 +493,8 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
.reg_off = 0x2C4, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
.reg_off = 0x2BC, .bit_off = 20},
+   .clk_ctrls[DPU_CLK_CTRL_WB2] = {
+   .reg_off = 0x3B8, .bit_off = 24},
},
 };
 
@@ -1235,6 +1282,29 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
 };
 
 /*
+ * Writeback blocks config
+ */
+#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
+   __xin_id, vbif_id, _reg, _wb_done_bit) \
+   { \
+   .name = _name, .id = _id, \
+   .base = _base, .len = 0x2c8, \
+   .features = _features, \
+   .format_list = wb2_formats, \
+   .num_formats = ARRAY_SIZE(wb2_formats), \
+   .clk_ctrl = _clk_ctrl, \
+   .xin_id = __xin_id, \
+   .vbif_idx = vbif_id, \
+   .maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \
+   .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
+   }
+
+static const struct dpu_wb_cfg sm8250_wb[] = {
+   WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
+   VBIF_RT, MDP_SSPP_TOP0_INTR, 4),
+};
+
+/*
  * VBIF sub blocks config
  */
 /* VBIF QOS remap */
@@ -1832,6 +1902,8 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.intf = sm8150_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
+   .wb_count = ARRAY_SIZE(sm8250_wb),
+   .wb = sm8250_wb,
.reg_dma_count = 1,
.dma_cfg = sm8250_regdma,
.perf = sm8250_perf_data,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 866fd7a..8cb6d1f

[PATCH v4 09/20] drm/msm/dpu: add changes to support writeback in hw_ctl

Add changes to support writeback module in the dpu_hw_ctl
interface.

changes in v4:
- fix the copyright year order

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 52 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 13 
 2 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 524f024..254fdf0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include 
@@ -23,10 +24,12 @@
 #define   CTL_SW_RESET  0x030
 #define   CTL_LAYER_EXTN_OFFSET 0x40
 #define   CTL_MERGE_3D_ACTIVE   0x0E4
+#define   CTL_WB_ACTIVE 0x0EC
 #define   CTL_INTF_ACTIVE   0x0F4
 #define   CTL_MERGE_3D_FLUSH0x100
 #define   CTL_DSC_ACTIVE0x0E8
 #define   CTL_DSC_FLUSH0x104
+#define   CTL_WB_FLUSH  0x108
 #define   CTL_INTF_FLUSH0x110
 #define   CTL_INTF_MASTER   0x134
 #define   CTL_FETCH_PIPE_ACTIVE 0x0FC
@@ -38,6 +41,7 @@
 #define  MERGE_3D_IDX   23
 #define  DSC_IDX22
 #define  INTF_IDX   31
+#define WB_IDX  16
 #define CTL_INVALID_BIT 0x
 #define CTL_DEFAULT_GROUP_ID   0xf
 
@@ -135,6 +139,9 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct 
dpu_hw_ctl *ctx)
if (ctx->pending_flush_mask & BIT(INTF_IDX))
DPU_REG_WRITE(>hw, CTL_INTF_FLUSH,
ctx->pending_intf_flush_mask);
+   if (ctx->pending_flush_mask & BIT(WB_IDX))
+   DPU_REG_WRITE(>hw, CTL_WB_FLUSH,
+   ctx->pending_wb_flush_mask);
 
DPU_REG_WRITE(>hw, CTL_FLUSH, ctx->pending_flush_mask);
 }
@@ -255,6 +262,26 @@ static void dpu_hw_ctl_update_pending_flush_intf(struct 
dpu_hw_ctl *ctx,
}
 }
 
+static void dpu_hw_ctl_update_pending_flush_wb(struct dpu_hw_ctl *ctx,
+   enum dpu_wb wb)
+{
+   switch (wb) {
+   case WB_0:
+   case WB_1:
+   case WB_2:
+   ctx->pending_flush_mask |= BIT(WB_IDX);
+   default:
+   break;
+   }
+}
+
+static void dpu_hw_ctl_update_pending_flush_wb_v1(struct dpu_hw_ctl *ctx,
+   enum dpu_wb wb)
+{
+   ctx->pending_wb_flush_mask |= BIT(wb - WB_0);
+   ctx->pending_flush_mask |= BIT(WB_IDX);
+}
+
 static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx,
enum dpu_intf intf)
 {
@@ -504,6 +531,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
 {
struct dpu_hw_blk_reg_map *c = >hw;
u32 intf_active = 0;
+   u32 wb_active = 0;
u32 mode_sel = 0;
 
/* CTL_TOP[31:28] carries group_id to collate CTL paths
@@ -520,10 +548,18 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
mode_sel |= BIT(17);
 
intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
-   intf_active |= BIT(cfg->intf - INTF_0);
+   wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);
+
+   if (cfg->intf)
+   intf_active |= BIT(cfg->intf - INTF_0);
+
+   if (cfg->wb)
+   wb_active |= BIT(cfg->wb - WB_0);
 
DPU_REG_WRITE(c, CTL_TOP, mode_sel);
DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
+   DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
+
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
  BIT(cfg->merge_3d - MERGE_3D_0));
@@ -546,6 +582,9 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
intf_cfg |= (cfg->mode_3d - 0x1) << 20;
}
 
+   if (cfg->wb)
+   intf_cfg |= (cfg->wb & 0x3) + 2;
+
switch (cfg->intf_mode_sel) {
case DPU_CTL_MODE_SEL_VID:
intf_cfg &= ~BIT(17);
@@ -568,12 +607,13 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct 
dpu_hw_ctl *ctx,
 {
struct dpu_hw_blk_reg_map *c = >hw;
u32 intf_active = 0;
+   u32 wb_active = 0;
u32 merge3d_active = 0;
 
/*
 * This API resets each portion of the CTL path namely,
 * clearing the sspps staged on the lm, merge_3d block,
-* interfaces etc to ensure clean teardown of the pipeline.
+* interfaces , writeback etc to ensure clean teardown of the pipeline.
 * This will be used for writeback to begin with to have a
 * proper teardown of the writeback session but upon further
 * validation, this can be extended to all interfaces.
@@ -592,6 +632,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl

[PATCH v4 06/20] drm/msm/dpu: rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg

Rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg and move it
to dpu_hw_utils file so that other modules in addition to
SSPP such as writeback can use it as all the fields can
be used by writeback as well.

Suggested-by: Dmitry Baryshkov 
Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c |  2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 18 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 15 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c   |  4 ++--
 4 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 09cdc35..0a0864d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -627,7 +627,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe 
*ctx,
 }
 
 static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx,
-   struct dpu_hw_pipe_cdp_cfg *cfg,
+   struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index)
 {
u32 idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 92b071b..a81e166 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -193,22 +193,6 @@ enum {
 };
 
 /**
- * struct dpu_hw_pipe_cdp_cfg : CDP configuration
- * @enable: true to enable CDP
- * @ubwc_meta_enable: true to enable ubwc metadata preload
- * @tile_amortize_enable: true to enable amortization control for tile format
- * @preload_ahead: number of request to preload ahead
- * DPU_SSPP_CDP_PRELOAD_AHEAD_32,
- * DPU_SSPP_CDP_PRELOAD_AHEAD_64
- */
-struct dpu_hw_pipe_cdp_cfg {
-   bool enable;
-   bool ubwc_meta_enable;
-   bool tile_amortize_enable;
-   u32 preload_ahead;
-};
-
-/**
  * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
  * @size: size to prefill in bytes, or zero to disable
  * @time: time to prefill in usec, or zero to disable
@@ -359,7 +343,7 @@ struct dpu_hw_sspp_ops {
 * @index: rectangle index in multirect
 */
void (*setup_cdp)(struct dpu_hw_pipe *ctx,
-   struct dpu_hw_pipe_cdp_cfg *cfg,
+   struct dpu_hw_cdp_cfg *cfg,
enum dpu_sspp_multirect_index index);
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 3913475..a200df1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -298,6 +298,21 @@ struct dpu_drm_scaler_v2 {
struct dpu_drm_de_v1 de;
 };
 
+/**
+ * struct dpu_hw_cdp_cfg : CDP configuration
+ * @enable: true to enable CDP
+ * @ubwc_meta_enable: true to enable ubwc metadata preload
+ * @tile_amortize_enable: true to enable amortization control for tile format
+ * @preload_ahead: number of request to preload ahead
+ * DPU_*_CDP_PRELOAD_AHEAD_32,
+ * DPU_*_CDP_PRELOAD_AHEAD_64
+ */
+struct dpu_hw_cdp_cfg {
+   bool enable;
+   bool ubwc_meta_enable;
+   bool tile_amortize_enable;
+   u32 preload_ahead;
+};
 
 u32 *dpu_hw_util_get_log_mask_ptr(void);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index c77c3d9d..08b8c64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1246,9 +1246,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane 
*plane)
pstate->multirect_index);
 
if (pdpu->pipe_hw->ops.setup_cdp) {
-   struct dpu_hw_pipe_cdp_cfg cdp_cfg;
+   struct dpu_hw_cdp_cfg cdp_cfg;
 
-   memset(_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
+   memset(_cfg, 0, sizeof(struct dpu_hw_cdp_cfg));
 
cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
[DPU_PERF_CDP_USAGE_RT].rd_enable;
-- 
2.7.4

[PATCH v4 08/20] drm/msm/dpu: add writeback blocks to DPU RM

Add writeback blocks to DPU resource manager so that
the encoders can directly request them through RM.

changes in v4:
- absorb dpu_rm.h header change from [1]
- since its a trivial change absorbed from an approved
  patch, preserving the previous ack on this

[1] https://patchwork.freedesktop.org/patch/483099/?series=102964=2

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 0e6634b..06f03e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -9,6 +9,7 @@
 #include "dpu_hw_ctl.h"
 #include "dpu_hw_pingpong.h"
 #include "dpu_hw_intf.h"
+#include "dpu_hw_wb.h"
 #include "dpu_hw_dspp.h"
 #include "dpu_hw_merge3d.h"
 #include "dpu_hw_dsc.h"
@@ -87,6 +88,9 @@ int dpu_rm_destroy(struct dpu_rm *rm)
}
}
 
+   for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++)
+   dpu_hw_wb_destroy(rm->hw_wb[i]);
+
return 0;
 }
 
@@ -186,6 +190,24 @@ int dpu_rm_init(struct dpu_rm *rm,
rm->hw_intf[intf->id - INTF_0] = hw;
}
 
+   for (i = 0; i < cat->wb_count; i++) {
+   struct dpu_hw_wb *hw;
+   const struct dpu_wb_cfg *wb = >wb[i];
+
+   if (wb->id < WB_0 || wb->id >= WB_MAX) {
+   DPU_ERROR("skip intf %d with invalid id\n", wb->id);
+   continue;
+   }
+
+   hw = dpu_hw_wb_init(wb->id, mmio, cat);
+   if (IS_ERR(hw)) {
+   rc = PTR_ERR(hw);
+   DPU_ERROR("failed wb object creation: err %d\n", rc);
+   goto fail;
+   }
+   rm->hw_wb[wb->id - WB_0] = hw;
+   }
+
for (i = 0; i < cat->ctl_count; i++) {
struct dpu_hw_ctl *hw;
const struct dpu_ctl_cfg *ctl = >ctl[i];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 32e0d8a..2f34a31 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -19,6 +19,7 @@ struct dpu_global_state;
  * @mixer_blks: array of layer mixer hardware resources
  * @ctl_blks: array of ctl hardware resources
  * @hw_intf: array of intf hardware resources
+ * @hw_wb: array of wb hardware resources
  * @dspp_blks: array of dspp hardware resources
  */
 struct dpu_rm {
@@ -26,6 +27,7 @@ struct dpu_rm {
struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
+   struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
@@ -96,5 +98,15 @@ static inline struct dpu_hw_intf *dpu_rm_get_intf(struct 
dpu_rm *rm, enum dpu_in
return rm->hw_intf[intf_idx - INTF_0];
 }
 
+/**
+ * dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
+ * @rm: DPU Resource Manager handle
+ * @wb_idx: WB index
+ */
+static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb 
wb_idx)
+{
+   return rm->hw_wb[wb_idx - WB_0];
+}
+
 #endif /* __DPU_RM_H__ */
 
-- 
2.7.4

[PATCH v4 05/20] drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl

Add a reset_intf_cfg operation for dpu_hw_ctl to reset the
entire CTL path by disabling each component namely layer mixer,
3d-merge and interface blocks.

changes in v3:
- none

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 32 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  8 
 2 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index dc27579..524f024 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -563,6 +563,37 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_TOP, intf_cfg);
 }
 
+static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx,
+   struct dpu_hw_intf_cfg *cfg)
+{
+   struct dpu_hw_blk_reg_map *c = >hw;
+   u32 intf_active = 0;
+   u32 merge3d_active = 0;
+
+   /*
+* This API resets each portion of the CTL path namely,
+* clearing the sspps staged on the lm, merge_3d block,
+* interfaces etc to ensure clean teardown of the pipeline.
+* This will be used for writeback to begin with to have a
+* proper teardown of the writeback session but upon further
+* validation, this can be extended to all interfaces.
+*/
+   if (cfg->merge_3d) {
+   merge3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE);
+   merge3d_active &= ~BIT(cfg->merge_3d - MERGE_3D_0);
+   DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
+   merge3d_active);
+   }
+
+   dpu_hw_ctl_clear_all_blendstages(ctx);
+
+   if (cfg->intf) {
+   intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
+   intf_active &= ~BIT(cfg->intf - INTF_0);
+   DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
+   }
+}
+
 static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
unsigned long *fetch_active)
 {
@@ -586,6 +617,7 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
+   ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
ops->update_pending_flush_intf =
dpu_hw_ctl_update_pending_flush_intf_v1;
ops->update_pending_flush_merge_3d =
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 97f326d..c61a8fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -140,6 +140,14 @@ struct dpu_hw_ctl_ops {
void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx,
struct dpu_hw_intf_cfg *cfg);
 
+   /**
+* reset ctl_path interface config
+* @ctx: ctl path ctx pointer
+* @cfg: interface config structure pointer
+*/
+   void (*reset_intf_cfg)(struct dpu_hw_ctl *ctx,
+   struct dpu_hw_intf_cfg *cfg);
+
int (*reset)(struct dpu_hw_ctl *c);
 
/*
-- 
2.7.4

[PATCH v4 03/20] drm: allow real encoder to be passed for drm_writeback_connector

For some vendor driver implementations, display hardware can
be shared between the encoder used for writeback and the physical
display.

In addition resources such as clocks and interrupts can
also be shared between writeback and the real encoder.

To accommodate such vendor drivers and hardware, allow
real encoder to be passed for drm_writeback_connector.

For existing clients, drm_writeback_connector_init() will use
an internal_encoder under the hood and hence no changes will
be needed.

changes in v7:
- move this change before the vc4 change in the series
  to minimize the changes to vendor drivers in drm core
  changes

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/drm_writeback.c | 18 --
 drivers/gpu/drm/vc4/vc4_txp.c   |  4 ++--
 include/drm/drm_writeback.h | 22 --
 3 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_writeback.c b/drivers/gpu/drm/drm_writeback.c
index 92658ad..0538674 100644
--- a/drivers/gpu/drm/drm_writeback.c
+++ b/drivers/gpu/drm/drm_writeback.c
@@ -180,21 +180,21 @@ int drm_writeback_connector_init(struct drm_device *dev,
 {
int ret = 0;
 
-   drm_encoder_helper_add(_connector->encoder, enc_helper_funcs);
+   drm_encoder_helper_add(_connector->internal_encoder, 
enc_helper_funcs);
 
-   wb_connector->encoder.possible_crtcs = possible_crtcs;
+   wb_connector->internal_encoder.possible_crtcs = possible_crtcs;
 
-   ret = drm_encoder_init(dev, _connector->encoder,
+   ret = drm_encoder_init(dev, _connector->internal_encoder,
   _writeback_encoder_funcs,
   DRM_MODE_ENCODER_VIRTUAL, NULL);
if (ret)
return ret;
 
-   ret = drm_writeback_connector_init_with_encoder(dev, wb_connector, 
_connector->encoder,
-   con_funcs, formats, n_formats);
+   ret = drm_writeback_connector_init_with_encoder(dev, wb_connector,
+   _connector->internal_encoder, con_funcs, formats, 
n_formats);
 
if (ret)
-   drm_encoder_cleanup(_connector->encoder);
+   drm_encoder_cleanup(_connector->internal_encoder);
 
return ret;
 }
@@ -239,6 +239,12 @@ int drm_writeback_connector_init_with_encoder(struct 
drm_device *dev,
struct drm_mode_config *config = >mode_config;
int ret = create_writeback_properties(dev);
 
+   /*
+* Assign the encoder passed to this API to the wb_connector's encoder.
+* For drm_writeback_connector_init(), this shall be the 
internal_encoder
+*/
+   wb_connector->encoder = enc;
+
if (ret != 0)
return ret;
 
diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c
index 3447eb6..7e063a9 100644
--- a/drivers/gpu/drm/vc4/vc4_txp.c
+++ b/drivers/gpu/drm/vc4/vc4_txp.c
@@ -159,7 +159,7 @@ struct vc4_txp {
 
 static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
 {
-   return container_of(encoder, struct vc4_txp, connector.encoder);
+   return container_of(encoder, struct vc4_txp, 
connector.internal_encoder);
 }
 
 static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
@@ -507,7 +507,7 @@ static int vc4_txp_bind(struct device *dev, struct device 
*master, void *data)
if (ret)
return ret;
 
-   encoder = >connector.encoder;
+   encoder = txp->connector.encoder;
encoder->possible_crtcs = drm_crtc_mask(crtc);
 
ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
diff --git a/include/drm/drm_writeback.h b/include/drm/drm_writeback.h
index bb306fa..3fbae9d 100644
--- a/include/drm/drm_writeback.h
+++ b/include/drm/drm_writeback.h
@@ -25,13 +25,31 @@ struct drm_writeback_connector {
struct drm_connector base;
 
/**
-* @encoder: Internal encoder used by the connector to fulfill
+* @encoder: handle to drm_encoder used by the connector to fulfill
 * the DRM framework requirements. The users of the
 * @drm_writeback_connector control the behaviour of the @encoder
 * by passing the @enc_funcs parameter to drm_writeback_connector_init()
 * function.
+*
+* For some vendor drivers, the hardware resources are shared between
+* writeback encoder and rest of the display pipeline.
+* To accommodate such cases, encoder is a handle to the real encoder
+* hardware.
+*
+* For current existing writeback users, this shall continue to be the
+* embedded encoder for the writeback connector.
+*/
+   struct drm_encoder *encoder;
+
+   /**
+* @internal_encoder: internal encoder used by writeback when
+* drm_writeback_connector_init() is used.
+* @encoder will be assigned to this for those cases
+*
+* This will be unused when

[PATCH v4 02/20] drm: introduce drm_writeback_connector_init_with_encoder() API

For vendors drivers which pass an already allocated and
initialized encoder especially for cases where the encoder
hardware is shared OR the writeback encoder shares the resources
with the rest of the display pipeline introduce a new API,
drm_writeback_connector_init_with_encoder() which expects
an initialized encoder as a parameter and only sets up the
writeback connector.

changes in v4:
- removed the possible_crtcs part

changes in v5:
- reorder this change to come before in the series
  to avoid incorrect functionality in subsequent changes
- continue using struct drm_encoder instead of
  struct drm_encoder * and switch it in next change

changes in v6:
- remove drm_writeback_connector_setup() and instead
  directly call drm_writeback_connector_init_with_encoder()
- fix a drm_writeback_connector typo and function doc which
  incorrectly shows that the function accepts enc_helper_funcs
- pass encoder as a parameter explicitly to the new API
  for better readability

changes in v7:
- fix the function doc slightly as suggested by Liviu

Reviewed-by: Liviu Dudau 
Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/drm_writeback.c | 72 +
 include/drm/drm_writeback.h |  6 
 2 files changed, 64 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/drm_writeback.c b/drivers/gpu/drm/drm_writeback.c
index 9e0b845..92658ad 100644
--- a/drivers/gpu/drm/drm_writeback.c
+++ b/drivers/gpu/drm/drm_writeback.c
@@ -178,6 +178,62 @@ int drm_writeback_connector_init(struct drm_device *dev,
 const u32 *formats, int n_formats,
 u32 possible_crtcs)
 {
+   int ret = 0;
+
+   drm_encoder_helper_add(_connector->encoder, enc_helper_funcs);
+
+   wb_connector->encoder.possible_crtcs = possible_crtcs;
+
+   ret = drm_encoder_init(dev, _connector->encoder,
+  _writeback_encoder_funcs,
+  DRM_MODE_ENCODER_VIRTUAL, NULL);
+   if (ret)
+   return ret;
+
+   ret = drm_writeback_connector_init_with_encoder(dev, wb_connector, 
_connector->encoder,
+   con_funcs, formats, n_formats);
+
+   if (ret)
+   drm_encoder_cleanup(_connector->encoder);
+
+   return ret;
+}
+EXPORT_SYMBOL(drm_writeback_connector_init);
+
+/**
+ * drm_writeback_connector_init_with_encoder - Initialize a writeback 
connector and its properties
+ * using the encoder which already assigned and initialized
+ *
+ * @dev: DRM device
+ * @wb_connector: Writeback connector to initialize
+ * @enc: handle to the already initialized drm encoder
+ * @con_funcs: Connector funcs vtable
+ * @formats: Array of supported pixel formats for the writeback engine
+ * @n_formats: Length of the formats array
+ *
+ * This function creates the writeback-connector-specific properties if they
+ * have not been already created, initializes the connector as
+ * type DRM_MODE_CONNECTOR_WRITEBACK, and correctly initializes the property
+ * values.
+ *
+ * This function assumes that the drm_writeback_connector's encoder has 
already been
+ * created and initialized before invoking this function.
+ *
+ * In addition, this function also assumes that callers of this API will manage
+ * assigning the encoder helper functions, possible_crtcs and any other encoder
+ * specific operation.
+ *
+ * Drivers should always use this function instead of drm_connector_init() to
+ * set up writeback connectors if they want to manage themselves the lifetime 
of the
+ * associated encoder.
+ *
+ * Returns: 0 on success, or a negative error code
+ */
+int drm_writeback_connector_init_with_encoder(struct drm_device *dev,
+   struct drm_writeback_connector *wb_connector, struct 
drm_encoder *enc,
+   const struct drm_connector_funcs *con_funcs, const u32 *formats,
+   int n_formats)
+{
struct drm_property_blob *blob;
struct drm_connector *connector = _connector->base;
struct drm_mode_config *config = >mode_config;
@@ -191,15 +247,6 @@ int drm_writeback_connector_init(struct drm_device *dev,
if (IS_ERR(blob))
return PTR_ERR(blob);
 
-   drm_encoder_helper_add(_connector->encoder, enc_helper_funcs);
-
-   wb_connector->encoder.possible_crtcs = possible_crtcs;
-
-   ret = drm_encoder_init(dev, _connector->encoder,
-  _writeback_encoder_funcs,
-  DRM_MODE_ENCODER_VIRTUAL, NULL);
-   if (ret)
-   goto fail;
 
connector->interlace_allowed = 0;
 
@@ -208,8 +255,7 @@ int drm_writeback_connector_init(struct drm_device *dev,
if (ret)
goto connector_fail;
 
-   ret = drm_connector_attach_encoder(connector,
-

[PATCH v4 00/20] Add writeback block support for DPU

This series adds support for writeback block on DPU. Writeback
block is extremely useful to validate boards having no physical displays
in addition to many other use-cases where we want to get the output
of the display pipeline to examine whether issue is with the display
pipeline or with the panel.

These changes have been validated on SM8250 RB5 boards with IGT KMS
writeback test-suite thereby further increasing the IGT test coverage
for DPU. I am sharing the test results below.

root@linaro-developer:~/igt_repo/igt-gpu-tools/build/tests# ./kms_writeback
[   35.066157] Console: switching to colour dummy device 80x25
[   35.071964] [IGT] kms_writeback: executing
IGT-Version: 1.26-gae2eb9e1 (aarch64) (Linux: 5.16.0-rc2-62171-g132577e2697b 
aarch64)
[   35.611418] [IGT] kms_writeback: starting subtest writeback-pixel-formats
Starting subtest: writeback-pixel-formats
[   35.618528] [IGT] kms_writeback: starting subtest 
writeback-invalid-parameters
Subtest writeback-pixel-formats: SUCCESS (0.000s)
Starting subtest: writeback-invalid-parameters
Subtest writeback-invalid-parameters: SUCCESS (0.028s)   35.657437] [IGT] 
kms_writeback: starting subtest writeback-fb-id
Starting subtest: writeback-fb-id
Subtest writeback-fb-id: SUCCESS (0.030s)
[   35.698957] [IGT] kms_writeback: starting subtest writeback-check-output
Starting subtest: writeback-check-output
[   35.852834] [IGT] kms_writeback: exiting, ret=0
Subtest writeback-check-output: SUCCESS (0.142s)
[   35.861291] Console: switching to colour frame buffer device 240x67
root@linaro-developer:~/igt_repo/igt-gpu-tools/build/tests# 

The changes can easily be extended to support any other chipset using
the DPU driver by adding the support in the catalog.

Writeback block supports various formats and features. The support
for all of them can be incrementally added on top of this framework when
validation is improved and the test frameworks are extended to validate
them.

changes in v4:
- absorb https://patchwork.freedesktop.org/series/102964/ into this
  and also preserve necessary acks for trivial changes
- fix order of copyright years for all the changes  

Abhinav Kumar (20):
  drm: allow passing possible_crtcs to drm_writeback_connector_init()
  drm: introduce drm_writeback_connector_init_with_encoder() API
  drm: allow real encoder to be passed for drm_writeback_connector
  drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog
  drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl
  drm/msm/dpu: rename dpu_hw_pipe_cdp_cfg to dpu_hw_cdp_cfg
  drm/msm/dpu: add dpu_hw_wb abstraction for writeback blocks
  drm/msm/dpu: add writeback blocks to DPU RM
  drm/msm/dpu: add changes to support writeback in hw_ctl
  drm/msm/dpu: add an API to reset the encoder related hw blocks
  drm/msm/dpu: make changes to dpu_encoder to support virtual encoder
  drm/msm/dpu: add encoder operations to prepare/cleanup wb job
  drm/msm/dpu: move _dpu_plane_get_qos_lut to dpu_hw_util file
  drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback
  drm/msm/dpu: add the writeback connector layer
  drm/msm/dpu: initialize dpu encoder and connector for writeback
  drm/msm/dpu: gracefully handle null fb commits for writeback
  drm/msm/dpu: add writeback blocks to the display snapshot
  drm/msm/dpu: add wb_idx to existing DRM prints in dpu_encoder
  drm/msm/dpu: add wb_idx to DRM traces in dpu_encoder

 .../drm/arm/display/komeda/komeda_wb_connector.c   |   4 +-
 drivers/gpu/drm/arm/malidp_mw.c|   4 +-
 drivers/gpu/drm/drm_writeback.c|  79 ++-
 drivers/gpu/drm/msm/Makefile   |   3 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |   9 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 306 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  22 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  50 ++
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 763 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  72 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  66 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |  82 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  21 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c|   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h|  18 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c|  25 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  19 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c  | 279 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h  | 115 
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  66 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  31 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  22 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  12 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h  |  26 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c  |  68 ++

[PATCH v4 01/20] drm: allow passing possible_crtcs to drm_writeback_connector_init()

Clients of drm_writeback_connector_init() initialize the
possible_crtcs and then invoke the call to this API.

To simplify things, allow passing possible_crtcs as a parameter
to drm_writeback_connector_init() and make changes to the
other drm drivers to make them compatible with this change.

changes in v2:
- split the changes according to their functionality

changes in v3:
- allow passing possible_crtcs for existing users of
  drm_writeback_connector_init()
- squash the vendor changes into the same commit so
  that each patch in the series can compile individually

changes in v4:
- keep only changes related to possible_crtcs
- add line breaks after ARRAY_SIZE
- stop using temporary variables for possible_crtcs

changes in v5:
- None

changes in v6:
- None

changes in v7:
- wrap long lines to match the coding style of existing drivers
- Fix indentation and remove parenthesis where not needed
- use u32 instead of uint32_t for possible_crtcs

Signed-off-by: Abhinav Kumar 
Acked-by: Liviu Dudau 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c | 4 ++--
 drivers/gpu/drm/arm/malidp_mw.c  | 4 ++--
 drivers/gpu/drm/drm_writeback.c  | 7 ++-
 drivers/gpu/drm/rcar-du/rcar_du_writeback.c  | 4 ++--
 drivers/gpu/drm/vc4/vc4_txp.c| 3 ++-
 drivers/gpu/drm/vkms/vkms_writeback.c| 4 ++--
 include/drm/drm_writeback.h  | 3 ++-
 7 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c 
b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
index e465cc4..ce4b760 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
@@ -155,7 +155,6 @@ static int komeda_wb_connector_add(struct komeda_kms_dev 
*kms,
kwb_conn->wb_layer = kcrtc->master->wb_layer;
 
wb_conn = _conn->base;
-   wb_conn->encoder.possible_crtcs = BIT(drm_crtc_index(>base));
 
formats = komeda_get_layer_fourcc_list(>fmt_tbl,
   kwb_conn->wb_layer->layer_type,
@@ -164,7 +163,8 @@ static int komeda_wb_connector_add(struct komeda_kms_dev 
*kms,
err = drm_writeback_connector_init(>base, wb_conn,
   _wb_connector_funcs,
   _wb_encoder_helper_funcs,
-  formats, n_formats);
+  formats, n_formats,
+  BIT(drm_crtc_index(>base)));
komeda_put_fourcc_list(formats);
if (err) {
kfree(kwb_conn);
diff --git a/drivers/gpu/drm/arm/malidp_mw.c b/drivers/gpu/drm/arm/malidp_mw.c
index f5847a7..204c869 100644
--- a/drivers/gpu/drm/arm/malidp_mw.c
+++ b/drivers/gpu/drm/arm/malidp_mw.c
@@ -212,7 +212,6 @@ int malidp_mw_connector_init(struct drm_device *drm)
if (!malidp->dev->hw->enable_memwrite)
return 0;
 
-   malidp->mw_connector.encoder.possible_crtcs = 1 << 
drm_crtc_index(>crtc);
drm_connector_helper_add(>mw_connector.base,
 _mw_connector_helper_funcs);
 
@@ -223,7 +222,8 @@ int malidp_mw_connector_init(struct drm_device *drm)
ret = drm_writeback_connector_init(drm, >mw_connector,
   _mw_connector_funcs,
   _mw_encoder_helper_funcs,
-  formats, n_formats);
+  formats, n_formats,
+  1 << drm_crtc_index(>crtc));
kfree(formats);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/drm_writeback.c b/drivers/gpu/drm/drm_writeback.c
index dccf4504..9e0b845 100644
--- a/drivers/gpu/drm/drm_writeback.c
+++ b/drivers/gpu/drm/drm_writeback.c
@@ -157,6 +157,7 @@ static const struct drm_encoder_funcs 
drm_writeback_encoder_funcs = {
  * @enc_helper_funcs: Encoder helper funcs vtable to be used by the internal 
encoder
  * @formats: Array of supported pixel formats for the writeback engine
  * @n_formats: Length of the formats array
+ * @possible_crtcs: possible crtcs for the internal writeback encoder
  *
  * This function creates the writeback-connector-specific properties if they
  * have not been already created, initializes the connector as
@@ -174,7 +175,8 @@ int drm_writeback_connector_init(struct drm_device *dev,
 struct drm_writeback_connector *wb_connector,
 const struct drm_connector_funcs *con_funcs,
 const struct drm_encoder_helper_funcs 
*enc_helper_funcs,
-

Re: [PATCH 37/48] ARM: pxa: move smemc register access from clk to platform

Quoting Arnd Bergmann (2022-04-19 09:37:59)
> From: Arnd Bergmann 
> 
> The get_sdram_rows() and get_memclkdiv() helpers need smemc
> register that are separate from the clk registers, move
> them out of the clk driver, and use an extern declaration
> instead.
> 
> Cc: Michael Turquette 
> Cc: Stephen Boyd 
> Cc: linux-...@vger.kernel.org
> Link: https://lore.kernel.org/lkml/87pnielzo4@belgarion.home/
> Signed-off-by: Arnd Bergmann 
> ---

Acked-by: Stephen Boyd

Re: [PATCH 36/48] cpufreq: pxa3: move clk register access to clk driver

Quoting Arnd Bergmann (2022-04-19 09:37:58)
> diff --git a/include/linux/clk/pxa.h b/include/linux/clk/pxa.h
> new file mode 100644
> index ..e5516c608c99
> --- /dev/null
> +++ b/include/linux/clk/pxa.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifdef CONFIG_PXA3xx
> +extern unsignedpxa3xx_get_clk_frequency_khz(int);

What is the spacing about here?

> +extern void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 
> mask);
> +#else
> +#define pxa3xx_get_clk_frequency_khz(x)(0)
> +#define pxa3xx_clk_update_accr(disable, enable, xclkcfg, mask) do { } while 
> (0)

Why not static inline with types?

Re: [PATCH] drm: msm: fix error check return value of irq_of_parse_and_map()


On 22/04/2022 13:42, Dmitry Baryshkov wrote:

On Fri, 22 Apr 2022 at 11:52,  wrote:


From: Lv Ruyi 

The irq_of_parse_and_map() function returns 0 on failure, and does not
return an negative value.

Reported-by: Zeal Robot 
Signed-off-by: Lv Ruyi 


Reviewed-by: Dmitry Baryshkov 


---
  drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 3b92372e7bdf..1fb1ed9e95d9 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -570,7 +570,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
 }

 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
-   if (irq < 0) {
+   if (!irq) {
 ret = irq;


As noted by Stephen, this will cause the function to prematurely return 
0 (success).



 DRM_DEV_ERROR(>dev, "failed to get irq: %d\n", ret);
 goto fail;
--
2.25.1







--
With best wishes
Dmitry

Re: [PATCH] drm/msm/dp: fix error check return value of irq_of_parse_and_map()


On 22/04/2022 21:39, Stephen Boyd wrote:

Quoting cgel@gmail.com (2022-04-22 01:49:51)

From: Lv Ruyi 

The irq_of_parse_and_map() function returns 0 on failure, and does not
return an negative value.

Fixes:  8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon 
Chipsets")
Reported-by: Zeal Robot 
Signed-off-by: Lv Ruyi 
---
  drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index a42732b67349..3926d2ac107d 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1239,7 +1239,7 @@ int dp_display_request_irq(struct msm_dp *dp_display)
 dp = container_of(dp_display, struct dp_display_private, dp_display);

 dp->irq = irq_of_parse_and_map(dp->pdev->dev.of_node, 0);


Why can't platform_get_irq() be used?


-   if (dp->irq < 0) {
+   if (!dp->irq) {
 rc = dp->irq;


zero as an error return value is an error?


Hmm, nice catch. Please fix it. And the other patch too.




 DRM_ERROR("failed to get irq: %d\n", rc);
 return rc;



--
With best wishes
Dmitry

[PATCH v3 2/2] drm/msm/dp: Implement oob_hotplug_event()

2022-04-22 Thread Bjorn Andersson

The Qualcomm DisplayPort driver contains traces of the necessary
plumbing to hook up USB HPD, in the form of the dp_hpd module and the
dp_usbpd_cb struct. Use this as basis for implementing the
oob_hotplug_event() callback, by amending the dp_hpd module with the
missing logic.

Overall the solution is similar to what's done downstream, but upstream
all the code to disect the HPD notification lives on the calling side of
drm_connector_oob_hotplug_event().

drm_connector_oob_hotplug_event() performs the lookup of the
drm_connector based on fwnode, hence the need to assign the fwnode in
dp_drm_connector_init().

Signed-off-by: Bjorn Andersson 
---

Changes since v2:
- Rebased patch

 drivers/gpu/drm/msm/dp/dp_display.c |  9 +
 drivers/gpu/drm/msm/dp/dp_display.h |  3 +++
 drivers/gpu/drm/msm/dp/dp_drm.c | 11 +++
 drivers/gpu/drm/msm/dp/dp_hpd.c | 21 +
 drivers/gpu/drm/msm/dp/dp_hpd.h |  5 +
 5 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
b/drivers/gpu/drm/msm/dp/dp_display.c
index a42732b67349..1019f6d8fd03 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -449,6 +449,14 @@ static int dp_display_usbpd_configure_cb(struct device 
*dev)
return dp_display_process_hpd_high(dp);
 }
 
+void dp_display_oob_hotplug_event(struct msm_dp *dp_display,
+ enum drm_connector_hpd_state hpd_state)
+{
+   struct dp_display_private *dp = container_of(dp_display, struct 
dp_display_private, dp_display);
+
+   dp->usbpd->oob_event(dp->usbpd, hpd_state);
+}
+
 static int dp_display_usbpd_disconnect_cb(struct device *dev)
 {
struct dp_display_private *dp = dev_get_dp_display_private(dev);
@@ -1302,6 +1310,7 @@ static int dp_display_probe(struct platform_device *pdev)
dp->pdev = pdev;
dp->name = "drm_dp";
dp->dp_display.connector_type = desc->connector_type;
+   dp->dp_display.dev = >dev;
 
rc = dp_init_sub_modules(dp);
if (rc) {
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h 
b/drivers/gpu/drm/msm/dp/dp_display.h
index 7af2b186d2d9..16658270df2c 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -11,6 +11,7 @@
 #include "disp/msm_disp_snapshot.h"
 
 struct msm_dp {
+   struct device *dev;
struct drm_device *drm_dev;
struct device *codec_dev;
struct drm_bridge *bridge;
@@ -40,5 +41,7 @@ bool dp_display_check_video_test(struct msm_dp *dp_display);
 int dp_display_get_test_bpp(struct msm_dp *dp_display);
 void dp_display_signal_audio_start(struct msm_dp *dp_display);
 void dp_display_signal_audio_complete(struct msm_dp *dp_display);
+void dp_display_oob_hotplug_event(struct msm_dp *dp_display,
+ enum drm_connector_hpd_state hpd_state);
 
 #endif /* _DP_DISPLAY_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 80f59cf99089..76904b1601b1 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -123,6 +123,14 @@ static enum drm_mode_status dp_connector_mode_valid(
return dp_display_validate_mode(dp_disp, mode->clock);
 }
 
+static void dp_oob_hotplug_event(struct drm_connector *connector,
+enum drm_connector_hpd_state hpd_state)
+{
+   struct msm_dp *dp_disp = to_dp_connector(connector)->dp_display;
+
+   dp_display_oob_hotplug_event(dp_disp, hpd_state);
+}
+
 static const struct drm_connector_funcs dp_connector_funcs = {
.detect = dp_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
@@ -130,6 +138,7 @@ static const struct drm_connector_funcs dp_connector_funcs 
= {
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+   .oob_hotplug_event = dp_oob_hotplug_event,
 };
 
 static const struct drm_connector_helper_funcs dp_connector_helper_funcs = {
@@ -160,6 +169,8 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp 
*dp_display)
if (ret)
return ERR_PTR(ret);
 
+   connector->fwnode = fwnode_handle_get(dev_fwnode(dp_display->dev));
+
drm_connector_helper_add(connector, _connector_helper_funcs);
 
/*
diff --git a/drivers/gpu/drm/msm/dp/dp_hpd.c b/drivers/gpu/drm/msm/dp/dp_hpd.c
index db98a1d431eb..cdb1feea5ebf 100644
--- a/drivers/gpu/drm/msm/dp/dp_hpd.c
+++ b/drivers/gpu/drm/msm/dp/dp_hpd.c
@@ -7,6 +7,8 @@
 
 #include 
 #include 
+#include 
+#include 
 
 #include "dp_hpd.h"
 
@@ -45,6 +47,24 @@ int dp_hpd_connect(struct dp_usbpd *dp_usbpd, bool hpd)
return rc;
 }
 
+static void dp_hpd_oob_event(struct dp_usbpd *dp_usbpd,
+enum drm_connector_hpd_state hpd_state)
+{
+   struct dp_hpd_private *hpd_priv =

[PATCH v3 1/2] drm: Add HPD state to drm_connector_oob_hotplug_event()

2022-04-22 Thread Bjorn Andersson

In some implementations, such as the Qualcomm platforms, the display
driver has no way to query the current HPD state and as such it's
impossible to distinguish between disconnect and attention events.

Add a parameter to drm_connector_oob_hotplug_event() to pass the HPD
state.

Also push the test for unchanged state in the displayport altmode driver
into the i915 driver, to allow other drivers to act upon each update.

Signed-off-by: Bjorn Andersson 
---

Changs since v2:
- The i915 cached hpd_state is tracked per encoder.

 drivers/gpu/drm/drm_connector.c  |  6 --
 drivers/gpu/drm/i915/display/intel_dp.c  | 17 ++---
 drivers/gpu/drm/i915/i915_drv.h  |  3 +++
 drivers/usb/typec/altmodes/displayport.c | 10 +++---
 include/drm/drm_connector.h  | 11 +--
 5 files changed, 33 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 76a8c707c34b..fff8c74d1ae6 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -2828,6 +2828,7 @@ struct drm_connector *drm_connector_find_by_fwnode(struct 
fwnode_handle *fwnode)
 /**
  * drm_connector_oob_hotplug_event - Report out-of-band hotplug event to 
connector
  * @connector_fwnode: fwnode_handle to report the event on
+ * @hpd_state: hot plug detect logical state
  *
  * On some hardware a hotplug event notification may come from outside the 
display
  * driver / device. An example of this is some USB Type-C setups where the 
hardware
@@ -2837,7 +2838,8 @@ struct drm_connector *drm_connector_find_by_fwnode(struct 
fwnode_handle *fwnode)
  * This function can be used to report these out-of-band events after obtaining
  * a drm_connector reference through calling drm_connector_find_by_fwnode().
  */
-void drm_connector_oob_hotplug_event(struct fwnode_handle *connector_fwnode)
+void drm_connector_oob_hotplug_event(struct fwnode_handle *connector_fwnode,
+enum drm_connector_hpd_state hpd_state)
 {
struct drm_connector *connector;
 
@@ -2846,7 +2848,7 @@ void drm_connector_oob_hotplug_event(struct fwnode_handle 
*connector_fwnode)
return;
 
if (connector->funcs->oob_hotplug_event)
-   connector->funcs->oob_hotplug_event(connector);
+   connector->funcs->oob_hotplug_event(connector, hpd_state);
 
drm_connector_put(connector);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index d55acc4a028a..2907d8e1f80e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4950,15 +4950,26 @@ static int intel_dp_connector_atomic_check(struct 
drm_connector *conn,
return intel_modeset_synced_crtcs(state, conn);
 }
 
-static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
+static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
+  enum drm_connector_hpd_state hpd_state)
 {
struct intel_encoder *encoder = 
intel_attached_encoder(to_intel_connector(connector));
struct drm_i915_private *i915 = to_i915(connector->dev);
+   bool hpd_high = hpd_state == DRM_CONNECTOR_HPD_HIGH;
+   unsigned int hpd_pin = encoder->hpd_pin;
+   bool need_work = false;
 
spin_lock_irq(>irq_lock);
-   i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
+   if (hpd_high != test_bit(hpd_pin, 
>hotplug.oob_hotplug_last_state)) {
+   i915->hotplug.event_bits |= BIT(hpd_pin);
+
+   __assign_bit(hpd_pin, >hotplug.oob_hotplug_last_state, 
hpd_high);
+   need_work = true;
+   }
spin_unlock_irq(>irq_lock);
-   queue_delayed_work(system_wq, >hotplug.hotplug_work, 0);
+
+   if (need_work)
+   queue_delayed_work(system_wq, >hotplug.hotplug_work, 0);
 }
 
 static const struct drm_connector_funcs intel_dp_connector_funcs = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3711d618a372..71d0c7130ddd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -134,6 +134,9 @@ struct i915_hotplug {
/* Whether or not to count short HPD IRQs in HPD storms */
u8 hpd_short_storm_enabled;
 
+   /* Last state reported by oob_hotplug_event for each encoder */
+   unsigned long oob_hotplug_last_state;
+
/*
 * if we get a HPD irq from DP and a HPD irq from non-DP
 * the non-DP HPD could block the workqueue on a mode config
diff --git a/drivers/usb/typec/altmodes/displayport.c 
b/drivers/usb/typec/altmodes/displayport.c
index c1d8c23baa39..ea9cb1d71fd2 100644
--- a/drivers/usb/typec/altmodes/displayport.c
+++ b/drivers/usb/typec/altmodes/displayport.c
@@ -59,7 +59,6 @@ struct dp_altmode {
struct typec_displayport_data data;
 
enum dp_state state;
-   bool hpd;
 
struct mutex lock; /*

Re: [PATCH v2 1/3] drm/msm/dpu: introduce a wb_idx to be used for writeback interfaces


On 22/04/2022 22:45, Abhinav Kumar wrote:

Using intf_idx even for writeback interfaces is confusing
because intf_idx is of type enum dpu_intf but the index used
for writeback is of type enum dpu_wb.

In addition, this makes it easier to separately check the
availability of the two as its possible that there are boards
which don't have any physical display connected but can still
work in writeback mode.

changes in v2:
- add check for invalid phys having both intf and wb
- merge the next change of using wb_idx in phys_wb

Signed-off-by: Abhinav Kumar 


Reviewed-by: Dmitry Baryshkov 


---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 68 +-
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  4 ++
  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 10 ++--
  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 +-
  4 files changed, 51 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c12841..9ae9bd4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -962,7 +962,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
int num_lm, num_ctl, num_pp, num_dsc;
unsigned int dsc_mask = 0;
-   enum dpu_hw_blk_type blk_type;
int i;
  
  	if (!drm_enc) {

@@ -1044,17 +1043,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
phys->hw_pp = dpu_enc->hw_pp[i];
phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
  
-		if (dpu_encoder_get_intf_mode(_enc->base) == INTF_MODE_WB_LINE)

-   blk_type = DPU_HW_BLK_WB;
-   else
-   blk_type = DPU_HW_BLK_INTF;
+   if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
+   phys->hw_intf = dpu_rm_get_intf(_kms->rm, 
phys->intf_idx);
  
-		if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) {

-   if (blk_type == DPU_HW_BLK_INTF)
-   phys->hw_intf = dpu_rm_get_intf(_kms->rm, 
phys->intf_idx);
-   else if (blk_type == DPU_HW_BLK_WB)
-   phys->hw_wb = dpu_rm_get_wb(_kms->rm, 
phys->intf_idx);
-   }
+   if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
+   phys->hw_wb = dpu_rm_get_wb(_kms->rm, phys->wb_idx);
  
  		if (!phys->hw_intf && !phys->hw_wb) {

DPU_ERROR_ENC(dpu_enc,
@@ -1062,6 +1055,12 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
return;
}
  
+		if (phys->hw_intf && phys->hw_wb) {

+   DPU_ERROR_ENC(dpu_enc,
+   "invalid phys both intf and wb block at idx: 
%d\n", i);
+   return;
+   }
+
phys->cached_mode = crtc_state->adjusted_mode;
if (phys->ops.atomic_mode_set)
phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
@@ -1201,7 +1200,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
mutex_unlock(_enc->enc_lock);
  }
  
-static enum dpu_intf dpu_encoder_get_intf_or_wb(struct dpu_mdss_cfg *catalog,

+static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
enum dpu_intf_type type, u32 controller_id)
  {
int i = 0;
@@ -1213,16 +1212,28 @@ static enum dpu_intf dpu_encoder_get_intf_or_wb(struct 
dpu_mdss_cfg *catalog,
return catalog->intf[i].id;
}
}
-   } else {
-   for (i = 0; i < catalog->wb_count; i++) {
-   if (catalog->wb[i].id == controller_id)
-   return catalog->wb[i].id;
-   }
}
  
  	return INTF_MAX;

  }
  
+static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,

+   enum dpu_intf_type type, u32 controller_id)
+{
+   int i = 0;
+
+   if (type != INTF_WB)
+   goto end;
+
+   for (i = 0; i < catalog->wb_count; i++) {
+   if (catalog->wb[i].id == controller_id)
+   return catalog->wb[i].id;
+   }
+
+end:
+   return WB_MAX;
+}
+
  static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
struct dpu_encoder_phys *phy_enc)
  {
@@ -2249,18 +2260,21 @@ static int dpu_encoder_setup_display(struct 
dpu_encoder_virt *dpu_enc,
DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
i, controller_id, phys_params.split_role);
  
-		/*

-* FIXME: have separate intf_idx and wb_idx to avoid using
-* enum dpu_intf type for wb_idx and also to be

Re: [PATCH v2 00/48] ARM: PXA multiplatform support

2022-04-22 Thread Arnd Bergmann

On Fri, Apr 22, 2022 at 10:55 PM Guenter Roeck  wrote:
> On 4/22/22 12:16, Arnd Bergmann wrote:
> > On Fri, Apr 22, 2022 at 7:05 PM Guenter Roeck  wrote:
> >
> > Which machine did you hit this on? Is this on hardware or in qemu?
> >
> qemu, as always. borzoi, spitz, terrier, tosa, z2, and sx1 fail.
> Also, I just noticed that the failure is not always the same.
> z2 fails to boot from initrd, and sx1 fails to boot completely.

That's a lot of machines failing, I hope at least we got the same bugs more
than once here.

For the I/O space, I found now that PXA was not using the standard
virtual I/O address yet, but instead used a NULL-based offset.

I'm not entirely happy with this patch, but this is an outline of what
I think we need to fix that: https://pastebin.com/3nVgQsEw
This one is probably incomplete, at least it breaks sa1100 for now,
and it adds a bogus CONFIG_PCI dependency. I'm also not sure
in what way the last patch in the series triggers it, rather than the
one that removed mach/io.h.

I had sx1 booting in qemu at least, with the omap1 multiplatform series only.
If you have a custom config for this one, make sure you get the right
DEBUG_LL address.

> I'll do another round of bisects.

Thanks!

   Arnd

Re: [PATCH] drm/virtio: Add execbuf flag to request no fence-event

2022-04-22 Thread Rob Clark

On Tue, Apr 5, 2022 at 10:57 AM Chia-I Wu  wrote:
>
> On Tue, Apr 5, 2022 at 10:38 AM Rob Clark  wrote:
> >
> > From: Rob Clark 
> >
> > It would have been cleaner to have a flag to *request* the fence event.
> > But that ship has sailed.  So add a flag so that userspace which doesn't
> > care about the events can opt-out.
> >
> > Signed-off-by: Rob Clark 
> Reviewed-by: Chia-I Wu 
>
> Might want to wait for Gurchetan to chime in as he added the mechanism.

It turns out this patch is unnecessary.. I can simply not set
VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK instead

so self-nak for this patch ;-)

BR,
-R

> > ---
> >  drivers/gpu/drm/virtio/virtgpu_ioctl.c | 8 +---
> >  include/uapi/drm/virtgpu_drm.h | 2 ++
> >  2 files changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c 
> > b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> > index 3a8078f2ee27..09f1aa263f91 100644
> > --- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> > +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
> > @@ -225,9 +225,11 @@ static int virtio_gpu_execbuffer_ioctl(struct 
> > drm_device *dev, void *data,
> > goto out_unresv;
> > }
> >
> > -   ret = virtio_gpu_fence_event_create(dev, file, out_fence, ring_idx);
> > -   if (ret)
> > -   goto out_unresv;
> > +   if (!(exbuf->flags & VIRTGPU_EXECBUF_NO_EVENT)) {
> > +   ret = virtio_gpu_fence_event_create(dev, file, out_fence, 
> > ring_idx);
> > +   if (ret)
> > +   goto out_unresv;
> > +   }
> >
> > if (out_fence_fd >= 0) {
> > sync_file = sync_file_create(_fence->f);
> > diff --git a/include/uapi/drm/virtgpu_drm.h b/include/uapi/drm/virtgpu_drm.h
> > index 0512fde5e697..d06cac3407cc 100644
> > --- a/include/uapi/drm/virtgpu_drm.h
> > +++ b/include/uapi/drm/virtgpu_drm.h
> > @@ -52,10 +52,12 @@ extern "C" {
> >  #define VIRTGPU_EXECBUF_FENCE_FD_IN0x01
> >  #define VIRTGPU_EXECBUF_FENCE_FD_OUT   0x02
> >  #define VIRTGPU_EXECBUF_RING_IDX   0x04
> > +#define VIRTGPU_EXECBUF_NO_EVENT   0x08
> >  #define VIRTGPU_EXECBUF_FLAGS  (\
> > VIRTGPU_EXECBUF_FENCE_FD_IN |\
> > VIRTGPU_EXECBUF_FENCE_FD_OUT |\
> > VIRTGPU_EXECBUF_RING_IDX |\
> > +   VIRTGPU_EXECBUF_NO_EVENT |\
> > 0)
> >
> >  struct drm_virtgpu_map {
> > --
> > 2.35.1
> >

Re: [PATCH v2 3/7] vfio/mdev: Pass in a struct vfio_device * to vfio_pin/unpin_pages()

On Fri, Apr 22, 2022 at 08:22:32AM +0200, Christoph Hellwig wrote:
> Nit: why do some of these patches that don't touch the mdev code
> mdev in the subject?

I consider these APIs to be 'mdev apis' because only mdev drivers
should call them.

Jason

Re: [PATCH v2 00/48] ARM: PXA multiplatform support


On 4/22/22 12:16, Arnd Bergmann wrote:

On Fri, Apr 22, 2022 at 7:05 PM Guenter Roeck  wrote:


On Tue, Apr 19, 2022 at 06:37:22PM +0200, Arnd Bergmann wrote:

From: Arnd Bergmann 

This revisits a series I sent a few years ago:

https://lore.kernel.org/lkml/20191018154052.1276506-1-a...@arndb.de/

All the other ARMv5 conversions are under way now, with
OMAP1 being the only one still not in linux-next yet,
and PXA completing the set.

Most of the patches are unchanged from before, furtunately
the PXA code is fairly stable. I addressed Robert's comments,
pulled in two patches from Dmitry, and added the last a the
final four patches to finish off the multiplatform conversion.

I hope someone is left to test these on PXA: if this works,
I'd like to merge it for 5.19. A git tree with these is avaialable
for testing at

https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=pxa-multiplatform-5.18



Unfortunately that crashes for me when trying to boot from ide.
Bisect points to the last patch of the series.


Thanks a lot for testing and the perfect bug report!


[1.403715] 8<--- cut here ---
[1.403848] Unable to handle kernel paging request at virtual address 
feeb000e
[1.404097] [feeb000e] *pgd=


Ok, this is the PCI I/O space area, which starts at 0xfee0,
clearly the way I/O space
gets mapped changed here. I don't yet see what happened, but it should
be straightforward
to find from here.


[1.416643]  pcmcia_init_one from pcmcia_device_probe+0xe4/0x2a0
[1.416882]  pcmcia_device_probe from really_probe+0xc8/0x3b4
[1.417070]  really_probe from __driver_probe_device+0x9c/0x214
[1.417255]  __driver_probe_device from driver_probe_device+0x38/0xe0
[1.417454]  driver_probe_device from __device_attach_driver+0xa4/0x11c
[1.417657]  __device_attach_driver from bus_for_each_drv+0x88/0xd8
[1.417864]  bus_for_each_drv from __device_attach+0xf4/0x194
[1.418047]  __device_attach from bus_probe_device+0x8c/0x94
[1.418224]  bus_probe_device from device_add+0x3d0/0x894
[1.418395]  device_add from pcmcia_device_add+0x2ec/0x3e0
[1.418568]  pcmcia_device_add from pcmcia_card_add+0xd4/0x1a0
[1.418756]  pcmcia_card_add from pcmcia_bus_add+0x44/0x4c
[1.418930]  pcmcia_bus_add from socket_insert+0x12c/0x150
[1.419103]  socket_insert from pccardd+0x398/0x44c
[1.419257]  pccardd from kthread+0xdc/0x114
[1.419400]  kthread from ret_from_fork+0x14/0x2c
[1.419569] Exception stack(0xc48a5fb0 to 0xc48a5ff8)
[1.419735] 5fa0:   
 
[1.419979] 5fc0:       
 
[1.420222] 5fe0:     0013 
[1.420501] Code: 1357 e1a06000 0a43 e3a03002 (e5c03000)
[1.420874] ---[ end trace  ]---

---
# bad: [7643a9ca9f8e08f71e15f89dd74863635e981e03] ARM: pxa: convert to 
multiplatform
# good: [3123109284176b1532874591f7c81f3837bbdc17] Linux 5.18-rc1
git bisect start 'HEAD' 'v5.18-rc1'
# good: [9b03d7f95bd4d97101ecb8ea1e822103b81fdb2d] ARM: pxa: mainstone-wm97xx: 
use gpio lookup table
git bisect good 9b03d7f95bd4d97101ecb8ea1e822103b81fdb2d
# good: [764063eee7620ea9abb940068a7ad0e7f9efa1b6] cpufreq: pxa3: move clk 
register access to clk driver
git bisect good 764063eee7620ea9abb940068a7ad0e7f9efa1b6
# good: [5153474f0a4388b7ddb59add4be73bfb42b2007f] ARM: mmp: remove tavorevb 
board support
git bisect good 5153474f0a4388b7ddb59add4be73bfb42b2007f
# good: [2746f7c78b428c8b01b691a29a972c08101ae343] ARM: PXA: fix multi-cpu 
build of xsc3
git bisect good 2746f7c78b428c8b01b691a29a972c08101ae343
# good: [73d5106e9489464eac84362705e93bcf3b376123] ARM: pxa: remove support for 
MTD_XIP
git bisect good 73d5106e9489464eac84362705e93bcf3b376123
# first bad commit: [7643a9ca9f8e08f71e15f89dd74863635e981e03] ARM: pxa: 
convert to multiplatform


I'll back out this patch for now while investigating further.

Which machine did you hit this on? Is this on hardware or in qemu?


qemu, as always. borzoi, spitz, terrier, tosa, z2, and sx1 fail.
Also, I just noticed that the failure is not always the same.
z2 fails to boot from initrd, and sx1 fails to boot completely.
I'll do another round of bisects.

Guenter


Arnd

Re: [PATCH v2 7/7] vfio: Remove calls to vfio_group_add_container_user()

On Fri, Apr 22, 2022 at 02:11:27AM +, Tian, Kevin wrote:

> > mutex_lock(>dev_set->lock);
> > -   if (!--device->open_count && device->ops->close_device)
> > +   vfio_assert_device_open(device);
> > +   if (device->open_count == 1 && device->ops->close_device)
> > device->ops->close_device(device);
> > +   device->open_count--;
> > mutex_unlock(>dev_set->lock);
> 
> Is it necessary to add assertion here? This is the only place to
> decrement the counter and no similar assertion in other release()/
> put() functions.

Necessary, no, but since we have it we may as well check it here. It
is common to check that refcounts don't underflow.

Jason

Re: [PATCH 0/1] add support for enum module parameters

2022-04-22 Thread Jakub Kicinski

On Wed, 20 Apr 2022 08:13:47 +0300 Kalle Valo wrote:
> Wireless drivers would also desperately need to pass device specific
> parameters at (or before) probe time. And not only debug parameters but
> also configuration parameters, for example firmware memory allocations
> schemes (optimise for features vs number of clients etc) and whatnot.
> 
> Any ideas how to implement that? Is there any prior work for anything
> like this? This is pretty hard limiting usability of upstream wireless
> drivers and I really want to find a proper solution.

In netdev we have devlink which is used for all sort of device
configuration. devlink-resource sounds like what you need,
but it'd have to be extended to support configuration which requires
reload/re-probe. Currently only devlink-params support that but params
were a mistake so don't use that.

[PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines

2022-04-22 Thread Matt Roper

From: Daniele Ceraolo Spurio 

Cc: Vinay Belgaumkar 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Matt Roper 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/i915_pci.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b60492826478..7739d6c33481 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = {
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
-   BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+   BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+   BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
.require_force_probe = 1,
 };
 
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = {
.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
-   BIT(VCS0) | BIT(VCS2)
+   BIT(VCS0) | BIT(VCS2) | \
+   BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
 
 static const struct intel_device_info dg2_info = {
DG2_FEATURES,
-- 
2.35.1

[PATCH 1/2] drm/i915/xehp: Add compute engine ABI

2022-04-22 Thread Matt Roper

We're now ready to start exposing compute engines to userspace.

While we're at it, let's extend the kerneldoc description for the other
engine types as well.

Cc: Daniele Ceraolo Spurio 
Cc: Tvrtko Ursulin 
Cc: Vinay Belgaumkar 
Cc: Jordan Justen 
Cc: Szymon Morek 
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_engine_user.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c  |  1 +
 drivers/gpu/drm/i915/i915_drm_client.c  |  1 +
 drivers/gpu/drm/i915/i915_drm_client.h  |  2 +-
 include/uapi/drm/i915_drm.h | 62 +++--
 5 files changed, 60 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c 
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 0f6cd96b459f..46a174f8aa00 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
-   /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
+   [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
 };
 
 static int engine_cmp(void *priv, const struct list_head *A,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 92394f13b42f..c96e123496a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
[VIDEO_DECODE_CLASS]= GEN12_VD_TLB_INV_CR,
[VIDEO_ENHANCEMENT_CLASS]   = GEN12_VE_TLB_INV_CR,
[COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
+   [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
};
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c 
b/drivers/gpu/drm/i915/i915_drm_client.c
index 475a6f824cad..18d38cb59923 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_COPY] = "copy",
[I915_ENGINE_CLASS_VIDEO] = "video",
[I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+   [I915_ENGINE_CLASS_COMPUTE] = "compute",
 };
 
 static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h 
b/drivers/gpu/drm/i915/i915_drm_client.h
index 5f5b02b01ba0..f796c5e8e060 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -13,7 +13,7 @@
 
 #include "gt/intel_engine_types.h"
 
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
+#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
 
 struct drm_i915_private;
 
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 35ca528803fd..a2def7b27009 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -154,21 +154,71 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
 };
 
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
  * Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role.  This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
  */
 enum drm_i915_gem_engine_class {
+   /**
+* @I915_ENGINE_CLASS_RENDER:
+*
+* Render engines support instructions used for 3D, Compute (GPGPU),
+* and programmable media workloads.  These instructions fetch data and
+* dispatch individual work items to threads that operate in parallel.
+* The threads run small programs (called "kernels" or "shaders") on
+* the GPU's execution units (EUs).
+*/
I915_ENGINE_CLASS_RENDER= 0,
+
+   /**
+* @I915_ENGINE_CLASS_COPY:
+*
+* Copy engines (also referred to as "blitters") support instructions
+* that move blocks of data from one location in memory to another,
+* or that fill a specified location of memory with fixed data.
+* Copy engines can perform pre-defined logical or bitwise operations
+* on the source, destination, or pattern data.
+

[PATCH 0/2] i915: Turn on compute engine support

2022-04-22 Thread Matt Roper

Now that the necessary GuC-based hardware workarounds have landed, we're
finally ready to actually enable compute engines for use by userspace.
All of the "under-the-hood" heavy lifting already landed a while back in
other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE
to the uapi enum and add the CCS engines to the engine lists for the
Xe_HP SDV and DG2.

Userspace (both Mesa and compute drivers) are linked in the ABI patch.
Existing IGT tests (e.g., i915_hangman) provide test coverage for
general engine behavior since compute engines should follow the same
general rules as other engines.  We've also recently added some
additional subtests like igt@gem_reset_stats@shared-reset-domain to
cover the user-visible impacts of the compute engines sharing the same
hardware reset domain as the render engine.

Cc: Lucas De Marchi 

Daniele Ceraolo Spurio (1):
  drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines

Matt Roper (1):
  drm/i915/xehp: Add compute engine ABI

 drivers/gpu/drm/i915/gt/intel_engine_user.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c  |  1 +
 drivers/gpu/drm/i915/i915_drm_client.c  |  1 +
 drivers/gpu/drm/i915/i915_drm_client.h  |  2 +-
 drivers/gpu/drm/i915/i915_pci.c |  6 +-
 include/uapi/drm/i915_drm.h | 62 +++--
 6 files changed, 64 insertions(+), 10 deletions(-)

-- 
2.35.1

[PATCH] drm/tilcdc: fix typos in comment

2022-04-22 Thread brookxu.cn

From: Chunguang Xu 

Fix typos in comment.

Signed-off-by: Chunguang Xu 
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c 
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 29890d7..b986946 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -996,7 +996,7 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
if (stat & LCDC_FRAME_DONE) {
tilcdc_crtc->frame_done = true;
wake_up(_crtc->frame_done_wq);
-   /* rev 1 lcdc appears to hang if irq is not disbaled here */
+   /* rev 1 lcdc appears to hang if irq is not disabled here */
if (priv->rev == 1)
tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
 LCDC_V1_FRAME_DONE_INT_ENA);
-- 
1.8.3.1

[PATCH v2 3/3] drm/msm/dpu: add wb_idx to DRM traces in dpu_encoder

Change the DRM traces to include both the intf_mode
and wb_idx similar to the DRM prints in the previous change.

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h   | 26 ++
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 7bd20fa..8255c46 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1353,8 +1353,9 @@ static void dpu_encoder_frame_done_callback(
 * suppress frame_done without waiter,
 * likely autorefresh
 */
-   trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc),
-   event, ready_phys->intf_idx);
+   trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), 
event,
+   
dpu_encoder_helper_get_intf_type(ready_phys->intf_mode),
+   ready_phys->intf_idx, 
ready_phys->wb_idx);
return;
}
 
@@ -1432,9 +1433,11 @@ static void _dpu_encoder_trigger_flush(struct 
drm_encoder *drm_enc,
if (ctl->ops.get_pending_flush)
ret = ctl->ops.get_pending_flush(ctl);
 
-   trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx,
-   pending_kickoff_cnt, ctl->idx,
-   extra_flush_bits, ret);
+   trace_dpu_enc_trigger_flush(DRMID(drm_enc),
+   dpu_encoder_helper_get_intf_type(phys->intf_mode),
+   phys->intf_idx, phys->wb_idx,
+   pending_kickoff_cnt, ctl->idx,
+   extra_flush_bits, ret);
 }
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index 58b411f..1106d44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -380,20 +380,26 @@ TRACE_EVENT(dpu_enc_rc,
 );
 
 TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
-   TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx),
-   TP_ARGS(drm_id, event, intf_idx),
+   TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf 
intf_idx,
+   enum dpu_wb wb_idx),
+   TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx),
TP_STRUCT__entry(
__field(uint32_t,   drm_id  )
__field(u32,event   )
+   __string(   intf_mode_str,  intf_mode   )
__field(enum dpu_intf,  intf_idx)
+   __field(enum dpu_wb,  wb_idx)
),
TP_fast_assign(
__entry->drm_id = drm_id;
__entry->event = event;
+   __assign_str(intf_mode_str, intf_mode);
__entry->intf_idx = intf_idx;
+   __entry->wb_idx = wb_idx;
),
-   TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event,
- __entry->intf_idx)
+   TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", 
__entry->drm_id,
+   __entry->event, __get_str(intf_mode_str),
+   __entry->intf_idx, __entry->wb_idx)
 );
 
 TRACE_EVENT(dpu_enc_frame_done_cb,
@@ -415,14 +421,16 @@ TRACE_EVENT(dpu_enc_frame_done_cb,
 );
 
 TRACE_EVENT(dpu_enc_trigger_flush,
-   TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
+   TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum 
dpu_wb wb_idx,
 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
 u32 pending_flush_ret),
-   TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx,
+   TP_ARGS(drm_id, intf_mode, intf_idx, pending_kickoff_cnt, ctl_idx,
extra_flush_bits, pending_flush_ret),
TP_STRUCT__entry(
__field(uint32_t,   drm_id  )
+   __string(   intf_mode_str,  intf_mode   )
__field(enum dpu_intf,  intf_idx)
+   __field(enum dpu_wb,  wb_idx)
__field(int,pending_kickoff_cnt )
__field(int,ctl_idx )
__field(u32,extra_flush_bits)
@@ -430,15 +438,17 @@ TRACE_EVENT(dpu_enc_trigger_flush,
),
TP_fast_assign(
__entry->drm_id = drm_id;
+   __assign_str(intf_mode_str, intf_mode);
__entry->intf_idx = intf_idx;
+   __entry->wb_idx = wb_idx;
__entry->pending_kickoff_cnt =

[PATCH v2 2/3] drm/msm/dpu: add wb_idx to existing DRM prints in dpu_encoder

Add wb_idx to existing DRM prints in dpu_encoder and also
print the intf_mode so that its clear that for any INTF_CMD/VID
there will be a valid intf_idx and any INTF_WB_* there will be a
valid wb_idx.

Update the debugfs to add the same information. Here is a sample
output with this change:

root:/sys/kernel/debug/dri/0/encoder31# cat status
intf:1  wb:-1  vsync: 31  underrun: 0mode: INTF_MODE_VIDEO
root:/sys/kernel/debug/dri/0/encoder33# cat status
intf:-1  wb:2  vsync:  7  underrun: 0mode: INTF_MODE_WB_LINE

Also remove DPU_DEBUG_PHYS macros as its unused because the
respective dpu_encoder_phys_* files have their own macros.

changes in v2:
- use switch case instead of if/else-if for get_intf_type

Signed-off-by: Abhinav Kumar 
Reviewed-by: Dmitry Baryshkov 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 52 +
 1 file changed, 24 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9ae9bd4..7bd20fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -37,18 +37,6 @@
 #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\
(e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
 
-#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\
-   (p) ? (p)->parent->base.id : -1, \
-   (p) ? (p)->intf_idx - INTF_0 : -1, \
-   (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
-   ##__VA_ARGS__)
-
-#define DPU_ERROR_PHYS(p, fmt, ...) DPU_ERROR("enc%d intf%d pp%d " fmt,\
-   (p) ? (p)->parent->base.id : -1, \
-   (p) ? (p)->intf_idx - INTF_0 : -1, \
-   (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
-   ##__VA_ARGS__)
-
 /*
  * Two to anticipate panels that can do cmd/vid dynamic switching
  * plan is to create all possible physical encoder types, and switch between
@@ -262,12 +250,30 @@ static void _dpu_encoder_setup_dither(struct 
dpu_hw_pingpong *hw_pp, unsigned bp
hw_pp->ops.setup_dither(hw_pp, _cfg);
 }
 
+static char *dpu_encoder_helper_get_intf_type(enum dpu_intf_mode intf_mode)
+{
+   switch (intf_mode) {
+   case INTF_MODE_VIDEO:
+   return "INTF_MODE_VIDEO";
+   case INTF_MODE_CMD:
+   return "INTF_MODE_CMD";
+   case INTF_MODE_WB_BLOCK:
+   return "INTF_MODE_WB_BLOCK";
+   case INTF_MODE_WB_LINE:
+   return "INTF_MODE_WB_LINE";
+   default:
+   return "INTF_MODE_UNKNOWN";
+   }
+}
+
 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
enum dpu_intr_idx intr_idx)
 {
-   DRM_ERROR("irq timeout id=%u, intf=%d, pp=%d, intr=%d\n",
- DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
- phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
+   DRM_ERROR("irq timeout id=%u, intf_mode=%s intf=%d wb=%d, pp=%d, 
intr=%d\n",
+   DRMID(phys_enc->parent),
+   dpu_encoder_helper_get_intf_type(phys_enc->intf_mode),
+   phys_enc->intf_idx - INTF_0, phys_enc->wb_idx - WB_0,
+   phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
 
if (phys_enc->parent_ops->handle_frame_done)
phys_enc->parent_ops->handle_frame_done(
@@ -2048,22 +2054,12 @@ static int _dpu_encoder_status_show(struct seq_file *s, 
void *data)
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 
-   seq_printf(s, "intf:%dvsync:%8d underrun:%8d",
-   phys->intf_idx - INTF_0,
+   seq_printf(s, "intf:%d  wb:%d  vsync:%8d underrun:%8d",
+   phys->intf_idx - INTF_0, phys->wb_idx - WB_0,
atomic_read(>vsync_cnt),
atomic_read(>underrun_cnt));
 
-   switch (phys->intf_mode) {
-   case INTF_MODE_VIDEO:
-   seq_puts(s, "mode: video\n");
-   break;
-   case INTF_MODE_CMD:
-   seq_puts(s, "mode: command\n");
-   break;
-   default:
-   seq_puts(s, "mode: ???\n");
-   break;
-   }
+   seq_printf(s, "mode: %s\n", 
dpu_encoder_helper_get_intf_type(phys->intf_mode));
}
mutex_unlock(_enc->enc_lock);
 
-- 
2.7.4

[PATCH v2 1/3] drm/msm/dpu: introduce a wb_idx to be used for writeback interfaces

Using intf_idx even for writeback interfaces is confusing
because intf_idx is of type enum dpu_intf but the index used
for writeback is of type enum dpu_wb.

In addition, this makes it easier to separately check the
availability of the two as its possible that there are boards
which don't have any physical display connected but can still
work in writeback mode.

changes in v2:
- add check for invalid phys having both intf and wb
- merge the next change of using wb_idx in phys_wb

Signed-off-by: Abhinav Kumar 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 68 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  4 ++
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c| 10 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |  2 +-
 4 files changed, 51 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c12841..9ae9bd4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -962,7 +962,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
int num_lm, num_ctl, num_pp, num_dsc;
unsigned int dsc_mask = 0;
-   enum dpu_hw_blk_type blk_type;
int i;
 
if (!drm_enc) {
@@ -1044,17 +1043,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
phys->hw_pp = dpu_enc->hw_pp[i];
phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
 
-   if (dpu_encoder_get_intf_mode(_enc->base) == 
INTF_MODE_WB_LINE)
-   blk_type = DPU_HW_BLK_WB;
-   else
-   blk_type = DPU_HW_BLK_INTF;
+   if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
+   phys->hw_intf = dpu_rm_get_intf(_kms->rm, 
phys->intf_idx);
 
-   if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) {
-   if (blk_type == DPU_HW_BLK_INTF)
-   phys->hw_intf = dpu_rm_get_intf(_kms->rm, 
phys->intf_idx);
-   else if (blk_type == DPU_HW_BLK_WB)
-   phys->hw_wb = dpu_rm_get_wb(_kms->rm, 
phys->intf_idx);
-   }
+   if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
+   phys->hw_wb = dpu_rm_get_wb(_kms->rm, phys->wb_idx);
 
if (!phys->hw_intf && !phys->hw_wb) {
DPU_ERROR_ENC(dpu_enc,
@@ -1062,6 +1055,12 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
return;
}
 
+   if (phys->hw_intf && phys->hw_wb) {
+   DPU_ERROR_ENC(dpu_enc,
+   "invalid phys both intf and wb block at 
idx: %d\n", i);
+   return;
+   }
+
phys->cached_mode = crtc_state->adjusted_mode;
if (phys->ops.atomic_mode_set)
phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
@@ -1201,7 +1200,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder 
*drm_enc)
mutex_unlock(_enc->enc_lock);
 }
 
-static enum dpu_intf dpu_encoder_get_intf_or_wb(struct dpu_mdss_cfg *catalog,
+static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
enum dpu_intf_type type, u32 controller_id)
 {
int i = 0;
@@ -1213,16 +1212,28 @@ static enum dpu_intf dpu_encoder_get_intf_or_wb(struct 
dpu_mdss_cfg *catalog,
return catalog->intf[i].id;
}
}
-   } else {
-   for (i = 0; i < catalog->wb_count; i++) {
-   if (catalog->wb[i].id == controller_id)
-   return catalog->wb[i].id;
-   }
}
 
return INTF_MAX;
 }
 
+static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,
+   enum dpu_intf_type type, u32 controller_id)
+{
+   int i = 0;
+
+   if (type != INTF_WB)
+   goto end;
+
+   for (i = 0; i < catalog->wb_count; i++) {
+   if (catalog->wb[i].id == controller_id)
+   return catalog->wb[i].id;
+   }
+
+end:
+   return WB_MAX;
+}
+
 static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
struct dpu_encoder_phys *phy_enc)
 {
@@ -2249,18 +2260,21 @@ static int dpu_encoder_setup_display(struct 
dpu_encoder_virt *dpu_enc,
DPU_DEBUG("h_tile_instance %d = %d, split_role %d\n",
i, controller_id, phys_params.split_role);
 
-   /*
-* FIXME: have separate intf_idx and wb_idx to avoid using
-* enum dpu_intf type for wb_idx and also to be able to
-* not bail

[PATCH v2 0/3] Separate wb_idx and intf_idx in dpu_encoder

As promised here [1], this is a follow up change to separate out
wb_idx and intf_idx for better clarity in dpu_encoder.

This also helps to easily handle boards which do not have a physical
display but can still be validated using writeback interface.

In addition, this also takes care of adding wb_idx to existing DRM prints
and traces.

Re-posting this without RFC tag to plan to absorb this in the
DPU writeback series [2]

[1] 
https://patchwork.freedesktop.org/patch/482637/?series=99724=2#comment_868460
[2] https://patchwork.freedesktop.org/series/99724/#rev3

changes in v2:
- drop the RFC tag
- add the check for phys->intf && phys->wb
- squash changes 1&2 of the previous series

Abhinav Kumar (3):
  drm/msm/dpu: introduce a wb_idx to be used for writeback interfaces
  drm/msm/dpu: add wb_idx to existing DRM prints in dpu_encoder
  drm/msm/dpu: add wb_idx to DRM traces in dpu_encoder

 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 133 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   4 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c|  10 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h  |  26 ++--
 5 files changed, 101 insertions(+), 74 deletions(-)

-- 
2.7.4

Re: [PATCH] drm/vmwgfx: Reserve fence slots on buffer objects in cotables

2022-04-22 Thread Christian König


Am 22.04.22 um 18:13 schrieb Zack Rusin:

From: Zack Rusin 

The buffer objects created by cotables were missing fence reservations.
They are created from vmw_validation_res_validate which makes them miss
the ttm_eu_reserve_buffers which is called from vmw_validation_bo_reserve.

Cotables are the only resources which create a buffer object in the
create callback so make sure the code also reserves the slots.

Signed-off-by: Zack Rusin 
Fixes: c8d4c18bfbc4 ("dma-buf/drivers: make reserving a shared slot mandatory 
v4")


Reviewed-by: Christian König 


---
  drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c | 4 
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
index 16f986b6cbea..79b30dc9d825 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
@@ -478,6 +478,10 @@ static int vmw_cotable_resize(struct vmw_resource *res, 
size_t new_size)
vmw_bo_unreference(_buf);
res->id = vcotbl->type;
  
+	ret = dma_resv_reserve_fences(bo->base.resv, 1);

+   if (unlikely(ret))
+   goto out_wait;
+
/* Release the pin acquired in vmw_bo_init */
ttm_bo_unpin(bo);

Re: [PATCH] drm/vmwgfx: reserve fence slots on new resources

2022-04-22 Thread Christian König


Am 22.04.22 um 18:13 schrieb Zack Rusin:

On Fri, 2022-04-22 at 11:21 +0200, Christian König wrote:

Am 22.04.22 um 11:20 schrieb Christian König:

When resources are allocated dynamically during an IOCTL we need to
make sure
that a fence slot is reserved so that the resulting fence can be
added in the
end.

I should probably add that this is only compile tested.

Zack you should probably give it a try for your issue.

I think we're on the right track but cotables are the only objects that
create a bo in the create callback so we endup double reserving all the
other backup objects. If you don't mind I'd prefer to move the code to
localize the reservation to the problematic spot. I'll send it in a sec
(6d0fdf27e98a ("drm/vmwgfx: Reserve fence slots on buffer objects in
cotables") let me know if I can add a Co-developed-by: Christian König
 tag to it.


Sure, please go ahead. You know the code much better than I do anyway.

Thanks,
Christian.



z

Re: [PATCH v2 00/48] ARM: PXA multiplatform support

2022-04-22 Thread Arnd Bergmann

On Fri, Apr 22, 2022 at 7:05 PM Guenter Roeck  wrote:
>
> On Tue, Apr 19, 2022 at 06:37:22PM +0200, Arnd Bergmann wrote:
> > From: Arnd Bergmann 
> >
> > This revisits a series I sent a few years ago:
> >
> > https://lore.kernel.org/lkml/20191018154052.1276506-1-a...@arndb.de/
> >
> > All the other ARMv5 conversions are under way now, with
> > OMAP1 being the only one still not in linux-next yet,
> > and PXA completing the set.
> >
> > Most of the patches are unchanged from before, furtunately
> > the PXA code is fairly stable. I addressed Robert's comments,
> > pulled in two patches from Dmitry, and added the last a the
> > final four patches to finish off the multiplatform conversion.
> >
> > I hope someone is left to test these on PXA: if this works,
> > I'd like to merge it for 5.19. A git tree with these is avaialable
> > for testing at
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=pxa-multiplatform-5.18
> >
>
> Unfortunately that crashes for me when trying to boot from ide.
> Bisect points to the last patch of the series.

Thanks a lot for testing and the perfect bug report!

> [1.403715] 8<--- cut here ---
> [1.403848] Unable to handle kernel paging request at virtual address 
> feeb000e
> [1.404097] [feeb000e] *pgd=

Ok, this is the PCI I/O space area, which starts at 0xfee0,
clearly the way I/O space
gets mapped changed here. I don't yet see what happened, but it should
be straightforward
to find from here.

> [1.416643]  pcmcia_init_one from pcmcia_device_probe+0xe4/0x2a0
> [1.416882]  pcmcia_device_probe from really_probe+0xc8/0x3b4
> [1.417070]  really_probe from __driver_probe_device+0x9c/0x214
> [1.417255]  __driver_probe_device from driver_probe_device+0x38/0xe0
> [1.417454]  driver_probe_device from __device_attach_driver+0xa4/0x11c
> [1.417657]  __device_attach_driver from bus_for_each_drv+0x88/0xd8
> [1.417864]  bus_for_each_drv from __device_attach+0xf4/0x194
> [1.418047]  __device_attach from bus_probe_device+0x8c/0x94
> [1.418224]  bus_probe_device from device_add+0x3d0/0x894
> [1.418395]  device_add from pcmcia_device_add+0x2ec/0x3e0
> [1.418568]  pcmcia_device_add from pcmcia_card_add+0xd4/0x1a0
> [1.418756]  pcmcia_card_add from pcmcia_bus_add+0x44/0x4c
> [1.418930]  pcmcia_bus_add from socket_insert+0x12c/0x150
> [1.419103]  socket_insert from pccardd+0x398/0x44c
> [1.419257]  pccardd from kthread+0xdc/0x114
> [1.419400]  kthread from ret_from_fork+0x14/0x2c
> [1.419569] Exception stack(0xc48a5fb0 to 0xc48a5ff8)
> [1.419735] 5fa0:   
>  
> [1.419979] 5fc0:       
>  
> [1.420222] 5fe0:     0013 
> [1.420501] Code: 1357 e1a06000 0a43 e3a03002 (e5c03000)
> [1.420874] ---[ end trace  ]---
>
> ---
> # bad: [7643a9ca9f8e08f71e15f89dd74863635e981e03] ARM: pxa: convert to 
> multiplatform
> # good: [3123109284176b1532874591f7c81f3837bbdc17] Linux 5.18-rc1
> git bisect start 'HEAD' 'v5.18-rc1'
> # good: [9b03d7f95bd4d97101ecb8ea1e822103b81fdb2d] ARM: pxa: 
> mainstone-wm97xx: use gpio lookup table
> git bisect good 9b03d7f95bd4d97101ecb8ea1e822103b81fdb2d
> # good: [764063eee7620ea9abb940068a7ad0e7f9efa1b6] cpufreq: pxa3: move clk 
> register access to clk driver
> git bisect good 764063eee7620ea9abb940068a7ad0e7f9efa1b6
> # good: [5153474f0a4388b7ddb59add4be73bfb42b2007f] ARM: mmp: remove tavorevb 
> board support
> git bisect good 5153474f0a4388b7ddb59add4be73bfb42b2007f
> # good: [2746f7c78b428c8b01b691a29a972c08101ae343] ARM: PXA: fix multi-cpu 
> build of xsc3
> git bisect good 2746f7c78b428c8b01b691a29a972c08101ae343
> # good: [73d5106e9489464eac84362705e93bcf3b376123] ARM: pxa: remove support 
> for MTD_XIP
> git bisect good 73d5106e9489464eac84362705e93bcf3b376123
> # first bad commit: [7643a9ca9f8e08f71e15f89dd74863635e981e03] ARM: pxa: 
> convert to multiplatform

I'll back out this patch for now while investigating further.

Which machine did you hit this on? Is this on hardware or in qemu?

   Arnd

Re: [RFC 1/4] drm/msm/dpu: introduce a wb_idx to be used for writeback interfaces

On Fri, 22 Apr 2022 at 21:18, Abhinav Kumar  wrote:
>
> Hi Dmitry
>
> On 4/22/2022 3:37 AM, Dmitry Baryshkov wrote:
> > On Fri, 22 Apr 2022 at 04:59, Abhinav Kumar  
> > wrote:
> >>
> >>
> >>
> >> On 4/21/2022 5:22 PM, Dmitry Baryshkov wrote:
> >>> On Fri, 22 Apr 2022 at 02:07, Abhinav Kumar  
> >>> wrote:
> 
>  Hi Dmitry
> 
>  Thanks for the review.
> 
>  One question below.
> 
>  On 4/21/2022 3:40 PM, Dmitry Baryshkov wrote:
> > On 21/04/2022 23:48, Abhinav Kumar wrote:
> >> Using intf_idx even for writeback interfaces is confusing
> >> because intf_idx is of type enum dpu_intf but the index used
> >> for writeback is of type enum dpu_wb.
> >>
> >> In addition, this makes it easier to separately check the
> >> availability of the two as its possible that there are boards
> >> which don't have any physical display connected but can still
> >> work in writeback mode.
> >>
> >> Signed-off-by: Abhinav Kumar 
> >
> > Looks good, two minor issues bellow.
> >
> > With them fixed, I'd even squash this patch into the corresponding patch
> > of the previous patchset.
> >
> >> ---
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 62
> >> +---
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  4 ++
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h   |  2 +-
> >> 3 files changed, 40 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> index 9c12841..054d7e4 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> @@ -962,7 +962,6 @@ static void
> >> dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> >> struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> >> int num_lm, num_ctl, num_pp, num_dsc;
> >> unsigned int dsc_mask = 0;
> >> -enum dpu_hw_blk_type blk_type;
> >> int i;
> >> if (!drm_enc) {
> >> @@ -1044,17 +1043,11 @@ static void
> >> dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> >> phys->hw_pp = dpu_enc->hw_pp[i];
> >> phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
> >> -if (dpu_encoder_get_intf_mode(_enc->base) ==
> >> INTF_MODE_WB_LINE)
> >> -blk_type = DPU_HW_BLK_WB;
> >> -else
> >> -blk_type = DPU_HW_BLK_INTF;
> >> +if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
> >> +phys->hw_intf = dpu_rm_get_intf(_kms->rm,
> >> phys->intf_idx);
> >> -if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) {
> >> -if (blk_type == DPU_HW_BLK_INTF)
> >> -phys->hw_intf = dpu_rm_get_intf(_kms->rm,
> >> phys->intf_idx);
> >> -else if (blk_type == DPU_HW_BLK_WB)
> >> -phys->hw_wb = dpu_rm_get_wb(_kms->rm,
> >> phys->intf_idx);
> >> -}
> >> +if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
> >> +phys->hw_wb = dpu_rm_get_wb(_kms->rm, phys->wb_idx);
> >
> > We also need a check for if (phus->hw_intf && phys->hw_wb) HERE
> 
>  So there is an error if
> 
>  1) Neither wb NOR intf are present
>  2) Both wb AND intf are present for the physical encoder?
> 
>  The second check is okay for now to add but considering concurrent
>  writeback then that wouldn't assumption be wrong since both physical and
>  wb interfaces can go with the same encoder?
> >>>
> >>> To the same encoder, but not to the same physical encoder. Here we
> >>> check the phys_enc parameters.
> >>
> >> Ok got it, let me re-spin this RFC with patches 2 & 3 squashed.
> >> Get the acks on them.
> >>
> >> Then will absorb into WB series and re-post it.
> >
> > Sounds like a good plan!
> >
> >>
> >>>
> 
> >
> >> if (!phys->hw_intf && !phys->hw_wb) {
> >> DPU_ERROR_ENC(dpu_enc,
> >> @@ -1201,7 +1194,7 @@ static void dpu_encoder_virt_disable(struct
> >> drm_encoder *drm_enc)
> >> mutex_unlock(_enc->enc_lock);
> >> }
> >> -static enum dpu_intf dpu_encoder_get_intf_or_wb(struct dpu_mdss_cfg
> >> *catalog,
> >> +static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg 
> >> *catalog,
> >> enum dpu_intf_type type, u32 controller_id)
> >> {
> >> int i = 0;
> >> @@ -1213,16 +1206,28 @@ static enum dpu_intf
> >> dpu_encoder_get_intf_or_wb(struct dpu_mdss_cfg *catalog,
> >> return catalog->intf[i].id;
> >> }
> >> }
> >> -} else {
> >> -for (i = 0; i < catalog->wb_count; i++) {
> >> -

[PATCH] drm/nouveau/kms/gv100: use static for gv100_disp_core_mthd_[base|sor]

2022-04-22 Thread Tom Rix

Sparse reports these issues
coregv100.c:27:1: warning: symbol 'gv100_disp_core_mthd_base' was not declared. 
Should it be static?
coregv100.c:43:1: warning: symbol 'gv100_disp_core_mthd_sor' was not declared. 
Should it be static?

These variables are only used in coregv100.c.  Single file use
variables should be static, so add static to their storage-class specifier.

Signed-off-by: Tom Rix 
---
 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c 
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c
index 448a515057c7..1d333c484a49 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c
@@ -23,7 +23,7 @@
 
 #include 
 
-const struct nv50_disp_mthd_list
+static const struct nv50_disp_mthd_list
 gv100_disp_core_mthd_base = {
.mthd = 0x,
.addr = 0x00,
@@ -39,7 +39,7 @@ gv100_disp_core_mthd_base = {
}
 };
 
-const struct nv50_disp_mthd_list
+static const struct nv50_disp_mthd_list
 gv100_disp_core_mthd_sor = {
.mthd = 0x0020,
.addr = 0x20,
-- 
2.27.0

Re: [PATCH v3 1/4] drm: mxsfb: Wrap FIFO reset and comments into mxsfb_reset_block()

On Sun, Apr 17, 2022 at 04:07:57AM +0200, Marek Vasut wrote:
> Wrap FIFO reset and comments into mxsfb_reset_block(), this is a clean up.
> No functional change.
> 
> Reviewed-by: Lucas Stach 
> Signed-off-by: Marek Vasut 
> Cc: Alexander Stein 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Peng Fan 
> Cc: Robby Cai 
> Cc: Sam Ravnborg 
> Cc: Stefan Agner 
Acked-by: Sam Ravnborg

Re: [PATCH] drm/msm/dp: fix error check return value of irq_of_parse_and_map()

Quoting cgel@gmail.com (2022-04-22 01:49:51)
> From: Lv Ruyi 
>
> The irq_of_parse_and_map() function returns 0 on failure, and does not
> return an negative value.
>
> Fixes:  8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon 
> Chipsets")
> Reported-by: Zeal Robot 
> Signed-off-by: Lv Ruyi 
> ---
>  drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c 
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index a42732b67349..3926d2ac107d 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -1239,7 +1239,7 @@ int dp_display_request_irq(struct msm_dp *dp_display)
> dp = container_of(dp_display, struct dp_display_private, dp_display);
>
> dp->irq = irq_of_parse_and_map(dp->pdev->dev.of_node, 0);

Why can't platform_get_irq() be used?

> -   if (dp->irq < 0) {
> +   if (!dp->irq) {
> rc = dp->irq;

zero as an error return value is an error?

> DRM_ERROR("failed to get irq: %d\n", rc);
> return rc;

Re: [PATCH v2 2/2] drm/panel: simple: Add Startek KD070WVFPA043-C069A panel support

On Fri, Apr 22, 2022 at 03:36:14PM -0300, Fabio Estevam wrote:
> From: Heiko Schocher 
> 
> Add Startek KD070WVFPA043-C069A 7" TFT LCD panel support.
> 
> Signed-off-by: Heiko Schocher 
> Signed-off-by: Fabio Estevam 
Acked-by: Sam Ravnborg

Re: [PATCH v3 4/4] drm: mxsfb: Reorder mxsfb_crtc_mode_set_nofb()

On Sun, Apr 17, 2022 at 04:08:00AM +0200, Marek Vasut wrote:
> Reorder mxsfb_crtc_mode_set_nofb() such that all functions which perform
> register IO are called from one single location in this function. This is
> a clean up. No functional change.
> 
> Reviewed-by: Lucas Stach 
> Signed-off-by: Marek Vasut 
> Cc: Alexander Stein 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Peng Fan 
> Cc: Robby Cai 
> Cc: Sam Ravnborg 
> Cc: Stefan Agner 
Acked-by: Sam Ravnborg

Re: [PATCH v3 3/4] drm: mxsfb: Factor out mxsfb_set_mode()

On Sun, Apr 17, 2022 at 04:07:59AM +0200, Marek Vasut wrote:
> Pull mode registers programming from mxsfb_enable_controller() into
> dedicated function mxsfb_set_mode(). This is a clean up. No functional
> change.
> 
> Signed-off-by: Marek Vasut 
> Cc: Alexander Stein 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Peng Fan 
> Cc: Robby Cai 
> Cc: Sam Ravnborg 
> Cc: Stefan Agner 
Acked-by: Sam Ravnborg

[PATCH v2 2/2] drm/panel: simple: Add Startek KD070WVFPA043-C069A panel support

2022-04-22 Thread Fabio Estevam

From: Heiko Schocher 

Add Startek KD070WVFPA043-C069A 7" TFT LCD panel support.

Signed-off-by: Heiko Schocher 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Put the panel entry in the correct order (Sam).

 drivers/gpu/drm/panel/panel-simple.c | 33 
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index a34f4198a534..61d82d7be1ba 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3284,6 +3284,36 @@ static const struct panel_desc starry_kr070pe2t = {
.connector_type = DRM_MODE_CONNECTOR_DPI,
 };
 
+static const struct display_timing startek_kd070wvfpa_mode = {
+   .pixelclock = { 2520, 2720, 3050 },
+   .hactive = { 800, 800, 800 },
+   .hfront_porch = { 19, 44, 115 },
+   .hback_porch = { 5, 16, 101 },
+   .hsync_len = { 1, 2, 100 },
+   .vactive = { 480, 480, 480 },
+   .vfront_porch = { 5, 43, 67 },
+   .vback_porch = { 5, 5, 67 },
+   .vsync_len = { 1, 2, 66 },
+};
+
+static const struct panel_desc startek_kd070wvfpa = {
+   .timings = _kd070wvfpa_mode,
+   .num_timings = 1,
+   .bpc = 8,
+   .size = {
+   .width = 152,
+   .height = 91,
+   },
+   .delay = {
+   .prepare = 20,
+   .enable = 200,
+   .disable = 200,
+   },
+   .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
+   .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+   .connector_type = DRM_MODE_CONNECTOR_DPI,
+};
+
 static const struct display_timing tsd_tst043015cmhx_timing = {
.pixelclock = { 500, 900, 1200 },
.hactive = { 480, 480, 480 },
@@ -3990,6 +4020,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "starry,kr070pe2t",
.data = _kr070pe2t,
+   }, {
+   .compatible = "startek,kd070wvfpa",
+   .data = _kd070wvfpa,
}, {
.compatible = "team-source-display,tst043015cmhx",
.data = _tst043015cmhx,
-- 
2.25.1

[PATCH v2 1/2] dt-bindings: display: simple: Add Startek KD070WVFPA043-C069A panel

2022-04-22 Thread Fabio Estevam

From: Fabio Estevam 

Add Startek KD070WVFPA043-C069A 7" TFT LCD panel compatible string.

Signed-off-by: Fabio Estevam 
Acked-by: Sam Ravnborg 
---
Changes since v1:
- None. Only added Sam's ack.

 .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 
b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
index 1eb9dd4f8f58..e190eef66872 100644
--- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
+++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
@@ -294,6 +294,8 @@ properties:
   - starry,kr070pe2t
 # Starry 12.2" (1920x1200 pixels) TFT LCD panel
   - starry,kr122ea0sra
+# Startek KD070WVFPA043-C069A 7" TFT LCD panel
+  - startek,kd070wvfpa
 # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel
   - team-source-display,tst043015cmhx
 # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
-- 
2.25.1

Re: [PATCH v3 2/4] drm: mxsfb: Replace mxsfb_get_fb_paddr() with drm_fb_cma_get_gem_addr()

On Sun, Apr 17, 2022 at 04:07:58AM +0200, Marek Vasut wrote:
> Replace mxsfb_get_fb_paddr() with drm_fb_cma_get_gem_addr() to correctly 
> handle
> FB offset.
> 
> Signed-off-by: Marek Vasut 
> Cc: Alexander Stein 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Peng Fan 
> Cc: Robby Cai 
> Cc: Sam Ravnborg 
> Cc: Stefan Agner 
Acked-by: Sam Ravnborg

Re: [PATCH v2 2/2] drm: bridge: ldb: Implement simple NXP i.MX8M LDB bridge

Hi Marek,

On Mon, Apr 18, 2022 at 04:51:05PM +0200, Marek Vasut wrote:
> The i.MX8MP contains two syscon registers which are responsible
> for configuring the on-SoC DPI-to-LVDS serializer. Implement a
> simple bridge driver for this serializer.
> 
> Signed-off-by: Marek Vasut 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Maxime Ripard 
> Cc: Peng Fan 
> Cc: Robby Cai 
> Cc: Robert Foss 
> Cc: Sam Ravnborg 
> Cc: Thomas Zimmermann 
> To: dri-devel@lists.freedesktop.org

Good to see a bridge driver that stays away from the deprecated stuff,
and it looks nice a clean. I like how disable is the exact opposite of
enable.

A few comments in the following - with the Kconfig text updated:
Reviewed-by: Sam Ravnborg 

Sam

> --
> V2: - Rename syscon to fsl,syscon
> ---
>  drivers/gpu/drm/bridge/Kconfig   |   8 +
>  drivers/gpu/drm/bridge/Makefile  |   1 +
>  drivers/gpu/drm/bridge/nxp-ldb.c | 343 +++
>  3 files changed, 352 insertions(+)
>  create mode 100644 drivers/gpu/drm/bridge/nxp-ldb.c
> 
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 20f9bc7f4be54..7fe7088a2bef5 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -185,6 +185,14 @@ config DRM_NWL_MIPI_DSI
> This enables the Northwest Logic MIPI DSI Host controller as
> for example found on NXP's i.MX8 Processors.
>  
> +config DRM_NXP_LDB
> + tristate "NXP i.MX8M LDB bridge"
> + depends on OF
> + select DRM_KMS_HELPER
> + select DRM_PANEL_BRIDGE
> + help
> +   Support for i.MX8M DPI-to-LVDS on-SoC encoder.
As commented in the bindings patch - is this i.MX8M or i.MX8MP?

> +
>  config DRM_NXP_PTN3460
>   tristate "NXP PTN3460 DP/LVDS bridge"
>   depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index bdffad2a7ed3a..f800b2331d9e0 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
>  obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o
>  obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
>  obj-$(CONFIG_DRM_MEGACHIPS_STDP_GE_B850V3_FW) += 
> megachips-stdp-ge-b850v3-fw.o
> +obj-$(CONFIG_DRM_NXP_LDB) += nxp-ldb.o
>  obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>  obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
>  obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
> diff --git a/drivers/gpu/drm/bridge/nxp-ldb.c 
> b/drivers/gpu/drm/bridge/nxp-ldb.c
> new file mode 100644
> index 0..7b8de235876ea
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/nxp-ldb.c
> @@ -0,0 +1,343 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2022 Marek Vasut 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define LDB_CTRL 0x5c
> +#define LDB_CTRL_CH0_ENABLE  BIT(0)
> +#define LDB_CTRL_CH0_DI_SELECT   BIT(1)
> +#define LDB_CTRL_CH1_ENABLE  BIT(2)
> +#define LDB_CTRL_CH1_DI_SELECT   BIT(3)
> +#define LDB_CTRL_SPLIT_MODE  BIT(4)
> +#define LDB_CTRL_CH0_DATA_WIDTH  BIT(5)
> +#define LDB_CTRL_CH0_BIT_MAPPING BIT(6)
> +#define LDB_CTRL_CH1_DATA_WIDTH  BIT(7)
> +#define LDB_CTRL_CH1_BIT_MAPPING BIT(8)
> +#define LDB_CTRL_DI0_VSYNC_POLARITY  BIT(9)
> +#define LDB_CTRL_DI1_VSYNC_POLARITY  BIT(10)
> +#define LDB_CTRL_REG_CH0_FIFO_RESET  BIT(11)
> +#define LDB_CTRL_REG_CH1_FIFO_RESET  BIT(12)
> +#define LDB_CTRL_ASYNC_FIFO_ENABLE   BIT(24)
> +#define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK   GENMASK(27, 25)
> +
> +#define LVDS_CTRL0x128
> +#define LVDS_CTRL_CH0_EN BIT(0)
> +#define LVDS_CTRL_CH1_EN BIT(1)
> +#define LVDS_CTRL_VBG_EN BIT(2)
> +#define LVDS_CTRL_HS_EN  BIT(3)
> +#define LVDS_CTRL_PRE_EMPH_ENBIT(4)
> +#define LVDS_CTRL_PRE_EMPH_ADJ(n)(((n) & 0x7) << 5)
> +#define LVDS_CTRL_PRE_EMPH_ADJ_MASK  GENMASK(7, 5)
> +#define LVDS_CTRL_CM_ADJ(n)  (((n) & 0x7) << 8)
> +#define LVDS_CTRL_CM_ADJ_MASKGENMASK(10, 8)
> +#define LVDS_CTRL_CC_ADJ(n)  (((n) & 0x7) << 11)
> +#define LVDS_CTRL_CC_ADJ_MASKGENMASK(13, 11)
> +#define LVDS_CTRL_SLEW_ADJ(n)(((n) & 0x7) << 14)
> +#define LVDS_CTRL_SLEW_ADJ_MASK  GENMASK(16, 14)
> +#define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17)
> +#define LVDS_CTRL_VBG_ADJ_MASK   GENMASK(19, 17)
> +
> +struct nxp_ldb {
> + struct device *dev;
> +

Re: [PATCH 1/2] dt-bindings: display: simple: Add Startek KD070WVFPA043-C069A panel

On Tue, Apr 19, 2022 at 09:56:24PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> Add Startek KD070WVFPA043-C069A 7" TFT LCD panel compatible string.
> 
> Signed-off-by: Fabio Estevam 
Acked-by: Sam Ravnborg 
> ---
>  .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git 
> a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 
> b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> index 1eb9dd4f8f58..e190eef66872 100644
> --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> @@ -294,6 +294,8 @@ properties:
>- starry,kr070pe2t
>  # Starry 12.2" (1920x1200 pixels) TFT LCD panel
>- starry,kr122ea0sra
> +# Startek KD070WVFPA043-C069A 7" TFT LCD panel
> +  - startek,kd070wvfpa
>  # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD 
> panel
>- team-source-display,tst043015cmhx
>  # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
> -- 
> 2.25.1

Re: [PATCH v2 2/2] drm/panel: simple: Add DataImage FG040346DSSWBG04 panel support

On Fri, Apr 22, 2022 at 12:22:42PM +0200, Marek Vasut wrote:
> Add DataImage FG040346DSSWBG04 4.3" 480x272 TFT LCD 24bit DPI panel
> support.
> 
> Acked-by: Thomas Zimmermann 
> Signed-off-by: Marek Vasut 
> Cc: Sam Ravnborg 
> Cc: Thomas Zimmermann 
> To: dri-devel@lists.freedesktop.org
Acked-by: Sam Ravnborg 

Sam

Re: [PATCH v2 1/2] dt-bindings: display: simple: Add DataImage FG040346DSSWBG04 compatible string

On Fri, Apr 22, 2022 at 12:22:41PM +0200, Marek Vasut wrote:
> Add DataImage FG040346DSSWBG04 4.3" 480x272 TFT LCD 24bit DPI panel
> compatible string.
> 
> Acked-by: Thomas Zimmermann 
> Signed-off-by: Marek Vasut 
> Cc: Rob Herring 
> Cc: Sam Ravnborg 
> Cc: Thomas Zimmermann 
> Cc: devicet...@vger.kernel.org
> To: dri-devel@lists.freedesktop.org
Acked-by: Sam Ravnborg 
> ---
> V2: Add AB from Thomas
> ---
>  .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git 
> a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml 
> b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> index 1eb9dd4f8f58..cfe7bb9f89de 100644
> --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
> @@ -105,6 +105,8 @@ properties:
>- chunghwa,claa101wb01
>  # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel
>- chunghwa,claa101wb03
> +# DataImage, Inc. 4.3" WQVGA (480x272) TFT LCD panel with 24-bit 
> parallel interface.
> +  - dataimage,fg040346dsswbg04
>  # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit 
> parallel interface.
>- dataimage,scf0700c48ggu18
>  # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel
> -- 
> 2.35.1

Re: [PATCH v2 1/2] dt-bindings: display: bridge: ldb: Implement simple NXP i.MX8M LDB bridge

Hi Marek, I read the patch once more.

On Mon, Apr 18, 2022 at 04:51:04PM +0200, Marek Vasut wrote:
> The i.MX8MP contains two syscon registers which are responsible

Here it says i.MX8MP

> for configuring the on-SoC DPI-to-LVDS serializer. Add DT binding
> which represents this serializer as a bridge.
> 
> Signed-off-by: Marek Vasut 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Maxime Ripard 
> Cc: Peng Fan 
> Cc: Rob Herring 
> Cc: Robby Cai 
> Cc: Robert Foss 
> Cc: Sam Ravnborg 
> Cc: Thomas Zimmermann 
> Cc: devicet...@vger.kernel.org
> To: dri-devel@lists.freedesktop.org
> ---
> V2: - Consistently use fsl,imx8mp-ldb as compatible
> - Drop items: from compatible:
> - Replace minItems with maxItems in clocks:
> - Drop quotes from clock-names const: ldb
> - Rename syscon to fsl,syscon
> - Use generic name of ldb-lvds in example
> ---
>  .../bindings/display/bridge/nxp,ldb.yaml  | 96 +++
>  1 file changed, 96 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml 
> b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
> new file mode 100644
> index 0..f3182566eb316
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/nxp,ldb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8M DPI to LVDS bridge chip
Here it says i.MX8M 
> +
> +maintainers:
> +  - Marek Vasut 
> +
> +description: |
> +  The i.MX8MP contains two syscon registers which are responsible
Here it says i.MX8MP

> +  for configuring the on-SoC DPI-to-LVDS serializer. This describes
> +  those registers as bridge within the DT.
> +
> +properties:
> +  compatible:
> +const: fsl,imx8mp-ldb
Here it says fsl,imx8mp


It looks a little inconsistent, I guess the title needs a fix.
a-b stands with the title fixed.

Sam
> +
> +  clocks:
> +maxItems: 1
> +
> +  clock-names:
> +const: ldb
> +
> +  fsl,syscon:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description: A phandle to media block controller.
> +
> +  ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +
> +properties:
> +  port@0:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Video port for DPI input.
> +
> +  port@1:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Video port for LVDS Channel-A output (panel or bridge).
> +
> +  port@2:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Video port for LVDS Channel-B output (panel or bridge).
> +
> +required:
> +  - port@0
> +  - port@1
> +
> +required:
> +  - compatible
> +  - clocks
> +  - fsl,syscon
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +#include 
> +
> +bridge {
> +compatible = "fsl,imx8mp-ldb";
> +clocks = < IMX8MP_CLK_MEDIA_LDB>;
> +clock-names = "ldb";
> +fsl,syscon = <_blk_ctrl>;
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +
> +ldb_from_lcdif2: endpoint {
> +remote-endpoint = <_to_ldb>;
> +};
> +};
> +
> +port@1 {
> +reg = <1>;
> +
> +ldb_lvds_ch0: endpoint {
> +remote-endpoint = <_to_lvdsx4panel>;
> +};
> +};
> +
> +port@2 {
> +reg = <2>;
> +
> +ldb_lvds_ch1: endpoint {
> +};
> +};
> +};
> +};
> -- 
> 2.35.1

Re: [PATCH v2 1/2] dt-bindings: display: bridge: ldb: Implement simple NXP i.MX8M LDB bridge

On Mon, Apr 18, 2022 at 04:51:04PM +0200, Marek Vasut wrote:
> The i.MX8MP contains two syscon registers which are responsible
> for configuring the on-SoC DPI-to-LVDS serializer. Add DT binding
> which represents this serializer as a bridge.
> 
> Signed-off-by: Marek Vasut 
> Cc: Laurent Pinchart 
> Cc: Lucas Stach 
> Cc: Maxime Ripard 
> Cc: Peng Fan 
> Cc: Rob Herring 
> Cc: Robby Cai 
> Cc: Robert Foss 
> Cc: Sam Ravnborg 
> Cc: Thomas Zimmermann 
> Cc: devicet...@vger.kernel.org
> To: dri-devel@lists.freedesktop.org
Acked-by: Sam Ravnborg  but you need an ack from
someone else before you apply as I am not an expert here.

Sam
> ---
> V2: - Consistently use fsl,imx8mp-ldb as compatible
> - Drop items: from compatible:
> - Replace minItems with maxItems in clocks:
> - Drop quotes from clock-names const: ldb
> - Rename syscon to fsl,syscon
> - Use generic name of ldb-lvds in example
> ---
>  .../bindings/display/bridge/nxp,ldb.yaml  | 96 +++
>  1 file changed, 96 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml 
> b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
> new file mode 100644
> index 0..f3182566eb316
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/nxp,ldb.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/nxp,ldb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8M DPI to LVDS bridge chip
> +
> +maintainers:
> +  - Marek Vasut 
> +
> +description: |
> +  The i.MX8MP contains two syscon registers which are responsible
> +  for configuring the on-SoC DPI-to-LVDS serializer. This describes
> +  those registers as bridge within the DT.
> +
> +properties:
> +  compatible:
> +const: fsl,imx8mp-ldb
> +
> +  clocks:
> +maxItems: 1
> +
> +  clock-names:
> +const: ldb
> +
> +  fsl,syscon:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description: A phandle to media block controller.
> +
> +  ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +
> +properties:
> +  port@0:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Video port for DPI input.
> +
> +  port@1:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Video port for LVDS Channel-A output (panel or bridge).
> +
> +  port@2:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Video port for LVDS Channel-B output (panel or bridge).
> +
> +required:
> +  - port@0
> +  - port@1
> +
> +required:
> +  - compatible
> +  - clocks
> +  - fsl,syscon
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +#include 
> +
> +bridge {
> +compatible = "fsl,imx8mp-ldb";
> +clocks = < IMX8MP_CLK_MEDIA_LDB>;
> +clock-names = "ldb";
> +fsl,syscon = <_blk_ctrl>;
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +
> +ldb_from_lcdif2: endpoint {
> +remote-endpoint = <_to_ldb>;
> +};
> +};
> +
> +port@1 {
> +reg = <1>;
> +
> +ldb_lvds_ch0: endpoint {
> +remote-endpoint = <_to_lvdsx4panel>;
> +};
> +};
> +
> +port@2 {
> +reg = <2>;
> +
> +ldb_lvds_ch1: endpoint {
> +};
> +};
> +};
> +};
> -- 
> 2.35.1

Re: [PATCH] drm/amdgpu: Remove useless kfree

2022-04-22 Thread Alex Deucher

Applied.  Thanks!

Alex

On Fri, Apr 22, 2022 at 2:04 AM Haowen Bai  wrote:
>
> After alloc fail, we do not need to kfree.
>
> Signed-off-by: Haowen Bai 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> index ec709997c9c7..5fb3e69c04c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
> @@ -1849,7 +1849,6 @@ static int amdgpu_ras_realloc_eh_data_space(struct 
> amdgpu_device *adev,
> void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
>
> if (!bps) {
> -   kfree(bps);
> return -ENOMEM;
> }
>
> --
> 2.7.4
>

Re: [PATCH 2/2] drm/panel: simple: Add Startek KD070WVFPA043-C069A panel support

On Tue, Apr 19, 2022 at 09:56:25PM -0300, Fabio Estevam wrote:
> From: Heiko Schocher 
> 
> Add Startek KD070WVFPA043-C069A 7" TFT LCD panel support.
> 
> Signed-off-by: Heiko Schocher 
> Signed-off-by: Fabio Estevam 

> ---
>  drivers/gpu/drm/panel/panel-simple.c | 33 
>  1 file changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> b/drivers/gpu/drm/panel/panel-simple.c
> index a34f4198a534..ca8cd017821d 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -3311,6 +3311,36 @@ static const struct panel_desc tsd_tst043015cmhx = {
>   .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
>  };
>  
> +static const struct display_timing startek_kd070wvfpa_mode = {
> + .pixelclock = { 2520, 2720, 3050 },
> + .hactive = { 800, 800, 800 },
> + .hfront_porch = { 19, 44, 115 },
> + .hback_porch = { 5, 16, 101 },
> + .hsync_len = { 1, 2, 100 },
> + .vactive = { 480, 480, 480 },
> + .vfront_porch = { 5, 43, 67 },
> + .vback_porch = { 5, 5, 67 },
> + .vsync_len = { 1, 2, 66 },
> +};
> +
> +static const struct panel_desc startek_kd070wvfpa = {
> + .timings = _kd070wvfpa_mode,
> + .num_timings = 1,
> + .bpc = 8,
> + .size = {
> + .width = 152,
> + .height = 91,
> + },
> + .delay = {
> + .prepare = 20,
> + .enable = 200,
> + .disable = 200,
> + },
> + .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
> + .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> + .connector_type = DRM_MODE_CONNECTOR_DPI,
> +};

Please fix so order of startek_kd070wvfpa is the same order in
platform_of_match.

startek_kd070wvfpa is after tsd_tst043015cmhx above, but before
tsd_tst043015cmhx below.

Sam

> +
>  static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
>   .clock = 3,
>   .hdisplay = 800,
> @@ -3990,6 +4020,9 @@ static const struct of_device_id platform_of_match[] = {
>   }, {
>   .compatible = "starry,kr070pe2t",
>   .data = _kr070pe2t,
> + }, {
> + .compatible = "startek,kd070wvfpa",
> + .data = _kd070wvfpa,
>   }, {
>   .compatible = "team-source-display,tst043015cmhx",
>   .data = _tst043015cmhx,
> -- 
> 2.25.1

Re: [RFC 1/4] drm/msm/dpu: introduce a wb_idx to be used for writeback interfaces


Hi Dmitry

On 4/22/2022 3:37 AM, Dmitry Baryshkov wrote:

On Fri, 22 Apr 2022 at 04:59, Abhinav Kumar  wrote:




On 4/21/2022 5:22 PM, Dmitry Baryshkov wrote:

On Fri, 22 Apr 2022 at 02:07, Abhinav Kumar  wrote:


Hi Dmitry

Thanks for the review.

One question below.

On 4/21/2022 3:40 PM, Dmitry Baryshkov wrote:

On 21/04/2022 23:48, Abhinav Kumar wrote:

Using intf_idx even for writeback interfaces is confusing
because intf_idx is of type enum dpu_intf but the index used
for writeback is of type enum dpu_wb.

In addition, this makes it easier to separately check the
availability of the two as its possible that there are boards
which don't have any physical display connected but can still
work in writeback mode.

Signed-off-by: Abhinav Kumar 


Looks good, two minor issues bellow.

With them fixed, I'd even squash this patch into the corresponding patch
of the previous patchset.


---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c  | 62
+---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  4 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h   |  2 +-
3 files changed, 40 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9c12841..054d7e4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -962,7 +962,6 @@ static void
dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
int num_lm, num_ctl, num_pp, num_dsc;
unsigned int dsc_mask = 0;
-enum dpu_hw_blk_type blk_type;
int i;
if (!drm_enc) {
@@ -1044,17 +1043,11 @@ static void
dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
phys->hw_pp = dpu_enc->hw_pp[i];
phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
-if (dpu_encoder_get_intf_mode(_enc->base) ==
INTF_MODE_WB_LINE)
-blk_type = DPU_HW_BLK_WB;
-else
-blk_type = DPU_HW_BLK_INTF;
+if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
+phys->hw_intf = dpu_rm_get_intf(_kms->rm,
phys->intf_idx);
-if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) {
-if (blk_type == DPU_HW_BLK_INTF)
-phys->hw_intf = dpu_rm_get_intf(_kms->rm,
phys->intf_idx);
-else if (blk_type == DPU_HW_BLK_WB)
-phys->hw_wb = dpu_rm_get_wb(_kms->rm,
phys->intf_idx);
-}
+if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
+phys->hw_wb = dpu_rm_get_wb(_kms->rm, phys->wb_idx);


We also need a check for if (phus->hw_intf && phys->hw_wb) HERE


So there is an error if

1) Neither wb NOR intf are present
2) Both wb AND intf are present for the physical encoder?

The second check is okay for now to add but considering concurrent
writeback then that wouldn't assumption be wrong since both physical and
wb interfaces can go with the same encoder?


To the same encoder, but not to the same physical encoder. Here we
check the phys_enc parameters.


Ok got it, let me re-spin this RFC with patches 2 & 3 squashed.
Get the acks on them.

Then will absorb into WB series and re-post it.


Sounds like a good plan!










if (!phys->hw_intf && !phys->hw_wb) {
DPU_ERROR_ENC(dpu_enc,
@@ -1201,7 +1194,7 @@ static void dpu_encoder_virt_disable(struct
drm_encoder *drm_enc)
mutex_unlock(_enc->enc_lock);
}
-static enum dpu_intf dpu_encoder_get_intf_or_wb(struct dpu_mdss_cfg
*catalog,
+static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog,
enum dpu_intf_type type, u32 controller_id)
{
int i = 0;
@@ -1213,16 +1206,28 @@ static enum dpu_intf
dpu_encoder_get_intf_or_wb(struct dpu_mdss_cfg *catalog,
return catalog->intf[i].id;
}
}
-} else {
-for (i = 0; i < catalog->wb_count; i++) {
-if (catalog->wb[i].id == controller_id)
-return catalog->wb[i].id;
-}
}
return INTF_MAX;
}
+static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog,
+enum dpu_intf_type type, u32 controller_id)
+{
+int i = 0;
+
+if (type != INTF_WB)
+goto end;
+
+for (i = 0; i < catalog->wb_count; i++) {
+if (catalog->wb[i].id == controller_id)
+return catalog->wb[i].id;
+}
+
+end:
+return WB_MAX;


I'd return INTF_NONE/WB_NONE if the interface or WB unit was not found.

ack, i guess in that case even the places checking the return value of
this function need to be changed.


Yes, of course.


INTF_NONE/WB_NONE is not of enum dpu_intf or enum dpu_wb, its of type 
enum dpu_intf_mode


Do we want to add them to dpu_intf/dpu_wb with a -1 value OR leave it 
as-it-is.







+}
+
static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
struct

Re: [PATCH v2 4/7] vfio/mdev: Pass in a struct vfio_device * to vfio_dma_rw()

On Fri, Apr 22, 2022 at 01:50:00AM +, Tian, Kevin wrote:
> > From: Jason Gunthorpe 
> > Sent: Friday, April 22, 2022 12:29 AM
> > 
> > Every caller has a readily available vfio_device pointer, use that instead
> > of passing in a generic struct device. The struct vfio_device already
> > contains the group we need so this avoids complexity, extra refcountings,
> > and a confusing lifecycle model.
> 
> Using the same description as last patch leaves the impression that
> the two patches do the exactly same type of change. But this
> patch actually includes one more change to grab a reference on the
> container. This is worth an explanation.

How about this:

Every caller has a readily available vfio_device pointer, use that instead
of passing in a generic struct device. Change vfio_dma_rw() to take in the
struct vfio_device and move the container users that would have been held
by vfio_group_get_external_user_from_dev() to vfio_dma_rw() directly, like
vfio_pin/unpin_pages().

Thanks,
Jason

Re: [PATCH v9 2/4] drm/msm/dp: Support only IRQ_HPD and REPLUG interrupts for eDP


Hi Doug

On 4/22/2022 9:10 AM, Doug Anderson wrote:

Hi,

On Fri, Apr 22, 2022 at 9:05 AM Abhinav Kumar  wrote:


Hi Doug

For the lockdep error, the splat looks similar to what kuogee fixed
recently.

Can you please check if below patch is present in your tree?

https://patchwork.freedesktop.org/patch/481396/


Indeed I did have that in my tree already, but the lockdep splat is
still there. I think the problem is that we're now calling
dp_hpd_plug_handle() directly in dp_bridge_enable()

-Doug


Yes, now i understood this particular issue better and not sure how this 
wasn't caught. Perhaps some difference in the USE flags. Sankeerth didnt 
have lockdebug and thats why didnt hit this.


I have discussed with kuogee about why this change is needed and why 
this wasnt being done in get_modes().


It seems like originally, this was done for a quirk in the DP compliance 
equipment that it did not publish the fail safe mode ( even though some 
other modes were present ). Typically, any sink (as long as EDID read 
went through ) adds the 640x480 fail safe mode.


We could have done it in get_modes() even earlier but not sure how it 
was missed or was there some other reason.


Nonetheless, kuogee will post the change to move this to get_modes() 
shortly.


Thanks

Abhinav

Re: [PATCH resend v8 1/5] drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_mode_set()

2022-04-22 Thread Guido Günther

Hi,
On Tue, Apr 19, 2022 at 09:08:48AM +0800, Liu Ying wrote:
> The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp
> works with a Mixel MIPI DPHY + LVDS PHY combo to support either
> a MIPI DSI display or a LVDS display.  So, this patch calls
> phy_set_mode() from nwl_dsi_mode_set() to set PHY mode to MIPI DPHY
> explicitly.
> 
> Cc: Guido Günther 
> Cc: Robert Chiras 
> Cc: Martin Kepplinger 
> Cc: Andrzej Hajda 
> Cc: Neil Armstrong 
> Cc: Laurent Pinchart 
> Cc: Jonas Karlman 
> Cc: Jernej Skrabec 
> Cc: David Airlie 
> Cc: Daniel Vetter 
> Cc: NXP Linux Team 
> Signed-off-by: Liu Ying 
> ---
> v7->v8:
> * Resend with Andrzej's and Jernej's mail addressed updated.
> 
> v6->v7:
> * No change.
> 
> v5->v6:
> * Rebase the series upon v5.17-rc1.
> * Set PHY mode in ->mode_set() instead of ->pre_enable() in the nwl-dsi
>   bridge driver due to the rebase.
> * Drop Guido's R-b tag due to the rebase.
> 
> v4->v5:
> * No change.
> 
> v3->v4:
> * No change.
> 
> v2->v3:
> * No change.
> 
> v1->v2:
> * Add Guido's R-b tag.
> 
>  drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c 
> b/drivers/gpu/drm/bridge/nwl-dsi.c
> index d5945501a5ee..85bab7372af1 100644
> --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> @@ -666,6 +666,12 @@ static int nwl_dsi_mode_set(struct nwl_dsi *dsi)
>   return ret;
>   }
>  
> + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", ret);
> + goto uninit_phy;
> + }
> +
>   ret = phy_configure(dsi->phy, phy_cfg);
>   if (ret < 0) {
>   DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n",
> ret);

I can't currently test this but it still looks good so

Reviewed-by: Guido Günther 

Cheers,
 -- Guido

> -- 
> 2.25.1
>

Re: [PATCH v2 1/7] vfio: Make vfio_(un)register_notifier accept a vfio_device

On Fri, Apr 22, 2022 at 01:39:09AM +, Tian, Kevin wrote:
> > From: Jason Gunthorpe
> > Sent: Friday, April 22, 2022 12:29 AM
> > 
> > All callers have a struct vfio_device trivially available, pass it in
> > directly and avoid calling the expensive vfio_group_get_from_dev().
> > 
> > To support the unconverted kvmgt mdev driver add
> > mdev_legacy_get_vfio_device() which will return the vfio_device pointer
> > vfio_mdev.c puts in the drv_data.
> 
> stale comment

woops, done

Thanks,
Jason

Re: [PATCH] drm/nouveau/gsp: change gv100_gsp from global to static

2022-04-22 Thread Lyude Paul

Reviewed-by: Lyude Paul 

Will push upstream in a moment

On Thu, 2022-04-21 at 09:30 -0400, Tom Rix wrote:
> Smatch reports this issue
> gv100.c:46:1: warning: symbol 'gv100_gsp' was not declared. Should it be
> static?
> 
> gv100_gsp is only used in gv100.c so change its
> storage-class specifier to static.
> 
> Signed-off-by: Tom Rix 
> ---
>  drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c
> index 2ac7fc934c09..6c4ef62a746a 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.c
> @@ -42,7 +42,7 @@ gv100_gsp_nofw(struct nvkm_gsp *gsp, int ver, const struct
> nvkm_gsp_fwif *fwif)
> return 0;
>  }
>  
> -struct nvkm_gsp_fwif
> +static struct nvkm_gsp_fwif
>  gv100_gsp[] = {
> { -1, gv100_gsp_nofw, _gsp_flcn },
> {}

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

Re: [PATCH v2 00/48] ARM: PXA multiplatform support

On Tue, Apr 19, 2022 at 06:37:22PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann 
> 
> This revisits a series I sent a few years ago:
> 
> https://lore.kernel.org/lkml/20191018154052.1276506-1-a...@arndb.de/
> 
> All the other ARMv5 conversions are under way now, with
> OMAP1 being the only one still not in linux-next yet,
> and PXA completing the set.
> 
> Most of the patches are unchanged from before, furtunately
> the PXA code is fairly stable. I addressed Robert's comments,
> pulled in two patches from Dmitry, and added the last a the
> final four patches to finish off the multiplatform conversion.
> 
> I hope someone is left to test these on PXA: if this works,
> I'd like to merge it for 5.19. A git tree with these is avaialable
> for testing at
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=pxa-multiplatform-5.18
> 

Unfortunately that crashes for me when trying to boot from ide.
Bisect points to the last patch of the series.

Guenter

---
[1.403715] 8<--- cut here ---
[1.403848] Unable to handle kernel paging request at virtual address 
feeb000e
[1.404097] [feeb000e] *pgd=
[1.404400] Internal error: Oops: 805 [#1] PREEMPT ARM
[1.404648] Modules linked in:
[1.404890] CPU: 0 PID: 22 Comm: pccardd Not tainted 
5.18.0-rc3-next-20220422 #1
[1.405159] Hardware name: SHARP Borzoi
[1.405319] PC is at pcmcia_init_one+0xf8/0x27c
[1.405476] LR is at devres_add+0x40/0x6c
[1.405611] pc : []lr : []psr: a113
[1.405846] sp : c48a5d00  ip : c15f4220  fp : 6113
[1.406026] r10:   r9 : c48b000e  r8 : c48b
[1.406195] r7 : feeb  r6 : feeb000e  r5 : c15ec090  r4 : c15ec020
[1.406395] r3 : 0002  r2 :   r1 : c15f4200  r0 : feeb000e
[1.406615] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
[1.406847] Control: 7977  Table: a0004000  DAC: 0071
[1.407042] Register r0 information: 0-page vmalloc region starting at 
0xfee0 allocated at pci_reserve_io+0x0/0x38
[1.407453] Register r1 information: slab
[1.407721] Register r2 information: NULL pointer
[1.407885] Register r3 information: non-paged memory
[1.408047] Register r4 information: slab
[1.408179] Register r5 information: slab
[1.408310] Register r6 information: 0-page vmalloc region starting at 
0xfee0 allocated at pci_reserve_io+0x0/0x38
[1.408622] Register r7 information: 0-page vmalloc region starting at 
0xfee0 allocated at pci_reserve_io+0x0/0x38
[1.408941] Register r8 information: 0-page vmalloc region starting at 
0xc48b allocated at soc_pcmcia_add_one+0xf0/0x370
[1.409291] Register r9 information: 0-page vmalloc region starting at 
0xc48b allocated at soc_pcmcia_add_one+0xf0/0x370
[1.409617] Register r10 information: NULL pointer
[1.409768] Register r11 information: non-paged memory
[1.409924] Register r12 information: slab
[1.410066] Process pccardd (pid: 22, stack limit = 0x(ptrval))
[1.410268] Stack: (0xc48a5d00 to 0xc48a6000)
[1.410448] 5d00: c15ebb78  001a 0110  c0ad702c 
ff00051a c15ec090
[1.410694] 5d20: c0b713ec c0b713ec c12f6048 c0b644fc   
6113 c053f6bc
[1.410938] 5d40: c16b3bf0 c15efa88 c09d4e48 0001 0007 0200 
000f 
[1.411174] 5d60:   c0b71300 c0ad702c c0b644fc  
c15ec090 c0b713ec
[1.411410] 5d80: c0b9f980 c04491a8 c15ec090  6113 c15ec090 
c0b713ec c15ec090
[1.411644] 5da0: 0003 c0449530 c078a988 c0399c90 ff08 c0be4d7c 
c0b713ec c15ec090
[1.411882] 5dc0: 0003 c0b644fc   6113 c04496e0 
0001 c0b713ec
[1.412117] 5de0: c48a5e2c c15ec090 c0b644fc c0449aa0  c48a5e2c 
c04499fc c0be4d50
[1.412352] 5e00: c0b644fc c044702c  c12f407c c16b3bd4 c0ad702c 
c15ec090 0001
[1.412587] 5e20: c15ec0d4 c0449030 c15ec090 c15ec090 0001 c0ad702c 
c15ec090 c15ec090
[1.412827] 5e40: c0b77a9c c0448044 c15ec090  c12f5030 c04458bc 
0001 c009c720
[1.413065] 5e60: c15ec090 c04590e4 c15ec090 0002 c12f6048 c12f6150 
c15ec088 c0ad702c
[1.413307] 5e80: c15ec090 c15ec020 c12f6150 c12f6048 c12f6150 c15ec088 
c15ec090 c12f6160
[1.413551] 5ea0: 6113 c0540820  c12f6048 c12f6150 ffe4 
c12f6178 c12f6900
[1.413804] 5ec0: c0bb6828 c05409e8  0011 c12f6048  
c12f6150 c0ba35c8
[1.414050] 5ee0: c12f6178 c12f6900 c0bb6828 c074c3a8 c48a5f04 c0ad702c 
c48a5f10 c074c44c
[1.414294] 5f00: c098de10 c09acdc0 c12f4fa0 c48a5f1c 31d0 c0ad702c 
c12f6048 c12f6048
[1.414538] 5f20:  c12f6150 c0ba35c8 c0540af8 c12f6048  
c12f6150 c053dcd4
[1.414791] 5f40: c12f6048  0080 c12f6144 c12f6900 c053e704 
 c12f6178
[1.415037] 5f60: 30d0 c0ad702c c12f6900 c12f4fe0 c12f21a0 c053e36c

Re: AMD display drivers handling DRM CRTC color mgmt props

2022-04-22 Thread Harry Wentland

On 2022-04-22 10:28, Melissa Wen wrote:

On 04/21, Harry Wentland wrote:

On 2022-04-21 15:20, Melissa Wen wrote:

On 04/21, Harry Wentland wrote:

On 2022-04-21 10:37, Melissa Wen wrote:

Hi all,

I'm examining how DRM color management properties (degamma, ctm, gamma)
are applied to AMD display drivers. As far I could understand thanks
Nicholas documentation on amdgpu_dm/amdgpu_dm_color, DC drivers have
per-plane color correction features:

Hi Harry,

Wow, thanks so much for all details!

DC programs some of the color correction features pre-blending but
DRM/KMS has not per-plane color correction properties.

See this series from Uma Shankar for an RFC on how to introduce those
properties for 1D LUTs and CSC matrix:
https://patchwork.freedesktop.org/series/90826/

Bhanuprakash has a series of IGT tests for these properties:
https://patchwork.freedesktop.org/series/96895/

I've rebased these on amd-staging-drm-next and maintain a kernel and IGT
branch with these patches:
https://gitlab.freedesktop.org/hwentland/linux/-/tree/color-and-hdr
https://gitlab.freedesktop.org/hwentland/igt-gpu-tools/-/tree/color-and-hdr

We've had many discussions with Weston guys on this. In order to merge the
kernel properties we need a canonical userspace implementation that are
using it. Weston guys are working towards that but if you want to suggest a
different userspace to serve as that vehicle I'd be all ears. :)

Note that in order to show this all working we also need a Wayland Protocol
update.

See
https://gitlab.freedesktop.org/pq/color-and-hdr
https://gitlab.freedesktop.org/swick/wayland-protocols
https://gitlab.freedesktop.org/wayland/weston/-/issues/467

So, I've followed these discussions (until the issue on naming) because
initially I considered it addresses our current goals for color
correction. But after some discussions, what we are targeting is a 3D
LUT after blending (per-CRTC). I found past proposals on dri-devel
[1][2] to extend the DRM CRTC color management properties, but they
didn't move forward and were never applied.

They're stuck in limbo until we have an upstream userspace
implementation that's making use of them.

Yes... afaiu, the basic requirements for all of these changes are IGT
tests + open userspace usage, right?

Correct. See [1] and [2].

[1] https://www.kernel.org/doc/html/latest/gpu/drm-kms.html#requirements
[2]
https://www.kernel.org/doc/html/latest/gpu/drm-uapi.html#open-source-userspace-requirements

* - Input gamma LUT (de-normalized)
* - Input CSC (normalized)
* - Surface degamma LUT (normalized)
* - Surface CSC (normalized)
* - Surface regamma LUT (normalized)
* - Output CSC (normalized)
so DM is "adapting" those DRM per-CRTC properties to fit into three of
these color correction stages, which I guess are the surface stages:

* - Surface degamma LUT (normalized)
* - Surface CSC (normalized)
* - Surface regamma LUT (normalized)

I'm trying to understand what this mapping is doing. A comment mentions
that is not possible to do these color corrections after blending, so,
the same color correction pipe is performed on every plane before
blending? (is the surface the plane?) Does this adaptation affect the
expected output? Moreover, is there something that I misunderstood? :)

What's possible to do before and after blending has changed quite a bit
between DCN generations. We program the CRTC Gamma and CTM after blending.
See attached picture for a view relating the color bits between the DRM
interface, DC interface and DCN 3.0 HW blocks.

This picture is really enlightening, thanks!
You said it changes between generations, therefore, I can't consider the
DCN 2.x family follow the same mapping, right? If so, can you share the
main differences for a DCN 2.x regarding per-CRTC properties?

See attached diagram for DCN 2.0.

Thanks again!

That said, if the DRM color mgmt supports per-CRTC 3D LUT as the last

Where do you see 3D LUT support in DRM? Is there a new proposal that I've
missed?

So, it's exactly what I aim to work: a proposal to add 3D LUT to the
current range of DRM per-CRTC color properties. But I also need to
understand how this property will be mapped to AMD display once it
exists in the DRM framework.

Ah, nice to see. :)

One of the things that caught my attention after seeing the attached
picture is the position of 3D LUT. I was expecting to see the 3D LUT
correction after gamma correction. Is this position a particularity of
DCN 3.0 (that varies between hw) or was I expecting a wrong color
correction pipeline at all?

Before DCN 3.0 there was no 3D LUT after blending.

By comparing these diagrams, I'm curious: in case we have a per-CRTC 3D
LUT support on DRM, DCN 2.0 generations would initially map this
property as a pre-blending property on DPP (currently the same approach
for CTM, for example), right? But after we also have a per-plane color
management property, those per-CRTC property would be ignored? And how
about degamma

Re: [PATCH v7 1/4] drm/loongson: Add DRM Driver for Loongson 7A1000 bridge chip

2022-04-22 Thread kernel test robot

Hi Chenyang,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on v5.18-rc3 next-20220422]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/intel-lab-lkp/linux/commits/Chenyang-Li/drm-loongson-Add-DRM-Driver-for-Loongson-7A1000-bridge-chip/20220422-161914
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm-randconfig-s031-20220422 
(https://download.01.org/0day-ci/archive/20220423/202204230030.kzgmtgoq-...@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.4-dirty
# 
https://github.com/intel-lab-lkp/linux/commit/e9a9964d58e6cc797a113fa47f54583c10908d63
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Chenyang-Li/drm-loongson-Add-DRM-Driver-for-Loongson-7A1000-bridge-chip/20220422-161914
git checkout e9a9964d58e6cc797a113fa47f54583c10908d63
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross C=1 
CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' O=build_dir ARCH=arm 
SHELL=/bin/bash drivers/gpu/drm/loongson/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 


sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/loongson/loongson_drv.c:91:9: sparse: sparse: cast removes 
>> address space '__iomem' of expression
   drivers/gpu/drm/loongson/loongson_drv.c:99:5: sparse: sparse: symbol 
'loongson_modeset_init' was not declared. Should it be static?

vim +/__iomem +91 drivers/gpu/drm/loongson/loongson_drv.c

36  
37  static int loongson_device_init(struct drm_device *dev)
38  {
39  struct loongson_device *ldev = to_loongson_device(dev);
40  struct pci_dev *pdev = to_pci_dev(dev->dev);
41  struct pci_dev *gpu_pdev;
42  resource_size_t aper_base;
43  resource_size_t aper_size;
44  resource_size_t mmio_base;
45  resource_size_t mmio_size;
46  int ret;
47  
48  /* GPU MEM */
49  /* We need get 7A-gpu pci device information for ldev->gpu_pdev 
*/
50  /* dev->pdev save 7A-dc pci device information */
51  gpu_pdev = pci_get_device(PCI_VENDOR_ID_LOONGSON,
52PCI_DEVICE_ID_LOONGSON_GPU, NULL);
53  ret = pci_enable_device(gpu_pdev);
54  if (ret)
55  return ret;
56  pci_set_drvdata(gpu_pdev, dev);
57  
58  aper_base = pci_resource_start(gpu_pdev, 2);
59  aper_size = pci_resource_len(gpu_pdev, 2);
60  ldev->vram_start = aper_base;
61  ldev->vram_size = aper_size;
62  
63  if (!devm_request_mem_region(dev->dev, ldev->vram_start,
64   ldev->vram_size, "loongson_vram")) 
{
65  drm_err(dev, "Can't reserve VRAM\n");
66  return -ENXIO;
67  }
68  
69  /* DC MEM */
70  mmio_base = pci_resource_start(pdev, 0);
71  mmio_size = pci_resource_len(pdev, 0);
72  ldev->mmio = devm_ioremap(dev->dev, mmio_base, mmio_size);
73  if (!ldev->mmio) {
74  drm_err(dev, "Cannot map mmio region\n");
75  return -ENOMEM;
76  }
77  
78  if (!devm_request_mem_region(dev->dev, mmio_base,
79   mmio_size, "loongson_mmio")) {
80  drm_err(dev, "Can't reserve mmio registers\n");
81  return -ENOMEM;
82  }
83  
84  /* DC IO */
85  ldev->io = devm_ioremap(dev->dev, LS7A_CHIPCFG_REG_BASE, 0xf);
86  if (!ldev->io)
87  return -ENOMEM;
88  
89  ldev->num_crtc = 2;
90  
  > 91  drm_info(dev, "DC mmio base 0x%llx size 0x%llx io 0x%llx\n",
92   mmio_base, mmio_size, *(u64 *)ldev->io);
93  drm_info(dev, "GPU vram start = 0x%x size = 0x%x\n",
94   ldev->vram_start, ldev->vram_size);
95  
96  return 0;
97  }
98  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

Re: [PATCH v7 2/4] drm/loongson: Add GPIO and I2C driver for loongson drm.

2022-04-22 Thread kernel test robot

Hi Chenyang,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on v5.18-rc3 next-20220422]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/intel-lab-lkp/linux/commits/Chenyang-Li/drm-loongson-Add-DRM-Driver-for-Loongson-7A1000-bridge-chip/20220422-161914
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: riscv-allmodconfig 
(https://download.01.org/0day-ci/archive/20220423/202204230046.2fbntjrk-...@intel.com/config)
compiler: riscv64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# 
https://github.com/intel-lab-lkp/linux/commit/4a5b6ac99c37617e030a054ca431c5c9aab227b8
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review 
Chenyang-Li/drm-loongson-Add-DRM-Driver-for-Loongson-7A1000-bridge-chip/20220422-161914
git checkout 4a5b6ac99c37617e030a054ca431c5c9aab227b8
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross W=1 
O=build_dir ARCH=riscv SHELL=/bin/bash drivers/gpu/drm/loongson/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/loongson/loongson_encoder.c:10:27: warning: no previous 
>> prototype for 'loongson_bridge_detect' [-Wmissing-prototypes]
  10 | enum drm_connector_status loongson_bridge_detect(struct drm_bridge 
*bridge)
 |   ^~


vim +/loongson_bridge_detect +10 drivers/gpu/drm/loongson/loongson_encoder.c

 9  
  > 10  enum drm_connector_status loongson_bridge_detect(struct drm_bridge 
*bridge)
11  {
12  unsigned char start = 0x0;
13  struct i2c_msg msgs = {
14  .addr = DDC_ADDR,
15  .flags = 0,
16  .len = 1,
17  .buf = ,
18  };
19  
20  if (i2c_transfer(bridge->ddc, , 1) != 1)
21  return connector_status_disconnected;
22  else
23  return connector_status_connected;
24  }
25  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

[PATCH] drm/vmwgfx: Reserve fence slots on buffer objects in cotables

2022-04-22 Thread Zack Rusin

From: Zack Rusin 

The buffer objects created by cotables were missing fence reservations.
They are created from vmw_validation_res_validate which makes them miss
the ttm_eu_reserve_buffers which is called from vmw_validation_bo_reserve.

Cotables are the only resources which create a buffer object in the
create callback so make sure the code also reserves the slots.

Signed-off-by: Zack Rusin 
Fixes: c8d4c18bfbc4 ("dma-buf/drivers: make reserving a shared slot mandatory 
v4")
---
 drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c 
b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
index 16f986b6cbea..79b30dc9d825 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
@@ -478,6 +478,10 @@ static int vmw_cotable_resize(struct vmw_resource *res, 
size_t new_size)
vmw_bo_unreference(_buf);
res->id = vcotbl->type;
 
+   ret = dma_resv_reserve_fences(bo->base.resv, 1);
+   if (unlikely(ret))
+   goto out_wait;
+
/* Release the pin acquired in vmw_bo_init */
ttm_bo_unpin(bo);
 
-- 
2.32.0

Re: [PATCH] drm/vmwgfx: reserve fence slots on new resources

2022-04-22 Thread Zack Rusin

On Fri, 2022-04-22 at 11:21 +0200, Christian König wrote:
> Am 22.04.22 um 11:20 schrieb Christian König:
> > When resources are allocated dynamically during an IOCTL we need to
> > make sure
> > that a fence slot is reserved so that the resulting fence can be
> > added in the
> > end.
> 
> I should probably add that this is only compile tested.
> 
> Zack you should probably give it a try for your issue.

I think we're on the right track but cotables are the only objects that
create a bo in the create callback so we endup double reserving all the
other backup objects. If you don't mind I'd prefer to move the code to
localize the reservation to the problematic spot. I'll send it in a sec
(6d0fdf27e98a ("drm/vmwgfx: Reserve fence slots on buffer objects in
cotables") let me know if I can add a Co-developed-by: Christian König
 tag to it.

z

Re: [PATCH v9 2/4] drm/msm/dp: Support only IRQ_HPD and REPLUG interrupts for eDP

2022-04-22 Thread Doug Anderson

Hi,

On Fri, Apr 22, 2022 at 9:05 AM Abhinav Kumar  wrote:
>
> Hi Doug
>
> For the lockdep error, the splat looks similar to what kuogee fixed
> recently.
>
> Can you please check if below patch is present in your tree?
>
> https://patchwork.freedesktop.org/patch/481396/

Indeed I did have that in my tree already, but the lockdep splat is
still there. I think the problem is that we're now calling
dp_hpd_plug_handle() directly in dp_bridge_enable()

-Doug

Re: [PATCH v9 2/4] drm/msm/dp: Support only IRQ_HPD and REPLUG interrupts for eDP