Re: [PATCH v2 1/2] dt-bindings: arm: sunxi: Add binding for RenewWorldOutReach R16-Vista-E board
Hi Samuel, On Sun, Jul 3, 2022 at 1:17 PM Samuel Holland wrote: > On 6/15/22 4:38 AM, Suniel Mahesh wrote: > > Add a binding for the RenewWorldOutReach R16-Vista-E board based on > > allwinner R16. > > > > Signed-off-by: Christopher Vollo > > Signed-off-by: Jagan Teki > > Signed-off-by: Suniel Mahesh > > The primary author of the commit (the From:) should be the first signer, > unless > you are using Co-developed-by:. See the examples here: > > > https://www.kernel.org/doc/html/latest/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by > > > --- > > Changes for v2: > > - Add missing compatible string > > - insert missing signatures of contributors > > --- > > Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml > b/Documentation/devicetree/bindings/arm/sunxi.yaml > > index 95278a6a9a8e..52b8c9aba6f3 100644 > > --- a/Documentation/devicetree/bindings/arm/sunxi.yaml > > +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml > > @@ -787,6 +787,12 @@ properties: > >- const: allwinner,r7-tv-dongle > >- const: allwinner,sun5i-a10s > > > > + - description: RenewWorldOutreach R16-Vista-E > > +items: > > + - const: renewworldoutreach,r16-vista-e > > This vendor prefix should be documented. > Thanks for the suggestions, sending a v3. > > Regards, > Samuel > > > + - const: allwinner,sun8i-r16 > > + - const: allwinner,sun8i-a33 > > + > >- description: RerVision H3-DVK > > items: > >- const: rervision,h3-dvk > > > >
Re: [PATCH] drm/i915/gvt: Fix kernel-doc
On 2022.06.02 15:35:19 +0800, Jiapeng Chong wrote: > Fix the following W=1 kernel warnings: > > drivers/gpu/drm/i915/gvt/aperture_gm.c:308: warning: expecting prototype > for inte_gvt_free_vgpu_resource(). Prototype was for > intel_vgpu_free_resource() instead. > > drivers/gpu/drm/i915/gvt/aperture_gm.c:344: warning: expecting prototype > for intel_alloc_vgpu_resource(). Prototype was for > intel_vgpu_alloc_resource() instead. > > Reported-by: Abaci Robot > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/i915/gvt/aperture_gm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c > b/drivers/gpu/drm/i915/gvt/aperture_gm.c > index 557f3314291a..3b81a6d35a7b 100644 > --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c > +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c > @@ -298,7 +298,7 @@ static int alloc_resource(struct intel_vgpu *vgpu, > } > > /** > - * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU > + * intel_vgpu_free_resource() - free HW resource owned by a vGPU > * @vgpu: a vGPU > * > * This function is used to free the HW resource owned by a vGPU. > @@ -328,7 +328,7 @@ void intel_vgpu_reset_resource(struct intel_vgpu *vgpu) > } > > /** > - * intel_alloc_vgpu_resource - allocate HW resource for a vGPU > + * intel_vgpu_alloc_resource() - allocate HW resource for a vGPU > * @vgpu: vGPU > * @param: vGPU creation params > * > -- > 2.20.1.7.g153144c > Acked-by: Zhenyu Wang Thanks! signature.asc Description: PGP signature
Re: [PATCH 2/2] drm/i915/gvt: Fix kernel-doc
On 2022.05.24 16:37:32 +0800, Jiapeng Chong wrote: > Fix the following W=1 kernel warnings: > > drivers/gpu/drm/i915/gvt/mmio_context.c:560: warning: expecting > prototype for intel_gvt_switch_render_mmio(). Prototype was for > intel_gvt_switch_mmio() instead. > > Reported-by: Abaci Robot > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c > b/drivers/gpu/drm/i915/gvt/mmio_context.c > index c85bafe7539e..1c6e941c9666 100644 > --- a/drivers/gpu/drm/i915/gvt/mmio_context.c > +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c > @@ -546,7 +546,7 @@ static void switch_mmio(struct intel_vgpu *pre, > } > > /** > - * intel_gvt_switch_render_mmio - switch mmio context of specific engine > + * intel_gvt_switch_mmio - switch mmio context of specific engine > * @pre: the last vGPU that own the engine > * @next: the vGPU to switch to > * @engine: the engine > -- > 2.20.1.7.g153144c > Acked-by: Zhenyu Wang Thanks! signature.asc Description: PGP signature
Re: [PATCH 1/2] drm/i915/gvt: Fix kernel-doc
On 2022.05.24 16:37:33 +0800, Jiapeng Chong wrote: > Fix the following W=1 kernel warnings: > > drivers/gpu/drm/i915/gvt/handlers.c:3066: warning: expecting prototype > for intel_t_default_mmio_write(). Prototype was for > intel_vgpu_default_mmio_write() instead. > > Reported-by: Abaci Robot > Signed-off-by: Jiapeng Chong > --- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index beea5895e499..9c8dde079cb4 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -3052,7 +3052,7 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu > *vgpu, unsigned int offset, > } > > /** > - * intel_t_default_mmio_write - default MMIO write handler > + * intel_vgpu_default_mmio_write() - default MMIO write handler > * @vgpu: a vGPU > * @offset: access offset > * @p_data: write data buffer > -- > 2.20.1.7.g153144c > Sorry for late reply! Acked-by: Zhenyu Wang signature.asc Description: PGP signature
Re: [PATCH] drm/i915/gvt: fix typo in comment
On 2022.05.21 13:10:59 +0200, Julia Lawall wrote:
> Spelling mistake (triple letters) in comment.
> Detected with the help of Coccinelle.
>
> Signed-off-by: Julia Lawall
>
> ---
> drivers/gpu/drm/i915/gvt/gtt.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 9c5cc2800975..c919f14c4fcb 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -2341,7 +2341,7 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu
> *vgpu, unsigned int off,
> gvt_vgpu_err("fail to populate guest ggtt entry\n");
> /* guest driver may read/write the entry when partial
>* update the entry in this situation p2m will fail
> - * settting the shadow entry to point to a scratch page
> + * setting the shadow entry to point to a scratch page
>*/
> ops->set_pfn(, gvt->gtt.scratch_mfn);
> } else
>
Sorry for late reply!
Acked-by: Zhenyu Wang
signature.asc
Description: PGP signature
linux-next: manual merge of the drm tree with the drm-misc-fixes tree
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
between commit:
925b6e59138c ("Revert "drm/amdgpu: add drm buddy support to amdgpu"")
from the drm-misc-fixes tree and commit:
5e3f1e7729ec ("drm/amdgpu: fix start calculation in amdgpu_vram_mgr_new")
from the drm tree.
This is a mess :-( I have just reverted the above revert before mergin
the drm tree for today, please fix it up.
--
Cheers,
Stephen Rothwell
pgpQ67FzucIPd.pgp
Description: OpenPGP digital signature
Re: [PATCH v5 04/13] dt-bindings: memory-controllers: add canaan k210 sram controller
On 7/11/22 04:39, conor.doo...@microchip.com wrote:
> Damien, Krzysztof,
>
> I know this particular version has not been posted for all that
> long, but this binding is (functionally) unchanged for a few
> versions now. Are you happy with this approach Damien?
> U-Boot only cares about the compatible & the clocks property,
> not the regs etc.
>
> I (lazily) tested it in U-Boot with the following diff:
If both the kernel and u-boot still work as expected with this change, I
am OK with it.
>
> diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
> index 3cc8379133..314db88340 100644
> --- a/arch/riscv/dts/k210.dtsi
> +++ b/arch/riscv/dts/k210.dtsi
> @@ -82,11 +82,14 @@
>
> sram: memory@8000 {
> device_type = "memory";
> + reg = <0x8000 0x40>, /* sram0 4 MiB */
> + <0x8040 0x20>, /* sram1 2 MiB */
> + <0x8060 0x20>; /* aisram 2 MiB */
> + u-boot,dm-pre-reloc;
> + };
> +
> + sram_controller: memory-controller {
> compatible = "canaan,k210-sram";
> - reg = <0x8000 0x40>,
> - <0x8040 0x20>,
> - <0x8060 0x20>;
> - reg-names = "sram0", "sram1", "aisram";
> clocks = < K210_CLK_SRAM0>,
> < K210_CLK_SRAM1>,
> < K210_CLK_AI>;
>
> If so, could you queue this for 5.20 please Krzysztof, unless
> you've got concerns about it?
>
> Thanks,
> Conor.
>
> On 05/07/2022 22:52, Conor Dooley wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
>> content is safe
>>
>> From: Conor Dooley
>>
>> The k210 U-Boot port has been using the clocks defined in the
>> devicetree to bring up the board's SRAM, but this violates the
>> dt-schema. As such, move the clocks to a dedicated node with
>> the same compatible string & document it.
>>
>> Signed-off-by: Conor Dooley
>> ---
>> .../memory-controllers/canaan,k210-sram.yaml | 52 +++
>> 1 file changed, 52 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml
>> b/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml
>> new file mode 100644
>> index ..f81fb866e319
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml
>> @@ -0,0 +1,52 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Canaan K210 SRAM memory controller
>> +
>> +description:
>> + The Canaan K210 SRAM memory controller is responsible for the system's 8
>> MiB
>> + of SRAM. The controller is initialised by the bootloader, which configures
>> + its clocks, before OS bringup.
>> +
>> +maintainers:
>> + - Conor Dooley
>> +
>> +properties:
>> + compatible:
>> +enum:
>> + - canaan,k210-sram
>> +
>> + clocks:
>> +minItems: 1
>> +items:
>> + - description: sram0 clock
>> + - description: sram1 clock
>> + - description: aisram clock
>> +
>> + clock-names:
>> +minItems: 1
>> +items:
>> + - const: sram0
>> + - const: sram1
>> + - const: aisram
>> +
>> +required:
>> + - compatible
>> + - clocks
>> + - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> +#include
>> +memory-controller {
>> +compatible = "canaan,k210-sram";
>> +clocks = < K210_CLK_SRAM0>,
>> + < K210_CLK_SRAM1>,
>> + < K210_CLK_AI>;
>> +clock-names = "sram0", "sram1", "aisram";
>> +};
>> --
>> 2.37.0
>>
>
--
Damien Le Moal
Western Digital Research
Re: [RFC PATCH 2/3] drm/bridge: ti-sn65dsi86: fetch bpc using drm_atomic_state
Hi Dmitry,
Thank you for the patch.
On Sun, Jul 10, 2022 at 09:45:35PM +0300, Dmitry Baryshkov wrote:
> Rather than reading the pdata->connector directly, fetch the connector
> using drm_atomic_state. This allows us to make pdata->connector optional
> (and thus supporting DRM_BRIDGE_ATTACH_NO_CONNECTOR).
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20 ++--
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 01171547f638..df08207d6223 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -779,9 +779,9 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86
> *pdata)
> regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
> }
>
> -static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
> +static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
> {
> - if (pdata->connector->display_info.bpc <= 6)
> + if (connector->display_info.bpc <= 6)
> return 18;
> else
> return 24;
> @@ -796,7 +796,7 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
> 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
> };
>
> -static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
> +static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata,
> unsigned int bpp)
> {
> unsigned int bit_rate_khz, dp_rate_mhz;
> unsigned int i;
> @@ -804,7 +804,7 @@ static int ti_sn_bridge_calc_min_dp_rate_idx(struct
> ti_sn65dsi86 *pdata)
> >bridge.encoder->crtc->state->adjusted_mode;
>
> /* Calculate minimum bit rate based on our pixel clock. */
> - bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
> + bit_rate_khz = mode->clock * bpp;
>
> /* Calculate minimum DP data rate, taking 80% as per DP spec */
> dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
> @@ -1016,12 +1016,19 @@ static void ti_sn_bridge_atomic_enable(struct
> drm_bridge *bridge,
> struct drm_bridge_state
> *old_bridge_state)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
> + struct drm_connector *connector;
> const char *last_err_str = "No supported DP rate";
> unsigned int valid_rates;
> int dp_rate_idx;
> unsigned int val;
> int ret = -EINVAL;
> int max_dp_lanes;
> + unsigned int bpp;
> +
> + connector =
> drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
> + bridge->encoder);
> + if (!connector)
As Sam mentioned, a dev_err() would be good here if you think this can
happen. If there's no risk that connector will be null, you could drop
the check.
> + return;
>
> max_dp_lanes = ti_sn_get_max_lanes(pdata);
> pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
> @@ -1047,8 +1054,9 @@ static void ti_sn_bridge_atomic_enable(struct
> drm_bridge *bridge,
> drm_dp_dpcd_writeb(>aux, DP_EDP_CONFIGURATION_SET,
> DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
>
> + bpp = ti_sn_bridge_get_bpp(connector);
> /* Set the DP output format (18 bpp or 24 bpp) */
> - val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
> + val = (bpp == 18) ? BPP_18_RGB : 0;
You can drop the parentheses.
Reviewed-by: Laurent Pinchart
> regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
>
> /* DP lane config */
> @@ -1059,7 +1067,7 @@ static void ti_sn_bridge_atomic_enable(struct
> drm_bridge *bridge,
> valid_rates = ti_sn_bridge_read_valid_rates(pdata);
>
> /* Train until we run out of rates */
> - for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
> + for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
>dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
>dp_rate_idx++) {
> if (!(valid_rates & BIT(dp_rate_idx)))
--
Regards,
Laurent Pinchart
Re: [RFC PATCH 3/3] drm/bridge: ti-sn65dsi86: support DRM_BRIDGE_ATTACH_NO_CONNECTOR
Hi Dmitry,
Thank you for the patch.
On Sun, Jul 10, 2022 at 09:45:36PM +0300, Dmitry Baryshkov wrote:
> Now as the driver does not depend on pdata->connector, add support for
> attaching the bridge with DRM_BRIDGE_ATTACH_NO_CONNECTOR.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 15 +--
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index df08207d6223..9bca4615f71b 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -698,11 +698,6 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge,
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
> int ret;
>
> - if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
> - DRM_ERROR("Fix bridge driver to make connector optional!");
> - return -EINVAL;
> - }
> -
> pdata->aux.drm_dev = bridge->dev;
> ret = drm_dp_aux_register(>aux);
> if (ret < 0) {
> @@ -710,15 +705,15 @@ static int ti_sn_bridge_attach(struct drm_bridge
> *bridge,
> return ret;
> }
>
> - /* We never want the next bridge to *also* create a connector: */
> - flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
> -
> - /* Attach the next bridge */
> + /* Attach the next bridge, We never want the next bridge to *also*
> create a connector. */
s/bridge,/bridge./
I also would have wrapped this line.
Reviewed-by: Laurent Pinchart
> ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
> - >bridge, flags);
> + >bridge, flags |
> DRM_BRIDGE_ATTACH_NO_CONNECTOR);
> if (ret < 0)
> goto err_initted_aux;
>
> + if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
> + return 0;
> +
> pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
>pdata->bridge.encoder);
> if (IS_ERR(pdata->connector)) {
--
Regards,
Laurent Pinchart
drm-tip amdgpu not compiling, possible fix attached
Hi All,
I've been rebasing my backlight refactor on top of drm-tip to submit
a new version upstream and I noticed that drm-tip does not compile.
This is caused by a mismerge of:
commit 925b6e59138cefa47275c67891c65d48d3266d57 (drm-misc/for-linux-next-fixes,
drm-misc/drm-misc-fixes, drm-misc-fixes)Selvam
Date: Fri Jul 8 02:30:47 2022 -0700
Revert "drm/amdgpu: add drm buddy support to amdgpu"
This reverts commit c9cad937c0c58618fe5b0310fd539a854dc1ae95.
This is part of a revert of the following commits:
commit 708d19d9f362 ("drm/amdgpu: move internal vram_mgr function into the
C file")
commit 5e3f1e7729ec ("drm/amdgpu: fix start calculation in
amdgpu_vram_mgr_new")
commit c9cad937c0c5 ("drm/amdgpu: add drm buddy support to amdgpu")
[WHY]
Few users reported garbaged graphics as soon as x starts,
reverting until this can be resolved.
Signed-off-by: Arunpravin Paneer Selvam
>From drm-misc/for-linux-next-fixes / drm-misc-fixes
The attached patch on top of drm-tip fixes the mismerge. Note compile-tested
only!
If someone with more rerere experience then me can use this to fix things that
would be great.
Regards,
Hans
From 49aacb8d7b29c8d448ce469e66ddb33f8a19e552 Mon Sep 17 00:00:00 2001
From: Hans de Goede
Date: Sun, 10 Jul 2022 21:27:41 +0200
Subject: [PATCH] fix amdpgu mismerge
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 84 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 62 ---
2 files changed, 2 insertions(+), 144 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 254954aa983c..0a7611648573 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -48,35 +48,6 @@ to_amdgpu_device(struct amdgpu_vram_mgr *mgr)
return container_of(mgr, struct amdgpu_device, mman.vram_mgr);
}
-static inline struct drm_buddy_block *
-amdgpu_vram_mgr_first_block(struct list_head *list)
-{
- return list_first_entry_or_null(list, struct drm_buddy_block, link);
-}
-
-static inline bool amdgpu_is_vram_mgr_blocks_contiguous(struct list_head *head)
-{
- struct drm_buddy_block *block;
- u64 start, size;
-
- block = amdgpu_vram_mgr_first_block(head);
- if (!block)
- return false;
-
- while (head != block->link.next) {
- start = amdgpu_vram_mgr_block_start(block);
- size = amdgpu_vram_mgr_block_size(block);
-
- block = list_entry(block->link.next, struct drm_buddy_block, link);
- if (start + size != amdgpu_vram_mgr_block_start(block))
- return false;
- }
-
- return true;
-}
-
-
-
/**
* DOC: mem_info_vram_total
*
@@ -485,59 +456,8 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man,
}
spin_unlock(>lock);
- if (cur_size != size) {
- struct drm_buddy_block *block;
- struct list_head *trim_list;
- u64 original_size;
- LIST_HEAD(temp);
-
- trim_list = >blocks;
- original_size = vres->base.num_pages << PAGE_SHIFT;
-
- /*
- * If size value is rounded up to min_block_size, trim the last
- * block to the required size
- */
- if (!list_is_singular(>blocks)) {
- block = list_last_entry(>blocks, typeof(*block), link);
- list_move_tail(>link, );
- trim_list =
- /*
- * Compute the original_size value by subtracting the
- * last block size with (aligned size - original size)
- */
- original_size = amdgpu_vram_mgr_block_size(block) - (size - cur_size);
- }
-
- mutex_lock(>lock);
- drm_buddy_block_trim(mm,
- original_size,
- trim_list);
- mutex_unlock(>lock);
-
- if (!list_empty())
- list_splice_tail(trim_list, >blocks);
- }
-
- vres->base.start = 0;
- list_for_each_entry(block, >blocks, link) {
- unsigned long start;
-
- start = amdgpu_vram_mgr_block_start(block) +
- amdgpu_vram_mgr_block_size(block);
- start >>= PAGE_SHIFT;
-
- if (start > vres->base.num_pages)
- start -= vres->base.num_pages;
- else
- start = 0;
- vres->base.start = max(vres->base.start, start);
-
- vis_usage += amdgpu_vram_mgr_vis_size(adev, block);
- }
-
- if (amdgpu_is_vram_mgr_blocks_contiguous(>blocks))
- vres->base.placement |= TTM_PL_FLAG_CONTIGUOUS;
+ if (i == 1)
+ node->base.placement |= TTM_PL_FLAG_CONTIGUOUS;
if (adev->gmc.xgmi.connected_to_cpu)
node->base.bus.caching = ttm_cached;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
deleted file mode 100644
index 4b267bf1c5db..
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: MIT
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use,
[PATCH 9/9] drm/panel/panel-sitronix-st7701: Split GIP and init sequences
The ST7701 initialization sequence is well parametrized, split the GIP
programming sequence, which is fully custom completely undocumented
TFT matrix specific magic register programming sequence into separate
callback so other TFT matrix definitions can add their own GIP sequence.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 20 +++
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index bf7237c1abcc..843495d607d5 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -107,6 +107,8 @@ enum op_bias {
OP_BIAS_MAX
};
+struct st7701;
+
struct st7701_panel_desc {
const struct drm_display_mode *mode;
unsigned int lanes;
@@ -129,6 +131,9 @@ struct st7701_panel_desc {
const u16 t2d_ns; /* T2D in ns */
const u16 t3d_ns; /* T3D in ns */
const bool eot_en;
+
+ /* GIP sequence, fully custom and undocumented. */
+ void(*gip_sequence)(struct st7701 *st7701);
};
struct st7701 {
@@ -297,7 +302,10 @@ static void st7701_init_sequence(struct st7701 *st7701)
ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1,
DSI_CMD2_BK1_MIPISET1_ONES |
(desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0));
+}
+static void ts8550b_gip_sequence(struct st7701 *st7701)
+{
/**
* ST7701_SPEC_V1.2 is unable to provide enough information above this
* specific command sequence, so grab the same from vendor BSP driver.
@@ -319,10 +327,6 @@ static void st7701_init_sequence(struct st7701 *st7701)
ST7701_DSI(st7701, 0xEC, 0x00, 0x00);
ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
-
- /* disable Command2 */
- ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
- 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);
}
static int st7701_prepare(struct drm_panel *panel)
@@ -343,6 +347,13 @@ static int st7701_prepare(struct drm_panel *panel)
st7701_init_sequence(st7701);
+ if (st7701->desc->gip_sequence)
+ st7701->desc->gip_sequence(st7701);
+
+ /* Disable Command2 */
+ ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
+ 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE);
+
return 0;
}
@@ -518,6 +529,7 @@ static const struct st7701_panel_desc ts8550b_desc = {
.t2d_ns = 1600,
.t3d_ns = 10400,
.eot_en = true,
+ .gip_sequence = ts8550b_gip_sequence,
};
static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
--
2.35.1
[PATCH 8/9] drm/panel/panel-sitronix-st7701: Parametrize voltage and timing
Instead of hard-coding TFT matrix voltage and timing settings, which can
even lead to permanent TFT matrix damage, parametrize them in TFT matrix
descriptor.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 155 ++
1 file changed, 127 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 177180f1c2c8..bf7237c1abcc 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -79,30 +79,34 @@
#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
/* Command2, BK1 bytes */
-#define DSI_CMD2_BK1_VRHA_SET 0x45
-#define DSI_CMD2_BK1_VCOM_SET 0x13
-#define DSI_CMD2_BK1_VGHSS_SET GENMASK(2, 0)
+#define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
+#define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
+#define DSI_CMD2_BK1_VGHSS_MASKGENMASK(3, 0)
#define DSI_CMD2_BK1_TESTCMD_VAL BIT(7)
-#define DSI_VGLS_DEFAULT BIT(6)
-#define DSI_VGLS_SEL GENMASK(2, 0)
-#define DSI_CMD2_BK1_VGLS_SET (DSI_VGLS_DEFAULT | DSI_VGLS_SEL)
-#define DSI_PWCTLR1_AP BIT(7) /* Gamma OP bias, max */
-#define DSI_PWCTLR1_APIS BIT(2) /* Source OP input bias, min */
-#define DSI_PWCTLR1_APOS BIT(0) /* Source OP output bias, min */
-#define DSI_CMD2_BK1_PWCTLR1_SET (DSI_PWCTLR1_AP | DSI_PWCTLR1_APIS | \
- DSI_PWCTLR1_APOS)
-#define DSI_PWCTLR2_AVDD BIT(5) /* AVDD 6.6v */
-#define DSI_PWCTLR2_AVCL 0x0/* AVCL -4.4v */
-#define DSI_CMD2_BK1_PWCTLR2_SET (DSI_PWCTLR2_AVDD | DSI_PWCTLR2_AVCL)
-#define DSI_SPD1_T2D BIT(3)
-#define DSI_CMD2_BK1_SPD1_SET (GENMASK(6, 4) | DSI_SPD1_T2D)
-#define DSI_CMD2_BK1_SPD2_SET DSI_CMD2_BK1_SPD1_SET
-#define DSI_MIPISET1_EOT_ENBIT(3)
-#define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN)
+#define DSI_CMD2_BK1_VGLS_ONES BIT(6)
+#define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
+#define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6)
+#define DSI_CMD2_BK1_PWRCTRL1_APIS_MASKGENMASK(3, 2)
+#define DSI_CMD2_BK1_PWRCTRL1_APOS_MASKGENMASK(1, 0)
+#define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASKGENMASK(5, 4)
+#define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASKGENMASK(1, 0)
+#define DSI_CMD2_BK1_SPD1_ONES_MASKGENMASK(6, 4)
+#define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
+#define DSI_CMD2_BK1_SPD2_ONES_MASKGENMASK(6, 4)
+#define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
+#define DSI_CMD2_BK1_MIPISET1_ONES BIT(7)
+#define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3)
#define CFIELD_PREP(_mask, _val) \
(((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))
+enum op_bias {
+ OP_BIAS_OFF = 0,
+ OP_BIAS_MIN,
+ OP_BIAS_MIDDLE,
+ OP_BIAS_MAX
+};
+
struct st7701_panel_desc {
const struct drm_display_mode *mode;
unsigned int lanes;
@@ -113,6 +117,18 @@ struct st7701_panel_desc {
const u8pv_gamma[16]; /* Positive voltage gamma control */
const u8nv_gamma[16]; /* Negative voltage gamma control */
const u8nlinv; /* Inversion selection */
+ const u32 vop_uv; /* Vop in uV */
+ const u32 vcom_uv;/* Vcom in uV */
+ const u16 vgh_mv; /* Vgh in mV */
+ const s16 vgl_mv; /* Vgl in mV */
+ const u16 avdd_mv;/* Avdd in mV */
+ const s16 avcl_mv;/* Avcl in mV */
+ const enum op_bias gamma_op_bias;
+ const enum op_bias input_op_bias;
+ const enum op_bias output_op_bias;
+ const u16 t2d_ns; /* T2D in ns */
+ const u16 t3d_ns; /* T3D in ns */
+ const bool eot_en;
};
struct st7701 {
@@ -142,6 +158,31 @@ static inline int st7701_dsi_write(struct st7701 *st7701,
const void *seq,
st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \
}
+static u8 st7701_vgls_map(struct st7701 *st7701)
+{
+ const struct st7701_panel_desc *desc = st7701->desc;
+ struct {
+ s32 vgl;
+ u8 val;
+ } map[16] = {
+ { -7060, 0x0 }, { -7470, 0x1 },
+ { -7910, 0x2 }, { -8140, 0x3 },
+ { -8650, 0x4 }, { -8920, 0x5 },
+ { -9210, 0x6 }, { -9510, 0x7 },
+ { -9830, 0x8 }, { -10170, 0x9 },
+ { -10530, 0xa }, { -10910, 0xb },
+ { -11310, 0xc }, { -11730, 0xd },
+ { -12200, 0xe }, { -12690, 0xf }
+ };
+ int i;
+
+
[PATCH 3/9] drm/panel/panel-sitronix-st7701: Make voltage supplies common to ST7701
The ST7701 and ST7701S all have two voltage supplies, one for internal
logic and one for the TFT matrix driver. The supplies are not property
of the TFT matrix driver, so move them to common ST7701 code.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 29 +--
1 file changed, 7 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index fe9f1d2fcf44..48206d8acca7 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -90,8 +90,6 @@ struct st7701_panel_desc {
const struct drm_display_mode *mode;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
- const char *const *supply_names;
- unsigned int num_supplies;
unsigned int panel_sleep_delay;
};
@@ -100,7 +98,7 @@ struct st7701 {
struct mipi_dsi_device *dsi;
const struct st7701_panel_desc *desc;
- struct regulator_bulk_data *supplies;
+ struct regulator_bulk_data supplies[2];
struct gpio_desc *reset;
unsigned int sleep_delay;
};
@@ -200,7 +198,7 @@ static int st7701_prepare(struct drm_panel *panel)
gpiod_set_value(st7701->reset, 0);
- ret = regulator_bulk_enable(st7701->desc->num_supplies,
+ ret = regulator_bulk_enable(ARRAY_SIZE(st7701->supplies),
st7701->supplies);
if (ret < 0)
return ret;
@@ -253,7 +251,7 @@ static int st7701_unprepare(struct drm_panel *panel)
*/
msleep(st7701->sleep_delay);
- regulator_bulk_disable(st7701->desc->num_supplies, st7701->supplies);
+ regulator_bulk_disable(ARRAY_SIZE(st7701->supplies), st7701->supplies);
return 0;
}
@@ -309,17 +307,10 @@ static const struct drm_display_mode ts8550b_mode = {
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
};
-static const char * const ts8550b_supply_names[] = {
- "VCC",
- "IOVCC",
-};
-
static const struct st7701_panel_desc ts8550b_desc = {
.mode = _mode,
.lanes = 2,
.format = MIPI_DSI_FMT_RGB888,
- .supply_names = ts8550b_supply_names,
- .num_supplies = ARRAY_SIZE(ts8550b_supply_names),
.panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
};
@@ -327,7 +318,7 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
{
const struct st7701_panel_desc *desc;
struct st7701 *st7701;
- int ret, i;
+ int ret;
st7701 = devm_kzalloc(>dev, sizeof(*st7701), GFP_KERNEL);
if (!st7701)
@@ -339,16 +330,10 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
dsi->format = desc->format;
dsi->lanes = desc->lanes;
- st7701->supplies = devm_kcalloc(>dev, desc->num_supplies,
- sizeof(*st7701->supplies),
- GFP_KERNEL);
- if (!st7701->supplies)
- return -ENOMEM;
-
- for (i = 0; i < desc->num_supplies; i++)
- st7701->supplies[i].supply = desc->supply_names[i];
+ st7701->supplies[0].supply = "VCC";
+ st7701->supplies[1].supply = "IOVCC";
- ret = devm_regulator_bulk_get(>dev, desc->num_supplies,
+ ret = devm_regulator_bulk_get(>dev, ARRAY_SIZE(st7701->supplies),
st7701->supplies);
if (ret < 0)
return ret;
--
2.35.1
[PATCH 1/9] drm/panel/panel-sitronix-st7701: Make DSI mode flags common to ST7701
The ST7701 and ST7701S are TFT matrix drivers with integrated multi
protocol decoder capable of DSI/DPI/SPI input and 480x360...864 line
TFT matrix output. Currently the only supported input is DSI.
The protocol decoder is separate from the TFT matrix driver and is
always capable of handling all of DSI non-burst mode with sync pulses
or sync events as well as DSI burst mode.
Move the DSI mode configuration from TFT matrix driver properties to
common ST7701 code, because this is common to all TFT matrices.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 320a2a8fd459..90b0e90eb6e2 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -89,7 +89,6 @@
struct st7701_panel_desc {
const struct drm_display_mode *mode;
unsigned int lanes;
- unsigned long flags;
enum mipi_dsi_pixel_format format;
const char *const *supply_names;
unsigned int num_supplies;
@@ -318,7 +317,6 @@ static const char * const ts8550b_supply_names[] = {
static const struct st7701_panel_desc ts8550b_desc = {
.mode = _mode,
.lanes = 2,
- .flags = MIPI_DSI_MODE_VIDEO,
.format = MIPI_DSI_FMT_RGB888,
.supply_names = ts8550b_supply_names,
.num_supplies = ARRAY_SIZE(ts8550b_supply_names),
@@ -336,7 +334,7 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
return -ENOMEM;
desc = of_device_get_match_data(>dev);
- dsi->mode_flags = desc->flags;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
dsi->format = desc->format;
dsi->lanes = desc->lanes;
--
2.35.1
[PATCH 5/9] drm/panel/panel-sitronix-st7701: Infer vertical line count from TFT mode
The vertical line count is a property of the TFT matrix. Currently the
driver hard-codes content of this register to specific value which is
only compatible with one TFT matrix, likely the TS8550B one.
Calculate the vertical line count from the mode instead.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 26 ++-
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index becf205c8ea8..57388b1d516f 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -8,6 +8,7 @@
#include
#include
+#include
#include
#include
#include
@@ -68,11 +69,9 @@
#define DSI_CMD2_BK0_GAMCTRL_VC247_MASKGENMASK(5, 0)
#define DSI_CMD2_BK0_GAMCTRL_VC251_MASKGENMASK(5, 0)
#define DSI_CMD2_BK0_GAMCTRL_VC255_MASKGENMASK(4, 0)
-#define DSI_LINESET_LINE 0x69
-#define DSI_LINESET_LDE_EN BIT(7)
-#define DSI_LINESET_LINEDELTA GENMASK(1, 0)
-#define DSI_CMD2_BK0_LNESET_B1 DSI_LINESET_LINEDELTA
-#define DSI_CMD2_BK0_LNESET_B0 (DSI_LINESET_LDE_EN | DSI_LINESET_LINE)
+#define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
+#define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7)
+#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
#define DSI_INVSEL_DEFAULT GENMASK(5, 4)
#define DSI_INVSEL_NLINV GENMASK(2, 0)
#define DSI_INVSEL_RTNIGENMASK(2, 1)
@@ -148,6 +147,8 @@ static void st7701_init_sequence(struct st7701 *st7701)
{
const struct st7701_panel_desc *desc = st7701->desc;
const struct drm_display_mode *mode = desc->mode;
+ const u8 linecount8 = mode->vdisplay / 8;
+ const u8 linecountrem2 = (mode->vdisplay % 8) / 2;
ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
@@ -165,8 +166,21 @@ static void st7701_init_sequence(struct st7701 *st7701)
desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma));
mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL,
desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma));
+ /*
+* Vertical line count configuration:
+* Line[6:0]: select number of vertical lines of the TFT matrix in
+*multiples of 8 lines
+* LDE_EN: enable sub-8-line granularity line count
+* Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected
+* using Line[6:0]
+*
+* Total number of vertical lines:
+* LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0)
+*/
ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
- DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1);
+ FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) |
+ (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0),
+ FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2));
ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
DSI_CMD2_BK0_PORCTRL_B0(mode),
DSI_CMD2_BK0_PORCTRL_B1(mode));
--
2.35.1
[PATCH 7/9] drm/panel/panel-sitronix-st7701: Infer horizontal pixel count from TFT mode
The horizontal pixel count is a property of the TFT matrix. Currently the
driver hard-codes content of this register to specific value which is
only compatible with one TFT matrix, likely the TS8550B one.
Calculate the horizontal pixel count from the mode instead.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 21 +--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 42e46e804146..177180f1c2c8 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -74,11 +74,9 @@
#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
-#define DSI_INVSEL_DEFAULT GENMASK(5, 4)
-#define DSI_INVSEL_NLINV GENMASK(2, 0)
-#define DSI_INVSEL_RTNIGENMASK(2, 1)
-#define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI
-#define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV)
+#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4)
+#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
+#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
/* Command2, BK1 bytes */
#define DSI_CMD2_BK1_VRHA_SET 0x45
@@ -114,6 +112,7 @@ struct st7701_panel_desc {
/* TFT matrix driver configuration, panel specific. */
const u8pv_gamma[16]; /* Positive voltage gamma control */
const u8nv_gamma[16]; /* Negative voltage gamma control */
+ const u8nlinv; /* Inversion selection */
};
struct st7701 {
@@ -186,8 +185,17 @@ static void st7701_init_sequence(struct st7701 *st7701)
mode->vtotal - mode->vsync_end),
FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK,
mode->vsync_start - mode->vdisplay));
+ /*
+* Horizontal pixel count configuration:
+* PCLK = 512 + (RTNI[4:0] * 16)
+* The PCLK is number of pixel clock per line, which matches
+* mode htotal. The minimum is 512 PCLK.
+*/
ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL,
- DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1);
+ DSI_CMD2_BK0_INVSEL_ONES_MASK |
+ FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv),
+ FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK,
+ DIV_ROUND_UP(mode->htotal, 16)));
/* Command2, BK1 */
ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
@@ -410,6 +418,7 @@ static const struct st7701_panel_desc ts8550b_desc = {
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
},
+ .nlinv = 7,
};
static int st7701_dsi_probe(struct mipi_dsi_device *dsi)
--
2.35.1
[PATCH 6/9] drm/panel/panel-sitronix-st7701: Adjust porch control bitfield name
Define DSI_CMD2_BK0_PORCTRL_VBP_MASK and DSI_CMD2_BK0_PORCTRL_VFP_MASK and move the vertical back and front porch calculation from macros into the st7701_init_sequence() function, so it is clear what this does. No functional change. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 57388b1d516f..42e46e804146 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -72,13 +72,13 @@ #define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) #define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) +#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) +#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) #define DSI_INVSEL_DEFAULT GENMASK(5, 4) #define DSI_INVSEL_NLINV GENMASK(2, 0) #define DSI_INVSEL_RTNIGENMASK(2, 1) #define DSI_CMD2_BK0_INVSEL_B1 DSI_INVSEL_RTNI #define DSI_CMD2_BK0_INVSEL_B0 (DSI_INVSEL_DEFAULT | DSI_INVSEL_NLINV) -#define DSI_CMD2_BK0_PORCTRL_B0(m) ((m)->vtotal - (m)->vsync_end) -#define DSI_CMD2_BK0_PORCTRL_B1(m) ((m)->vsync_start - (m)->vdisplay) /* Command2, BK1 bytes */ #define DSI_CMD2_BK1_VRHA_SET 0x45 @@ -182,8 +182,10 @@ static void st7701_init_sequence(struct st7701 *st7701) (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, - DSI_CMD2_BK0_PORCTRL_B0(mode), - DSI_CMD2_BK0_PORCTRL_B1(mode)); + FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK, + mode->vtotal - mode->vsync_end), + FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, + mode->vsync_start - mode->vdisplay)); ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, DSI_CMD2_BK0_INVSEL_B0, DSI_CMD2_BK0_INVSEL_B1); -- 2.35.1
[PATCH 4/9] drm/panel/panel-sitronix-st7701: Make gamma correction TFT specific
The gamma correction values are specific to the TFT which is attached to
the ST7701 TFT matrix driver, move the gamma correction values from what
incorrectly looks like common init sequence into TFT matrix specific
settings.
While doing so, add macros which defined fields within the gamma register
file and a macro which mimics FIELD_PREP except works with constant
expressions.
Signed-off-by: Marek Vasut
Cc: Guido Günther
Cc: Jagan Teki
Cc: Laurent Pinchart
Cc: Linus Walleij
Cc: Sam Ravnborg
Cc: Thierry Reding
---
drivers/gpu/drm/panel/panel-sitronix-st7701.c | 96 +--
1 file changed, 89 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
index 48206d8acca7..becf205c8ea8 100644
--- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c
+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c
@@ -51,6 +51,23 @@
#define DSI_CMD2BKX_SEL_NONE 0x00
/* Command2, BK0 bytes */
+#define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6)
+#define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC108_MASKGENMASK(3, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC147_MASKGENMASK(3, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC175_MASKGENMASK(5, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC203_MASKGENMASK(3, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC231_MASKGENMASK(4, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC239_MASKGENMASK(4, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC247_MASKGENMASK(5, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC251_MASKGENMASK(5, 0)
+#define DSI_CMD2_BK0_GAMCTRL_VC255_MASKGENMASK(4, 0)
#define DSI_LINESET_LINE 0x69
#define DSI_LINESET_LDE_EN BIT(7)
#define DSI_LINESET_LINEDELTA GENMASK(1, 0)
@@ -86,11 +103,18 @@
#define DSI_MIPISET1_EOT_ENBIT(3)
#define DSI_CMD2_BK1_MIPISET1_SET (BIT(7) | DSI_MIPISET1_EOT_EN)
+#define CFIELD_PREP(_mask, _val) \
+ (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask))
+
struct st7701_panel_desc {
const struct drm_display_mode *mode;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
unsigned int panel_sleep_delay;
+
+ /* TFT matrix driver configuration, panel specific. */
+ const u8pv_gamma[16]; /* Positive voltage gamma control */
+ const u8nv_gamma[16]; /* Negative voltage gamma control */
};
struct st7701 {
@@ -122,7 +146,8 @@ static inline int st7701_dsi_write(struct st7701 *st7701,
const void *seq,
static void st7701_init_sequence(struct st7701 *st7701)
{
- const struct drm_display_mode *mode = st7701->desc->mode;
+ const struct st7701_panel_desc *desc = st7701->desc;
+ const struct drm_display_mode *mode = desc->mode;
ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00);
@@ -136,12 +161,10 @@ static void st7701_init_sequence(struct st7701 *st7701)
/* Command2, BK0 */
ST7701_DSI(st7701, DSI_CMD2BKX_SEL,
0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL);
- ST7701_DSI(st7701, DSI_CMD2_BK0_PVGAMCTRL, 0x00, 0x0E, 0x15, 0x0F,
- 0x11, 0x08, 0x08, 0x08, 0x08, 0x23, 0x04, 0x13, 0x12,
- 0x2B, 0x34, 0x1F);
- ST7701_DSI(st7701, DSI_CMD2_BK0_NVGAMCTRL, 0x00, 0x0E, 0x95, 0x0F,
- 0x13, 0x07, 0x09, 0x08, 0x08, 0x22, 0x04, 0x10, 0x0E,
- 0x2C, 0x34, 0x1F);
+ mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL,
+ desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma));
+ mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL,
+ desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma));
ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET,
DSI_CMD2_BK0_LNESET_B0, DSI_CMD2_BK0_LNESET_B1);
ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL,
@@ -312,6 +335,65 @@ static const struct st7701_panel_desc ts8550b_desc = {
.lanes = 2,
.format = MIPI_DSI_FMT_RGB888,
.panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */
+
+ .pv_gamma = {
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
+ CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
+
+
[PATCH 2/9] drm/panel/panel-sitronix-st7701: Enable DSI burst mode, LPM, non-continuous clock
The ST7701(S) is capable of DSI burst mode, which is more energy efficient than the non-burst modes. Make use of it. The ST7701(S) is capable of DSI non-continuous clock, since it sources the TFT matrix driver clock from internal clock source. The DSI non-continuous clock further reduce power utilization. The ST7701(S) uses DSI LPM for command transmissions, make sure this is configured correctly in the DSI mode flags. Signed-off-by: Marek Vasut Cc: Guido Günther Cc: Jagan Teki Cc: Laurent Pinchart Cc: Linus Walleij Cc: Sam Ravnborg Cc: Thierry Reding --- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 90b0e90eb6e2..fe9f1d2fcf44 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -334,7 +334,8 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) return -ENOMEM; desc = of_device_get_match_data(>dev); - dsi->mode_flags = MIPI_DSI_MODE_VIDEO; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; dsi->format = desc->format; dsi->lanes = desc->lanes; -- 2.35.1
Re: [RFC PATCH 3/3] drm/bridge: ti-sn65dsi86: support DRM_BRIDGE_ATTACH_NO_CONNECTOR
Hi Dmitry, On Sun, Jul 10, 2022 at 09:45:36PM +0300, Dmitry Baryshkov wrote: > Now as the driver does not depend on pdata->connector, add support for > attaching the bridge with DRM_BRIDGE_ATTACH_NO_CONNECTOR. > > Signed-off-by: Dmitry Baryshkov Looks good, Reviewed-by: Sam Ravnborg
Re: [RFC PATCH 2/3] drm/bridge: ti-sn65dsi86: fetch bpc using drm_atomic_state
Hi Dmitry,
On Sun, Jul 10, 2022 at 09:45:35PM +0300, Dmitry Baryshkov wrote:
> Rather than reading the pdata->connector directly, fetch the connector
> using drm_atomic_state. This allows us to make pdata->connector optional
> (and thus supporting DRM_BRIDGE_ATTACH_NO_CONNECTOR).
>
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20 ++--
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 01171547f638..df08207d6223 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -779,9 +779,9 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86
> *pdata)
> regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
> }
>
> -static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
> +static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
> {
> - if (pdata->connector->display_info.bpc <= 6)
> + if (connector->display_info.bpc <= 6)
> return 18;
> else
> return 24;
> @@ -796,7 +796,7 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
> 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
> };
>
> -static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
> +static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata,
> unsigned int bpp)
> {
> unsigned int bit_rate_khz, dp_rate_mhz;
> unsigned int i;
> @@ -804,7 +804,7 @@ static int ti_sn_bridge_calc_min_dp_rate_idx(struct
> ti_sn65dsi86 *pdata)
> >bridge.encoder->crtc->state->adjusted_mode;
>
> /* Calculate minimum bit rate based on our pixel clock. */
> - bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
> + bit_rate_khz = mode->clock * bpp;
>
> /* Calculate minimum DP data rate, taking 80% as per DP spec */
> dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
> @@ -1016,12 +1016,19 @@ static void ti_sn_bridge_atomic_enable(struct
> drm_bridge *bridge,
> struct drm_bridge_state
> *old_bridge_state)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
> + struct drm_connector *connector;
> const char *last_err_str = "No supported DP rate";
> unsigned int valid_rates;
> int dp_rate_idx;
> unsigned int val;
> int ret = -EINVAL;
> int max_dp_lanes;
> + unsigned int bpp;
> +
> + connector =
> drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
> + bridge->encoder);
> + if (!connector)
> + return;
It would be prudent with a dev_err() logging here as we do not expect to
fail.
I looked into something similar, but with a less elegant solution, and
could not convince myself that the display driver would create the
connector before ti_sn_bridge_atomic_enable() was called.
This is another reason why a dev_err would be nice - so tester could see
if this fails or not.
With the dev_err added:
Reviewed-by: Sam Ravnborg
>
> max_dp_lanes = ti_sn_get_max_lanes(pdata);
> pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
> @@ -1047,8 +1054,9 @@ static void ti_sn_bridge_atomic_enable(struct
> drm_bridge *bridge,
> drm_dp_dpcd_writeb(>aux, DP_EDP_CONFIGURATION_SET,
> DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
>
> + bpp = ti_sn_bridge_get_bpp(connector);
> /* Set the DP output format (18 bpp or 24 bpp) */
> - val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
> + val = (bpp == 18) ? BPP_18_RGB : 0;
> regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
>
> /* DP lane config */
> @@ -1059,7 +1067,7 @@ static void ti_sn_bridge_atomic_enable(struct
> drm_bridge *bridge,
> valid_rates = ti_sn_bridge_read_valid_rates(pdata);
>
> /* Train until we run out of rates */
> - for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
> + for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
>dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
>dp_rate_idx++) {
> if (!(valid_rates & BIT(dp_rate_idx)))
> --
> 2.35.1
Re: [RFC PATCH 1/3] drm/bridge: ti-sn65dsi86: switch to atomic ops
Hi Dmitry,
On Sun, Jul 10, 2022 at 09:45:34PM +0300, Dmitry Baryshkov wrote:
> Make ti-sn65dsi86 use atomic_enable / atomic_disable / atomic_pre_enable
> / atomic_post_disable rather than their non-atomic versions.
>
> Signed-off-by: Dmitry Baryshkov
a more or less identical patch was applied to drm-misc-next
the other day.
See d8b599bf625d1d818fdbb322a272fd2a5ea32e38.
Sam
> ---
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 8cad662de9bb..01171547f638 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -752,7 +752,8 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
> return MODE_OK;
> }
>
> -static void ti_sn_bridge_disable(struct drm_bridge *bridge)
> +static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state
> *old_bridge_state)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
>
> @@ -1011,7 +1012,8 @@ static int ti_sn_link_training(struct ti_sn65dsi86
> *pdata, int dp_rate_idx,
> return ret;
> }
>
> -static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> +static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
> +struct drm_bridge_state
> *old_bridge_state)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
> const char *last_err_str = "No supported DP rate";
> @@ -1080,7 +1082,8 @@ static void ti_sn_bridge_enable(struct drm_bridge
> *bridge)
> VSTREAM_ENABLE);
> }
>
> -static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
> +static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
> +struct drm_bridge_state
> *old_bridge_state)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
>
> @@ -1093,7 +1096,8 @@ static void ti_sn_bridge_pre_enable(struct drm_bridge
> *bridge)
> usleep_range(100, 110);
> }
>
> -static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
> +static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state
> *old_bridge_state)
> {
> struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
>
> @@ -1114,10 +1118,10 @@ static const struct drm_bridge_funcs
> ti_sn_bridge_funcs = {
> .attach = ti_sn_bridge_attach,
> .detach = ti_sn_bridge_detach,
> .mode_valid = ti_sn_bridge_mode_valid,
> - .pre_enable = ti_sn_bridge_pre_enable,
> - .enable = ti_sn_bridge_enable,
> - .disable = ti_sn_bridge_disable,
> - .post_disable = ti_sn_bridge_post_disable,
> + .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
> + .atomic_enable = ti_sn_bridge_atomic_enable,
> + .atomic_disable = ti_sn_bridge_atomic_disable,
> + .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
> };
>
> static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
> --
> 2.35.1
[RFC PATCH 3/3] drm/bridge: ti-sn65dsi86: support DRM_BRIDGE_ATTACH_NO_CONNECTOR
Now as the driver does not depend on pdata->connector, add support for
attaching the bridge with DRM_BRIDGE_ATTACH_NO_CONNECTOR.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index df08207d6223..9bca4615f71b 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -698,11 +698,6 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge,
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
int ret;
- if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
- DRM_ERROR("Fix bridge driver to make connector optional!");
- return -EINVAL;
- }
-
pdata->aux.drm_dev = bridge->dev;
ret = drm_dp_aux_register(>aux);
if (ret < 0) {
@@ -710,15 +705,15 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge,
return ret;
}
- /* We never want the next bridge to *also* create a connector: */
- flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
-
- /* Attach the next bridge */
+ /* Attach the next bridge, We never want the next bridge to *also*
create a connector. */
ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
- >bridge, flags);
+ >bridge, flags |
DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (ret < 0)
goto err_initted_aux;
+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
+ return 0;
+
pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
pdata->bridge.encoder);
if (IS_ERR(pdata->connector)) {
--
2.35.1
[RFC PATCH 2/3] drm/bridge: ti-sn65dsi86: fetch bpc using drm_atomic_state
Rather than reading the pdata->connector directly, fetch the connector
using drm_atomic_state. This allows us to make pdata->connector optional
(and thus supporting DRM_BRIDGE_ATTACH_NO_CONNECTOR).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 01171547f638..df08207d6223 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -779,9 +779,9 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86
*pdata)
regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
}
-static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
+static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
{
- if (pdata->connector->display_info.bpc <= 6)
+ if (connector->display_info.bpc <= 6)
return 18;
else
return 24;
@@ -796,7 +796,7 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
};
-static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
+static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata,
unsigned int bpp)
{
unsigned int bit_rate_khz, dp_rate_mhz;
unsigned int i;
@@ -804,7 +804,7 @@ static int ti_sn_bridge_calc_min_dp_rate_idx(struct
ti_sn65dsi86 *pdata)
>bridge.encoder->crtc->state->adjusted_mode;
/* Calculate minimum bit rate based on our pixel clock. */
- bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
+ bit_rate_khz = mode->clock * bpp;
/* Calculate minimum DP data rate, taking 80% as per DP spec */
dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
@@ -1016,12 +1016,19 @@ static void ti_sn_bridge_atomic_enable(struct
drm_bridge *bridge,
struct drm_bridge_state
*old_bridge_state)
{
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
+ struct drm_connector *connector;
const char *last_err_str = "No supported DP rate";
unsigned int valid_rates;
int dp_rate_idx;
unsigned int val;
int ret = -EINVAL;
int max_dp_lanes;
+ unsigned int bpp;
+
+ connector =
drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
+bridge->encoder);
+ if (!connector)
+ return;
max_dp_lanes = ti_sn_get_max_lanes(pdata);
pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
@@ -1047,8 +1054,9 @@ static void ti_sn_bridge_atomic_enable(struct drm_bridge
*bridge,
drm_dp_dpcd_writeb(>aux, DP_EDP_CONFIGURATION_SET,
DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
+ bpp = ti_sn_bridge_get_bpp(connector);
/* Set the DP output format (18 bpp or 24 bpp) */
- val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
+ val = (bpp == 18) ? BPP_18_RGB : 0;
regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
/* DP lane config */
@@ -1059,7 +1067,7 @@ static void ti_sn_bridge_atomic_enable(struct drm_bridge
*bridge,
valid_rates = ti_sn_bridge_read_valid_rates(pdata);
/* Train until we run out of rates */
- for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
+ for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
dp_rate_idx++) {
if (!(valid_rates & BIT(dp_rate_idx)))
--
2.35.1
[RFC PATCH 1/3] drm/bridge: ti-sn65dsi86: switch to atomic ops
Make ti-sn65dsi86 use atomic_enable / atomic_disable / atomic_pre_enable
/ atomic_post_disable rather than their non-atomic versions.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 8cad662de9bb..01171547f638 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -752,7 +752,8 @@ ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
return MODE_OK;
}
-static void ti_sn_bridge_disable(struct drm_bridge *bridge)
+static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state
*old_bridge_state)
{
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
@@ -1011,7 +1012,8 @@ static int ti_sn_link_training(struct ti_sn65dsi86
*pdata, int dp_rate_idx,
return ret;
}
-static void ti_sn_bridge_enable(struct drm_bridge *bridge)
+static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state
*old_bridge_state)
{
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
const char *last_err_str = "No supported DP rate";
@@ -1080,7 +1082,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
VSTREAM_ENABLE);
}
-static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
+static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state
*old_bridge_state)
{
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
@@ -1093,7 +1096,8 @@ static void ti_sn_bridge_pre_enable(struct drm_bridge
*bridge)
usleep_range(100, 110);
}
-static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
+static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
+struct drm_bridge_state
*old_bridge_state)
{
struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
@@ -1114,10 +1118,10 @@ static const struct drm_bridge_funcs ti_sn_bridge_funcs
= {
.attach = ti_sn_bridge_attach,
.detach = ti_sn_bridge_detach,
.mode_valid = ti_sn_bridge_mode_valid,
- .pre_enable = ti_sn_bridge_pre_enable,
- .enable = ti_sn_bridge_enable,
- .disable = ti_sn_bridge_disable,
- .post_disable = ti_sn_bridge_post_disable,
+ .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
+ .atomic_enable = ti_sn_bridge_atomic_enable,
+ .atomic_disable = ti_sn_bridge_atomic_disable,
+ .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
};
static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
--
2.35.1
[RFC PATCH 0/3] drm/bridge: ti-sn65dsi86: support DRM_BRIDGE_ATTACH_NO_CONNECTOR
An RFC (or rather RFT, Request-for-Testing) series adding support for DRM_BRIDGE_ATTACH_NO_CONNECTOR. Note, it was compile-tested only. This bridge is the last one used on the Qualcomm platforms (in upstream-supported devices) and thus it is the only bridge that prevents us from removing support for bridge-created connectors from MSM DSI code. Dmitry Baryshkov (3): drm/bridge: ti-sn65dsi86: switch to atomic ops drm/bridge: ti-sn65dsi86: fetch bpc using drm_atomic_state drm/bridge: ti-sn65dsi86: support DRM_BRIDGE_ATTACH_NO_CONNECTOR drivers/gpu/drm/bridge/ti-sn65dsi86.c | 55 +++ 1 file changed, 31 insertions(+), 24 deletions(-) -- 2.35.1
Re: [PATCH v11 20/24] arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a
> Wiadomość napisana przez Piotr Oniszczuk w dniu > 25.06.2022, o godz. 17:31: > > > >> Wiadomość napisana przez Peter Geis w dniu 25.06.2022, >> o godz. 16:00: >> >> >> The first issue you have is the TV isn't responding until the absolute >> end. > > I suspect this is because lack on idle gaps between cec commands sent from > board to tv. > Maybe TV sw. can't deal with consecutive commands without any idle between > them? > > It is interesting that disconnecting TV - so CEC line is driven only by board > - rock3a still don't have any idle gaps while rock3b (and radxa 4.19 bsp) has > them (very similar between 5.18mailine and 4.19 bsp). > > How this is possible that change I/O from m0->m1 impacts _timings_ on free > hanging CEC line? > >> This strikes me as a signal integrity issue. Do you have an >> oscilloscope (not a logic analyzer, you need voltages and ramp times) >> to compare the working vs non-working signals? Check both sides of the >> level shifter. > > Indeed - i will verify this with digital oscilloscope. Peter, fyi I got my oscilloscope and do measurements on hdmi cable cec line on: working rock3b and non-working rock3a. sw was exactly the same (same sd card; only dtb changed) Pls see measurements for: start pulse "0" pulse "1" pulse non-working rock3-a: http://warped.inet2.org/rock3a-one.png http://warped.inet2.org/rock3a-start.png http://warped.inet2.org/rock3a-zero.png working rock3-b http://warped.inet2.org/rock3b-one.png http://warped.inet2.org/rock3b-start.png http://warped.inet2.org/rock3b-zero.png Now i'm 99% sure issue is not hw related but sw (kernel)... br
Re: [PATCH v2 04/11] dt-bindings: display/msm: split qcom, mdss bindings
On 10/07/2022 19:54, Rob Herring wrote: On Sun, 10 Jul 2022 12:00:33 +0300, Dmitry Baryshkov wrote: Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added (optional) "core" clock added recently to the mdss driver - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/mdp5.txt | 30 +--- .../devicetree/bindings/display/msm/mdss.yaml | 161 ++ 2 files changed, 162 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/display/msm/mdss.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml The tree is based on linux-next (well, msm-next, which is a part of linux-next). -- With best wishes Dmitry
Re: [PATCH v2 04/11] dt-bindings: display/msm: split qcom, mdss bindings
On Sun, 10 Jul 2022 12:00:33 +0300, Dmitry Baryshkov wrote: > Split Mobile Display SubSystem (MDSS) root node bindings to the separate > yaml file. Changes to the existing (txt) schema: > - Added optional "vbif_nrt_phys" region used by msm8996 > - Made "bus" and "vsync" clocks optional (they are not used by some >platforms) > - Added (optional) "core" clock added recently to the mdss driver > - Added optional resets property referencing MDSS reset > - Defined child nodes pointing to corresponding reference schema. > - Dropped the "lut" clock. It was added to the schema by mistake (it is >a part of mdp4 schema, not the mdss). > > Signed-off-by: Dmitry Baryshkov > --- > .../devicetree/bindings/display/msm/mdp5.txt | 30 +--- > .../devicetree/bindings/display/msm/mdss.yaml | 161 ++ > 2 files changed, 162 insertions(+), 29 deletions(-) > create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/display/msm/mdss.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Re: [PATCH v2 1/2] dt-bindings: display: panel: Add Novatek NT35596S panel bindings
On Sat, 09 Jul 2022 22:11:35 +0800, MollySophia wrote: > Add documentation for "novatek,nt35596s" panel. > > Signed-off-by: MollySophia > --- > .../display/panel/novatek,nt35596s.yaml | 83 +++ > 1 file changed, 83 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/panel/novatek,nt35596s.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/panel/novatek,nt35596s.example.dtb: panel@0: 'reset-gpios' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/panel/novatek,nt35596s.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
VKMS driver Kernel 5.4 - vkms_vblank_simulate: vblank timer overrun
Hi Developers, I am seeing thrashing of errors print once Android kernel trying to enable SurfaceFlinger (swiftshader) stuff. [drm:drm_calc_timestamping_constants] *ERROR* crtc 32: Can't calculate constants, dotclock = 0! [ 19.985323][C0] vkms_vblank_simulate: vblank timer overrun [ 19.991839][C0] vkms_vblank_simulate: vblank timer overrun [ 19.998235][C0] vkms_vblank_simulate: vblank timer overrun [ 20.024009][C0] vkms_vblank_simulate: vblank timer overrun ... I am afraid I am new to all of these - I have access to Lauterbach debugger and can debug in code. I would love to get some perspective or pointers of areas I could look into. Other details: I was able to use Kernel 5.10 + VKMS + SwiftShader in Android 12 in Raspberry Pi 4. However, in my new dev board, I cant get all the gpio/pinctrl/sdcard drivers working in Kernel 5.10, I had to stay w/ 5.4. Thanks for all the help in advance. Mohd Yusuf Abdul Hamid
[PATCH -next] drm/amdgpu: double free error and freeing uninitialized null pointer
Fix two coverity warning's double free and and an uninitialized pointer
read. Both tmp and new are pointing at same address and both are freed
which leads to double free. Freeing tmp in the condition after new is
assigned with new address fixes the double free issue. new is not
initialized to null which also leads to a free on an uninitialized
pointer.
Coverity issue: 1518665 (uninitialized pointer read)
1518679 (double free)
Signed-off-by: Sebin Sebastian
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f3b3c688e4e7..d82fe0e1b06b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1660,7 +1660,7 @@ static ssize_t
amdgpu_reset_dump_register_list_write(struct file *f,
{
struct amdgpu_device *adev = (struct amdgpu_device
*)file_inode(f)->i_private;
char reg_offset[11];
- uint32_t *new, *tmp = NULL;
+ uint32_t *new = NULL, *tmp = NULL;
int ret, i = 0, len = 0;
do {
@@ -1692,17 +1692,19 @@ static ssize_t
amdgpu_reset_dump_register_list_write(struct file *f,
goto error_free;
}
ret = down_write_killable(>reset_domain->sem);
- if (ret)
+ if (ret) {
+ kfree(tmp);
goto error_free;
+ }
swap(adev->reset_dump_reg_list, tmp);
swap(adev->reset_dump_reg_value, new);
adev->num_regs = i;
up_write(>reset_domain->sem);
+ kfree(tmp);
ret = size;
error_free:
- kfree(tmp);
kfree(new);
return ret;
}
--
2.34.1
[pull] drm/msm: drm-msm-next-2022-07-10 for v5.20
Hi Dave & Daniel,
Here is main drm/msm pull for v5.20, description below and in tag
The following changes since commit b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3:
Linux 5.19-rc2 (2022-06-12 16:11:37 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/drm/msm.git tags/drm-msm-next-2022-07-10
for you to fetch changes up to cb77085b1f0a86ef9dfba86b5f3ed6c3340c2ea3:
drm/msm/dpu: Fix for non-visible planes (2022-07-08 08:10:58 -0700)
Next for v5.20
GPU:
- a619 support
- Fix for unclocked GMU register access
- Devcore dump enhancements
Core:
- client utilization via fdinfo support
- fix fence rollover issue
- gem: Lockdep false-positive warning fix
- gem: Switch to pfn mappings
DPU:
- constification of HW catalog
- support for using encoder as CRC source
- WB support on sc7180
- WB resolution fixes
DP:
- dropped custom bulk clock implementation
- made dp_bridge_mode_valid() return MODE_CLOCK_HIGH where applicable
- fix link retraining on resolution change
MDP5:
- MSM8953 perf data
HDMI:
- YAML'ification of schema
- dropped obsolete GPIO support
- misc cleanups
Abhinav Kumar (5):
drm/msm/dpu: limit wb modes based on max_mixer_width
drm/msm/dpu: add writeback support for sc7180
drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display()
drm/msm/dpu: fix maxlinewidth for writeback block
drm/msm/dpu: remove hard-coded linewidth limit for writeback
Dmitry Baryshkov (45):
drm/msm/dpu: use feature bit for LM combined alpha check
drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to hw_catalog
drm/msm/dpu: remove hwversion field from data structures
drm/msm/dpu: change catalog->perf to be a const pointer
drm/msm/dpu: change catalog->dma_cfg to be a const pointer
drm/msm/dpu: constify struct dpu_mdss_cfg
drm/msm/dpu: make dpu hardware catalog static const
drm/msm/dpu: dont_use IS_ERR_OR_NULL for encoder phys backends
drm/msm/dpu: drop enum msm_display_caps
drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link")
drm/msm/dp: set stream_pixel rate directly
drm/msm/dp: inline dp_power_clk_set_rate()
drm/msm/dp: rewrite dss_module_power to use bulk clock functions
drm/msm/dpu: simplify and unify dpu_encoder_get_intf and
dpu_encoder_get_wb
drm/msm/dp: make dp_bridge_mode_valid() more precise
drm/msm/hdmi: fill the pwr_regs bulk regulators
drm/msm/dp: use ARRAY_SIZE for calculating num_descs
dt-bindings: display/msm: hdmi: split and convert to yaml
dt-bindings: display/msm: hdmi: mark old GPIO properties as deprecated
dt-bindings: display/msm: hdmi: mark hdmi-mux-supply as deprecated
drm/msm/hdmi: drop the hdmi-mux support
drm/msm/hdmi: drop unused GPIO support
drm/msm/hdmi: enable core-vcc/core-vdda-supply for 8996 platform
drm/msm/hdmi: drop empty 'none' regulator lists
drm/msm/hdmi: drop hpd_regs usage on 8x74/8084
drm/msm/hdmi: merge platform config for 8974/8084/8994/8996
drm/msm/hdmi: reuse MSM8960's config for MSM8660
drm/msm/hdmi-phy: populate 8x60 HDMI PHY requirements
drm/msm/hdmi: drop empty bridge callbacks
drm/msm/hdmi: support attaching the "next" bridge
drm/msm/mdp4: move iommu_domain_alloc() call close to its usage
drm/msm/mdp4: get rid of struct mdp4_platform_config
Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu',
'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi',
'msm-next-lumag-mdp5' and 'msm-next-lumag-mdp4' into msm-next-lumag
drm/msm/dpu: drop xin_id from struct dpu_hw_blk_reg_map
drm/msm/dpu: drop length from struct dpu_hw_blk_reg_map
drm/msm/dpu: merge base_off with blk_off in struct dpu_hw_blk_reg_map
drm/msm/dpu: move struct dpu_hw_blk definition to dpu_hw_utils.h
drm/msm/dpu: check both DPU and MDSS devices for the IOMMU
drm/msm/mdp5: move iommu_domain_alloc() call close to its usage
drm/msm: Stop using iommu_present()
drm/msm: move KMS aspace init to the separate helper
drm/msm: switch msm_kms_init_aspace() to use device_iommu_mapped()
drm/msm/dp: remove unused stubs
drm/msm/dp: rename second dp_display_enable()'s argument
drm/msm/dp: remove dp_display_en/disable prototypes and data argument
Douglas Anderson (2):
dt-bindings: msm/dp: List supplies in the bindings
drm/msm: Avoid unclocked GMU register access in 6xx gpu_busy
Geert Uytterhoeven (1):
drm/msm/adreno: Do not propagate void return values
Jessica Zhang (4):
drm/msm/dpu: Move LM CRC code into separate method
drm/msm/dpu: Move MISR methods to dpu_hw_util
drm/msm/dpu: Add MISR register support for interface
drm/msm/dpu: Add interface support for CRC debugfs
Jonathan Marek (1):
drm/msm:
Re: [PATCH 1/6] dt-bindings/display: ingenic: Add compatible string for the JZ4760(B)
On 08/07/2022 22:54, Paul Cercueil wrote: > Add compatible strings for the LCD controllers found in the JZ4760 and > JZ4760B SoCs from Ingenic. > Acked-by: Krzysztof Kozlowski Best regards, Krzysztof
Re: [PATCH] staging: fbtft: replace udelay with usleep_range
On Sat, Jul 09, 2022 at 12:30:51PM +0200, Greg KH wrote: > On Sat, Jul 09, 2022 at 01:06:56PM +0300, Christos Kollintzas wrote: > > Adhere to Linux kernel coding style. > > > > Reported by checkpatch: > > > > CHECK: usleep_range is preferred over udelay > > > > Signed-off-by: Christos Kollintzas > > --- > > drivers/staging/fbtft/fb_upd161704.c | 18 +- > > 1 file changed, 9 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/staging/fbtft/fb_upd161704.c > > b/drivers/staging/fbtft/fb_upd161704.c > > index c680160d6380..eeafbab4ace1 100644 > > --- a/drivers/staging/fbtft/fb_upd161704.c > > +++ b/drivers/staging/fbtft/fb_upd161704.c > > @@ -32,27 +32,27 @@ static int init_display(struct fbtft_par *par) > > > > /* oscillator start */ > > write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ > > - udelay(100); > > + usleep_range(100, 110); > > When doing these types of changes, you really need access to the > hardware involved in order to be able to properly test it. > > Especially for this type of function which is trying to do timing > changes which the hardware requires. > > Did you test this on the real hardware and did it work properly? > > thanks, > > greg k-h I did not. I will try to find the hardware and send a patch that is properly tested. thanks, Christos Kollintzas
Re: [PATCH libdrm v2 00/10] Add support for low-color frame buffer formats
Hi Sam,
On Sun, Jul 10, 2022 at 12:40 PM Sam Ravnborg wrote:
> On Fri, Jul 08, 2022 at 08:21:30PM +0200, Geert Uytterhoeven wrote:
> > A long outstanding issue with the DRM subsystem has been the lack of
> > support for low-color displays, as used typically on older desktop
> > systems, and on small embedded displays.
> >
> > This patch series adds support for color-indexed frame buffer formats
> > with 2, 4, and 16 colors. It has been tested on ARAnyM using a
> > work-in-progress Atari DRM driver.
> >
> > Changes compared to v1:
> > - SMPTE color LUT accuracy,
> > - Factor out smpte color LUT,
> > - Restructure patches,
> > - Improve descriptions.
> > - Store number of colors for indexed formats,
> > - Add SMPTE pattern support for the C1 and C2 formats.
> >
> > Please refer to [2] for related Linux DRM patches and background
> > information.
> >
> > Thanks for your comments!
> >
> > [1] "[PATCH libdrm 0/3] Add support for low-color frame buffer formats"
> > https://lore.kernel.org/r/cover.1646683737.git.ge...@linux-m68k.org
> > [2] "[PATCH v3 00/10] drm: Add support for low-color frame buffer formats"
> > https://lore.kernel.org/r/cover.1657294931.git.ge...@linux-m68k.org
> >
> > Geert Uytterhoeven (10):
> > util: Improve SMPTE color LUT accuracy
> > util: Factor out and optimize C8 SMPTE color LUT
> > [RFC] drm_fourcc: Add DRM_FORMAT_C[124]
> > util: Add support for DRM_FORMAT_C[124]
> > util: Store number of colors for indexed formats
> > util: Add SMPTE pattern support for C4 format
> > util: Add SMPTE pattern support for C1 format
> > util: Add SMPTE pattern support for C2 format
> > modetest: Add support for DRM_FORMAT_C[124]
> > modetest: Add SMPTE pattern support for C4 format
>
> I have browsed the patches - everything looked good.
> The parts with Floyd-Steinberg dithering did get less
> attention as I do not know it.
As a picture says more than 1 words, I shared screenshots of
modetest showing the SMPTE pattern in C1 (monochrome FS-dithered
[1]), C2 (PenTile RG-GB FS-dithered [2]), and C4 ([3]).
And Wikipedia[4] is your friend for the algorithm ;-)
> But everything looked good and the series is:
>
> Acked-by: Sam Ravnborg
Thanks!
[1]
https://drive.google.com/file/d/1waJczErrIaEKRhBCCU1ynxRG8agpo0Xx/view?usp=sharing
[2]
https://drive.google.com/file/d/1g5O8XeacrjrC8rgaVENvR65YeI6QvmtO/view?usp=sharing
[3]
https://drive.google.com/file/d/1VIMqz_OkjJbbFS2OCX1O8GBm4bag6y2n/view?usp=sharing
[4] https://en.wikipedia.org/wiki/Floyd%E2%80%93Steinberg_dithering
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH libdrm v2 01/10] util: Improve SMPTE color LUT accuracy
Hi Geert, On Sun, Jul 10, 2022 at 01:04:23PM +0200, Geert Uytterhoeven wrote: > Hi Sam, > > On Sun, Jul 10, 2022 at 12:31 PM Sam Ravnborg wrote: > > On Fri, Jul 08, 2022 at 08:21:31PM +0200, Geert Uytterhoeven wrote: > > > Fill in the LSB when converting color components from 8-bit to 16-bit. > > > > > > Signed-off-by: Geert Uytterhoeven > > > --- > > > v2: > > > - New. > > > --- > > > tests/util/pattern.c | 6 +++--- > > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > > > diff --git a/tests/util/pattern.c b/tests/util/pattern.c > > > index 178aee8341a38920..3753ebc1eeae6c9a 100644 > > > --- a/tests/util/pattern.c > > > +++ b/tests/util/pattern.c > > > @@ -646,9 +646,9 @@ void util_smpte_c8_gamma(unsigned size, struct > > > drm_color_lut *lut) > > > memset(lut, 0, size * sizeof(struct drm_color_lut)); > > > > > > #define FILL_COLOR(idx, r, g, b) \ > > > - lut[idx].red = (r) << 8; \ > > > - lut[idx].green = (g) << 8; \ > > > - lut[idx].blue = (b) << 8 > > > + lut[idx].red = (r) * 0x101; \ > > > > (lut[idx].red = (r) << 8) | 1; > > > > had IMO been easier to read. > > I guess you mean "| (r)" instead of "| 1"? Well, I meant what I wrote but it is obviously wrong. So yes lut[idx].red = (r) << 8 | (r); is the equivalent of multiplying with 0x101. Whatever works, but if you update this patch, then please update the later patch where the multiply with 0x101 is also used. Sam
Re: [PATCH v2 1/2] dt-bindings: display: panel: Add Novatek NT35596S panel bindings
Hi Sam, Thank you again for your support. I forgot that point, which is really important to know. Molly Sam Ravnborg 于2022年7月10日周日 18:13写道： > Hi Molly, > > On Sun, Jul 10, 2022 at 02:19:41PM +0800, Molly Sophia wrote: > > Hi Sam, > > > > Thanks for your suggestions. > > > > Sam Ravnborg 于 2022年7月10日周日 上午4:47写道： > > > > > Hi Molly, > > > > > > thanks for the quick response to the review comments. > > > > > > On Sat, Jul 09, 2022 at 10:11:35PM +0800, MollySophia wrote: > > > > Add documentation for "novatek,nt35596s" panel. > > > > > > > > Signed-off-by: MollySophia > > > The s-o-b needs your real name - guess the above is a concatenation of > > > first name and surname. > > > > > > The binding included in this patch fails the check: > > > $ make DT_CHECKER_FLAGS=-m dt_binding_check > > > > > > You may need to run: > > > $ pip3 install dtschema --upgrade > > > > > > Or you may have to install some dependencies first. > > > The problem is that the patch is missing a "reset-gpios: true" > > > > > > On top of this I looked at the binding - and the description > > > this is copied from is almost identical. > > > So another approach would be to extend the existing binding like > > > in the following. > > > > > > And this also gives a good hint that maybe this can be embedded in > > > the existing driver - and there is no need for a new driver. > > > Could you try to give this a spin and get back on this. > > > > > > > That's reasonable. Actually, this driver was modified from > > novatek,nt35596s, with different panel initialization commands, and it > > seems easy to be embedded in > > the existing driver. However, I wonder what the driver file name would > > be...? "panel-novatek-nt35596s-nt36672a.c" or something else? > > Just keep the current driver name - we cannot embed all the supported HW > in one driver name anyway. And then you do not break currents users in > case they have hardwired the current driver name. > > Sam >
Re: [PATCH libdrm v2 01/10] util: Improve SMPTE color LUT accuracy
Hi Sam,
On Sun, Jul 10, 2022 at 12:31 PM Sam Ravnborg wrote:
> On Fri, Jul 08, 2022 at 08:21:31PM +0200, Geert Uytterhoeven wrote:
> > Fill in the LSB when converting color components from 8-bit to 16-bit.
> >
> > Signed-off-by: Geert Uytterhoeven
> > ---
> > v2:
> > - New.
> > ---
> > tests/util/pattern.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/tests/util/pattern.c b/tests/util/pattern.c
> > index 178aee8341a38920..3753ebc1eeae6c9a 100644
> > --- a/tests/util/pattern.c
> > +++ b/tests/util/pattern.c
> > @@ -646,9 +646,9 @@ void util_smpte_c8_gamma(unsigned size, struct
> > drm_color_lut *lut)
> > memset(lut, 0, size * sizeof(struct drm_color_lut));
> >
> > #define FILL_COLOR(idx, r, g, b) \
> > - lut[idx].red = (r) << 8; \
> > - lut[idx].green = (g) << 8; \
> > - lut[idx].blue = (b) << 8
> > + lut[idx].red = (r) * 0x101; \
>
> (lut[idx].red = (r) << 8) | 1;
>
> had IMO been easier to read.
I guess you mean "| (r)" instead of "| 1"?
>
> Patch is:
> Acked-by: Sam Ravnborg
>
> for both ways to do it.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
[Bug 216143] [bisected] garbled screen when starting X + dmesg cluttered with "[drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed in the dependencies handling -1431655766!"
https://bugzilla.kernel.org/show_bug.cgi?id=216143 --- Comment #8 from Erhard F. (erhar...@mailbox.org) --- Tried https://cgit.freedesktop.org/drm/drm-misc/commit/?h=drm-misc-fixes=925b6e59138cefa47275c67891c65d48d3266d57 suggested in https://gitlab.freedesktop.org/drm/amd/-/issues/2050#note_1461646 but it did not work out. This bug here seems an entirely different matter. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.
Re: [PATCH libdrm v2 00/10] Add support for low-color frame buffer formats
Hi Geert, On Fri, Jul 08, 2022 at 08:21:30PM +0200, Geert Uytterhoeven wrote: > Hi all, > > A long outstanding issue with the DRM subsystem has been the lack of > support for low-color displays, as used typically on older desktop > systems, and on small embedded displays. > > This patch series adds support for color-indexed frame buffer formats > with 2, 4, and 16 colors. It has been tested on ARAnyM using a > work-in-progress Atari DRM driver. > > Changes compared to v1: > - SMPTE color LUT accuracy, > - Factor out smpte color LUT, > - Restructure patches, > - Improve descriptions. > - Store number of colors for indexed formats, > - Add SMPTE pattern support for the C1 and C2 formats. > > Please refer to [2] for related Linux DRM patches and background > information. > > Thanks for your comments! > > [1] "[PATCH libdrm 0/3] Add support for low-color frame buffer formats" > https://lore.kernel.org/r/cover.1646683737.git.ge...@linux-m68k.org > [2] "[PATCH v3 00/10] drm: Add support for low-color frame buffer formats" > https://lore.kernel.org/r/cover.1657294931.git.ge...@linux-m68k.org > > Geert Uytterhoeven (10): > util: Improve SMPTE color LUT accuracy > util: Factor out and optimize C8 SMPTE color LUT > [RFC] drm_fourcc: Add DRM_FORMAT_C[124] > util: Add support for DRM_FORMAT_C[124] > util: Store number of colors for indexed formats > util: Add SMPTE pattern support for C4 format > util: Add SMPTE pattern support for C1 format > util: Add SMPTE pattern support for C2 format > modetest: Add support for DRM_FORMAT_C[124] > modetest: Add SMPTE pattern support for C4 format I have browsed the patches - everything looked good. The parts with Floyd-Steinberg dithering did get less attention as I do not know it. But everything looked good and the series is: Acked-by: Sam Ravnborg Sam
Re: [PATCH libdrm v2 01/10] util: Improve SMPTE color LUT accuracy
Hi Geert, On Fri, Jul 08, 2022 at 08:21:31PM +0200, Geert Uytterhoeven wrote: > Fill in the LSB when converting color components from 8-bit to 16-bit. > > Signed-off-by: Geert Uytterhoeven > --- > v2: > - New. > --- > tests/util/pattern.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/tests/util/pattern.c b/tests/util/pattern.c > index 178aee8341a38920..3753ebc1eeae6c9a 100644 > --- a/tests/util/pattern.c > +++ b/tests/util/pattern.c > @@ -646,9 +646,9 @@ void util_smpte_c8_gamma(unsigned size, struct > drm_color_lut *lut) > memset(lut, 0, size * sizeof(struct drm_color_lut)); > > #define FILL_COLOR(idx, r, g, b) \ > - lut[idx].red = (r) << 8; \ > - lut[idx].green = (g) << 8; \ > - lut[idx].blue = (b) << 8 > + lut[idx].red = (r) * 0x101; \ (lut[idx].red = (r) << 8) | 1; had IMO been easier to read. Patch is: Acked-by: Sam Ravnborg for both ways to do it. > + lut[idx].green = (g) * 0x101; \ > + lut[idx].blue = (b) * 0x101 > > FILL_COLOR( 0, 192, 192, 192); /* grey */ > FILL_COLOR( 1, 192, 192, 0 ); /* yellow */ > -- > 2.25.1
Re: [PATCH v2 1/2] dt-bindings: display: panel: Add Novatek NT35596S panel bindings
Hi Molly, On Sun, Jul 10, 2022 at 02:19:41PM +0800, Molly Sophia wrote: > Hi Sam, > > Thanks for your suggestions. > > Sam Ravnborg 于 2022年7月10日周日 上午4:47写道： > > > Hi Molly, > > > > thanks for the quick response to the review comments. > > > > On Sat, Jul 09, 2022 at 10:11:35PM +0800, MollySophia wrote: > > > Add documentation for "novatek,nt35596s" panel. > > > > > > Signed-off-by: MollySophia > > The s-o-b needs your real name - guess the above is a concatenation of > > first name and surname. > > > > The binding included in this patch fails the check: > > $ make DT_CHECKER_FLAGS=-m dt_binding_check > > > > You may need to run: > > $ pip3 install dtschema --upgrade > > > > Or you may have to install some dependencies first. > > The problem is that the patch is missing a "reset-gpios: true" > > > > On top of this I looked at the binding - and the description > > this is copied from is almost identical. > > So another approach would be to extend the existing binding like > > in the following. > > > > And this also gives a good hint that maybe this can be embedded in > > the existing driver - and there is no need for a new driver. > > Could you try to give this a spin and get back on this. > > > > That's reasonable. Actually, this driver was modified from > novatek,nt35596s, with different panel initialization commands, and it > seems easy to be embedded in > the existing driver. However, I wonder what the driver file name would > be...? "panel-novatek-nt35596s-nt36672a.c" or something else? Just keep the current driver name - we cannot embed all the supported HW in one driver name anyway. And then you do not break currents users in case they have hardwired the current driver name. Sam
[PATCH v2 10/11] dt-bindings: display/mdm: add gcc-bus clock to dpu-smd845
Add gcc-bus clock required for the SDM845 DPU device tree node. This
change was made in the commit 111c52854102 ("arm64: dts: qcom: sdm845:
move bus clock to mdp node for sdm845 target"), but was not reflected in
the schema.
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dpu-sdm845.yaml| 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
index 2074e954372f..42ff85e80f45 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -29,6 +29,7 @@ properties:
clocks:
items:
+ - description: Display GCC bus clock
- description: Display ahb clock
- description: Display axi clock
- description: Display core clock
@@ -36,6 +37,7 @@ properties:
clock-names:
items:
+ - const: gcc-bus
- const: iface
- const: bus
- const: core
@@ -114,11 +116,12 @@ examples:
<0x0aeb 0x2008>;
reg-names = "mdp", "vbif";
-clocks = < DISP_CC_MDSS_AHB_CLK>,
+clocks = < GCC_DISP_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_AXI_CLK>,
< DISP_CC_MDSS_MDP_CLK>,
< DISP_CC_MDSS_VSYNC_CLK>;
-clock-names = "iface", "bus", "core", "vsync";
+clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
interrupt-parent = <>;
interrupts = <0>;
--
2.35.1
[PATCH v2 11/11] dt-bindings: display/msm: move common DPU properties to dpu-common.yaml
Move properties common to all DPU DT nodes to the dpu-common.yaml. Note, this removes description of individual DPU port@ nodes. However such definitions add no additional value. The reg values do not correspond to hardware INTF indices. The driver discovers and binds these ports not paying any care for the order of these items. Thus just leave the reference to graph.yaml#/properties/ports and the description. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-common.yaml | 42 ++ .../bindings/display/msm/dpu-msm8998.yaml | 43 ++- .../bindings/display/msm/dpu-qcm2290.yaml | 39 ++--- .../bindings/display/msm/dpu-sc7180.yaml | 43 ++- .../bindings/display/msm/dpu-sc7280.yaml | 43 ++- .../bindings/display/msm/dpu-sdm845.yaml | 43 ++- 6 files changed, 62 insertions(+), 191 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-common.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml new file mode 100644 index ..14eda883e149 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -0,0 +1,42 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties (common properties) + +maintainers: + - Dmitry Baryshkov + - Krishna Manikandan + - Rob Clark + +description: | + Common properties for QCom DPU display controller. + +properties: + interrupts: +maxItems: 1 + + power-domains: +maxItems: 1 + + operating-points-v2: true + + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 5caf46a1dd88..158bd93a157f 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -47,45 +47,10 @@ properties: - const: core - const: vsync - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - - port@1: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF2 (DSI2) - -required: - - port@0 - - port@1 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 8027319b1aad..0364261bf3d2 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -43,41 +43,10 @@ properties: - const: lut - const: vsync - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - -required: - - port@0 - -required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports - -additionalProperties: false +allOf: + - $ref: "/schemas/display/msm/dpu-common.yaml#" + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
[PATCH v2 03/11] arm64: dts: qcom: sm8250: rename DPU device node
Rename DPU device node to display-controller@ae01000 to follow the
DPU schema.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 43c2d04b226f..48c60df59080 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3444,7 +3444,7 @@ mdss: mdss@ae0 {
#size-cells = <2>;
ranges;
- mdss_mdp: mdp@ae01000 {
+ mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
--
2.35.1
[PATCH v2 04/11] dt-bindings: display/msm: split qcom, mdss bindings
Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added (optional) "core" clock added recently to the mdss driver - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/mdp5.txt | 30 +--- .../devicetree/bindings/display/msm/mdss.yaml | 161 ++ 2 files changed, 162 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/mdp5.txt b/Documentation/devicetree/bindings/display/msm/mdp5.txt index 43d11279c925..65d03c58dee6 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp5.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp5.txt @@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller Description: -This is the bindings documentation for the Mobile Display Subsytem(MDSS) that -encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display +This is the bindings documentation for the MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. -MDSS: -Required properties: -- compatible: - * "qcom,mdss" - MDSS -- reg: Physical base address and length of the controller's registers. -- reg-names: The names of register regions. The following regions are required: - * "mdss_phys" - * "vbif_phys" -- interrupts: The interrupt signal from MDSS. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: specifies the number of cells needed to encode an interrupt - source, should be 1. -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt -- clocks: device clocks. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required. - * "iface" - * "bus" - * "vsync" -- #address-cells: number of address cells for the MDSS children. Should be 1. -- #size-cells: Should be 1. -- ranges: parent bus address space is the same as the child bus address space. - -Optional properties: -- clock-names: the following clocks are optional: - * "lut" - MDP5: Required properties: - compatible: diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml new file mode 100644 index ..ba674a261b18 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Mobile Display SubSystem (MDSS) + +maintainers: + - Dmitry Baryshkov + - Rob Clark + +description: + This is the bindings documentation for the Mobile Display Subsytem(MDSS) that + encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. + +properties: + compatible: +enum: + - qcom,mdss + + reg: +minItems: 2 +maxItems: 3 + + reg-names: +minItems: 2 +items: + - const: mdss_phys + - const: vbif_phys + - const: vbif_nrt_phys + + interrupts: +maxItems: 1 + + interrupt-controller: +true + + "#interrupt-cells": +const: 1 + + power-domains: +maxItems: 1 +description: | + The MDSS power domain provided by GCC + + clocks: +minItems: 1 +maxItems: 4 + + clock-names: +minItems: 1 +maxItems: 4 + + "#address-cells": +const: 1 + + "#size-cells": +const: 1 + + ranges: +true + + resets: +items: + - description: MDSS_CORE reset + +oneOf: + - properties: + clocks: +minItems: 3 +maxItems: 4 + + clock-names: +minItems: 3 +items: + - const: iface + - const: bus + - const: vsync + - const: core + - properties: + clocks: +minItems: 1 +maxItems: 2 + + clock-names: +minItems: 1 +items: + - const: iface + - const: core + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - "#interrupt-cells" + - power-domains + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^mdp@(0|[1-9a-f][0-9a-f]*)$": +type: object +# TODO: add reference once the mdp5 is converted + + "^dsi@(0|[1-9a-f][0-9a-f]*)$": +$ref: dsi-controller-main.yaml# + + "^dsi-phy@(0|[1-9a-f][0-9a-f]*)$": +oneOf: + - $ref: dsi-phy-28nm.yaml# + - $ref:
[PATCH v2 09/11] dt-bindings: display/msm: move qcom, msm8998-mdss schema to mdss.yaml
Move schema for qcom,msm8998-mdss from dpu-msm8998.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-msm8998.yaml | 142 +- .../devicetree/bindings/display/msm/mdss.yaml | 24 +++ 2 files changed, 64 insertions(+), 102 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml index 2df64afb76e6..5caf46a1dd88 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml @@ -10,142 +10,80 @@ maintainers: - AngeloGioacchino Del Regno description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for MSM8998 target. + Device tree bindings for the DPU display controller for MSM8998 target. properties: compatible: items: - - const: qcom,msm8998-mdss + - const: qcom,msm8998-dpu reg: -maxItems: 1 +items: + - description: Address offset and size for mdp register set + - description: Address offset and size for regdma register set + - description: Address offset and size for vbif register set + - description: Address offset and size for non-realtime vbif register set reg-names: -const: mdss - - power-domains: -maxItems: 1 +items: + - const: mdp + - const: regdma + - const: vbif + - const: vbif_nrt clocks: items: - - description: Display AHB clock - - description: Display AXI clock + - description: Display ahb clock + - description: Display axi clock + - description: Display mem-noc clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface - const: bus + - const: mnoc - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true + power-domains: +maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": -type: object -description: Node containing the properties of DPU. + operating-points-v2: true + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: -items: - - const: qcom,msm8998-dpu - - reg: -items: - - description: Address offset and size for mdp register set - - description: Address offset and size for regdma register set - - description: Address offset and size for vbif register set - - description: Address offset and size for non-realtime vbif register set - - reg-names: -items: - - const: mdp - - const: regdma - - const: vbif - - const: vbif_nrt - - clocks: -items: - - description: Display ahb clock - - description: Display axi clock - - description: Display mem-noc clock - - description: Display core clock - - description: Display vsync clock - - clock-names: -items: - - const: iface - - const: bus - - const: mnoc - - const: core - - const: vsync - - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - - port@1: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF2 (DSI2) - -required: - - port@0 - - port@1 + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF1 (DSI1) + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF2 (DSI2) required: - - compatible -
[PATCH v2 07/11] dt-bindings: display/msm: move qcom, sc7280-mdss schema to mdss.yaml
Move schema for qcom,sc7280-mdss from dpu-sc7280.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7280.yaml | 148 +- .../devicetree/bindings/display/msm/mdss.yaml | 19 +++ 2 files changed, 57 insertions(+), 110 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml index f427eec3d3a4..349a454099ad 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -10,149 +10,77 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7280. + Device tree bindings for the DPU display controller for SC7280 target. properties: compatible: -const: qcom,sc7280-mdss +const: qcom,sc7280-dpu reg: -maxItems: 1 +items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: -const: mdss - - power-domains: -maxItems: 1 +items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus + - const: nrt_bus - const: iface - - const: ahb + - const: lut - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: -items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: -const: mdp0-mem + power-domains: +maxItems: 1 - resets: -items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": -type: object -description: Node containing the properties of DPU. + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: -const: qcom,sc7280-dpu - - reg: -items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: -items: - - const: mdp - - const: vbif - - clocks: -items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: -items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI) - - port@1: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF5 (EDP) - -required: - - port@0 + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF1 (DSI) + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF5 (EDP) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - -
[PATCH v2 06/11] dt-bindings: display/msm: move qcom, sc7180-mdss schema to mdss.yaml
Move schema for qcom,sc7180-mdss from dpu-sc7180.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sc7180.yaml | 149 +- .../devicetree/bindings/display/msm/mdss.yaml | 45 +- 2 files changed, 80 insertions(+), 114 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml index d3c3e4b07897..9d4ec0b60c25 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml @@ -10,151 +10,78 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SC7180 target. + Device tree bindings for the DPU display controller for SC7180 target. properties: compatible: items: - - const: qcom,sc7180-mdss + - const: qcom,sc7180-dpu reg: -maxItems: 1 +items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: -const: mdss - - power-domains: -maxItems: 1 +items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AHB clock from dispcc + - description: Display hf axi clock + - description: Display ahb clock + - description: Display rotator clock + - description: Display lut clock - description: Display core clock + - description: Display vsync clock clock-names: items: + - const: bus - const: iface - - const: ahb + - const: rot + - const: lut - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - ranges: true - - interconnects: -items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: -const: mdp0-mem + power-domains: +maxItems: 1 - resets: -items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": -type: object -description: Node containing the properties of DPU. + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: -items: - - const: qcom,sc7180-dpu - - reg: -items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: -items: - - const: mdp - - const: vbif - - clocks: -items: - - description: Display hf axi clock - - description: Display ahb clock - - description: Display rotator clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: -items: - - const: bus - - const: iface - - const: rot - - const: lut - - const: core - - const: vsync - - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - - port@2: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF0 (DP) - -required: - - port@0 + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF1 (DSI1) + + port@2: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF0 (DP) required: - - compatible - - reg - - reg-names - - clocks - -
[PATCH v2 05/11] dt-bindings: display/msm: move qcom, sdm845-mdss schema to mdss.yaml
Move schema for qcom,sdm845-mdss from dpu-sdm845.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sdm845.yaml | 135 --- .../devicetree/bindings/display/msm/mdss.yaml | 156 ++ 2 files changed, 160 insertions(+), 131 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml index 2bb8896beffc..2074e954372f 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml @@ -10,139 +10,74 @@ maintainers: - Krishna Manikandan description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree - bindings of MDSS and DPU are mentioned for SDM845 target. + Device tree bindings for the DPU display controller for SDM845 target. properties: compatible: items: - - const: qcom,sdm845-mdss + - const: qcom,sdm845-dpu reg: -maxItems: 1 +items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: -const: mdss - - power-domains: -maxItems: 1 +items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc + - description: Display ahb clock + - description: Display axi clock - description: Display core clock + - description: Display vsync clock clock-names: items: - const: iface + - const: bus - const: core + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - resets: -items: - - description: MDSS_CORE reset + power-domains: +maxItems: 1 -patternProperties: - "^display-controller@[0-9a-f]+$": -type: object -description: Node containing the properties of DPU. + operating-points-v2: true + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: -items: - - const: qcom,sdm845-dpu - - reg: -items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: -items: - - const: mdp - - const: vbif - - clocks: -items: - - description: Display ahb clock - - description: Display axi clock - - description: Display core clock - - description: Display vsync clock - - clock-names: -items: - - const: iface - - const: bus - - const: core - - const: vsync - - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI, DP etc. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - - port@1: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF2 (DSI2) - -required: - - port@0 - - port@1 + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF1 (DSI1) + + port@1: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF2 (DSI2) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 + - port@1 required: - compatible - reg - reg-names - - power-domains - clocks - interrupts - - interrupt-controller - - iommus - - ranges + - power-domains + - operating-points-v2 + - ports additionalProperties: false diff --git
[PATCH v2 08/11] dt-bindings: display/msm: move qcom, qcm2290-mdss schema to mdss.yaml
Move schema for qcom,qcm2290-mdss from dpu-qcm2290.yaml to mdss.yaml so that the dpu file describes only the DPU schema. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-qcm2290.yaml | 140 +- .../devicetree/bindings/display/msm/mdss.yaml | 24 +++ 2 files changed, 57 insertions(+), 107 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml index 734d14de966d..8027319b1aad 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml @@ -10,146 +10,72 @@ maintainers: - Loic Poulain description: | - Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates - sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS - and DPU are mentioned for QCM2290 target. + Device tree bindings for the DPU display controller for QCM2290 target. properties: compatible: items: - - const: qcom,qcm2290-mdss + - const: qcom,qcm2290-dpu reg: -maxItems: 1 +items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set reg-names: -const: mdss - - power-domains: -maxItems: 1 +items: + - const: mdp + - const: vbif clocks: items: - - description: Display AHB clock from gcc - - description: Display AXI clock - - description: Display core clock + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display vsync clock from dispcc clock-names: items: - - const: iface - const: bus + - const: iface - const: core + - const: lut + - const: vsync interrupts: maxItems: 1 - interrupt-controller: true - - "#address-cells": true - - "#size-cells": true - - "#interrupt-cells": -const: 1 - - iommus: -items: - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 - - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1 - - ranges: true - - interconnects: -items: - - description: Interconnect path specifying the port ids for data bus - - interconnect-names: -const: mdp0-mem + power-domains: +maxItems: 1 - resets: -items: - - description: MDSS_CORE reset + operating-points-v2: true -patternProperties: - "^display-controller@[0-9a-f]+$": -type: object -description: Node containing the properties of DPU. + ports: +$ref: /schemas/graph.yaml#/properties/ports +description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI. Each output port contains an endpoint that + describes how it is connected to an external interface. properties: - compatible: -items: - - const: qcom,qcm2290-dpu - - reg: -items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: -items: - - const: mdp - - const: vbif - - clocks: -items: - - description: Display AXI clock from gcc - - description: Display AHB clock from dispcc - - description: Display core clock from dispcc - - description: Display lut clock from dispcc - - description: Display vsync clock from dispcc - - clock-names: -items: - - const: bus - - const: iface - - const: core - - const: lut - - const: vsync - - interrupts: -maxItems: 1 - - power-domains: -maxItems: 1 - - operating-points-v2: true - - ports: -$ref: /schemas/graph.yaml#/properties/ports -description: | - Contains the list of output ports from DPU device. These ports - connect to interfaces that are external to the DPU hardware, - such as DSI. Each output port contains an endpoint that - describes how it is connected to an external interface. - -properties: - port@0: -$ref: /schemas/graph.yaml#/properties/port -description: DPU_INTF1 (DSI1) - -required: - - port@0 + port@0: +$ref: /schemas/graph.yaml#/properties/port +description: DPU_INTF1 (DSI1) required: - - compatible - - reg - - reg-names - - clocks - - interrupts - - power-domains - - operating-points-v2 - - ports + - port@0 required: - compatible - reg - reg-names - - power-domains - clocks
[PATCH v2 02/11] arm64: dts: qcom: sc7180: rename DPU device node
Rename DPU device node to display-controller@ae01000 to follow the
DPU schema.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 72994f599825..e63b4515453f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2911,7 +2911,7 @@ mdss: mdss@ae0 {
status = "disabled";
- mdp: mdp@ae01000 {
+ mdp: display-controller@ae01000 {
compatible = "qcom,sc7180-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
--
2.35.1
[PATCH v2 01/11] arm64: dts: qcom: sdm845: rename DPU device node
Rename DPU device node to display-controller@ae01000 to follow the
DPU schema.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 32ad5972a642..7c66f490e822 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4265,7 +4265,7 @@ mdss: mdss@ae0 {
#size-cells = <2>;
ranges;
- mdss_mdp: mdp@ae01000 {
+ mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sdm845-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
--
2.35.1
[PATCH v2 00/11] dt-bindings: display/msm: rework MDSS and DPU bindings
Create separate YAML schema for MDSS devicesd$ (both for MDP5 and DPU devices). Cleanup DPU schema files, so that they do not contain schema for both MDSS and DPU nodes. Apply misc small fixes to the DPU schema afterwards. Changes since v1: - Renamed DPU device nodes from mdp@ to display-controller@ - Described removal of mistakenly mentioned "lut" clock - Switched mdss.yaml to use $ref instead of fixing compatible strings - Dropped mdp-opp-table description (renamed by Krzysztof in his patchset) - Reworked DPU's ports definitions. Dropped description of individual ports, left only /ports $ref and description in dpu-common.yaml. Dmitry Baryshkov (11): arm64: dts: qcom: sdm845: rename DPU device node arm64: dts: qcom: sc7180: rename DPU device node arm64: dts: qcom: sm8250: rename DPU device node dt-bindings: display/msm: split qcom, mdss bindings dt-bindings: display/msm: move qcom,sdm845-mdss schema to mdss.yaml dt-bindings: display/msm: move qcom,sc7180-mdss schema to mdss.yaml dt-bindings: display/msm: move qcom,sc7280-mdss schema to mdss.yaml dt-bindings: display/msm: move qcom,qcm2290-mdss schema to mdss.yaml dt-bindings: display/msm: move qcom,msm8998-mdss schema to mdss.yaml dt-bindings: display/mdm: add gcc-bus clock to dpu-smd845 dt-bindings: display/msm: move common DPU properties to dpu-common.yaml .../bindings/display/msm/dpu-common.yaml | 42 ++ .../bindings/display/msm/dpu-msm8998.yaml | 139 +-- .../bindings/display/msm/dpu-qcm2290.yaml | 143 +-- .../bindings/display/msm/dpu-sc7180.yaml | 148 +-- .../bindings/display/msm/dpu-sc7280.yaml | 147 +-- .../bindings/display/msm/dpu-sdm845.yaml | 139 +-- .../devicetree/bindings/display/msm/mdp5.txt | 30 +- .../devicetree/bindings/display/msm/mdss.yaml | 361 ++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 11 files changed, 508 insertions(+), 647 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-common.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/mdss.yaml -- 2.35.1
[PATCH v1 11/11] drm/via: Update to the latest via_3d_reg file
Updated the 3d_reg header file to match what is used by the openchrome driver. This verifies that the two drivers can use the same header file. Signed-off-by: Sam Ravnborg --- drivers/gpu/drm/via/via_3d_reg.h | 395 --- 1 file changed, 304 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/via/via_3d_reg.h b/drivers/gpu/drm/via/via_3d_reg.h index 462375d543b9..fc74647f512a 100644 --- a/drivers/gpu/drm/via/via_3d_reg.h +++ b/drivers/gpu/drm/via/via_3d_reg.h @@ -1,6 +1,6 @@ /* - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * Copyright 1998-2011 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2011 S3 Graphics, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -16,7 +16,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. @@ -50,6 +50,7 @@ #define HC_ParaType_Palette 0x0003 #define HC_ParaType_PreCR 0x0010 #define HC_ParaType_Auto0x00fe +#define INV_ParaType_Dummy 0x0030 /* Transmission Space */ @@ -176,7 +177,7 @@ /* Command * Command A */ -#define HC_HCmdHeader_MASK 0xfe00 /*0xffe0 */ +#define HC_HCmdHeader_MASK 0xfe00 /*0xffe0 */ #define HC_HE3Fire_MASK 0x0010 #define HC_HPMType_MASK 0x000f #define HC_HEFlag_MASK 0xe000 @@ -236,6 +237,8 @@ /* Enable Setting */ #define HC_SubA_HEnable 0x +#define HC_HenForce1P_MASK 0x0080 /* [Force 1 Pipe] */ +#define HC_HenZDCheck_MASK 0x0040 /* [Z dirty bit settings] */ #define HC_HenTXEnvMap_MASK 0x0020 #define HC_HenVertexCNT_MASK0x0010 #define HC_HenCPUDAZ_MASK 0x0008 @@ -682,6 +685,12 @@ #define HC_FogDenst_MASK0x001fff00 #define HC_FogEndL_MASK 0x00ff +/* Texture subtype definitions + */ +#define HC_SubType_Samp00x0020 +#define HC_SubType_Samp10x0021 + + /* Texture subtype definitions */ #define HC_SubType_Tex0 0x @@ -762,7 +771,13 @@ #define HC_SubA_HTXnBumpM10 0x0092 #define HC_SubA_HTXnBumpM11 0x0093 #define HC_SubA_HTXnLScale 0x0094 -#define HC_SubA_HTXSMD 0x + +#define HC_SubA_HTXSMD 0x +#define HC_SubA_HTXYUV2RGB10x0001 +#define HC_SubA_HTXYUV2RGB20x0002 +#define HC_SubA_HTXYUV2RGB30x0003 +#define HTXYUV2RGB4BT601 (1<<23) +#define HTXYUV2RGB4BT709 (1<<22) /* HC_SubA_HTXnL012BasH0x0020 */ #define HC_HTXnL0BasH_MASK 0x00ff @@ -965,6 +980,7 @@ #define HC_HTXnFM_Lum 0x0010 #define HC_HTXnFM_Alpha 0x0018 #define HC_HTXnFM_DX0x0028 +#define HC_HTXnFM_YUV 0x0030 #define HC_HTXnFM_ARGB160x0088 #define HC_HTXnFM_ARGB320x0098 #define HC_HTXnFM_ABGR160x00a8 @@ -995,6 +1011,12 @@ #define HC_HTXnFM_DX1 (HC_HTXnFM_DX| 0x0001) #define HC_HTXnFM_DX23 (HC_HTXnFM_DX| 0x0002) #define HC_HTXnFM_DX45 (HC_HTXnFM_DX| 0x0003) +/* YUV package mode */ +#define HC_HTXnFM_YUY2 (HC_HTXnFM_YUV | 0x) +/* YUV planner mode */ +#define HC_HTXnFM_YV12 (HC_HTXnFM_YUV | 0x0004) +/* YUV planner mode */ +#define HC_HTXnFM_IYUV (HC_HTXnFM_YUV | 0x0004) #define HC_HTXnFM_RGB555(HC_HTXnFM_ARGB16| 0x) #define HC_HTXnFM_RGB565(HC_HTXnFM_ARGB16| 0x0001) #define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16| 0x0002) @@ -1023,6 +1045,13 @@ #define HC_HTXnLoc_Local0x #define HC_HTXnLoc_Sys 0x0002 #define HC_HTXnLoc_AGP 0x0003 + +/* Video Texture */ +#define HC_HTXnYUV2RGBMode_RGB 0x +#define HC_HTXnYUV2RGBMode_SDTV 0x0001 +#define HC_HTXnYUV2RGBMode_HDTV 0x0002 +#define HC_HTXnYUV2RGBMode_TABLE0x0003 + /* HC_SubA_HTXnTRAH0x007f */ #define HC_HTXnTRAH_MASK0x00ff @@ -1330,9 +1359,9 @@ */ #define HC_HFthRTXA_MASK0x00ff -/**
[PATCH v1 10/11] drm/via: Rename the via driver to via_dri1
The via driver is a dri1 driver. Make this obvious in the name of the driver. This also make the diver name "via" free for the upcoming openchrome driver. Signed-off-by: Sam Ravnborg --- drivers/gpu/drm/via/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile index 8b978dd51a25..ae36eda2d01e 100644 --- a/drivers/gpu/drm/via/Makefile +++ b/drivers/gpu/drm/via/Makefile @@ -3,6 +3,4 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -via-y:= via_dri1.o - -obj-$(CONFIG_DRM_VIA) +=via.o +obj-$(CONFIG_DRM_VIA) += via_dri1.o -- 2.34.1
[PATCH v1 08/11] drm/via: Embed via_verifier in via_dri1
Embed the header file in via_drv.h and the code in via_dri1.
All functions are made static as there are no more external users.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile |2 +-
drivers/gpu/drm/via/via_dri1.c | 1071 +++
drivers/gpu/drm/via/via_drv.h | 29 +-
drivers/gpu/drm/via/via_verifier.c | 1110
drivers/gpu/drm/via/via_verifier.h | 62 --
5 files changed, 1099 insertions(+), 1175 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_verifier.c
delete mode 100644 drivers/gpu/drm/via/via_verifier.h
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index 66125b150478..8b978dd51a25 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_dri1.o via_verifier.o
+via-y:= via_dri1.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dri1.c b/drivers/gpu/drm/via/via_dri1.c
index f8b1f837feb1..f9285cc3e1c7 100644
--- a/drivers/gpu/drm/via/via_dri1.c
+++ b/drivers/gpu/drm/via/via_dri1.c
@@ -201,7 +201,1078 @@ typedef struct _drm_via_descriptor {
uint32_t next;
} drm_via_descriptor_t;
+typedef enum {
+ state_command,
+ state_header2,
+ state_header1,
+ state_vheader5,
+ state_vheader6,
+ state_error
+} verifier_state_t;
+
+typedef enum {
+ no_check = 0,
+ check_for_header2,
+ check_for_header1,
+ check_for_header2_err,
+ check_for_header1_err,
+ check_for_fire,
+ check_z_buffer_addr0,
+ check_z_buffer_addr1,
+ check_z_buffer_addr_mode,
+ check_destination_addr0,
+ check_destination_addr1,
+ check_destination_addr_mode,
+ check_for_dummy,
+ check_for_dd,
+ check_texture_addr0,
+ check_texture_addr1,
+ check_texture_addr2,
+ check_texture_addr3,
+ check_texture_addr4,
+ check_texture_addr5,
+ check_texture_addr6,
+ check_texture_addr7,
+ check_texture_addr8,
+ check_texture_addr_mode,
+ check_for_vertex_count,
+ check_number_texunits,
+ forbidden_command
+} hazard_t;
+/*
+ * Associates each hazard above with a possible multi-command
+ * sequence. For example an address that is split over multiple
+ * commands and that needs to be checked at the first command
+ * that does not include any part of the address.
+ */
+
+static drm_via_sequence_t seqs[] = {
+ no_sequence,
+ no_sequence,
+ no_sequence,
+ no_sequence,
+ no_sequence,
+ no_sequence,
+ z_address,
+ z_address,
+ z_address,
+ dest_address,
+ dest_address,
+ dest_address,
+ no_sequence,
+ no_sequence,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ tex_address,
+ no_sequence
+};
+
+typedef struct {
+ unsigned int code;
+ hazard_t hz;
+} hz_init_t;
+
+static hz_init_t init_table1[] = {
+ {0xf2, check_for_header2_err},
+ {0xf0, check_for_header1_err},
+ {0xee, check_for_fire},
+ {0xcc, check_for_dummy},
+ {0xdd, check_for_dd},
+ {0x00, no_check},
+ {0x10, check_z_buffer_addr0},
+ {0x11, check_z_buffer_addr1},
+ {0x12, check_z_buffer_addr_mode},
+ {0x13, no_check},
+ {0x14, no_check},
+ {0x15, no_check},
+ {0x23, no_check},
+ {0x24, no_check},
+ {0x33, no_check},
+ {0x34, no_check},
+ {0x35, no_check},
+ {0x36, no_check},
+ {0x37, no_check},
+ {0x38, no_check},
+ {0x39, no_check},
+ {0x3A, no_check},
+ {0x3B, no_check},
+ {0x3C, no_check},
+ {0x3D, no_check},
+ {0x3E, no_check},
+ {0x40, check_destination_addr0},
+ {0x41, check_destination_addr1},
+ {0x42, check_destination_addr_mode},
+ {0x43, no_check},
+ {0x44, no_check},
+ {0x50, no_check},
+ {0x51, no_check},
+ {0x52, no_check},
+ {0x53, no_check},
+ {0x54, no_check},
+ {0x55, no_check},
+ {0x56, no_check},
+ {0x57, no_check},
+ {0x58, no_check},
+ {0x70, no_check},
+ {0x71, no_check},
+ {0x78, no_check},
+ {0x79, no_check},
+ {0x7A, no_check},
+ {0x7B, no_check},
+ {0x7C, no_check},
+ {0x7D, check_for_vertex_count}
+};
+
+static hz_init_t init_table2[] = {
+ {0xf2, check_for_header2_err},
+ {0xf0, check_for_header1_err},
+ {0xee, check_for_fire},
+ {0xcc, check_for_dummy},
+ {0x00, check_texture_addr0},
+ {0x01, check_texture_addr0},
+ {0x02, check_texture_addr0},
+ {0x03,
[PATCH v1 09/11] drm/via: Embed via_drv.h in via_dri1
With this change the driver is now a signle file driver.
The only remaning heder file describes the HW and can be shared with the
new openchrome driver.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/via_dri1.c | 229 +++-
drivers/gpu/drm/via/via_drv.h | 265 -
2 files changed, 228 insertions(+), 266 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_drv.h
diff --git a/drivers/gpu/drm/via/via_dri1.c b/drivers/gpu/drm/via/via_dri1.c
index f9285cc3e1c7..d695d9291ece 100644
--- a/drivers/gpu/drm/via/via_dri1.c
+++ b/drivers/gpu/drm/via/via_dri1.c
@@ -36,13 +36,240 @@
#include
#include
+#include
+#include
+#include
#include
+#include
#include
#include
-#include "via_drv.h"
#include "via_3d_reg.h"
+#define DRIVER_AUTHOR "Various"
+
+#define DRIVER_NAME"via"
+#define DRIVER_DESC"VIA Unichrome / Pro"
+#define DRIVER_DATE"20070202"
+
+#define DRIVER_MAJOR 2
+#define DRIVER_MINOR 11
+#define DRIVER_PATCHLEVEL 1
+
+typedef enum {
+ no_sequence = 0,
+ z_address,
+ dest_address,
+ tex_address
+} drm_via_sequence_t;
+
+typedef struct {
+ unsigned texture;
+ uint32_t z_addr;
+ uint32_t d_addr;
+ uint32_t t_addr[2][10];
+ uint32_t pitch[2][10];
+ uint32_t height[2][10];
+ uint32_t tex_level_lo[2];
+ uint32_t tex_level_hi[2];
+ uint32_t tex_palette_size[2];
+ uint32_t tex_npot[2];
+ drm_via_sequence_t unfinished;
+ int agp_texture;
+ int multitex;
+ struct drm_device *dev;
+ drm_local_map_t *map_cache;
+ uint32_t vertex_count;
+ int agp;
+ const uint32_t *buf_start;
+} drm_via_state_t;
+
+#define VIA_PCI_BUF_SIZE 6
+#define VIA_FIRE_BUF_SIZE 1024
+#define VIA_NUM_IRQS 4
+
+
+#define VIA_NUM_BLIT_ENGINES 2
+#define VIA_NUM_BLIT_SLOTS 8
+
+struct _drm_via_descriptor;
+
+typedef struct _drm_via_sg_info {
+ struct page **pages;
+ unsigned long num_pages;
+ struct _drm_via_descriptor **desc_pages;
+ int num_desc_pages;
+ int num_desc;
+ enum dma_data_direction direction;
+ unsigned char *bounce_buffer;
+ dma_addr_t chain_start;
+ uint32_t free_on_sequence;
+ unsigned int descriptors_per_page;
+ int aborted;
+ enum {
+ dr_via_device_mapped,
+ dr_via_desc_pages_alloc,
+ dr_via_pages_locked,
+ dr_via_pages_alloc,
+ dr_via_sg_init
+ } state;
+} drm_via_sg_info_t;
+
+typedef struct _drm_via_blitq {
+ struct drm_device *dev;
+ uint32_t cur_blit_handle;
+ uint32_t done_blit_handle;
+ unsigned serviced;
+ unsigned head;
+ unsigned cur;
+ unsigned num_free;
+ unsigned num_outstanding;
+ unsigned long end;
+ int aborting;
+ int is_active;
+ drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS];
+ spinlock_t blit_lock;
+ wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS];
+ wait_queue_head_t busy_queue;
+ struct work_struct wq;
+ struct timer_list poll_timer;
+} drm_via_blitq_t;
+
+typedef struct drm_via_ring_buffer {
+ drm_local_map_t map;
+ char *virtual_start;
+} drm_via_ring_buffer_t;
+
+typedef uint32_t maskarray_t[5];
+
+typedef struct drm_via_irq {
+ atomic_t irq_received;
+ uint32_t pending_mask;
+ uint32_t enable_mask;
+ wait_queue_head_t irq_queue;
+} drm_via_irq_t;
+
+typedef struct drm_via_private {
+ drm_via_sarea_t *sarea_priv;
+ drm_local_map_t *sarea;
+ drm_local_map_t *fb;
+ drm_local_map_t *mmio;
+ unsigned long agpAddr;
+ wait_queue_head_t decoder_queue[VIA_NR_XVMC_LOCKS];
+ char *dma_ptr;
+ unsigned int dma_low;
+ unsigned int dma_high;
+ unsigned int dma_offset;
+ uint32_t dma_wrap;
+ volatile uint32_t *last_pause_ptr;
+ volatile uint32_t *hw_addr_ptr;
+ drm_via_ring_buffer_t ring;
+ ktime_t last_vblank;
+ int last_vblank_valid;
+ ktime_t nsec_per_vblank;
+ atomic_t vbl_received;
+ drm_via_state_t hc_state;
+ char pci_buf[VIA_PCI_BUF_SIZE];
+ const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
+ uint32_t num_fire_offsets;
+ int chipset;
+ drm_via_irq_t via_irqs[VIA_NUM_IRQS];
+ unsigned num_irqs;
+ maskarray_t *irq_masks;
+ uint32_t irq_enable_mask;
+ uint32_t irq_pending_mask;
+ int *irq_map;
+ unsigned int idle_fault;
+ int vram_initialized;
+ struct drm_mm vram_mm;
+ int agp_initialized;
+ struct drm_mm agp_mm;
+ /** Mapping of userspace keys to mm objects */
+ struct idr object_idr;
+ unsigned long vram_offset;
+ unsigned long agp_offset;
+ drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES];
+ uint32_t dma_diff;
+}
[PATCH v1 05/11] drm/via: Embed via_video in via_dri1
All functions are made static as there are no more external users.
The file had a new copyright that is kept.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile| 2 +-
drivers/gpu/drm/via/via_dri1.c | 66 ++-
drivers/gpu/drm/via/via_drv.h | 4 --
drivers/gpu/drm/via/via_video.c | 94 -
4 files changed, 66 insertions(+), 100 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_video.c
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index daadc0d3233f..398be21c6df8 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_irq.o via_dri1.o via_verifier.o via_video.o via_dmablit.o
+via-y:= via_irq.o via_dri1.o via_verifier.o via_dmablit.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dri1.c b/drivers/gpu/drm/via/via_dri1.c
index 3ebe17649ec2..4c5517330110 100644
--- a/drivers/gpu/drm/via/via_dri1.c
+++ b/drivers/gpu/drm/via/via_dri1.c
@@ -5,7 +5,8 @@
* Copyright 2006 Tungsten Graphics Inc., Bismarck, ND., USA.
* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. All Rights Reserved.
* Copyright 2004 The Unichrome project. All Rights Reserved.
- *
+ * Copyright 2005 Thomas Hellstrom. All Rights Reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
@@ -76,6 +77,69 @@ struct via_memblock {
struct list_head owner_list;
};
+static void via_init_futex(drm_via_private_t *dev_priv)
+{
+ unsigned int i;
+
+ DRM_DEBUG("\n");
+
+ for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
+ init_waitqueue_head(&(dev_priv->decoder_queue[i]));
+ XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0;
+ }
+}
+
+static void via_cleanup_futex(drm_via_private_t *dev_priv)
+{
+}
+
+static void via_release_futex(drm_via_private_t *dev_priv, int context)
+{
+ unsigned int i;
+ volatile int *lock;
+
+ if (!dev_priv->sarea_priv)
+ return;
+
+ for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
+ lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i);
+ if ((_DRM_LOCKING_CONTEXT(*lock) == context)) {
+ if (_DRM_LOCK_IS_HELD(*lock)
+ && (*lock & _DRM_LOCK_CONT)) {
+ wake_up(&(dev_priv->decoder_queue[i]));
+ }
+ *lock = 0;
+ }
+ }
+}
+
+static int via_decoder_futex(struct drm_device *dev, void *data, struct
drm_file *file_priv)
+{
+ drm_via_futex_t *fx = data;
+ volatile int *lock;
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+ drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
+ int ret = 0;
+
+ DRM_DEBUG("\n");
+
+ if (fx->lock >= VIA_NR_XVMC_LOCKS)
+ return -EFAULT;
+
+ lock = (volatile int *)XVMCLOCKPTR(sAPriv, fx->lock);
+
+ switch (fx->func) {
+ case VIA_FUTEX_WAIT:
+ VIA_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock],
+ (fx->ms / 10) * (HZ / 100), *lock != fx->val);
+ return ret;
+ case VIA_FUTEX_WAKE:
+ wake_up(&(dev_priv->decoder_queue[fx->lock]));
+ return 0;
+ }
+ return 0;
+}
+
static int via_agp_init(struct drm_device *dev, void *data, struct drm_file
*file_priv)
{
drm_via_agp_t *agp = data;
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index c1a5fdf0bc4b..312e86b850f6 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -183,7 +183,6 @@ do {
\
remove_wait_queue(&(queue), );\
} while (0)
-extern int via_decoder_futex(struct drm_device *dev, void *data, struct
drm_file *file_priv);
extern int via_wait_irq(struct drm_device *dev, void *data, struct drm_file
*file_priv);
extern int via_dma_blit_sync(struct drm_device *dev, void *data, struct
drm_file *file_priv);
extern int via_dma_blit(struct drm_device *dev, void *data, struct drm_file
*file_priv);
@@ -203,9 +202,6 @@ extern void via_driver_irq_uninstall(struct drm_device
*dev);
extern int via_dma_cleanup(struct drm_device *dev);
extern void via_init_command_verifier(void);
extern int via_driver_dma_quiescent(struct drm_device *dev);
-extern void via_init_futex(drm_via_private_t *dev_priv);
-extern void via_cleanup_futex(drm_via_private_t *dev_priv);
-extern void via_release_futex(drm_via_private_t *dev_priv, int context);
extern void
[PATCH v1 07/11] drm/via: Embed via_dmablit in via_dri1
Embed some of the header file in via_drv.h and
the rest in via_dri1.c
While embedding deleted extra empty lines and functions that
has no external users are made static.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile | 2 +-
drivers/gpu/drm/via/via_dmablit.c | 807 --
drivers/gpu/drm/via/via_dmablit.h | 140 --
drivers/gpu/drm/via/via_dri1.c| 786 +
drivers/gpu/drm/via/via_drv.h | 56 ++-
5 files changed, 835 insertions(+), 956 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_dmablit.c
delete mode 100644 drivers/gpu/drm/via/via_dmablit.h
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index dd75ea8a1423..66125b150478 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_dri1.o via_verifier.o via_dmablit.o
+via-y:= via_dri1.o via_verifier.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dmablit.c
b/drivers/gpu/drm/via/via_dmablit.c
deleted file mode 100644
index e016a4d62090..
--- a/drivers/gpu/drm/via/via_dmablit.c
+++ /dev/null
@@ -1,807 +0,0 @@
-/* via_dmablit.c -- PCI DMA BitBlt support for the VIA Unichrome/Pro
- *
- * Copyright (C) 2005 Thomas Hellstrom, All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *Thomas Hellstrom.
- *Partially based on code obtained from Digeo Inc.
- */
-
-
-/*
- * Unmaps the DMA mappings.
- * FIXME: Is this a NoOp on x86? Also
- * FIXME: What happens if this one is called and a pending blit has previously
done
- * the same DMA mappings?
- */
-
-#include
-#include
-#include
-#include
-
-#include
-#include
-
-#include "via_dmablit.h"
-#include "via_drv.h"
-
-#define VIA_PGDN(x) (((unsigned long)(x)) & PAGE_MASK)
-#define VIA_PGOFF(x) (((unsigned long)(x)) & ~PAGE_MASK)
-#define VIA_PFN(x) ((unsigned long)(x) >> PAGE_SHIFT)
-
-typedef struct _drm_via_descriptor {
- uint32_t mem_addr;
- uint32_t dev_addr;
- uint32_t size;
- uint32_t next;
-} drm_via_descriptor_t;
-
-
-/*
- * Unmap a DMA mapping.
- */
-
-
-
-static void
-via_unmap_blit_from_device(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
-{
- int num_desc = vsg->num_desc;
- unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page;
- unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page;
- drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] +
- descriptor_this_page;
- dma_addr_t next = vsg->chain_start;
-
- while (num_desc--) {
- if (descriptor_this_page-- == 0) {
- cur_descriptor_page--;
- descriptor_this_page = vsg->descriptors_per_page - 1;
- desc_ptr = vsg->desc_pages[cur_descriptor_page] +
- descriptor_this_page;
- }
- dma_unmap_single(>dev, next, sizeof(*desc_ptr),
DMA_TO_DEVICE);
- dma_unmap_page(>dev, desc_ptr->mem_addr, desc_ptr->size,
vsg->direction);
- next = (dma_addr_t) desc_ptr->next;
- desc_ptr--;
- }
-}
-
-/*
- * If mode = 0, count how many descriptors are needed.
- * If mode = 1, Map the DMA pages for the device, put together and map also
the descriptors.
- * Descriptors are run in reverse order by the hardware because we are not
allowed to update the
- * 'next' field without syncing calls when the descriptor is already mapped.
- */
-
-static void
-via_map_blit_for_device(struct pci_dev *pdev,
- const drm_via_dmablit_t *xfer,
- drm_via_sg_info_t *vsg,
[PATCH v1 06/11] drm/via: Embed via_irq in via_dri1
All functions are made static as there are no more external users.
The file had new copyrights that are kept.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile | 2 +-
drivers/gpu/drm/via/via_dri1.c | 347 +
drivers/gpu/drm/via/via_drv.h | 9 -
drivers/gpu/drm/via/via_irq.c | 388 -
4 files changed, 348 insertions(+), 398 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_irq.c
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index 398be21c6df8..dd75ea8a1423 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_irq.o via_dri1.o via_verifier.o via_dmablit.o
+via-y:= via_dri1.o via_verifier.o via_dmablit.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dri1.c b/drivers/gpu/drm/via/via_dri1.c
index 4c5517330110..32aae172c6f3 100644
--- a/drivers/gpu/drm/via/via_dri1.c
+++ b/drivers/gpu/drm/via/via_dri1.c
@@ -1,10 +1,12 @@
/*
* Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
+ * Copyright 2002 Tungsten Graphics, Inc.
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. All Rights
Reserved.
* Copyright 2006 Tungsten Graphics Inc., Bismarck, ND., USA.
* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. All Rights Reserved.
* Copyright 2004 The Unichrome project. All Rights Reserved.
+ * Copyright 2004 BEAM Ltd.
* Copyright 2005 Thomas Hellstrom. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -77,6 +79,351 @@ struct via_memblock {
struct list_head owner_list;
};
+#define VIA_REG_INTERRUPT 0x200
+
+/* VIA_REG_INTERRUPT */
+#define VIA_IRQ_GLOBAL (1 << 31)
+#define VIA_IRQ_VBLANK_ENABLE (1 << 19)
+#define VIA_IRQ_VBLANK_PENDING (1 << 3)
+#define VIA_IRQ_HQV0_ENABLE (1 << 11)
+#define VIA_IRQ_HQV1_ENABLE (1 << 25)
+#define VIA_IRQ_HQV0_PENDING(1 << 9)
+#define VIA_IRQ_HQV1_PENDING(1 << 10)
+#define VIA_IRQ_DMA0_DD_ENABLE (1 << 20)
+#define VIA_IRQ_DMA0_TD_ENABLE (1 << 21)
+#define VIA_IRQ_DMA1_DD_ENABLE (1 << 22)
+#define VIA_IRQ_DMA1_TD_ENABLE (1 << 23)
+#define VIA_IRQ_DMA0_DD_PENDING (1 << 4)
+#define VIA_IRQ_DMA0_TD_PENDING (1 << 5)
+#define VIA_IRQ_DMA1_DD_PENDING (1 << 6)
+#define VIA_IRQ_DMA1_TD_PENDING (1 << 7)
+
+/*
+ * Device-specific IRQs go here. This type might need to be extended with
+ * the register if there are multiple IRQ control registers.
+ * Currently we activate the HQV interrupts of Unichrome Pro group A.
+ */
+
+static maskarray_t via_pro_group_a_irqs[] = {
+ {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x03D0, 0x8010,
+0x },
+ {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x13D0, 0x8010,
+0x },
+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
+VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x0008},
+ {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
+VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x0008},
+};
+static int via_num_pro_group_a = ARRAY_SIZE(via_pro_group_a_irqs);
+static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
+
+static maskarray_t via_unichrome_irqs[] = {
+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
+VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x0008},
+ {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
+VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x0008}
+};
+static int via_num_unichrome = ARRAY_SIZE(via_unichrome_irqs);
+static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
+
+
+static u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
+{
+ drm_via_private_t *dev_priv = dev->dev_private;
+
+ if (pipe != 0)
+ return 0;
+
+ return atomic_read(_priv->vbl_received);
+}
+
+static irqreturn_t via_driver_irq_handler(int irq, void *arg)
+{
+ struct drm_device *dev = (struct drm_device *) arg;
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+ u32 status;
+ int handled = 0;
+ ktime_t cur_vblank;
+ drm_via_irq_t *cur_irq = dev_priv->via_irqs;
+ int i;
+
+ status = via_read(dev_priv, VIA_REG_INTERRUPT);
+ if (status & VIA_IRQ_VBLANK_PENDING) {
+ atomic_inc(_priv->vbl_received);
+ if (!(atomic_read(_priv->vbl_received) & 0x0F)) {
+ cur_vblank = ktime_get();
+ if (dev_priv->last_vblank_valid) {
+ dev_priv->nsec_per_vblank =
+ ktime_sub(cur_vblank,
+
[PATCH v1 03/11] drm/via: Embed via_map in via_dri1
A few functions has no external use and are made static.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile | 2 +-
drivers/gpu/drm/via/via_dri1.c | 102 +
drivers/gpu/drm/via/via_drv.h | 4 -
drivers/gpu/drm/via/via_map.c | 132 -
4 files changed, 103 insertions(+), 137 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_map.c
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index 824198c0c2ea..be12cbfa4d7f 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_irq.o via_dri1.o via_map.o via_mm.o via_verifier.o via_video.o
via_dmablit.o
+via-y:= via_irq.o via_dri1.o via_mm.o via_verifier.o via_video.o
via_dmablit.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dri1.c b/drivers/gpu/drm/via/via_dri1.c
index d5d4a64437da..2fa22359b1f6 100644
--- a/drivers/gpu/drm/via/via_dri1.c
+++ b/drivers/gpu/drm/via/via_dri1.c
@@ -32,6 +32,7 @@
#include
#include
#include
+#include
#include
#include "via_drv.h"
@@ -66,6 +67,107 @@
dev_priv->dma_low += 8; \
} while (0)
+static int via_do_init_map(struct drm_device *dev, drm_via_init_t *init)
+{
+ drm_via_private_t *dev_priv = dev->dev_private;
+
+ DRM_DEBUG("\n");
+
+ dev_priv->sarea = drm_legacy_getsarea(dev);
+ if (!dev_priv->sarea) {
+ DRM_ERROR("could not find sarea!\n");
+ dev->dev_private = (void *)dev_priv;
+ via_do_cleanup_map(dev);
+ return -EINVAL;
+ }
+
+ dev_priv->fb = drm_legacy_findmap(dev, init->fb_offset);
+ if (!dev_priv->fb) {
+ DRM_ERROR("could not find framebuffer!\n");
+ dev->dev_private = (void *)dev_priv;
+ via_do_cleanup_map(dev);
+ return -EINVAL;
+ }
+ dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
+ if (!dev_priv->mmio) {
+ DRM_ERROR("could not find mmio region!\n");
+ dev->dev_private = (void *)dev_priv;
+ via_do_cleanup_map(dev);
+ return -EINVAL;
+ }
+
+ dev_priv->sarea_priv =
+ (drm_via_sarea_t *) ((u8 *) dev_priv->sarea->handle +
+init->sarea_priv_offset);
+
+ dev_priv->agpAddr = init->agpAddr;
+
+ via_init_futex(dev_priv);
+
+ via_init_dmablit(dev);
+
+ dev->dev_private = (void *)dev_priv;
+ return 0;
+}
+
+int via_do_cleanup_map(struct drm_device *dev)
+{
+ via_dma_cleanup(dev);
+
+ return 0;
+}
+
+static int via_map_init(struct drm_device *dev, void *data, struct drm_file
*file_priv)
+{
+ drm_via_init_t *init = data;
+
+ DRM_DEBUG("\n");
+
+ switch (init->func) {
+ case VIA_INIT_MAP:
+ return via_do_init_map(dev, init);
+ case VIA_CLEANUP_MAP:
+ return via_do_cleanup_map(dev);
+ }
+
+ return -EINVAL;
+}
+
+static int via_driver_load(struct drm_device *dev, unsigned long chipset)
+{
+ struct pci_dev *pdev = to_pci_dev(dev->dev);
+ drm_via_private_t *dev_priv;
+ int ret = 0;
+
+ dev_priv = kzalloc(sizeof(drm_via_private_t), GFP_KERNEL);
+ if (dev_priv == NULL)
+ return -ENOMEM;
+
+ idr_init(_priv->object_idr);
+ dev->dev_private = (void *)dev_priv;
+
+ dev_priv->chipset = chipset;
+
+ pci_set_master(pdev);
+
+ ret = drm_vblank_init(dev, 1);
+ if (ret) {
+ kfree(dev_priv);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void via_driver_unload(struct drm_device *dev)
+{
+ drm_via_private_t *dev_priv = dev->dev_private;
+
+ idr_destroy(_priv->object_idr);
+
+ kfree(dev_priv);
+}
+
static void via_cmdbuf_start(drm_via_private_t *dev_priv);
static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 5757422ea634..4eaad17c0e02 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -187,15 +187,11 @@ extern int via_fb_init(struct drm_device *dev, void
*data, struct drm_file *file
extern int via_mem_alloc(struct drm_device *dev, void *data, struct drm_file
*file_priv);
extern int via_mem_free(struct drm_device *dev, void *data, struct drm_file
*file_priv);
extern int via_agp_init(struct drm_device *dev, void *data, struct drm_file
*file_priv);
-extern int via_map_init(struct drm_device *dev, void *data, struct drm_file
*file_priv);
extern int via_decoder_futex(struct drm_device *dev, void *data, struct
drm_file *file_priv);
extern int via_wait_irq(struct
[PATCH v1 04/11] drm/via: Embed via_mm in via_dri1
All functions was made static as there are no external users.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile | 2 +-
drivers/gpu/drm/via/via_dri1.c | 208
drivers/gpu/drm/via/via_drv.h | 9 --
drivers/gpu/drm/via/via_mm.c | 241 -
4 files changed, 209 insertions(+), 251 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_mm.c
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index be12cbfa4d7f..daadc0d3233f 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_irq.o via_dri1.o via_mm.o via_verifier.o via_video.o
via_dmablit.o
+via-y:= via_irq.o via_dri1.o via_verifier.o via_video.o via_dmablit.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dri1.c b/drivers/gpu/drm/via/via_dri1.c
index 2fa22359b1f6..3ebe17649ec2 100644
--- a/drivers/gpu/drm/via/via_dri1.c
+++ b/drivers/gpu/drm/via/via_dri1.c
@@ -2,6 +2,7 @@
* Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. All Rights
Reserved.
+ * Copyright 2006 Tungsten Graphics Inc., Bismarck, ND., USA.
* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. All Rights Reserved.
* Copyright 2004 The Unichrome project. All Rights Reserved.
*
@@ -67,6 +68,213 @@
dev_priv->dma_low += 8; \
} while (0)
+#define VIA_MM_ALIGN_SHIFT 4
+#define VIA_MM_ALIGN_MASK ((1 << VIA_MM_ALIGN_SHIFT) - 1)
+
+struct via_memblock {
+ struct drm_mm_node mm_node;
+ struct list_head owner_list;
+};
+
+static int via_agp_init(struct drm_device *dev, void *data, struct drm_file
*file_priv)
+{
+ drm_via_agp_t *agp = data;
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+
+ mutex_lock(>struct_mutex);
+ drm_mm_init(_priv->agp_mm, 0, agp->size >> VIA_MM_ALIGN_SHIFT);
+
+ dev_priv->agp_initialized = 1;
+ dev_priv->agp_offset = agp->offset;
+ mutex_unlock(>struct_mutex);
+
+ DRM_DEBUG("offset = %u, size = %u\n", agp->offset, agp->size);
+ return 0;
+}
+
+static int via_fb_init(struct drm_device *dev, void *data, struct drm_file
*file_priv)
+{
+ drm_via_fb_t *fb = data;
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+
+ mutex_lock(>struct_mutex);
+ drm_mm_init(_priv->vram_mm, 0, fb->size >> VIA_MM_ALIGN_SHIFT);
+
+ dev_priv->vram_initialized = 1;
+ dev_priv->vram_offset = fb->offset;
+
+ mutex_unlock(>struct_mutex);
+ DRM_DEBUG("offset = %u, size = %u\n", fb->offset, fb->size);
+
+ return 0;
+
+}
+
+static int via_final_context(struct drm_device *dev, int context)
+{
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+
+ via_release_futex(dev_priv, context);
+
+ /* Linux specific until context tracking code gets ported to BSD */
+ /* Last context, perform cleanup */
+ if (list_is_singular(>ctxlist)) {
+ DRM_DEBUG("Last Context\n");
+ drm_legacy_irq_uninstall(dev);
+ via_cleanup_futex(dev_priv);
+ via_do_cleanup_map(dev);
+ }
+ return 1;
+}
+
+static void via_lastclose(struct drm_device *dev)
+{
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+
+ if (!dev_priv)
+ return;
+
+ mutex_lock(>struct_mutex);
+ if (dev_priv->vram_initialized) {
+ drm_mm_takedown(_priv->vram_mm);
+ dev_priv->vram_initialized = 0;
+ }
+ if (dev_priv->agp_initialized) {
+ drm_mm_takedown(_priv->agp_mm);
+ dev_priv->agp_initialized = 0;
+ }
+ mutex_unlock(>struct_mutex);
+}
+
+static int via_mem_alloc(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ drm_via_mem_t *mem = data;
+ int retval = 0, user_key;
+ struct via_memblock *item;
+ drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
+ struct via_file_private *file_priv = file->driver_priv;
+ unsigned long tmpSize;
+
+ if (mem->type > VIA_MEM_AGP) {
+ DRM_ERROR("Unknown memory type allocation\n");
+ return -EINVAL;
+ }
+ mutex_lock(>struct_mutex);
+ if (0 == ((mem->type == VIA_MEM_VIDEO) ? dev_priv->vram_initialized :
+ dev_priv->agp_initialized)) {
+ mutex_unlock(>struct_mutex);
+ DRM_ERROR
+ ("Attempt to allocate from uninitialized memory
manager.\n");
+ return -EINVAL;
+ }
+
+ item = kzalloc(sizeof(*item),
[PATCH v1 02/11] drm/via: Embed via_dma in via_dri1
Moved the copyright notices so all copyrights are kept.
A few variables was made static as there are no more users outside this
file.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile | 2 +-
drivers/gpu/drm/via/via_dma.c | 744 -
drivers/gpu/drm/via/via_dri1.c | 703 ++-
drivers/gpu/drm/via/via_drv.h | 3 -
4 files changed, 703 insertions(+), 749 deletions(-)
delete mode 100644 drivers/gpu/drm/via/via_dma.c
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index acfd916541ea..824198c0c2ea 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_irq.o via_dri1.o via_map.o via_mm.o via_dma.o via_verifier.o
via_video.o via_dmablit.o
+via-y:= via_irq.o via_dri1.o via_map.o via_mm.o via_verifier.o via_video.o
via_dmablit.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_dma.c b/drivers/gpu/drm/via/via_dma.c
deleted file mode 100644
index 177b0499abf1..
--- a/drivers/gpu/drm/via/via_dma.c
+++ /dev/null
@@ -1,744 +0,0 @@
-/* via_dma.c -- DMA support for the VIA Unichrome/Pro
- *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
- * All Rights Reserved.
- *
- * Copyright 2004 The Unichrome project.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *Tungsten Graphics,
- *Erdi Chen,
- *Thomas Hellstrom.
- */
-
-#include
-#include
-
-#include
-#include
-#include
-#include
-
-#include "via_drv.h"
-#include "via_3d_reg.h"
-
-#define CMDBUF_ALIGNMENT_SIZE (0x100)
-#define CMDBUF_ALIGNMENT_MASK (0x0ff)
-
-/* defines for VIA 3D registers */
-#define VIA_REG_STATUS 0x400
-#define VIA_REG_TRANSET 0x43C
-#define VIA_REG_TRANSPACE 0x440
-
-/* VIA_REG_STATUS(0x400): Engine Status */
-#define VIA_CMD_RGTR_BUSY 0x0080 /* Command Regulator is busy */
-#define VIA_2D_ENG_BUSY 0x0001 /* 2D Engine is busy */
-#define VIA_3D_ENG_BUSY 0x0002 /* 3D Engine is busy */
-#define VIA_VR_QUEUE_BUSY 0x0002 /* Virtual Queue is busy */
-
-#define SetReg2DAGP(nReg, nData) { \
- *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1; \
- *((uint32_t *)(vb) + 1) = (nData); \
- vb = ((uint32_t *)vb) + 2; \
- dev_priv->dma_low += 8; \
-}
-
-#define via_flush_write_combine() mb()
-
-#define VIA_OUT_RING_QW(w1, w2)do {\
- *vb++ = (w1); \
- *vb++ = (w2); \
- dev_priv->dma_low += 8; \
-} while (0)
-
-static void via_cmdbuf_start(drm_via_private_t *dev_priv);
-static void via_cmdbuf_pause(drm_via_private_t *dev_priv);
-static void via_cmdbuf_reset(drm_via_private_t *dev_priv);
-static void via_cmdbuf_rewind(drm_via_private_t *dev_priv);
-static int via_wait_idle(drm_via_private_t *dev_priv);
-static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
-
-/*
- * Free space in command buffer.
- */
-
-static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
-{
- uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
- uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
-
- return ((hw_addr <= dev_priv->dma_low) ?
- (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
- (hw_addr - dev_priv->dma_low));
-}
-
-/*
- * How much does the command regulator lag behind?
- */
-
-static
[PATCH v1 01/11] drm/via: Rename via_drv to via_dri1
The via driver implements the DRI1 interface, and we have a new
implementation of the via driver coming that supports atomic
modesetting.
It is not acceptable just to replace the existing driver so
this is first step to make it a single-file implementation allowing
it to stay without interfering with the new driver.
Signed-off-by: Sam Ravnborg
---
drivers/gpu/drm/via/Makefile | 2 +-
drivers/gpu/drm/via/{via_drv.c => via_dri1.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/gpu/drm/via/{via_drv.c => via_dri1.c} (100%)
diff --git a/drivers/gpu/drm/via/Makefile b/drivers/gpu/drm/via/Makefile
index 84db4eee7828..acfd916541ea 100644
--- a/drivers/gpu/drm/via/Makefile
+++ b/drivers/gpu/drm/via/Makefile
@@ -3,6 +3,6 @@
# Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
-via-y:= via_irq.o via_drv.o via_map.o via_mm.o via_dma.o via_verifier.o
via_video.o via_dmablit.o
+via-y:= via_irq.o via_dri1.o via_map.o via_mm.o via_dma.o via_verifier.o
via_video.o via_dmablit.o
obj-$(CONFIG_DRM_VIA) +=via.o
diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_dri1.c
similarity index 100%
rename from drivers/gpu/drm/via/via_drv.c
rename to drivers/gpu/drm/via/via_dri1.c
--
2.34.1
[PATCH v1 0/11] drm/via: Make via a single file driver
We have an upcoming openchrome driver for VIA where some of the files conflicts with the existing via driver. It is not acceptable to just delete the existing DRI1 based driver as there are most likely users out there, so a different approach was required. It was disccussed what to do and the least invasive solution was to keep the DRI1 driver in the current directory as a single file. Thomas Zimmermann already posted a patch to do the same but it attemped to have a single driver for the DRI1 and the upcoming new driver. This patchset embeds the files one by one to make the diffs remotely readable and end up with an independent DRI1 driver. The driver was built tested for each step. The driver is in the end renamed to via_dri1. Some feedback on this would be good as I do not know what impact it will have on users. The very last patch synchronize the via_3d_reg header file with the one used in the openchrome driver. This was added to verify that the new header would not break the DRI1 driver. Sam Sam Ravnborg (11): drm/via: Rename via_drv to via_dri1 drm/via: Embed via_dma in via_dri1 drm/via: Embed via_map in via_dri1 drm/via: Embed via_mm in via_dri1 drm/via: Embed via_video in via_dri1 drm/via: Embed via_irq in via_dri1 drm/via: Embed via_dmablit in via_dri1 drm/via: Embed via_verifier in via_dri1 drm/via: Embed via_drv.h in via_dri1 drm/via: Rename the via driver to via_dri1 drm/via: Update to the latest via_3d_reg file drivers/gpu/drm/via/Makefile |4 +- drivers/gpu/drm/via/via_3d_reg.h | 395 +++- drivers/gpu/drm/via/via_dma.c | 744 drivers/gpu/drm/via/via_dmablit.c | 807 drivers/gpu/drm/via/via_dmablit.h | 140 -- drivers/gpu/drm/via/via_dri1.c | 3630 drivers/gpu/drm/via/via_drv.c | 124 -- drivers/gpu/drm/via/via_drv.h | 229 --- drivers/gpu/drm/via/via_irq.c | 388 drivers/gpu/drm/via/via_map.c | 132 -- drivers/gpu/drm/via/via_mm.c | 241 --- drivers/gpu/drm/via/via_verifier.c | 1110 --- drivers/gpu/drm/via/via_verifier.h | 62 - drivers/gpu/drm/via/via_video.c| 94 - 14 files changed, 3935 insertions(+), 4165 deletions(-)
[PATCH v2 9/9] dt-bindings: msm/dp: handle DP vs eDP difference
The #sound-dai-cells property should be used only for DP controllers. It doesn't make sense for eDP, there is no support for audio output. The aux-bus should not be used for DP controllers. Also p1 MMIO region should be used only for DP controllers. Take care of these differences. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dp-controller.yaml | 26 ++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 52cbf00df0ba..f2515af8256f 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -24,6 +24,7 @@ properties: - qcom,sm8350-dp reg: +minItems: 4 items: - description: ahb register block - description: aux register block @@ -112,10 +113,33 @@ required: - clock-names - phys - phy-names - - "#sound-dai-cells" - power-domains - ports +allOf: + # AUX BUS does not exist on DP controllers + # Audio output also is present only on DP output + # p1 regions is present on DP, but not on eDP + - if: + properties: +compatible: + contains: +enum: + - qcom,sc7280-edp + - qcom,sc8180x-edp +then: + properties: +"#sound-dai-cells": false +reg: + maxItems: 4 +else: + properties: +aux-bus: false +reg: + minItems: 5 + required: +- "#sound-dai-cells" + additionalProperties: false examples: -- 2.35.1
[PATCH v2 5/9] arm64: dts: qcom: sc7280: drop address/size-cells from eDP node
Drop #address/#size-cells from eDP device node. For eDP the panels are
not described directly under the controller node. They are either
present under aux-bus child node, or they are declared separately (e.g.
in a /soc node).
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index a55e6cdc..13590e84772e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3740,9 +3740,6 @@ mdss_edp: edp@aea {
operating-points-v2 = <_opp_table>;
power-domains = < SC7280_CX>;
- #address-cells = <1>;
- #size-cells = <0>;
-
status = "disabled";
ports {
--
2.35.1
[PATCH v2 8/9] dt-bindings: msm/dp: add missing properties
Document missing definitions for opp-table (DP controller OPPs), aux-bus (DP AUX BUS) and data-lanes (DP/eDP lanes mapping) properties. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dp-controller.yaml | 12 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 391910d91e43..52cbf00df0ba 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -70,9 +70,21 @@ properties: operating-points-v2: maxItems: 1 + opp-table: true + power-domains: maxItems: 1 + aux-bus: +$ref: /schemas/display/dp-aux-bus.yaml# + + data-lanes: +$ref: /schemas/types.yaml#/definitions/uint32-array +minItems: 1 +maxItems: 4 +items: + maximum: 3 + "#sound-dai-cells": const: 0 -- 2.35.1
[PATCH v2 2/9] arm64: dts: qcom: sc7180: drop #clock-cells from displayport-controller
Drop #clock-cells from DP device node. It is a leftover from the times
before splitting the device into controller and PHY devices. Now the
clocks are provided by the PHY, while the controller doesn't provide any
clocks.
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 875808cf0614..72994f599825 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3096,7 +3096,6 @@ mdss_dp: displayport-controller@ae9 {
< DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
- #clock-cells = <1>;
assigned-clocks = <
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <_phy 0>, <_phy
1>;
--
2.35.1
[PATCH v2 7/9] dt-bindings: msm/dp: mark vdda supplies as deprecated
The commit fa384dd8b9b8 ("drm/msm/dp: delete vdda regulator related
functions from eDP/DP controller") removed support for VDDA supplies
from the DP controller driver. These supplies are now handled by the eDP
or QMP PHYs. Mark these properties as deprecated and drop them from the
example.
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dp-controller.yaml | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 94bc6e1b6451..391910d91e43 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -76,8 +76,10 @@ properties:
"#sound-dai-cells":
const: 0
- vdda-0p9-supply: true
- vdda-1p2-supply: true
+ vdda-0p9-supply:
+deprecated: true
+ vdda-1p2-supply:
+deprecated: true
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -140,9 +142,6 @@ examples:
power-domains = < SC7180_CX>;
-vdda-0p9-supply = <_usb_ss_dp_core>;
-vdda-1p2-supply = <_usb_ss_dp_1p2>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.35.1
[PATCH v2 6/9] arm64: dts: qcom: sc7280: drop unused clocks from eDP node
The eDP node includes two clocks which are used by the eDP PHY rather
than eDP controller itself. Drop these clocks to remove extra difference
between eDP and DP controllers.
Suggested-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 13590e84772e..5bb536d76f5e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3716,16 +3716,12 @@ mdss_edp: edp@aea {
interrupt-parent = <>;
interrupts = <14>;
- clocks = < RPMH_CXO_CLK>,
-< GCC_EDP_CLKREF_EN>,
-< DISP_CC_MDSS_AHB_CLK>,
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
< DISP_CC_MDSS_EDP_AUX_CLK>,
< DISP_CC_MDSS_EDP_LINK_CLK>,
<
DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
< DISP_CC_MDSS_EDP_PIXEL_CLK>;
- clock-names = "core_xo",
- "core_ref",
- "core_iface",
+ clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
--
2.35.1
[PATCH v2 4/9] arm64: dts: qcom: sc7280: drop #clock-cells from displayport-controller
Drop #clock-cells from DP device node. It is a leftover from the times
before splitting the deviice into controller and PHY devices. Now the
clocks are provided by the PHY, while the controller doesn't provide any
clocks.
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e54c2000b098..a55e6cdc 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3730,7 +3730,6 @@ mdss_edp: edp@aea {
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
- #clock-cells = <1>;
assigned-clocks = <
DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
<
DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
assigned-clock-parents = <_edp_phy 0>,
<_edp_phy 1>;
@@ -3829,7 +3828,6 @@ mdss_dp: displayport-controller@ae9 {
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
- #clock-cells = <1>;
assigned-clocks = <
DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<
DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <_phy 0>, <_phy
1>;
--
2.35.1
[PATCH v2 1/9] arm64: dts: qcom: sc7180: split register block for DP controller
Follow the schema for the DP controller and declare 5 register regions
instead of using a single region for all the registers. Note, this
extends the dts by adding p1 region to the DP node (to be used for DP
MST).
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 47ce5787ed5b..875808cf0614 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3080,7 +3080,11 @@ mdss_dp: displayport-controller@ae9 {
compatible = "qcom,sc7180-dp";
status = "disabled";
- reg = <0 0x0ae9 0 0x1400>;
+ reg = <0 0xae9 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0xc00>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
interrupt-parent = <>;
interrupts = <12>;
--
2.35.1
[PATCH v2 3/9] arm64: dts: qcom: sc7280: split register block for DP controller
Follow the schema for the DP controller and declare 5 register regions
instead of using a single region for all the registers. Note, this
extends the dts by adding p1 region to the DP node (to be used for DP
MST).
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index a3def1022ea2..e54c2000b098 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3810,7 +3810,11 @@ mdss_edp_phy: phy@aec2a00 {
mdss_dp: displayport-controller@ae9 {
compatible = "qcom,sc7280-dp";
- reg = <0 0x0ae9 0 0x1400>;
+ reg = <0 0xae9 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0xc00>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
interrupt-parent = <>;
interrupts = <12>;
--
2.35.1
[PATCH v2 0/9] dt-bindings: msm/dp: cleanup Qualcomm DP and eDP bidndings
Fix several issues with the DP and eDP bindings on the Qualcomm platforms. While we are at it, fix several small issues with platform files declaring these controllers. Changes since v1: - Reordered patches to cleanup dts first, to remove warnings from DP schema - Split DP register blocks in sc7180.dtsi and sc7280.dtsi - Cleaned up the p1 register block handling: marked it as required for DP and absent for eDP controllers - Dropped unused xo and ref clocks from sc7280-edp node, they belong to eDP PHY. Dmitry Baryshkov (9): arm64: dts: qcom: sc7180: split register block for DP controller arm64: dts: qcom: sc7180: drop #clock-cells from displayport-controller arm64: dts: qcom: sc7280: split register block for DP controller arm64: dts: qcom: sc7280: drop #clock-cells from displayport-controller arm64: dts: qcom: sc7280: drop address/size-cells from eDP node arm64: dts: qcom: sc7280: drop unused clocks from eDP node dt-bindings: msm/dp: mark vdda supplies as deprecated dt-bindings: msm/dp: add missing properties dt-bindings: msm/dp: handle DP vs eDP difference .../bindings/display/msm/dp-controller.yaml | 47 --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 ++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++- 3 files changed, 53 insertions(+), 20 deletions(-) -- 2.35.1
Re: [PATCH v2 1/2] dt-bindings: display: panel: Add Novatek NT35596S panel bindings
Hi Sam,
Thanks for your suggestions.
Sam Ravnborg 于 2022年7月10日周日 上午4:47写道：
> Hi Molly,
>
> thanks for the quick response to the review comments.
>
> On Sat, Jul 09, 2022 at 10:11:35PM +0800, MollySophia wrote:
> > Add documentation for "novatek,nt35596s" panel.
> >
> > Signed-off-by: MollySophia
> The s-o-b needs your real name - guess the above is a concatenation of
> first name and surname.
>
> The binding included in this patch fails the check:
> $ make DT_CHECKER_FLAGS=-m dt_binding_check
>
> You may need to run:
> $ pip3 install dtschema --upgrade
>
> Or you may have to install some dependencies first.
> The problem is that the patch is missing a "reset-gpios: true"
>
> On top of this I looked at the binding - and the description
> this is copied from is almost identical.
> So another approach would be to extend the existing binding like
> in the following.
>
> And this also gives a good hint that maybe this can be embedded in
> the existing driver - and there is no need for a new driver.
> Could you try to give this a spin and get back on this.
>
That's reasonable. Actually, this driver was modified from
novatek,nt35596s, with different panel initialization commands, and it
seems easy to be embedded in
the existing driver. However, I wonder what the driver file name would
be...? "panel-novatek-nt35596s-nt36672a.c" or something else?
Molly
Sorry for not seeing this in the first place.
>
> Sam
>
> diff --git
> a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
> b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
> index 41ee3157a1cd..913bb81ae93d 100644
> --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
> +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
> @@ -20,14 +20,20 @@ allOf:
>
> properties:
>compatible:
> -items:
> - - enum:
> - - tianma,fhd-video
> - - const: novatek,nt36672a
> +oneOf:
> + - items:
> + - enum:
> + - tianma,fhd-video
> + - const: novatek,nt36672a
> +
> + - items:
> + - enum:
> + - jdi,fhd-nt35596s
> + - const: novatek,nt35596s
> +
> description: This indicates the panel manufacturer of the panel that
> is
> - in turn using the NT36672A panel driver. This compatible string
> - determines how the NT36672A panel driver is configured for the
> indicated
> - panel. The novatek,nt36672a compatible shall always be provided as
> a fallback.
> + in turn using the NT36672A or the NT35596S panel driver. This
> compatible string
> + determines how the panel driver is configured for the indicated
> panel.
>
>reset-gpios:
> maxItems: 1
> @@ -85,4 +91,27 @@ examples:
> };
> };
>
> +dsi1 {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +panel@0 {
> +compatible = "jdi,fhd-nt35596s", "novatek,nt35596s";
> +reg = <0>;
> +vddi0-supply = <_l14a_1p88>;
> +vddpos-supply = <>;
> +vddneg-supply = <>;
> +
> +backlight = <_wled>;
> +reset-gpios = < 6 GPIO_ACTIVE_HIGH>;
> +
> +port {
> +jdi_nt35596s_in_1: endpoint {
> +remote-endpoint = <_out>;
> +};
> +};
> +};
> +};
> +
> +
> ...
>
> > ---
> > .../display/panel/novatek,nt35596s.yaml | 83 +++
> > 1 file changed, 83 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/display/panel/novatek,nt35596s.yaml
> >
> > diff --git
> a/Documentation/devicetree/bindings/display/panel/novatek,nt35596s.yaml
> b/Documentation/devicetree/bindings/display/panel/novatek,nt35596s.yaml
> > new file mode 100644
> > index ..f724f101a6fd
> > --- /dev/null
> > +++
> b/Documentation/devicetree/bindings/display/panel/novatek,nt35596s.yaml
> > @@ -0,0 +1,83 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/panel/novatek,nt35596s.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Novatek NT35596S based DSI display Panels
> > +
> > +maintainers:
> > + - Molly Sophia
> > +
> > +description: |
> > + The nt35596s IC from Novatek is a generic DSI Panel IC used to drive
> dsi
> > + panels.
> > + Right now, support is added only for a JDI FHD+ LCD display panel
> with a
> > + resolution of 1080x2160. It is a video mode DSI panel.
> > +
> > +allOf:
> > + - $ref: panel-common.yaml#
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - enum:
> > + - jdi,fhd-nt35596s
> > + - const: novatek,nt35596s
> > +description: This indicates the panel manufacturer of the panel
> that is
> > + in turn using the NT35596S panel driver. This compatible string
> > + determines how the NT35596S panel driver
