Re: [PATCH v5 3/3] dt-binding: mediatek: add MediaTek mt8195 MDP3 components
Hi Krzysztof, On Tue, 2023-09-12 at 10:19 +0200, Krzysztof Kozlowski wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 12/09/2023 09:56, Moudy Ho wrote: > > Introduce more MDP3 components present in MT8195. > > Please use subject prefixes matching the subsystem. You can get them > for > example with `git log --oneline -- DIRECTORY_OR_FILE` on the > directory > your patch is touching. > > > > > Signed-off-by: Moudy Ho > > --- > > .../display/mediatek/mediatek,aal.yaml| 2 +- > > .../display/mediatek/mediatek,color.yaml | 2 +- > > .../display/mediatek/mediatek,merge.yaml | 1 + > > .../display/mediatek/mediatek,ovl.yaml| 2 +- > > .../display/mediatek/mediatek,split.yaml | 1 + > > .../bindings/media/mediatek,mdp3-fg.yaml | 61 > +++ > > .../bindings/media/mediatek,mdp3-hdr.yaml | 60 > ++ > > .../bindings/media/mediatek,mdp3-pad.yaml | 61 > +++ > > .../bindings/media/mediatek,mdp3-rdma.yaml| 16 ++--- > > .../bindings/media/mediatek,mdp3-stitch.yaml | 61 > +++ > > .../bindings/media/mediatek,mdp3-tcc.yaml | 60 > ++ > > .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 > +++ > > 12 files changed, 378 insertions(+), 10 deletions(-) > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml > > > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > > index 7fd42c8fdc32..04b1314d00f2 100644 > > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yam > l > > @@ -24,6 +24,7 @@ properties: > >- enum: > >- mediatek,mt8173-disp-aal > >- mediatek,mt8183-disp-aal > > + - mediatek,mt8195-mdp3-aal > >- items: > >- enum: > >- mediatek,mt2712-disp-aal > > @@ -63,7 +64,6 @@ properties: > > required: > >- compatible > >- reg > > - - interrupts > > Why? commit msg tells nothing about it. Why interrupt is not erquired > in > mt8173? How dropping such requirement is anyhow related to mt8195? > > The signals of the MDP engines are completely controlled by MTK's MUTEX for starting and stopping frame processing, eliminating the need for additional interrupts. Considering the discussion in the previous version, it is advisable to merge it into the existing display binding files. Therefore, I tried removing the required conditions to facilitate file merging. However, for file integrity purposes, I should revert these changes and set the corresponding settings in DTS(even if they are not used). The other YAML files - color, merge and ovl - mentioned below will also be rectified in the next version. > >- power-domains > >- clocks > > > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > > index f21e44092043..8e97b0a6a7b3 100644 > > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.y > aml > > @@ -26,6 +26,7 @@ properties: > >- mediatek,mt2701-disp-color > >- mediatek,mt8167-disp-color > >- mediatek,mt8173-disp-color > > + - mediatek,mt8195-mdp3-color > >- items: > >- enum: > >- mediatek,mt7623-disp-color > > @@ -66,7 +67,6 @@ properties: > > required: > >- compatible > >- reg > > - - interrupts > > Why? > > >- power-domains > >- clocks > > > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y > aml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y > aml > > index eead5cb8636e..401498523404 100644 > > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y > aml > > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y > aml > > @@ -24,6 +24,7 @@ properties: > >- enum: > >- mediatek,mt8173-disp-merge > >- mediatek,mt8195-disp-merge > > + - mediatek,mt8195-mdp3-merge > >- items: > >- const: mediatek,mt6795-disp-merge
[PATCH v2 2/2] backlight: mp3309c: Add support for MPS MP3309C
The Monolithic Power (MPS) MP3309C is a WLED step-up converter, featuring a
programmable switching frequency to optimize efficiency.
The brightness can be controlled either by I2C commands (called "analog"
mode) or by a PWM input signal (PWM mode).
This driver supports both modes.
For DT configuration details, please refer to:
- Documentation/devicetree/bindings/leds/backlight/mps,mp3309c.yaml
The datasheet is available at:
- https://www.monolithicpower.com/en/mp3309c.html
Signed-off-by: Flavio Suligoi
---
v2:
- fix dependecies in Kconfig
- fix Kconfig MP3309C entry order
- remove switch-on-delay-ms property
- remove optional gpio property to reset external devices
- remove dimming-mode property (the analog-i2c dimming mode is the default; the
presence of the pwms property, in DT, selects automatically the pwm dimming
mode)
- substitute three boolean properties, used for the overvoltage-protection
values, with a single enum property
- drop simple tracing messages
- use dev_err_probe() in probe function
- change device name from mp3309c_bl to the simple mp3309c
- remove shutdown function
v1:
- first version
MAINTAINERS | 6 +
drivers/video/backlight/Kconfig | 11 +
drivers/video/backlight/Makefile | 1 +
drivers/video/backlight/mp3309c.c | 395 ++
4 files changed, 413 insertions(+)
create mode 100644 drivers/video/backlight/mp3309c.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 3be1bdfe8ecc..f779df433af1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14333,6 +14333,12 @@ S: Maintained
F: Documentation/driver-api/tty/moxa-smartio.rst
F: drivers/tty/mxser.*
+MP3309C BACKLIGHT DRIVER
+M: Flavio Suligoi
+S: Maintained
+F: Documentation/devicetree/bindings/leds/backlight/mps,mp3309c.yaml
+F: drivers/video/backlight/mp3309c.c
+
MR800 AVERMEDIA USB FM RADIO DRIVER
M: Alexey Klimov
L: linux-me...@vger.kernel.org
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 51387b1ef012..1144a54a35c0 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -402,6 +402,17 @@ config BACKLIGHT_LP8788
help
This supports TI LP8788 backlight driver.
+config BACKLIGHT_MP3309C
+ tristate "Backlight Driver for MPS MP3309C"
+ depends on I2C && PWM
+ select REGMAP_I2C
+ help
+ This supports MPS MP3309C backlight WLED driver in both PWM and
+ analog/I2C dimming modes.
+
+ To compile this driver as a module, choose M here: the module will
+ be called mp3309c.
+
config BACKLIGHT_PANDORA
tristate "Backlight driver for Pandora console"
depends on TWL4030_CORE
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index f72e1c3c59e9..1af583de665b 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_BACKLIGHT_LP855X)+= lp855x_bl.o
obj-$(CONFIG_BACKLIGHT_LP8788) += lp8788_bl.o
obj-$(CONFIG_BACKLIGHT_LV5207LP) += lv5207lp.o
obj-$(CONFIG_BACKLIGHT_MAX8925)+= max8925_bl.o
+obj-$(CONFIG_BACKLIGHT_MP3309C)+= mp3309c.o
obj-$(CONFIG_BACKLIGHT_MT6370) += mt6370-backlight.o
obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
obj-$(CONFIG_BACKLIGHT_PANDORA)+= pandora_bl.o
diff --git a/drivers/video/backlight/mp3309c.c
b/drivers/video/backlight/mp3309c.c
new file mode 100644
index ..470c960d7438
--- /dev/null
+++ b/drivers/video/backlight/mp3309c.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for MPS MP3309C White LED driver with I2C interface
+ *
+ * Copyright (C) 2023 ASEM Srl
+ * Author: Flavio Suligoi
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define REG_I2C_0 0x00
+#define REG_I2C_1 0x01
+
+#define REG_I2C_0_EN 0x80
+#define REG_I2C_0_D0 0x40
+#define REG_I2C_0_D1 0x20
+#define REG_I2C_0_D2 0x10
+#define REG_I2C_0_D3 0x08
+#define REG_I2C_0_D4 0x04
+#define REG_I2C_0_RSRV10x02
+#define REG_I2C_0_RSRV20x01
+
+#define REG_I2C_1_RSRV10x80
+#define REG_I2C_1_DIMS 0x40
+#define REG_I2C_1_SYNC 0x20
+#define REG_I2C_1_OVP0 0x10
+#define REG_I2C_1_OVP1 0x08
+#define REG_I2C_1_VOS 0x04
+#define REG_I2C_1_LEDO 0x02
+#define REG_I2C_1_OTP 0x01
+
+#define ANALOG_MAX_VAL 31
+#define ANALOG_REG_MASK 0x7c
+
+enum mp3309c_status_value {
+ FIRST_POWER_ON,
+ BACKLIGHT_OFF,
+ BACKLIGHT_ON,
+};
+
+enum mp3309c_dimming_mode_value {
+ DIMMING_PWM,
+ DIMMING_ANALOG_I2C,
+};
+
+struct mp3309c_platform_data {
+ u32 max_brightness;
+ u32 default_brightness;
+ u8 dimming_mode;
+ u8 over_voltage_protection;
+ bool sync_mode;
+ u8 status;
+};
+
+struct mp3309c_chip {
+ struct device *dev;
+ struct mp3309c_platform_data
Re: [PATCH v5 02/14] arm64: dts: mediatek: mt8195: add MDP3 nodes
On Tue, 2023-09-12 at 10:23 +0200, Krzysztof Kozlowski wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 12/09/2023 09:57, Moudy Ho wrote: > > Add device nodes for Media Data Path 3 (MDP3) modules. > > > > Signed-off-by: Moudy Ho > > --- > > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 378 > +++ > > 1 file changed, 378 insertions(+) > > Why is this targeting media? No, don't. DTS goes via SoC, not media. > Don't mix patches. > > Best regards, > Krzysztof > Hi Krzysztof, My apologies. I'll split these DTS into separate series. Sincerely, Moudy
[PATCH v5 07/14] media: platform: mtk-mdp3: add checks for dummy components
Some components act as bridges only and do not require full configuration.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 8 +++
.../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 1 +
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 58 ++-
3 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index 58792902abb5..b7efdafb1620 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -451,3 +451,11 @@ enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev
*mdp_dev, s32 inner_id
err_public_id:
return public_id;
}
+
+bool mdp_cfg_comp_is_dummy(struct mdp_dev *mdp_dev, s32 inner_id)
+{
+ enum mtk_mdp_comp_id id = mdp_cfg_get_id_public(mdp_dev, inner_id);
+ enum mdp_comp_type type = mdp_dev->mdp_data->comp_data[id].match.type;
+
+ return (type == MDP_COMP_TYPE_DUMMY);
+}
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
index dee57cc4a954..dfffc72868e4 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h
@@ -16,5 +16,6 @@ enum mtk_mdp_comp_id;
s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id);
enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 id);
+bool mdp_cfg_comp_is_dummy(struct mdp_dev *mdp_dev, s32 inner_id);
#endif /* __MTK_MDP3_CFG_H__ */
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index 6d04f72cf86f..6204173ecc5d 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -6,6 +6,7 @@
#include
#include
+#include "mtk-mdp3-cfg.h"
#include "mtk-mdp3-cmdq.h"
#include "mtk-mdp3-comp.h"
#include "mtk-mdp3-core.h"
@@ -115,6 +116,12 @@ static int mdp_path_subfrm_require(const struct mdp_path
*path,
/* Set mutex mod */
for (index = 0; index < num_comp; index++) {
+ s32 inner_id = MDP_COMP_NONE;
+
+ if (CFG_CHECK(MT8183, p_id))
+ inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
+ continue;
ctx = >comps[index];
if (is_output_disabled(p_id, ctx->param, count))
continue;
@@ -139,6 +146,7 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
int index;
u32 num_comp = 0;
s32 event;
+ s32 inner_id = MDP_COMP_NONE;
if (-1 == p->mutex_id) {
dev_err(dev, "Incorrect mutex id");
@@ -151,6 +159,10 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
/* Wait WROT SRAM shared to DISP RDMA */
/* Clear SOF event for each engine */
for (index = 0; index < num_comp; index++) {
+ if (CFG_CHECK(MT8183, p_id))
+ inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
+ continue;
ctx = >comps[index];
if (is_output_disabled(p_id, ctx->param, count))
continue;
@@ -165,6 +177,10 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
/* Wait SOF events and clear mutex modules (optional) */
for (index = 0; index < num_comp; index++) {
+ if (CFG_CHECK(MT8183, p_id))
+ inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
+ continue;
ctx = >comps[index];
if (is_output_disabled(p_id, ctx->param, count))
continue;
@@ -190,6 +206,12 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct
mdp_path *path)
return -EINVAL;
for (index = 0; index < num_comp; index++) {
+ s32 inner_id = MDP_COMP_NONE;
+
+ if (CFG_CHECK(MT8183, p_id))
+ inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
+ continue;
if (CFG_CHECK(MT8183, p_id))
param = (void *)CFG_ADDR(MT8183, path->config,
components[index]);
ret = mdp_comp_ctx_config(mdp, >comps[index],
@@ -211,6 +233,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
struct mdp_pipe_info pipe;
int index, ret;
u32 num_comp = 0;
+ s32 inner_id = MDP_COMP_NONE;
if (CFG_CHECK(MT8183, p_id))
[PATCH v5 3/3] dt-binding: mediatek: add MediaTek mt8195 MDP3 components
Introduce more MDP3 components present in MT8195. Signed-off-by: Moudy Ho --- .../display/mediatek/mediatek,aal.yaml| 2 +- .../display/mediatek/mediatek,color.yaml | 2 +- .../display/mediatek/mediatek,merge.yaml | 1 + .../display/mediatek/mediatek,ovl.yaml| 2 +- .../display/mediatek/mediatek,split.yaml | 1 + .../bindings/media/mediatek,mdp3-fg.yaml | 61 +++ .../bindings/media/mediatek,mdp3-hdr.yaml | 60 ++ .../bindings/media/mediatek,mdp3-pad.yaml | 61 +++ .../bindings/media/mediatek,mdp3-rdma.yaml| 16 ++--- .../bindings/media/mediatek,mdp3-stitch.yaml | 61 +++ .../bindings/media/mediatek,mdp3-tcc.yaml | 60 ++ .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++ 12 files changed, 378 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 7fd42c8fdc32..04b1314d00f2 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal @@ -63,7 +64,6 @@ properties: required: - compatible - reg - - interrupts - power-domains - clocks diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index f21e44092043..8e97b0a6a7b3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-disp-color - mediatek,mt8167-disp-color - mediatek,mt8173-disp-color + - mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color @@ -66,7 +67,6 @@ properties: required: - compatible - reg - - interrupts - power-domains - clocks diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index eead5cb8636e..401498523404 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-merge - mediatek,mt8195-disp-merge + - mediatek,mt8195-mdp3-merge - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 3e1069b00b56..10d4d4f64e09 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl + - mediatek,mt8195-mdp3-ovl - items: - enum: - mediatek,mt7623-disp-ovl @@ -76,7 +77,6 @@ properties: required: - compatible - reg - - interrupts - power-domains - clocks - iommus diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index a8a5c9608598..a96b271e3240 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt8173-disp-split + - mediatek,mt8195-mdp3-split - items: - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml new file mode 100644 index ..71fd449de8b4 ---
[PATCH] drm/msm/adreno: Add support for SM7150 SoC machine
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
to zero decimal places.
The vendor's FW GMU is called a618_gmu.bin. And also a618 on SM7150 uses
a615 zapfw.
Add this as machine = "qcom,sm7150", because speed-bin values are
different from atoll (sc7180/sm7125).
Signed-off-by: Danila Tikhonov
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index fa527935ffd4..64ef9813e9ae 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -293,6 +293,28 @@ static const struct adreno_info gpulist[] = {
{ 157, 3 },
{ 127, 4 },
),
+ }, {
+ .machine = "qcom,sm7150",
+ .chip_ids = ADRENO_CHIP_IDS(0x06010800),
+ .family = ADRENO_6XX_GEN1,
+ .revn = 618,
+ .fw = {
+ [ADRENO_FW_SQE] = "a630_sqe.fw",
+ [ADRENO_FW_GMU] = "a618_gmu.bin",
+ },
+ .gmem = SZ_512K,
+ .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+ .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
+ .init = a6xx_gpu_init,
+ .zapfw = "a615_zap.mdt",
+ .hwcg = a615_hwcg,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 128, 1 },
+ { 146, 2 },
+ { 167, 3 },
+ { 172, 4 },
+ ),
}, {
.chip_ids = ADRENO_CHIP_IDS(0x06010800),
.family = ADRENO_6XX_GEN1,
@@ -507,6 +529,10 @@ MODULE_FIRMWARE("qcom/a530_zap.b00");
MODULE_FIRMWARE("qcom/a530_zap.b01");
MODULE_FIRMWARE("qcom/a530_zap.b02");
MODULE_FIRMWARE("qcom/a540_gpmu.fw2");
+MODULE_FIRMWARE("qcom/a615_zap.mbt");
+MODULE_FIRMWARE("qcom/a615_zap.b00");
+MODULE_FIRMWARE("qcom/a615_zap.b01");
+MODULE_FIRMWARE("qcom/a615_zap.b02");
MODULE_FIRMWARE("qcom/a619_gmu.bin");
MODULE_FIRMWARE("qcom/a630_sqe.fw");
MODULE_FIRMWARE("qcom/a630_gmu.bin");
--
2.41.0
[PATCH v5 03/14] media: platform: mtk-mdp3: add support second sets of MMSYS
MT8195 has two MMSYS sets, VPPSYS0 and VPPSYS1.
These sets coordinate and control the clock, power, and
register settings needed for the components of MDP3.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 44 +--
.../platform/mediatek/mdp3/mtk-mdp3-comp.h| 1 +
.../platform/mediatek/mdp3/mtk-mdp3-core.c| 40 +++--
.../platform/mediatek/mdp3/mtk-mdp3-core.h| 3 ++
4 files changed, 53 insertions(+), 35 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index 502eeae0bfdc..58792902abb5 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -73,75 +73,75 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = {
static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {
[MDP_COMP_WPEI] = {
- {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI},
+ {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, 0},
{0, 0, 0}
},
[MDP_COMP_WPEO] = {
- {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO},
+ {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO, 0},
{0, 0, 0}
},
[MDP_COMP_WPEI2] = {
- {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2},
+ {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2, 0},
{0, 0, 0}
},
[MDP_COMP_WPEO2] = {
- {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2},
+ {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2, 0},
{0, 0, 0}
},
[MDP_COMP_ISP_IMGI] = {
- {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI},
+ {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, 0},
{0, 0, 4}
},
[MDP_COMP_ISP_IMGO] = {
- {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO},
+ {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO, 0},
{0, 0, 4}
},
[MDP_COMP_ISP_IMG2O] = {
- {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O},
+ {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O, 0},
{0, 0, 0}
},
[MDP_COMP_CAMIN] = {
- {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN},
+ {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN, 0},
{2, 2, 1}
},
[MDP_COMP_CAMIN2] = {
- {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2},
+ {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2, 0},
{2, 4, 1}
},
[MDP_COMP_RDMA0] = {
- {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0},
+ {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0, 0},
{2, 0, 0}
},
[MDP_COMP_CCORR0] = {
- {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0},
+ {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0, 0},
{1, 0, 0}
},
[MDP_COMP_RSZ0] = {
- {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0},
+ {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0, 0},
{1, 0, 0}
},
[MDP_COMP_RSZ1] = {
- {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1},
+ {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1, 0},
{1, 0, 0}
},
[MDP_COMP_TDSHP0] = {
- {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0},
+ {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0, 0},
{0, 0, 0}
},
[MDP_COMP_PATH0_SOUT] = {
- {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT},
+ {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT, 0},
{0, 0, 0}
},
[MDP_COMP_PATH1_SOUT] = {
- {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT},
+ {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT, 0},
{0, 0, 0}
},
[MDP_COMP_WROT0] = {
- {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0},
+ {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0, 0},
{1, 0, 0}
},
[MDP_COMP_WDMA] = {
- {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA},
+ {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA, 0},
{1, 0, 0}
},
};
@@ -402,10 +402,10 @@ static const struct mdp_limit mt8183_mdp_def_limit = {
};
static const struct mdp_pipe_info mt8183_pipe_info[] = {
- [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0},
- [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 1},
- [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 2},
- [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 3}
+ [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0, 0},
+ [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 0, 1},
+ [MDP_PIPE_IMGI] =
[PATCH v5 13/14] media: platform: mtk-mdp3: add mt8195 MDP3 component settings
Extend the component settings used in MT8195 MDP3.
Additionally, it is crucial to read all component settings in
a specific manner to ensure that shared memory data structure lengths
are aligned across different platforms.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 57 ++
.../platform/mediatek/mdp3/mtk-mdp3-comp.c| 787 +-
2 files changed, 840 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index 9c2afd002e7c..37964d230d9a 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -40,6 +40,10 @@ static bool is_output_disabled(int p_id, const struct
img_compparam *param, u32
num = CFG_COMP(MT8183, param, num_subfrms);
dis_output = CFG_COMP(MT8183, param, frame.output_disable);
dis_tile = CFG_COMP(MT8183, param, frame.output_disable);
+ } else if (CFG_CHECK(MT8195, p_id)) {
+ num = CFG_COMP(MT8195, param, num_subfrms);
+ dis_output = CFG_COMP(MT8195, param, frame.output_disable);
+ dis_tile = CFG_COMP(MT8195, param, frame.output_disable);
}
return (count < num) ? (dis_output || dis_tile) : true;
@@ -108,6 +112,8 @@ static int mdp_path_subfrm_require(const struct mdp_path
*path,
if (CFG_CHECK(MT8183, p_id))
num_comp = CFG_GET(MT8183, path->config, num_components);
+ else if (CFG_CHECK(MT8195, p_id))
+ num_comp = CFG_GET(MT8195, path->config, num_components);
/* Decide which mutex to use based on the current pipeline */
index = __get_pipe(path->mdp_dev, path->comps[0].comp->public_id);
@@ -122,6 +128,9 @@ static int mdp_path_subfrm_require(const struct mdp_path
*path,
if (CFG_CHECK(MT8183, p_id))
inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ else if (CFG_CHECK(MT8195, p_id))
+ inner_id = CFG_GET(MT8195, path->config,
components[index].type);
+
if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
continue;
@@ -163,12 +172,17 @@ static int mdp_path_subfrm_run(const struct mdp_path
*path,
if (CFG_CHECK(MT8183, p_id))
num_comp = CFG_GET(MT8183, path->config, num_components);
+ else if (CFG_CHECK(MT8195, p_id))
+ num_comp = CFG_GET(MT8195, path->config, num_components);
/* Wait WROT SRAM shared to DISP RDMA */
/* Clear SOF event for each engine */
for (index = 0; index < num_comp; index++) {
if (CFG_CHECK(MT8183, p_id))
inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ else if (CFG_CHECK(MT8195, p_id))
+ inner_id = CFG_GET(MT8195, path->config,
components[index].type);
+
if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
continue;
ctx = >comps[index];
@@ -187,6 +201,9 @@ static int mdp_path_subfrm_run(const struct mdp_path *path,
for (index = 0; index < num_comp; index++) {
if (CFG_CHECK(MT8183, p_id))
inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ else if (CFG_CHECK(MT8195, p_id))
+ inner_id = CFG_GET(MT8195, path->config,
components[index].type);
+
if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
continue;
ctx = >comps[index];
@@ -209,6 +226,8 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct
mdp_path *path)
if (CFG_CHECK(MT8183, p_id))
num_comp = CFG_GET(MT8183, path->config, num_components);
+ else if (CFG_CHECK(MT8195, p_id))
+ num_comp = CFG_GET(MT8195, path->config, num_components);
if (num_comp < 1)
return -EINVAL;
@@ -218,10 +237,15 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct
mdp_path *path)
if (CFG_CHECK(MT8183, p_id))
inner_id = CFG_GET(MT8183, path->config,
components[index].type);
+ else if (CFG_CHECK(MT8195, p_id))
+ inner_id = CFG_GET(MT8195, path->config,
components[index].type);
+
if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id))
continue;
if (CFG_CHECK(MT8183, p_id))
param = (void *)CFG_ADDR(MT8183, path->config,
components[index]);
+ else if (CFG_CHECK(MT8195, p_id))
+ param = (void *)CFG_ADDR(MT8195, path->config,
components[index]);
ret = mdp_comp_ctx_config(mdp, >comps[index],
param, path->param);
[PATCH v5 05/14] media: platform: mtk-mdp3: introduce more pipelines from MT8195
Increasing the number of sets built by MMSYS and MUTEX in MT8195
will enable the creation of more pipelines in MDP3.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 80 ---
.../platform/mediatek/mdp3/mtk-mdp3-core.h| 7 ++
2 files changed, 60 insertions(+), 27 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index 606651687465..6d04f72cf86f 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -57,6 +57,43 @@ static struct mtk_mutex *__get_mutex(const struct mdp_dev
*mdp_dev,
return m;
}
+static enum mdp_pipe_id __get_pipe(const struct mdp_dev *mdp_dev,
+ enum mtk_mdp_comp_id id)
+{
+ enum mdp_pipe_id pipe_id;
+
+ switch (id) {
+ case MDP_COMP_RDMA0:
+ pipe_id = MDP_PIPE_RDMA0;
+ break;
+ case MDP_COMP_ISP_IMGI:
+ pipe_id = MDP_PIPE_IMGI;
+ break;
+ case MDP_COMP_WPEI:
+ pipe_id = MDP_PIPE_WPEI;
+ break;
+ case MDP_COMP_WPEI2:
+ pipe_id = MDP_PIPE_WPEI2;
+ break;
+ case MDP_COMP_RDMA1:
+ pipe_id = MDP_PIPE_RDMA1;
+ break;
+ case MDP_COMP_RDMA2:
+ pipe_id = MDP_PIPE_RDMA2;
+ break;
+ case MDP_COMP_RDMA3:
+ pipe_id = MDP_PIPE_RDMA3;
+ break;
+ default:
+ /* Avoid exceptions when operating MUTEX */
+ pipe_id = MDP_PIPE_RDMA0;
+ dev_err(_dev->pdev->dev, "Unknown pipeline id %d", id);
+ break;
+ }
+
+ return pipe_id;
+}
+
static int mdp_path_subfrm_require(const struct mdp_path *path,
struct mdp_cmdq_cmd *cmd,
struct mdp_pipe_info *p, u32 count)
@@ -64,7 +101,6 @@ static int mdp_path_subfrm_require(const struct mdp_path
*path,
const int p_id = path->mdp_dev->mdp_data->mdp_plat_id;
const struct mdp_comp_ctx *ctx;
const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
- struct device *dev = >mdp_dev->pdev->dev;
struct mtk_mutex *mutex;
int id, index;
u32 num_comp = 0;
@@ -73,23 +109,7 @@ static int mdp_path_subfrm_require(const struct mdp_path
*path,
num_comp = CFG_GET(MT8183, path->config, num_components);
/* Decide which mutex to use based on the current pipeline */
- switch (path->comps[0].comp->public_id) {
- case MDP_COMP_RDMA0:
- index = MDP_PIPE_RDMA0;
- break;
- case MDP_COMP_ISP_IMGI:
- index = MDP_PIPE_IMGI;
- break;
- case MDP_COMP_WPEI:
- index = MDP_PIPE_WPEI;
- break;
- case MDP_COMP_WPEI2:
- index = MDP_PIPE_WPEI2;
- break;
- default:
- dev_err(dev, "Unknown pipeline and no mutex is assigned");
- return -EINVAL;
- }
+ index = __get_pipe(path->mdp_dev, path->comps[0].comp->public_id);
memcpy(p, >pipe_info[index], sizeof(struct mdp_pipe_info));
mutex = __get_mutex(path->mdp_dev, p);
@@ -343,11 +363,13 @@ static void mdp_auto_release_work(struct work_struct
*work)
struct mdp_cmdq_cmd *cmd;
struct mdp_dev *mdp;
struct mtk_mutex *mutex;
+ enum mdp_pipe_id pipe_id;
cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work);
mdp = cmd->mdp;
- mutex = __get_mutex(mdp, >mdp_data->pipe_info[MDP_PIPE_RDMA0]);
+ pipe_id = __get_pipe(mdp, cmd->comps[0].public_id);
+ mutex = __get_mutex(mdp, >mdp_data->pipe_info[pipe_id]);
mtk_mutex_unprepare(mutex);
mdp_comp_clocks_off(>pdev->dev, cmd->comps,
cmd->num_comps);
@@ -368,6 +390,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client
*cl, void *mssg)
struct cmdq_cb_data *data;
struct mdp_dev *mdp;
struct device *dev;
+ enum mdp_pipe_id pipe_id;
if (!mssg) {
pr_info("%s:no callback data\n", __func__);
@@ -395,7 +418,8 @@ static void mdp_handle_cmdq_callback(struct mbox_client
*cl, void *mssg)
struct mtk_mutex *mutex;
dev_err(dev, "%s:queue_work fail!\n", __func__);
- mutex = __get_mutex(mdp,
>mdp_data->pipe_info[MDP_PIPE_RDMA0]);
+ pipe_id = __get_pipe(mdp, cmd->comps[0].public_id);
+ mutex = __get_mutex(mdp, >mdp_data->pipe_info[pipe_id]);
mtk_mutex_unprepare(mutex);
mdp_comp_clocks_off(>pdev->dev, cmd->comps,
cmd->num_comps);
@@ -419,6 +443,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct
mdp_cmdq_param
[PATCH v5 14/14] media: platform: mtk-mdp3: add support for parallel pipe to improve FPS
In some chips, MDP3 has the ability to utilize two pipelines to
parallelly process a single frame.
To enable this feature, multiple CMDQ clients and packets need to
be configured at the same time.
Signed-off-by: Moudy Ho
---
.../platform/mediatek/mdp3/mdp_cfg_data.c | 8 +
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 188 +-
.../platform/mediatek/mdp3/mtk-mdp3-cmdq.h| 1 +
.../platform/mediatek/mdp3/mtk-mdp3-core.c| 18 +-
.../platform/mediatek/mdp3/mtk-mdp3-core.h| 12 +-
.../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 15 ++
.../platform/mediatek/mdp3/mtk-mdp3-regs.c| 18 ++
.../platform/mediatek/mdp3/mtk-mdp3-regs.h| 1 +
.../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 3 +-
9 files changed, 208 insertions(+), 56 deletions(-)
diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
index e23647c202c6..43ec37d34e38 100644
--- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
+++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c
@@ -1060,6 +1060,11 @@ static const struct mdp_pipe_info mt8195_pipe_info[] = {
[MDP_PIPE_VPP0_SOUT] = {MDP_PIPE_VPP0_SOUT, 1, 5},
};
+static const struct v4l2_rect mt8195_mdp_pp_criteria = {
+ .width = 1920,
+ .height = 1080,
+};
+
const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_plat_id = MT8183,
.mdp_con_res = 0x14001000,
@@ -1074,6 +1079,7 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data =
{
.def_limit = _mdp_def_limit,
.pipe_info = mt8183_pipe_info,
.pipe_info_len = ARRAY_SIZE(mt8183_pipe_info),
+ .pp_used = MDP_PP_USED_1,
};
const struct mtk_mdp_driver_data mt8195_mdp_driver_data = {
@@ -1090,6 +1096,8 @@ const struct mtk_mdp_driver_data mt8195_mdp_driver_data =
{
.def_limit = _mdp_def_limit,
.pipe_info = mt8195_pipe_info,
.pipe_info_len = ARRAY_SIZE(mt8195_pipe_info),
+ .pp_criteria = _mdp_pp_criteria,
+ .pp_used = MDP_PP_USED_2,
};
s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)
diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
index 37964d230d9a..41bd5fe416af 100644
--- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
@@ -62,6 +62,16 @@ static struct mtk_mutex *__get_mutex(const struct mdp_dev
*mdp_dev,
return m;
}
+static u8 __get_pp_num(enum mdp_stream_type type)
+{
+ switch (type) {
+ case MDP_STREAM_TYPE_DUAL_BITBLT:
+ return MDP_PP_USED_2;
+ default:
+ return MDP_PP_USED_1;
+ }
+}
+
static enum mdp_pipe_id __get_pipe(const struct mdp_dev *mdp_dev,
enum mtk_mdp_comp_id id)
{
@@ -99,6 +109,44 @@ static enum mdp_pipe_id __get_pipe(const struct mdp_dev
*mdp_dev,
return pipe_id;
}
+static struct img_config *__get_config_offset(struct mdp_dev *mdp,
+ struct mdp_cmdq_param *param,
+ u8 pp_idx)
+{
+ const int p_id = mdp->mdp_data->mdp_plat_id;
+ struct device *dev = >pdev->dev;
+ void *cfg_c, *cfg_n;
+ long bound = mdp->vpu.config_size;
+
+ if (pp_idx >= mdp->mdp_data->pp_used)
+ goto err_param;
+
+ if (CFG_CHECK(MT8183, p_id))
+ cfg_c = CFG_OFST(MT8183, param->config, pp_idx);
+ else if (CFG_CHECK(MT8195, p_id))
+ cfg_c = CFG_OFST(MT8195, param->config, pp_idx);
+ else
+ goto err_param;
+
+ if (CFG_CHECK(MT8183, p_id))
+ cfg_n = CFG_OFST(MT8183, param->config, pp_idx + 1);
+ else if (CFG_CHECK(MT8195, p_id))
+ cfg_n = CFG_OFST(MT8195, param->config, pp_idx + 1);
+ else
+ goto err_param;
+
+ if ((long)cfg_n - (long)mdp->vpu.config > bound) {
+ dev_err(dev, "config offset %ld OOB %ld\n", (long)cfg_n, bound);
+ cfg_c = ERR_PTR(-EFAULT);
+ }
+
+ return (struct img_config *)cfg_c;
+
+err_param:
+ cfg_c = ERR_PTR(-EINVAL);
+ return (struct img_config *)cfg_c;
+}
+
static int mdp_path_subfrm_require(const struct mdp_path *path,
struct mdp_cmdq_cmd *cmd,
struct mdp_pipe_info *p, u32 count)
@@ -483,8 +531,19 @@ static void mdp_auto_release_work(struct work_struct *work)
mdp_comp_clocks_off(>pdev->dev, cmd->comps,
cmd->num_comps);
- atomic_dec(>job_count);
- wake_up(>callback_wq);
+ if (atomic_dec_and_test(>job_count)) {
+ if (cmd->mdp_ctx)
+ mdp_m2m_job_finish(cmd->mdp_ctx);
+
+ if (cmd->user_cmdq_cb) {
+ struct cmdq_cb_data user_cb_data;
+
+
Re: [RFC PATCH 8/8] dt-bindings: display: panel: add Fascontek FS035VG158 panel
On Tue, Sep 12, 2023 at 08:55:31AM +0200, Krzysztof Kozlowski wrote: > On 11/09/2023 18:47, John Watts wrote: > > On Mon, Sep 11, 2023 at 01:49:39PM +0200, Krzysztof Kozlowski wrote: > >> If the other panel has exactly the same case, then yes, you can do like > >> this. But it depends on the bindings - to which ones do you refer as > >> your tmeplate? > > > > Documentation/devicetree/bindings/display/panel/leadtek,ltk035c5444t.yaml > > The file is indeed serving as poor example. I'm happy to fix it up according to your response and include it in v2 of the RFC. Should this be split in to two RFCs- one for cleanup, one for the new panel? > > Best regards, > Krzysztof > John.
Re: [PATCH v5 03/14] media: platform: mtk-mdp3: add support second sets of MMSYS
Hi Angelo,
On Tue, 2023-09-12 at 11:18 +0200, AngeloGioacchino Del Regno wrote:
> Il 12/09/23 09:57, Moudy Ho ha scritto:
> > MT8195 has two MMSYS sets, VPPSYS0 and VPPSYS1.
> > These sets coordinate and control the clock, power, and
> > register settings needed for the components of MDP3.
> >
> > Signed-off-by: Moudy Ho
> > ---
> > .../platform/mediatek/mdp3/mdp_cfg_data.c | 44 +-
> > -
> > .../platform/mediatek/mdp3/mtk-mdp3-comp.h| 1 +
> > .../platform/mediatek/mdp3/mtk-mdp3-core.c| 40 +++---
> > ---
> > .../platform/mediatek/mdp3/mtk-mdp3-core.h| 3 ++
> > 4 files changed, 53 insertions(+), 35 deletions(-)
(snip)
> > diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
> > b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
> > index cc44be10fdb7..9c33d3aaf9cd 100644
> > --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
> > +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
> > @@ -26,39 +26,45 @@ static const struct of_device_id mdp_of_ids[] =
> > {
> > MODULE_DEVICE_TABLE(of, mdp_of_ids);
> >
> > static struct platform_device *__get_pdev_by_id(struct
> > platform_device *pdev,
> > + struct platform_device
> > *from,
> > enum mdp_infra_id id)
> > {
> > - struct device_node *node;
> > + struct device_node *node, *f = NULL;
> > struct platform_device *mdp_pdev = NULL;
> > const struct mtk_mdp_driver_data *mdp_data;
> > const char *compat;
> >
> > if (!pdev)
> > - return NULL;
> > + return ERR_PTR(-ENODEV);
> >
>
> Fixing the error handling shall be done in a different commit, which
> shall also
> have a Fixes tag: this is both for backporting purposes and because
> those fixes
> are not relevant to adding support for secondary sets of MMSYS (so,
> those are
> not relevant for this specific commit).
>
Thanks forreminding me. I will address this error handing separately in
a dedicated fix patch.
> > if (id < MDP_INFRA_MMSYS || id >= MDP_INFRA_MAX) {
> > dev_err(>dev, "Illegal infra id %d\n", id);
> > - return NULL;
> > + return ERR_PTR(-ENODEV);
> > }
> >
> > mdp_data = of_device_get_match_data(>dev);
> > if (!mdp_data) {
> > dev_err(>dev, "have no driver data to find
> > node\n");
> > - return NULL;
> > + return ERR_PTR(-ENODEV);
> > }
> > +
> > compat = mdp_data->mdp_probe_infra[id].compatible;
> > + if (strlen(compat) == 0)
> > + return NULL;
> >
> > - node = of_find_compatible_node(NULL, NULL, compat);
> > + if (from)
> > + f = from->dev.of_node;
> > + node = of_find_compatible_node(f, NULL, compat);
> > if (WARN_ON(!node)) {
> > dev_err(>dev, "find node from id %d failed\n",
> > id);
> > - return NULL;
> > + return ERR_PTR(-ENODEV);
> > }
> >
> > mdp_pdev = of_find_device_by_node(node);
> > of_node_put(node);
> > if (WARN_ON(!mdp_pdev)) {
> > dev_err(>dev, "find pdev from id %d failed\n",
> > id);
> > - return NULL;
> > + return ERR_PTR(-ENODEV);
> > }
> >
> > return mdp_pdev;
> > @@ -152,7 +158,7 @@ static int mdp_probe(struct platform_device
> > *pdev)
> > {
> > struct device *dev = >dev;
> > struct mdp_dev *mdp;
> > - struct platform_device *mm_pdev;
> > + struct platform_device *mm_pdev, *mm2_pdev;
> > int ret, i, mutex_id;
> >
> > mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
> > @@ -164,15 +170,23 @@ static int mdp_probe(struct platform_device
> > *pdev)
> > mdp->pdev = pdev;
> > mdp->mdp_data = of_device_get_match_data(>dev);
> >
> > - mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_MMSYS);
> > - if (!mm_pdev) {
> > + mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_MMSYS);
> > + if (IS_ERR_OR_NULL(mm_pdev)) {
> > ret = -ENODEV;
> > goto err_destroy_device;
> > }
> > mdp->mdp_mmsys = _pdev->dev;
> >
> > - mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_MUTEX);
> > - if (WARN_ON(!mm_pdev)) {
> > + /* MMSYS2 is not available on all chips, so the config may be
> > null. */
> > + mm2_pdev = __get_pdev_by_id(pdev, mm_pdev, MDP_INFRA_MMSYS2);
> > + if (IS_ERR(mm2_pdev)) {
> > + ret = PTR_ERR(mm2_pdev);
> > + goto err_destroy_device;
> > + }
> > + mdp->mdp_mmsys2 = _pdev->dev;
> > +
> > + mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_MUTEX);
> > + if (IS_ERR_OR_NULL(mm_pdev)) {
> > ret = -ENODEV;
> > goto err_destroy_device;
> > }
> > @@ -208,7 +222,7 @@ static int mdp_probe(struct platform_device
> > *pdev)
> > goto err_destroy_job_wq;
> > }
> >
> > - mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_SCP);
> > + mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_SCP);
> > if (WARN_ON(!mm_pdev)) {
> >
[PATCH v5 2/3] dt-binding: mediatek: integrate MDP RDMA to one binding
Due to the same hardware design, MDP RDMA needs to
be integrated into the same binding.
Signed-off-by: Moudy Ho
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 88 ---
.../bindings/media/mediatek,mdp3-rdma.yaml| 5 +-
2 files changed, 3 insertions(+), 90 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
deleted file mode 100644
index dd12e2ff685c..
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ /dev/null
@@ -1,88 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek MDP RDMA
-
-maintainers:
- - Chun-Kuang Hu
- - Philipp Zabel
-
-description:
- The MediaTek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for
details.
-
-properties:
- compatible:
-const: mediatek,mt8195-vdo1-rdma
-
- reg:
-maxItems: 1
-
- interrupts:
-maxItems: 1
-
- power-domains:
-maxItems: 1
-
- clocks:
-items:
- - description: RDMA Clock
-
- iommus:
-maxItems: 1
-
- mediatek,gce-client-reg:
-description:
- The register of display function block to be set by gce. There are 4
arguments,
- such as gce node, subsys id, offset and register size. The subsys id
that is
- mapping to the register of display function blocks is defined in the gce
header
- include/dt-bindings/gce/-gce.h of each chips.
-$ref: /schemas/types.yaml#/definitions/phandle-array
-items:
- items:
-- description: phandle of GCE
-- description: GCE subsys id
-- description: register offset
-- description: register size
-maxItems: 1
-
-required:
- - compatible
- - reg
- - power-domains
- - clocks
- - iommus
- - mediatek,gce-client-reg
-
-additionalProperties: false
-
-examples:
- - |
-#include
-#include
-#include
-#include
-#include
-
-soc {
-#address-cells = <2>;
-#size-cells = <2>;
-
-rdma@1c104000 {
-compatible = "mediatek,mt8195-vdo1-rdma";
-reg = <0 0x1c104000 0 0x1000>;
-interrupts = ;
-clocks = < CLK_VDO1_MDP_RDMA0>;
-power-domains = < MT8195_POWER_DOMAIN_VDOSYS1>;
-iommus = <_vdo M4U_PORT_L2_MDP_RDMA0>;
-mediatek,gce-client-reg = < SUBSYS_1c10 0x4000 0x1000>;
-};
-};
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index 3e128733ef53..0c22571d8c22 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -20,8 +20,9 @@ description: |
properties:
compatible:
-items:
- - const: mediatek,mt8183-mdp3-rdma
+enum:
+ - mediatek,mt8183-mdp3-rdma
+ - mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
--
2.18.0
[PATCH v5 0/3] introduce more MDP3 components in mt8195
Changes since v4: - Rebase on v6.6-rc1 - Organize identical hardware components into their respective files. Hi, The purpose of this patch is to separate the MDP3-related bindings from the original mailing list mentioned below: https://lore.kernel.org/all/20230208092209.19472-1-moudy...@mediatek.com/ Those binding files describe additional components that are present in the mt8195. Moudy Ho (3): dt-binding: mediatek: correct MDP3 node with generic names dt-binding: mediatek: integrate MDP RDMA to one binding dt-binding: mediatek: add MediaTek mt8195 MDP3 components .../display/mediatek/mediatek,aal.yaml| 2 +- .../display/mediatek/mediatek,color.yaml | 2 +- .../display/mediatek/mediatek,mdp-rdma.yaml | 88 --- .../display/mediatek/mediatek,merge.yaml | 1 + .../display/mediatek/mediatek,ovl.yaml| 2 +- .../display/mediatek/mediatek,split.yaml | 1 + .../bindings/media/mediatek,mdp3-fg.yaml | 61 + .../bindings/media/mediatek,mdp3-hdr.yaml | 60 + .../bindings/media/mediatek,mdp3-pad.yaml | 61 + .../bindings/media/mediatek,mdp3-rdma.yaml| 50 ++- .../bindings/media/mediatek,mdp3-stitch.yaml | 61 + .../bindings/media/mediatek,mdp3-tcc.yaml | 60 + .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 + .../bindings/media/mediatek,mdp3-wrot.yaml| 23 +++-- 14 files changed, 412 insertions(+), 121 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml -- 2.18.0
[PATCH v5 06/14] media: platform: mtk-mdp3: introduce more MDP3 components
Add configuration of more components in MT8195 MDP3. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_reg_aal.h | 25 ++ .../platform/mediatek/mdp3/mdp_reg_color.h| 31 +++ .../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 + .../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 +++ .../platform/mediatek/mdp3/mdp_reg_merge.h| 25 ++ .../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 ++ .../platform/mediatek/mdp3/mdp_reg_pad.h | 21 + .../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 ++ .../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 + .../platform/mediatek/mdp3/mdp_reg_tdshp.h| 34 .../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.h| 85 +++ 12 files changed, 318 insertions(+), 16 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h new file mode 100644 index ..4b9513e54543 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_AAL_H__ +#define __MDP_REG_AAL_H__ + +#define MDP_AAL_EN (0x000) +#define MDP_AAL_CFG(0x020) +#define MDP_AAL_SIZE (0x030) +#define MDP_AAL_OUTPUT_SIZE(0x034) +#define MDP_AAL_OUTPUT_OFFSET (0x038) +#define MDP_AAL_CFG_MAIN (0x200) + +/* MASK */ +#define MDP_AAL_EN_MASK(0x01) +#define MDP_AAL_CFG_MASK (0x70FF00B3) +#define MDP_AAL_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_AAL_CFG_MAIN_MASK (0x0FE) + +#endif // __MDP_REG_AAL_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h new file mode 100644 index ..f72503975b24 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_COLOR_H__ +#define __MDP_REG_COLOR_H__ + +#define MDP_COLOR_WIN_X_MAIN (0x40C) +#define MDP_COLOR_WIN_Y_MAIN (0x410) +#define MDP_COLOR_START(0xC00) +#define MDP_COLOR_INTEN(0xC04) +#define MDP_COLOR_OUT_SEL (0xC0C) +#define MDP_COLOR_INTERNAL_IP_WIDTH(0xC50) +#define MDP_COLOR_INTERNAL_IP_HEIGHT (0xC54) +#define MDP_COLOR_CM1_EN (0xC60) +#define MDP_COLOR_CM2_EN (0xCA0) + +/* MASK */ +#define MDP_COLOR_WIN_X_MAIN_MASK (0x) +#define MDP_COLOR_WIN_Y_MAIN_MASK (0x) +#define MDP_COLOR_START_MASK (0x0FF013F) +#define MDP_COLOR_INTEN_MASK (0x07) +#define MDP_COLOR_OUT_SEL_MASK (0x0777) +#define MDP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF) +#define MDP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF) +#define MDP_COLOR_CM1_EN_MASK (0x03) +#define MDP_COLOR_CM2_EN_MASK (0x017) + +#endif // __MDP_REG_COLOR_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h new file mode 100644 index ..d90bcad33a59 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_FG_H__ +#define __MDP_REG_FG_H__ + +#define MDP_FG_TRIGGER (0x0) +#define MDP_FG_FG_CTRL_0 (0x20) +#define MDP_FG_FG_CK_EN(0x24) +#define MDP_FG_TILE_INFO_0 (0x418) +#define MDP_FG_TILE_INFO_1 (0x41c) + +/* MASK */ +#define MDP_FG_TRIGGER_MASK(0x0007) +#define MDP_FG_FG_CTRL_0_MASK (0x0033) +#define MDP_FG_FG_CK_EN_MASK (0x000F) +#define MDP_FG_TILE_INFO_0_MASK(0x) +#define MDP_FG_TILE_INFO_1_MASK
Re: [PATCH v5 2/3] dt-binding: mediatek: integrate MDP RDMA to one binding
On Tue, 2023-09-12 at 10:16 +0200, Krzysztof Kozlowski wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 12/09/2023 09:56, Moudy Ho wrote: > > Due to the same hardware design, MDP RDMA needs to > > be integrated into the same binding. > > > > Please use subject prefixes matching the subsystem. You can get them > for > example with `git log --oneline -- DIRECTORY_OR_FILE` on the > directory > your patch is touching. > > This applies to entire patchset. It is not dt-binding, but dt- > bindings. > > > Signed-off-by: Moudy Ho > > --- > > .../display/mediatek/mediatek,mdp-rdma.yaml | 88 - > -- > > .../bindings/media/mediatek,mdp3-rdma.yaml| 5 +- > > 2 files changed, 3 insertions(+), 90 deletions(-) > > delete mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > > > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > > deleted file mode 100644 > > index dd12e2ff685c.. > > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp- > rdma.yaml > > +++ /dev/null > > @@ -1,88 +0,0 @@ > > -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > -%YAML 1.2 > > > > -$id: > http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# > > -$schema: http://devicetree.org/meta-schemas/core.yaml# > > - > > -title: MediaTek MDP RDMA > > - > > -maintainers: > > - - Chun-Kuang Hu > > - - Philipp Zabel > > - > > -description: > > - The MediaTek MDP RDMA stands for Read Direct Memory Access. > > - It provides real time data to the back-end panel driver, such as > DSI, > > - DPI and DP_INTF. > > - It contains one line buffer to store the sufficient pixel data. > > - RDMA device node must be siblings to the central MMSYS_CONFIG > node. > > - For a description of the MMSYS_CONFIG binding, see > > > - Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > for details. > > - > > -properties: > > - compatible: > > -const: mediatek,mt8195-vdo1-rdma > > - > > - reg: > > -maxItems: 1 > > - > > - interrupts: > > -maxItems: 1 > > - > > - power-domains: > > -maxItems: 1 > > - > > - clocks: > > -items: > > - - description: RDMA Clock > > This is different and you did not explain it in commit msg. > > Another difference - mboxes. Looks like you did not test your DTS... > > Best regards, > Krzysztof > Hi Krzysztof, Sorry for the inconvenience. The property you mentioned was removed on [3/3]. This incorrect configuration went unnoticed because I passed the test with the entire series. It will be recified in the next version. Sincerely, Moudy
[PATCH] staging: fbtft: Removed unnecessary parenthesis around conditions to comply with the checkpatch coding style.
---
drivers/staging/fbtft/fb_ra8875.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/fbtft/fb_ra8875.c
b/drivers/staging/fbtft/fb_ra8875.c
index 398bdbf53c9a..658f915b8528 100644
--- a/drivers/staging/fbtft/fb_ra8875.c
+++ b/drivers/staging/fbtft/fb_ra8875.c
@@ -50,7 +50,7 @@ static int init_display(struct fbtft_par *par)
par->fbtftops.reset(par);
- if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
+ if (par->info->var.xres == 320 && par->info->var.yres == 240) {
/* PLL clock frequency */
write_reg(par, 0x88, 0x0A);
write_reg(par, 0x89, 0x02);
@@ -74,8 +74,7 @@ static int init_display(struct fbtft_par *par)
write_reg(par, 0x1D, 0x0E);
write_reg(par, 0x1E, 0x00);
write_reg(par, 0x1F, 0x02);
- } else if ((par->info->var.xres == 480) &&
- (par->info->var.yres == 272)) {
+ } else if (par->info->var.xres == 480 && par->info->var.yres == 272) {
/* PLL clock frequency */
write_reg(par, 0x88, 0x0A);
write_reg(par, 0x89, 0x02);
@@ -99,8 +98,7 @@ static int init_display(struct fbtft_par *par)
write_reg(par, 0x1D, 0x07);
write_reg(par, 0x1E, 0x00);
write_reg(par, 0x1F, 0x09);
- } else if ((par->info->var.xres == 640) &&
- (par->info->var.yres == 480)) {
+ } else if (par->info->var.xres == 640 && par->info->var.yres == 480) {
/* PLL clock frequency */
write_reg(par, 0x88, 0x0B);
write_reg(par, 0x89, 0x02);
@@ -124,8 +122,7 @@ static int init_display(struct fbtft_par *par)
write_reg(par, 0x1D, 0x0E);
write_reg(par, 0x1E, 0x00);
write_reg(par, 0x1F, 0x01);
- } else if ((par->info->var.xres == 800) &&
- (par->info->var.yres == 480)) {
+ } else if (par->info->var.xres == 800 && par->info->var.yres == 480) {
/* PLL clock frequency */
write_reg(par, 0x88, 0x0B);
write_reg(par, 0x89, 0x02);
--
2.40.1
Re: [PATCH] drm/tests: provide exit function
On 2023-09-14 15:00, Maxime Ripard wrote: On Wed, Sep 13, 2023 at 07:35:57PM +0300, José Pekkarinen wrote: On 2023-09-13 17:41, mrip...@kernel.org wrote: > On Wed, Sep 13, 2023 at 05:01:40PM +0300, José Pekkarinen wrote: > > On 2023-09-13 12:50, Maxime Ripard wrote: > > > Hi, > > > > > > On Wed, Sep 13, 2023 at 11:32:23AM +0300, José Pekkarinen wrote: > > > > Running drm_exec_test by modprobing the module I > > > > observe the following output: > > > > > > > > [ 424.471936] KTAP version 1 > > > > [ 424.471942] 1..1 > > > > [ 424.472446] KTAP version 1 > > > > [ 424.472450] # Subtest: drm_exec > > > > [ 424.472453] # module: drm_exec_test > > > > [ 424.472459] 1..7 > > > > [ 424.479082] > > > > == > > > > [ 424.479095] BUG: KASAN: slab-use-after-free in > > > > drm_dev_put.part.0+0x4b/0x90 [drm] > > > > [ 424.479426] Read of size 8 at addr 888132d3e028 by task > > > > kunit_try_catch/1866 > > > > [ 424.479436] > > > > [ 424.479442] CPU: 1 PID: 1866 Comm: kunit_try_catch Tainted: G > > > > N 6.6.0-rc1-dirty #2 > > > > > > That's suspicious > > > > > > > [ 424.479446] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), > > > > BIOS 0.0.0 02/06/2015 > > > > [ 424.479446] Call Trace: > > > > [ 424.479446] > > > > [ 424.479446] dump_stack_lvl+0x43/0x60 > > > > [ 424.479446] print_report+0xcf/0x660 > > > > [ 424.479446] ? __virt_addr_valid+0xd9/0x160 > > > > [ 424.479446] ? drm_dev_put.part.0+0x4b/0x90 [drm] > > > > [ 424.479446] kasan_report+0xda/0x110 > > > > [ 424.479446] ? drm_dev_put.part.0+0x4b/0x90 [drm] > > > > [ 424.479446] drm_dev_put.part.0+0x4b/0x90 [drm] > > > > [ 424.479446] release_nodes+0x83/0x160 > > > > [ 424.479446] devres_release_all+0xe6/0x130 > > > > [ 424.479446] ? __pfx_devres_release_all+0x10/0x10 > > > > [ 424.479446] ? mutex_unlock+0x80/0xd0 > > > > [ 424.479446] ? __pfx_mutex_unlock+0x10/0x10 > > > > [ 424.479446] device_unbind_cleanup+0x16/0xc0 > > > > [ 424.479446] device_release_driver_internal+0x28b/0x2e0 > > > > [ 424.479446] bus_remove_device+0x124/0x1d0 > > > > [ 424.479446] device_del+0x23d/0x580 > > > > [ 424.479446] ? __pfx_device_del+0x10/0x10 > > > > [ 424.479446] ? kasan_set_track+0x21/0x30 > > > > [ 424.479446] ? _raw_spin_lock_irqsave+0x98/0xf0 > > > > [ 424.479446] platform_device_del.part.0+0x19/0xe0 > > > > [ 424.479446] kunit_remove_resource+0xfa/0x140 [kunit] > > > > [ 424.479446] kunit_cleanup+0x47/0xa0 [kunit] > > > > [ 424.479446] ? __pfx_kunit_try_run_case_cleanup+0x10/0x10 [kunit] > > > > [ 424.479446] ? __pfx_kunit_generic_run_threadfn_adapter+0x10/0x10 > > > > [kunit] > > > > [ 424.479446] kunit_generic_run_threadfn_adapter+0x29/0x50 [kunit] > > > > [ 424.479446] kthread+0x184/0x1c0 > > > > [ 424.479446] ? __pfx_kthread+0x10/0x10 > > > > [ 424.479446] ret_from_fork+0x30/0x50 > > > > [ 424.479446] ? __pfx_kthread+0x10/0x10 > > > > [ 424.479446] ret_from_fork_asm+0x1b/0x30 > > > > [ 424.479446] > > > > [ 424.479446] > > > > [ 424.479446] Allocated by task 1865: > > > > [ 424.479446] kasan_save_stack+0x2f/0x50 > > > > [ 424.479446] kasan_set_track+0x21/0x30 > > > > [ 424.479446] __kasan_kmalloc+0xa6/0xb0 > > > > [ 424.479446] __kmalloc+0x5d/0x160 > > > > [ 424.479446] kunit_kmalloc_array+0x1c/0x50 [kunit] > > > > [ 424.479446] drm_exec_test_init+0xef/0x260 [drm_exec_test] > > > > [ 424.479446] kunit_try_run_case+0x6e/0x100 [kunit] > > > > [ 424.479446] kunit_generic_run_threadfn_adapter+0x29/0x50 [kunit] > > > > [ 424.479446] kthread+0x184/0x1c0 > > > > [ 424.479446] ret_from_fork+0x30/0x50 > > > > [ 424.479446] ret_from_fork_asm+0x1b/0x30 > > > > [ 424.479446] > > > > [ 424.479446] Freed by task 1866: > > > > [ 424.479446] kasan_save_stack+0x2f/0x50 > > > > [ 424.479446] kasan_set_track+0x21/0x30 > > > > [ 424.479446] kasan_save_free_info+0x27/0x40 > > > > [ 424.479446] kasan_slab_free+0x166/0x1c0 > > > > [ 424.479446] slab_free_freelist_hook+0x9f/0x1e0 > > > > [ 424.479446] __kmem_cache_free+0x187/0x2d0 > > > > [ 424.479446] kunit_remove_resource+0xfa/0x140 [kunit] > > > > [ 424.479446] kunit_cleanup+0x47/0xa0 [kunit] > > > > [ 424.479446] kunit_generic_run_threadfn_adapter+0x29/0x50 [kunit] > > > > [ 424.479446] kthread+0x184/0x1c0 > > > > [ 424.479446] ret_from_fork+0x30/0x50 > > > > [ 424.479446] ret_from_fork_asm+0x1b/0x30 > > > > [ 424.479446] > > > > [ 424.479446] The buggy address belongs to the object at > > > > 888132d3e000 > > > > [ 424.479446] which belongs to the cache kmalloc-256 of size 256 > > > > [ 424.479446] The buggy address is located 40 bytes inside of > > > > [ 424.479446] freed 256-byte region [888132d3e000, > > > > 888132d3e100) > > > > [ 424.479446] > > > > [ 424.479446] The buggy address belongs to the physical page: > > > > [ 424.479446] page:92ff6551 refcount:1 mapcount:0 > > > >
[PATCH v5 00/14] add support MDP3 on MT8195 platform
Changes since v4: - Rebase on v6.6-rc1 - Remove any unnecessary DTS settings. - Adjust the usage of MOD and clock in blending components. Changes since v3: - Depend on : [1] https://patchwork.kernel.org/project/linux-media/list/?series=719841 - Suggested by Krzysztof, integrating all newly added bindings for the mt8195 MDP3 into the file "mediatek,mt8195-mdp3.yaml". - Revise MDP3 nodes with generic names. Changes since v2: - Depend on : [1] MMSYS/MUTEX: https://patchwork.kernel.org/project/linux-mediatek/list/?series=711592 [2] MDP3: https://patchwork.kernel.org/project/linux-mediatek/list/?series=711618 - Suggested by Rob to revise MDP3 bindings to pass dtbs check - Add parallel paths feature. - Add blended components settings. Changes since v1: - Depend on : [1] MDP3 : https://patchwork.kernel.org/project/linux-mediatek/list/?series=698872 [2] MMSYS/MUTEX: https://patchwork.kernel.org/project/linux-mediatek/list/?series=684959 - Fix compilation failure due to use of undeclared identifier in file "mtk-mdp3-cmdq.c" Hello, This patch is used to add support for MDP3 on the MT8195 platform that contains more picture quality components, and can arrange more pipelines through two sets of MMSYS and MUTEX respectively. Moudy Ho (14): arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes arm64: dts: mediatek: mt8195: add MDP3 nodes media: platform: mtk-mdp3: add support second sets of MMSYS media: platform: mtk-mdp3: add support second sets of MUTEX media: platform: mtk-mdp3: introduce more pipelines from MT8195 media: platform: mtk-mdp3: introduce more MDP3 components media: platform: mtk-mdp3: add checks for dummy components media: platform: mtk-mdp3: avoid multiple driver registrations media: platform: mtk-mdp3: extend GCE event waiting in RDMA and WROT media: platform: mtk-mdp3: add support for blending multiple components media: platform: mtk-mdp3: add mt8195 platform configuration media: platform: mtk-mdp3: add mt8195 shared memory configurations media: platform: mtk-mdp3: add mt8195 MDP3 component settings media: platform: mtk-mdp3: add support for parallel pipe to improve FPS arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 +- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 378 .../platform/mediatek/mdp3/mdp_cfg_data.c | 729 ++- .../platform/mediatek/mdp3/mdp_reg_aal.h | 25 + .../platform/mediatek/mdp3/mdp_reg_color.h| 31 + .../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 + .../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 + .../platform/mediatek/mdp3/mdp_reg_merge.h| 25 + .../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 + .../platform/mediatek/mdp3/mdp_reg_pad.h | 21 + .../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 + .../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 + .../platform/mediatek/mdp3/mdp_reg_tdshp.h| 34 + .../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 + .../platform/mediatek/mdp3/mdp_sm_mt8195.h| 283 ++ .../platform/mediatek/mdp3/mtk-img-ipi.h | 4 + .../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 2 + .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c| 447 +++-- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.h| 1 + .../platform/mediatek/mdp3/mtk-mdp3-comp.c| 860 +- .../platform/mediatek/mdp3/mtk-mdp3-comp.h| 93 +- .../platform/mediatek/mdp3/mtk-mdp3-core.c| 103 ++- .../platform/mediatek/mdp3/mtk-mdp3-core.h| 33 +- .../platform/mediatek/mdp3/mtk-mdp3-m2m.c | 15 + .../platform/mediatek/mdp3/mtk-mdp3-regs.c| 18 + .../platform/mediatek/mdp3/mtk-mdp3-regs.h| 1 + .../platform/mediatek/mdp3/mtk-mdp3-vpu.c | 3 +- 27 files changed, 3051 insertions(+), 174 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_sm_mt8195.h -- 2.18.0
Re: [PATCH v2] drm/simpledrm: Add support for multiple "power-domains"
Hi
Am 12.09.23 um 22:22 schrieb Janne Grunau via B4 Relay:
From: Janne Grunau
Multiple power domains need to be handled explicitly in each driver. The
driver core can not handle it automatically since it is not aware of
power sequencing requirements the hardware might have. This is not a
problem for simpledrm since everything is expected to be powered on by
the bootloader. simpledrm has just ensure it remains powered on during
its lifetime.
This is required on Apple silicon M2 and M2 Pro/Max/Ultra desktop
systems. The HDMI output initialized by the bootloader requires keeping
the display controller and a DP phy power domain on.
Signed-off-by: Janne Grunau
As a simpledrm patch:
Reviewed-by: Thomas Zimmermann
Do you want to wait for another review from someone with
power-management expertise?
Do we need a similar patch for ofdrm?
Best regards
Thomas
---
Changes in v2:
- removed broken drm_err() log statement only ment for debugging
- removed commented cast
- use correct format spcifier for 'int' in log statement
- add 'continue;' after failure to get device for power_domain
- use drm_warn() in non fatal error cases
- removed duplicate PTR_ERR conversion
- Link to v1:
https://lore.kernel.org/r/20230910-simpledrm-multiple-power-domains-v1-1-f8718aefc...@jannau.net
---
drivers/gpu/drm/tiny/simpledrm.c | 105 +++
1 file changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/tiny/simpledrm.c b/drivers/gpu/drm/tiny/simpledrm.c
index ff86ba1ae1b8..9c597461d1e2 100644
--- a/drivers/gpu/drm/tiny/simpledrm.c
+++ b/drivers/gpu/drm/tiny/simpledrm.c
@@ -6,6 +6,7 @@
#include
#include
#include
+#include
#include
#include
@@ -227,6 +228,12 @@ struct simpledrm_device {
unsigned int regulator_count;
struct regulator **regulators;
#endif
+ /* power-domains */
+#if defined CONFIG_OF && defined CONFIG_PM_GENERIC_DOMAINS
+ int pwr_dom_count;
+ struct device **pwr_dom_devs;
+ struct device_link **pwr_dom_links;
+#endif
/* simplefb settings */
struct drm_display_mode mode;
@@ -468,6 +475,101 @@ static int simpledrm_device_init_regulators(struct
simpledrm_device *sdev)
}
#endif
+#if defined CONFIG_OF && defined CONFIG_PM_GENERIC_DOMAINS
+/*
+ * Generic power domain handling code.
+ *
+ * Here we handle the power-domains properties of our "simple-framebuffer"
+ * dt node. This is only necessary if there is more than one power-domain.
+ * A single power-domains is handled automatically by the driver core. Multiple
+ * power-domains have to be handled by drivers since the driver core can't know
+ * the correct power sequencing. Power sequencing is not an issue for simpledrm
+ * since the bootloader has put the power domains already in the correct state.
+ * simpledrm has only to ensure they remain active for its lifetime.
+ *
+ * When the driver unloads, we detach from the power-domains.
+ *
+ * We only complain about errors here, no action is taken as the most likely
+ * error can only happen due to a mismatch between the bootloader which set
+ * up the "simple-framebuffer" dt node, and the PM domain providers in the
+ * device tree. Chances are that there are no adverse effects, and if there
are,
+ * a clean teardown of the fb probe will not help us much either. So just
+ * complain and carry on, and hope that the user actually gets a working fb at
+ * the end of things.
+ */
+static void simpledrm_device_detach_genpd(void *res)
+{
+ int i;
+ struct simpledrm_device *sdev = res;
+
+ if (sdev->pwr_dom_count <= 1)
+ return;
+
+ for (i = sdev->pwr_dom_count - 1; i >= 0; i--) {
+ if (!sdev->pwr_dom_links[i])
+ device_link_del(sdev->pwr_dom_links[i]);
+ if (!IS_ERR_OR_NULL(sdev->pwr_dom_devs[i]))
+ dev_pm_domain_detach(sdev->pwr_dom_devs[i], true);
+ }
+}
+
+static int simpledrm_device_attach_genpd(struct simpledrm_device *sdev)
+{
+ struct device *dev = sdev->dev.dev;
+ int i;
+
+ sdev->pwr_dom_count = of_count_phandle_with_args(dev->of_node,
"power-domains",
+"#power-domain-cells");
+ /*
+* Single power-domain devices are handled by driver core nothing to do
+* here. The same for device nodes without "power-domains" property.
+*/
+ if (sdev->pwr_dom_count <= 1)
+ return 0;
+
+ sdev->pwr_dom_devs = devm_kcalloc(dev, sdev->pwr_dom_count,
+ sizeof(*sdev->pwr_dom_devs),
+ GFP_KERNEL);
+ if (!sdev->pwr_dom_devs)
+ return -ENOMEM;
+
+ sdev->pwr_dom_links = devm_kcalloc(dev, sdev->pwr_dom_count,
+ sizeof(*sdev->pwr_dom_links),
+ GFP_KERNEL);
+
Re: [PATCH v9 6/7] drm/mediatek: dsi: Support dynamic connector selection
Re: [PATCH v9 5/7] drm/mediatek: Add connector dynamic selection capability for mt8188
Re: [PATCH v2 1/5] string.h: add array-wrappers for (v)memdup_user()
On Sat, Sep 16, 2023 at 05:32:42PM +0300, Dan Carpenter wrote:
> On Fri, Sep 08, 2023 at 09:59:40PM +0200, Philipp Stanner wrote:
...
> > +static inline void *memdup_array_user(const void __user *src, size_t n,
> > size_t size)
> > +{
> > + size_t nbytes;
> > +
> > + if (unlikely(check_mul_overflow(n, size, )))
> > + return ERR_PTR(-EOVERFLOW);
>
> No need for an unlikely() because check_mul_overflow() already has one
> inside.
Makes sense.
> I feel like -ENOMEM is more traditional but I doubt anyone/userspace
> cares.
ENOMEM is good for the real allocation calls, here is not the one (the one is
below). Hence ENOMEM is not good candidate above. And whenever functions returns
an error pointer the caller must not assume that it will be only ENOMEM for
allocators.
> > + return memdup_user(src, nbytes);
> > +}
--
With Best Regards,
Andy Shevchenko
Re: [PATCH] drm/ssd130x: Drop _helper prefix from struct drm_*_helper_funcs callbacks
Hi
Am 14.09.23 um 21:51 schrieb Javier Martinez Canillas:
The driver uses a naming convention where functions for struct drm_*_funcs
callbacks are named ssd130x_$object_$operation, while the callbacks for
struct drm_*_helper_funcs are named ssd130x_$object_helper_$operation.
The idea is that this helper_ prefix in the function names denote that are
for struct drm_*_helper_funcs callbacks. This convention was copied from
other drivers, when ssd130x was written but Maxime pointed out that is the
exception rather than the norm.
I guess you found this in my code. I want to point out that I use the
_helper infix to signal that these are callback for
drm_primary_plane_helper_funcs and *not* drm_primary_plane_funcs. The
naming is intentional.
Best regards
Thomas
So let's get rid of the _helper prefixes from the function handlers names.
Suggested-by: Maxime Ripard
Signed-off-by: Javier Martinez Canillas
---
drivers/gpu/drm/solomon/ssd130x.c | 46 +++
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/solomon/ssd130x.c
b/drivers/gpu/drm/solomon/ssd130x.c
index 8ab02724f65f..245e4ba1c041 100644
--- a/drivers/gpu/drm/solomon/ssd130x.c
+++ b/drivers/gpu/drm/solomon/ssd130x.c
@@ -630,8 +630,8 @@ static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb,
return ret;
}
-static int ssd130x_primary_plane_helper_atomic_check(struct drm_plane *plane,
-struct drm_atomic_state
*state)
+static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane,
+ struct drm_atomic_state *state)
{
struct drm_device *drm = plane->dev;
struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
@@ -667,8 +667,8 @@ static int ssd130x_primary_plane_helper_atomic_check(struct
drm_plane *plane,
return 0;
}
-static void ssd130x_primary_plane_helper_atomic_update(struct drm_plane *plane,
- struct drm_atomic_state
*state)
+static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
{
struct drm_plane_state *plane_state =
drm_atomic_get_new_plane_state(state, plane);
struct drm_plane_state *old_plane_state =
drm_atomic_get_old_plane_state(state, plane);
@@ -701,8 +701,8 @@ static void
ssd130x_primary_plane_helper_atomic_update(struct drm_plane *plane,
drm_dev_exit(idx);
}
-static void ssd130x_primary_plane_helper_atomic_disable(struct drm_plane *plane,
- struct drm_atomic_state
*state)
+static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane,
+struct drm_atomic_state *state)
{
struct drm_device *drm = plane->dev;
struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
@@ -777,9 +777,9 @@ static void ssd130x_primary_plane_destroy_state(struct
drm_plane *plane,
static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs = {
DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
- .atomic_check = ssd130x_primary_plane_helper_atomic_check,
- .atomic_update = ssd130x_primary_plane_helper_atomic_update,
- .atomic_disable = ssd130x_primary_plane_helper_atomic_disable,
+ .atomic_check = ssd130x_primary_plane_atomic_check,
+ .atomic_update = ssd130x_primary_plane_atomic_update,
+ .atomic_disable = ssd130x_primary_plane_atomic_disable,
};
static const struct drm_plane_funcs ssd130x_primary_plane_funcs = {
@@ -791,8 +791,8 @@ static const struct drm_plane_funcs
ssd130x_primary_plane_funcs = {
.destroy = drm_plane_cleanup,
};
-static enum drm_mode_status ssd130x_crtc_helper_mode_valid(struct drm_crtc *crtc,
- const struct
drm_display_mode *mode)
+static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc,
+ const struct
drm_display_mode *mode)
{
struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev);
@@ -807,8 +807,8 @@ static enum drm_mode_status ssd130x_crtc_helper_mode_valid(struct drm_crtc *crtc
return MODE_OK;
}
-static int ssd130x_crtc_helper_atomic_check(struct drm_crtc *crtc,
- struct drm_atomic_state *state)
+static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc,
+struct drm_atomic_state *state)
{
struct drm_device *drm = crtc->dev;
struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
@@ -882,8 +882,8 @@ static void ssd130x_crtc_destroy_state(struct drm_crtc
*crtc,
* the screen in the primary plane's atomic_disable function.
*/
static const struct drm_crtc_helper_funcs
