from:"Adrian Ratiu"

Re: [PATCH v9 00/11] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-10-23 Thread Adrian Ratiu


Hi Neil,

On Tue, 15 Sep 2020, Neil Armstrong  
wrote:
Hi Adrian, 

Gentle ping. 

can you rebase on drm-misc-next so I can apply the IMX and STM 
patches ?


Sorry for the late reply, somehow missed this e-mail chain.

I have a rebase of the series but further investigation revealed 
we might regress Rockchip with a partial integration, so I'm 
getting a panel for RK to test to be sure and will re-submit.




On 24/08/2020 11:47, Neil Armstrong wrote:

Hi,


On 15/08/2020 15:05, Ezequiel Garcia wrote:

Hi Neil,

On Wed, 2020-07-01 at 09:35 +0300, Adrian Ratiu wrote:

Hi Neil,

On Mon, 29 Jun 2020, Neil Armstrong  
wrote:
Hi Adrian, 

On 09/06/2020 19:49, Adrian Ratiu wrote: 

[...]




It's been a month so I think it's a good idea to go forward
applying IMX and STM patches (probably with the usual
rebase dance).

As for Rockchip...

The binding API removal change which directly touches RK can also 
be applied separately, but unfortunately I do not have access to a 
RK board with a DSI display to test it (or the bridge regmap logic 
on RK btw...), I just "eye-balled" the RK code based on the public 
docs and it LGTM.




... I'll be getting some DSI hardware to help with the pending
Rockchip issues, so we can tackle Rockchip as well. I'm quite sure
we'll loop Heiko as well if needed :-)


Sure, Adrian, can you rebase on drm-misc-next so I can apply the IMX and STM 
patches ?



Cheers,
Ezequiel


Neil


Big thank you to everyone who has contributed to this up to now,
Adrian

Adrian Ratiu (11):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: dw_mipi_dsi: add dsi v1.01 support
  drm: bridge: dw_mipi_dsi: remove bind/unbind API
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  ARM: dts: imx6qdl: add missing mipi dsi properties
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets
  Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 112 +++
 Documentation/gpu/todo.rst|  25 +
 arch/arm/boot/dts/imx6qdl.dtsi|   8 +
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 --
 drivers/gpu/drm/imx/Kconfig   |   8 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 399 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |   7 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  16 +-
 10 files changed, 1059 insertions(+), 231 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c






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Re: [PATCH v9 00/11] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-07-01 Thread Adrian Ratiu


Hi Heiko,

On Wed, 01 Jul 2020, Heiko Stübner  wrote:
Hi Adrian, 

Am Dienstag, 9. Juni 2020, 19:49:48 CEST schrieb Adrian Ratiu: 
[Re-submitting to cc dri-devel, sorry about the noise]  Hello 
all,  v9 cleanly applies on top of latest next-20200609 tree. 


at least it doesn't apply on top of current drm-misc-next for me 
which I really don't understand. 

Like patch 2/11 does 

@@ -31,6 +31,7 @@ 
 #include  
. 
 #define HWVER_131<><--><-->0x31333100<>/* IP 
 version 1.31 */ 
+#define HWVER_130<><--><-->0x31333000<>/* IP 
version 1.30 */ . 
 #define DSI_VERSION<--><--><-->0x00 #define 
 VERSION<--><--><--><-->GENMASK(31, 8) 

where the file currently looks like 

#include  #include  
#include  #include  #include 
 #include  #include 
 

#define HWVER_131			0x31333100	/* IP 
version 1.31 */ 

#define DSI_VERSION			0x00 #define VERSION 
GENMASK(31, 8) 
 
even in Linux-next 
 
So I guess ideally rebase on top of drm-misc-next


I will send a rebase on top of drm-misc-next soon (with the last 
DTS nitpick fixed and the latest acks and reviewed-by tags added).


In the meantime I also found someone within Collabora who has a RK 
with a DSI panel and found a bug (likely clock is not enabled 
early enough to access the cfg registers to get the version for 
regmap).


I'm super happy this is getting tested on RK, thank you!




Thanks
Heiko

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Re: [PATCH v9 00/11] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-07-01 Thread Adrian Ratiu


Hi Neil,

On Mon, 29 Jun 2020, Neil Armstrong  
wrote:
Hi Adrian, 

On 09/06/2020 19:49, Adrian Ratiu wrote: 
[Re-submitting to cc dri-devel, sorry about the noise]  Hello 
all,  v9 cleanly applies on top of latest next-20200609 tree. 
v9 does not depend on other patches as the last binding doc has 
been merged.   All feedback up to this point has been 
addressed. Specific details in individual patch changelogs. 
The biggest changes are the deprecation of the Synopsys DW 
bridge bind() API in favor of of_drm_find_bridge() and .attach 
callbacks, the addition of a TODO entry which outlines future 
planned bridge driver refactorings and a reordering of some 
i.MX 6 patches to appease checkpatch.   The idea behind the 
TODO is to get this regmap and i.MX 6 driver merged and then do 
the rest of refactorings in-tree because it's easier and the 
refactorings themselves are out-of-scope of this series which 
is adding i.MX 6 support and is quite big already, so please, 
if there are more refactoring ideas, let's add them to the TODO 
doc. :) I intend to tackle those after this series is merged to 
avoid two complex inter-dependent simultaneous series. 


This has been around here for a long time and you seem to have 
addressed all the reviews. 

 As always more testing is welcome especially on Rockchip and 
STM SoCs. 


It has been tested on STM, but I'd like a feedback on RK 
platform before applying the bridge parts. 

Can the imx & stm patches be applied separately ? 



Yes the IMX and STM patches can be applied separately, they just 
both depend on the common regmap patches.


The binding API removal change which directly touches RK can also 
be applied separately, but unfortunately I do not have access to a 
RK board with a DSI display to test it (or the bridge regmap logic 
on RK btw...), I just "eye-balled" the RK code based on the public 
docs and it LGTM.



Neil



Big thank you to everyone who has contributed to this up to now,
Adrian

Adrian Ratiu (11):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: dw_mipi_dsi: add dsi v1.01 support
  drm: bridge: dw_mipi_dsi: remove bind/unbind API
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  ARM: dts: imx6qdl: add missing mipi dsi properties
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets
  Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 112 +++
 Documentation/gpu/todo.rst|  25 +
 arch/arm/boot/dts/imx6qdl.dtsi|   8 +
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 --
 drivers/gpu/drm/imx/Kconfig   |   8 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 399 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |   7 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  16 +-
 10 files changed, 1059 insertions(+), 231 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c


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[PATCH v9 10/11] drm: bridge: dw-mipi-dsi: fix bad register field offsets

2020-06-09 Thread Adrian Ratiu

According to the DSI Host Registers sections available in the IMX,
STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
are smaller or bigger than what's coded in the driver, leading to
r/w in reserved spaces which might cause undefined behaviours.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +--
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 1e47d40b5becb..d274216c5a7c2 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
 static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
.cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
-   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 2),
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 1),
.cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
.cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
.cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
@@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_cmd_mode_dcs_sw_sr_en =REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
.cfg_cmd_mode_dcs_lw_en =   REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
.cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
-   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
-   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
-   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
+   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
+   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
+   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
.cfg_vid_mode_type =REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
.cfg_vid_mode_low_power =   REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
.cfg_vid_mode_vpg_en =  REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
.cfg_vid_mode_vpg_horiz =   REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
-   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
-   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
-   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
-   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
-   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
-   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
-   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
-   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
+   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
+   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
+   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
+   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
+   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
+   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
+   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
.cfg_phy_txrequestclkhs =   REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
-   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
-   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
+   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
.cfg_phy_lp2hs_time =   REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
.cfg_phy_hs2lp_time =   REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
-   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
-   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
-   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
+   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
+   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
.cfg_phy_clklp2hs_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
.cfg_phy_clkhs2lp_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 
31),
.cfg_phy_testclr =  REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
@@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant

[PATCH v9 03/11] drm: bridge: dw_mipi_dsi: add dsi v1.01 support

2020-06-09 Thread Adrian Ratiu

The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v7:
  - Minor commit msg rewording for consistency

Changes since v5:
  - Fixed cfg_phy_status range from [0,0] to [0,2]

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f453df4eb5072..16fd87055e7b7 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
 #define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10

[PATCH v9 02/11] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2020-06-09 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.

The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fix CONFIG_DEBUG_FS build (Adrian)
  - Fix DRM_MODE_FLAG_* test negation (Adrian)
  - Fixed cfg_phy_status range from [0,0] to [0,2]
  - Replace do {} while(0) with GCC extension ({}) (Andrzej)
  - Fixed payload no-op writes on STM devices (Adrian & Arnaud)

Changes since v4:
  - Move regmap infrastructure logic to a separate commit (Ezequiel)
  - Consolidate field infrastructure in this commit (Ezequiel)
  - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)

Changes since v2:
  - Added const declarations to dw_mipi_dsi structs (Emil)
  - Fixed commit tags (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 499 --
 1 file changed, 347 insertions(+), 152 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 34b8668ae24ea..f453df4eb5072 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -47,7 +48,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +56,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +112,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP

[PATCH v9 04/11] drm: bridge: dw_mipi_dsi: remove bind/unbind API

2020-06-09 Thread Adrian Ratiu

The DW mipi-dsi bind/unbind API was only used to attach the bridge to
the encoder in the Rockchip driver, but with the addition of i.MX6 it
gets more complicated because the i.MX6 part of the bridge is another
bridge in itself which needs to daisy chain to the dw-mipi-dsi core.

So, instead of extending this API to allow daisy-chaining bridges and
risk having trouble with multiple connectors added by various bridges
just delete it and let the DW core bridge be accesed by SoC-specific
parts via the of_drm_find_bridge() API.

This just fixes the Rockchip driver for the bind() deprecation, it
doesn't convert it to a proper bridge daisy-chain with simple encoder
and bridge .attach call-backs, that refactoring work should be done
separately (and the i.MX6 driver can be used as reference).

Suggested-by: Laurent Pinchart 
Signed-off-by: Adrian Ratiu 
---
New in v9.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 22 ---
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  7 +++---
 2 files changed, 3 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 16fd87055e7b7..70df0578cbe7b 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -1453,28 +1453,6 @@ void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 }
 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
 
-/*
- * Bind/unbind API, used from platforms based on the component framework.
- */
-int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
-{
-   int ret;
-
-   ret = drm_bridge_attach(encoder, >bridge, NULL, 0);
-   if (ret) {
-   DRM_ERROR("Failed to initialize bridge with drm\n");
-   return ret;
-   }
-
-   return ret;
-}
-EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
-
-void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
-{
-}
-EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
-
 MODULE_AUTHOR("Chris Zhong ");
 MODULE_AUTHOR("Philippe Cornu ");
 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 3feff0c45b3f7..86f87c7ea03cf 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -876,6 +876,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 {
struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
struct drm_device *drm_dev = data;
+   struct drm_bridge *dw_bridge = of_drm_find_bridge(dev->of_node);
struct device *second;
bool master1, master2;
int ret;
@@ -929,9 +930,9 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
return ret;
}
 
-   ret = dw_mipi_dsi_bind(dsi->dmd, >encoder);
+   ret = drm_bridge_attach(>encoder, dw_bridge, NULL, 0);
if (ret) {
-   DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
+   DRM_DEV_ERROR(dev, "Failed to attach DW DSI bridge: %d\n", ret);
return ret;
}
 
@@ -947,8 +948,6 @@ static void dw_mipi_dsi_rockchip_unbind(struct device *dev,
if (dsi->is_slave)
return;
 
-   dw_mipi_dsi_unbind(dsi->dmd);
-
clk_disable_unprepare(dsi->pllref_clk);
 }
 
-- 
2.27.0

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[PATCH v9 06/11] ARM: dts: imx6qdl: add missing mipi dsi properties

2020-06-09 Thread Adrian Ratiu

Now that we have a proper driver for the imx6 mipi dsi host controller
we can fill in the missing properties to get it working.

Cc: Laurent Pinchart 
Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Signed-off-by: Adrian Ratiu 
---
New in v8.
---
 arch/arm/boot/dts/imx6qdl.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 7eec1122e5d74..d2f4fdfe4a252 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1222,7 +1222,15 @@ mipi_csi: mipi@21dc000 {
};
 
mipi_dsi: mipi@21e {
+   compatible = "fsl,imx6-mipi-dsi", 
"snps,dw-mipi-dsi";
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x021e 0x4000>;
+   interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+   fsl,gpr = <>;
+   clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_IPG>;
+   clock-names = "ref", "pclk";
status = "disabled";
 
ports {
-- 
2.27.0

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[PATCH v9 08/11] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

2020-06-09 Thread Adrian Ratiu

The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.

Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.

The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.

Tested on STM32F769 and STM32MP1.

Cc: linux-st...@st-md-mailman.stormreply.com
Cc: Emil Velikov 
Reported-by: Adrian Pop 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +++-
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d0..45f67f8a5f6c8 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -396,26 +396,19 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
+   /* enable pclk so MMIO register values can be read, else reads == 0x0 */
ret = clk_prepare_enable(pclk);
if (ret) {
DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
goto err_dsi_probe;
}
 
-   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
-   clk_disable_unprepare(pclk);
-
-   if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
-   ret = -ENODEV;
-   DRM_ERROR("bad dsi hardware version\n");
-   goto err_dsi_probe;
-   }
-
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
platform_set_drvdata(pdev, dsi);
 
+   /* setup the bridge, this will also access MMIO registers via regmap */
dsi->dsi = dw_mipi_dsi_probe(pdev, _mipi_dsi_stm_plat_data);
if (IS_ERR(dsi->dsi)) {
ret = PTR_ERR(dsi->dsi);
@@ -423,6 +416,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
+   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+
+   /* initial MMIO config done, disable clk to save power */
+   clk_disable_unprepare(pclk);
+
return 0;
 
 err_dsi_probe:
-- 
2.27.0

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[PATCH v9 07/11] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-06-09 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

Cc: Fabio Estevam 
Cc: Enric Balletbo i Serra 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v8:
  - Changed Enric's email in the CC tag to his work address
  - pllref_clk != 27Mhz promoted from WARN to DRM_DEV_ERROR and
  is tested ASAP after clk enable in probe() (Enric)
  - Multiple small bridge init cleanups (Enric)
  - Multiple debug/error msg fixes to make them more clear or
  avoid redundancy (Enric)
  - Simplified imx_mipi_dsi_bind() as a result of the DW bridge
  bind() removal (Laurent)
  - Added a bridge .attach callback
  - Dropped unnecessary bridge_to_imxdsi() conversion
  - Fixed minor whitespace checkpatch warnings and moved the
  bindings doc before this patch to appease checkpatch

Changes since v7:
  - Removed encoder helper ops and added drm_bridge (Laurent)
  - Brought back drm_simple_encoder_init and dropped dependency on
  external unify encoder creation patch (Laurent)
  - Minor typo fixes

Changes since v6:
  - Replaced custom noop encoder with the simple drm encoder (Enric)
  - Added CONFIG_DRM_IMX6_MIPI_DSI depends on CONFIG_OF (Enric)
  - Dropped imx_mipi_dsi_register() because now it only creates the
  dummy encoder which can easily be done directly in imx_dsi_bind()

Changes since v5:
  - Reword to remove unrelated device tree patch mention (Fabio)
  - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
  - Fix freescale.com -> nxp.com email addresses (Fabio)
  - Also added myself as module author (Fabio)
  - Use DRM_DEV_* macros for consistency, print more error msg

Changes since v4:
  - Split off driver-specific configuration of phy timings due
  to new upstream API.
  - Move regmap infrastructure logic to separate commit (Ezequiel)
  - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
  - Minor warnings and driver name fixes

Changes since v3:
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio)

Changes since v2:
  - Fixed commit tags. (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after
  calling the bridge probe. (Emil)
---
 drivers/gpu/drm/imx/Kconfig|   8 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +
 3 files changed, 408 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 874cc532eabad..5f5b925ed09ca 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -46,3 +46,11 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+   tristate "Freescale i.MX6 DRM MIPI DSI"
+   select DRM_DW_MIPI_DSI
+   depends on DRM_IMX
+   depends on OF
+   help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 94fc8e2d92344..205d7e65aa170 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 obj-$(CONFIG_DRM_IMX_DCIC) += imx-dcic.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index 0..f19b355c6c06d
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019-2020 Collabora, Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_PHY_IF_CTRL0x5c
+#define PHY_IF_CTRL_RESET  0x0
+
+#define DSI_PHY_TST_CTRL0  0x64
+#define PHY_TESTCLKBIT(1)
+#define PHY_UNTESTCLK  0
+#define PHY_TESTCLRBIT(0)
+#define PHY_UNTESTCLR  0
+
+#define DSI_PHY_TST_CTRL1  0x68
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN

[PATCH v9 00/11] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-06-09 Thread Adrian Ratiu

[Re-submitting to cc dri-devel, sorry about the noise]

Hello all,

v9 cleanly applies on top of latest next-20200609 tree.

v9 does not depend on other patches as the last binding doc has been merged.

All feedback up to this point has been addressed. Specific details in
individual patch changelogs.

The biggest changes are the deprecation of the Synopsys DW bridge bind()
API in favor of of_drm_find_bridge() and .attach callbacks, the addition
of a TODO entry which outlines future planned bridge driver refactorings
and a reordering of some i.MX 6 patches to appease checkpatch.

The idea behind the TODO is to get this regmap and i.MX 6 driver merged
and then do the rest of refactorings in-tree because it's easier and the
refactorings themselves are out-of-scope of this series which is adding
i.MX 6 support and is quite big already, so please, if there are more
refactoring ideas, let's add them to the TODO doc. :) I intend to tackle
those after this series is merged to avoid two complex inter-dependent
simultaneous series.

As always more testing is welcome especially on Rockchip and STM SoCs.

Big thank you to everyone who has contributed to this up to now,
Adrian

Adrian Ratiu (11):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: dw_mipi_dsi: add dsi v1.01 support
  drm: bridge: dw_mipi_dsi: remove bind/unbind API
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  ARM: dts: imx6qdl: add missing mipi dsi properties
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets
  Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 112 +++
 Documentation/gpu/todo.rst|  25 +
 arch/arm/boot/dts/imx6qdl.dtsi|   8 +
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 --
 drivers/gpu/drm/imx/Kconfig   |   8 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 399 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |   7 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  16 +-
 10 files changed, 1059 insertions(+), 231 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
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[PATCH v9 01/11] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-06-09 Thread Adrian Ratiu

In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.

The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.

Suggested-by: Ezequiel Garcia 
Reviewed-by: Enric Balletbo i Serra 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v8:
  - Minor typo fix
  - Added Reviewed-by Enric tag

Changes since v7:
  - Minor checkpatch line fix

Changes since v6:
  - Select REGMAP_MMIO in Kconfig (Enric)
  - Drop unnecessary stack variable inits (Enric)
  - Make bridge error ASAP after a bad revision read (Enric)
  - Drop redundant read of hw_version in dphy_timing_config (Enric)

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 210 ++
 2 files changed, 121 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 21a1be3ced0f3..080146093b68e 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -39,3 +39,4 @@ config DRM_DW_MIPI_DSI
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
+   select REGMAP_MMIO
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7bd..34b8668ae24ea 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+   u32 hw_version;
 
 #ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,8 +366,8 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,20 +375,20 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct 
dw_mipi_dsi *dsi, u32 hdr_val)
int ret;
u32 val, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi-&

[PATCH v9 05/11] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-06-09 Thread Adrian Ratiu

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring 
Cc: Neil Armstrong 
Cc: Fabio Estevam 
Cc: Laurent Pinchart 
Cc: devicet...@vger.kernel.org
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v8:
  - Fixed small compatible string typo caught by checkpatch
  - Added custom select for 'fsl,imx6-mipi-dsi' (Rob)
  - Replaced additionalProperties -> unevaluatedProperties (Rob)
  - Dropped all nodes not adding any new constraints apart from
  the recently upstreamed snps,dw-mipi-dsi.yaml (Rob)

Changes since v7:
  - Clarified port@0,1 descriptions, marked them as required and
  added missing port@0 in example (Laurent)

Changes since v6:
  - Added ref to the newly created snps,dw-mipi-dsi.yaml (Laurent)
  - Moved *-cells properties outside patternProperties (Laurent)
  - Removed the panel port documentation (Laurent)
  - Wrapped lines at 80 chars, typo fixes, sort includes (Laurent)

Changes since v5:
  - Fixed missing reg warning (Fabio)
  - Updated dt-schema and fixed warnings (Rob)

Changes since v4:
  - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
  and addressed received binding feedback (Rob)

Changes since v3:
  - Added commit message (Neil)
  - Converted to yaml format (Neil)
  - Minor dt node + driver fixes (Rob)
  - Added small panel example to the host controller binding

Changes since v2:
  - Fixed commit tags (Emil)
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 112 ++
 1 file changed, 112 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index 0..86093729fd5f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+  - Adrian Ratiu 
+
+description: |
+  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+  IP block with a companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+allOf:
+  - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
+
+# Need a custom select here or 'snps,dw-mipi-dsi' will match lots of nodes
+select:
+  properties:
+compatible:
+  contains:
+enum:
+  - fsl,imx6-mipi-dsi
+  required:
+- compatible
+
+properties:
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+  compatible:
+items:
+  - const: fsl,imx6-mipi-dsi
+  - const: snps,dw-mipi-dsi
+
+  interrupts:
+maxItems: 1
+
+  fsl,gpr:
+description:
+  Phandle to the iomuxc-gpr region containing the multiplexer ctrl 
register.
+$ref: /schemas/types.yaml#/definitions/phandle
+
+unevaluatedProperties: false
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - interrupts
+
+examples:
+  - |+
+#include 
+#include 
+#include 
+
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+mipi_mux_0: endpoint {
+remote-endpoint = <_di0_mipi>;
+};
+};
+port@1 {
+reg = <1>;
+dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+panel@0 {
+compatible = "sharp,ls032b3sx01";
+reg = <0>;
+reset-gpios = < 8 GPIO_ACTIVE_LOW>;
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+panel_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+

[PATCH v9 11/11] Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan

2020-06-09 Thread Adrian Ratiu

This documents the longer-term plan to cleanup the dw-mipi-dsi bridge
based drivers after the regmap refactor and i.MX6 driver have landed.

The goal is to get the entire bridge logic in one place and continue
the refactorings under the drm/bridge tree.

Cc: Laurent Pinchart 
Cc: Boris Brezillon 
Cc: Sam Ravnborg 
Cc: Daniel Vetter 
Signed-off-by: Adrian Ratiu 
---
 Documentation/gpu/todo.rst | 25 +
 1 file changed, 25 insertions(+)

diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 658b52f7ffc6c..2b142980a4b16 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -548,6 +548,31 @@ See drivers/gpu/drm/amd/display/TODO for tasks.
 
 Contact: Harry Wentland, Alex Deucher
 
+Reorganize dw-mipi-dsi bridge-based host-controller drivers
+---
+
+The Synopsys DW MIPI DSI bridge is used by a number of SoC platform drivers
+(STM, Rockchip, i.MX) which don't cleanly encapsulate their bridge logic which
+gets split between the Synopsys bridge (drm/bridge/synopsys/dw-mipi-dsi.c) and
+platform drivers like drm/imx/dw_mipi_dsi-imx6.c by passing around the bridge
+configuration regmap, creating new bridges / daisy chaining in platform 
drivers,
+duplicating encoder creation, having too much encoder logic instead of using 
the
+simple encoder interface and so on.
+
+The goal of this rework is to make the dw-mipi-dsi driver a better encapsulated
+bridge by moving all bridge-related logic under drm/bridge, including the SoC
+bindings which chain to the core Synopsys code under drm/bridge/dw-mipi-dsi/
+from which they can be further consolidated and cleaned up.
+
+If this goal proves to be impossible then drm_bridge might not be the correct
+abstraction for these host controllers and unifying their logic into a helper
+library encapsulating a drm_encoder might be more desirable, in other words to
+move away from drm_bridge entirely.
+
+Contact: Adrian Ratiu, Daniel Vetter, Laurent Pinchart
+
+Level: Intermediate
+
 Bootsplash
 ==
 
-- 
2.27.0

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[PATCH v9 09/11] drm: bridge: dw-mipi-dsi: split low power cfg register into fields

2020-06-09 Thread Adrian Ratiu

According to the Host Registers documentation for IMX, STM and RK
the LP cfg register should not be written entirely in one go because
some bits are reserved and should be kept to reset values, for eg.
BIT(15) which is reserved in all versions.

This also cleans up the code by removing the the ugly defines
and making field ranges & values written more explicit.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++
 1 file changed, 33 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 70df0578cbe7b..1e47d40b5becb 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -120,60 +120,6 @@
 #define DSI_TO_CNT_CFG_V1010x40
 #define DSI_PCKHDL_CFG_V1010x18
 
-#define MAX_RD_PKT_SIZE_LP BIT(24)
-#define DCS_LW_TX_LP   BIT(19)
-#define DCS_SR_0P_TX_LPBIT(18)
-#define DCS_SW_1P_TX_LPBIT(17)
-#define DCS_SW_0P_TX_LPBIT(16)
-#define GEN_LW_TX_LP   BIT(14)
-#define GEN_SR_2P_TX_LPBIT(13)
-#define GEN_SR_1P_TX_LPBIT(12)
-#define GEN_SR_0P_TX_LPBIT(11)
-#define GEN_SW_2P_TX_LPBIT(10)
-#define GEN_SW_1P_TX_LPBIT(9)
-#define GEN_SW_0P_TX_LPBIT(8)
-#define TEAR_FX_EN BIT(0)
-
-#define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
-DCS_LW_TX_LP | \
-DCS_SR_0P_TX_LP | \
-DCS_SW_1P_TX_LP | \
-DCS_SW_0P_TX_LP | \
-GEN_LW_TX_LP | \
-GEN_SR_2P_TX_LP | \
-GEN_SR_1P_TX_LP | \
-GEN_SR_0P_TX_LP | \
-GEN_SW_2P_TX_LP | \
-GEN_SW_1P_TX_LP | \
-GEN_SW_0P_TX_LP)
-
-#define EN_TEAR_FX_V101BIT(14)
-#define DCS_LW_TX_LP_V101  BIT(12)
-#define GEN_LW_TX_LP_V101  BIT(11)
-#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
-#define DCS_SW_2P_TX_LP_V101   BIT(9)
-#define DCS_SW_1P_TX_LP_V101   BIT(8)
-#define DCS_SW_0P_TX_LP_V101   BIT(7)
-#define GEN_SR_2P_TX_LP_V101   BIT(6)
-#define GEN_SR_1P_TX_LP_V101   BIT(5)
-#define GEN_SR_0P_TX_LP_V101   BIT(4)
-#define GEN_SW_2P_TX_LP_V101   BIT(3)
-#define GEN_SW_1P_TX_LP_V101   BIT(2)
-#define GEN_SW_0P_TX_LP_V101   BIT(1)
-
-#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
-GEN_LW_TX_LP_V101 | \
-MAX_RD_PKT_SIZE_LP_V101 | \
-DCS_SW_2P_TX_LP_V101 | \
-DCS_SW_1P_TX_LP_V101 | \
-DCS_SW_0P_TX_LP_V101 | \
-GEN_SR_2P_TX_LP_V101 | \
-GEN_SR_1P_TX_LP_V101 | \
-GEN_SR_0P_TX_LP_V101 | \
-GEN_SW_2P_TX_LP_V101 | \
-GEN_SW_1P_TX_LP_V101 | \
-GEN_SW_0P_TX_LP_V101)
-
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -257,7 +203,11 @@ struct dw_mipi_dsi {
struct regmap_field *field_dpi_vsync_active_low;
struct regmap_field *field_dpi_hsync_active_low;
struct regmap_field *field_cmd_mode_ack_rqst_en;
-   struct regmap_field *field_cmd_mode_all_lp_en;
+   struct regmap_field *field_cmd_mode_gen_sw_sr_en;
+   struct regmap_field *field_cmd_mode_dcs_sw_sr_en;
+   struct regmap_field *field_cmd_mode_gen_lw_en;
+   struct regmap_field *field_cmd_mode_dcs_lw_en;
+   struct regmap_field *field_cmd_mode_max_rd_pkt_size;
struct regmap_field *field_cmd_mode_en;
struct regmap_field *field_cmd_pkt_status;
struct regmap_field *field_vid_mode_en;
@@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant {
struct reg_fieldcfg_dpi_hsync_active_low;
struct reg_fieldcfg_cmd_mode_en;
struct reg_fieldcfg_cmd_mode_ack_rqst_en;
-   struct reg_fieldcfg_cmd_mode_all_lp_en;
+   struct reg_fieldcfg_cmd_mode_gen_sw_sr_en;
+   st

Re: [PATCH v8 04/10] drm: bridge: dw_mipi_dsi: allow bridge daisy chaining

2020-06-03 Thread Adrian Ratiu

On Wed, 03 Jun 2020, Laurent Pinchart 
 wrote:
Hi Adrian, 


Hi Laurent,



Thank you for the patch. 

On Mon, Apr 27, 2020 at 11:19:46AM +0300, Adrian Ratiu wrote: 
Up until now the assumption was that the synopsis dsi bridge 
will directly connect to an encoder provided by the platform 
driver, but the current practice for drivers is to leave the 
encoder empty via the simple encoder API and add their logic to 
their own drm_bridge.   Thus we need an ablility to connect the 
DSI bridge to another bridge provided by the platform driver, 
so we extend the dw_mipi_dsi bind() API with a new "previous 
bridge" arg instead of just hardcoding NULL.   Cc: Laurent 
Pinchart  Signed-off-by: 
Adrian Ratiu  --- New in v8.  --- 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c   | 6 -- 
 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 2 +- 
 include/drm/bridge/dw_mipi_dsi.h| 5 - 3 
 files changed, 9 insertions(+), 4 deletions(-) 
 diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
16fd87055e7b7..140ff40fa1b62 100644 --- 
a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -1456,11 
+1456,13 @@ EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 
 /* 
  * Bind/unbind API, used from platforms based on the component 
  framework.  */ 
-int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct 
drm_encoder *encoder) +int dw_mipi_dsi_bind(struct dw_mipi_dsi 
*dsi, +		 struct drm_encoder *encoder, + 
struct drm_bridge *prev_bridge) 
 { int ret;  
-	ret = drm_bridge_attach(encoder, >bridge, NULL, 0); + 
ret = drm_bridge_attach(encoder, >bridge, prev_bridge, 0); 


Please note that chaining of bridges doesn't work well if 
multiple bridges in the chain try to create a connector. This is 
why a DRM_BRIDGE_ATTACH_NO_CONNECTOR flag has been added, with a 
helper to create a connector for a chain of bridges 
(drm_bridge_connector_init()).  This won't play well with the 
component framework. I would recommend using the 
of_drm_find_bridge() instead in the rockchip driver, and 
deprecating dw_mipi_dsi_bind(). 



Thank you for this insight, indeed the bridge dw_mipi_dsi_bind() 
is clunky and we're making it even more so by possibly 
re-inventing drm_bridge_connector_init() with it in a way which 
can't work (well it does work but can lead to those nasty 
multiple-encoder corner-cases you mention).


I'll address this before posting v9, to try to move to 
of_drm_find_bridge() and remove dw_mipi_dsi_bind().



if (ret) {
DRM_ERROR("Failed to initialize bridge with drm\n");
return ret;
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 3feff0c45b3f7..83ef43be78135 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -929,7 +929,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
return ret;
}
 
-	ret = dw_mipi_dsi_bind(dsi->dmd, >encoder);

+   ret = dw_mipi_dsi_bind(dsi->dmd, >encoder, NULL);
if (ret) {
DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
return ret;
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
index b0e390b3288e8..699b3531f5b36 100644
--- a/include/drm/bridge/dw_mipi_dsi.h
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -14,6 +14,7 @@
 #include 
 
 struct drm_display_mode;

+struct drm_bridge;
 struct drm_encoder;
 struct dw_mipi_dsi;
 struct mipi_dsi_device;
@@ -62,7 +63,9 @@ struct dw_mipi_dsi *dw_mipi_dsi_probe(struct platform_device 
*pdev,
  const struct dw_mipi_dsi_plat_data
  *plat_data);
 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi);
-int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder);
+int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi,
+struct drm_encoder *encoder,
+struct drm_bridge *prev_bridge);
 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi);
 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave);
 


--
Regards,

Laurent Pinchart

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Re: [Linux-stm32] [PATCH v8 08/10] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

2020-06-03 Thread Adrian Ratiu

On Tue, 02 Jun 2020, Emil Velikov  
wrote:
Hi Adrian, 

Hi Email,

On Mon, 1 Jun 2020 at 10:14, Adrian Ratiu 
 wrote: 

On Fri, 29 May 2020, Philippe CORNU  
wrote: 
> Hi Adrian, and thank you very much for the patchset.  Thank 
> you also for having tested it on STM32F769 and STM32MP1. 
> Sorry for the late response, Yannick and I will review it as 
> soon as possible and we will keep you posted.  Note: Do not 
> hesitate to put us in copy for the next version 
> (philippe.co...@st.com, yannick.fer...@st.com) Regards, 
> Philippe :-) 

Hi Philippe, 

Thank you very much for your previous and future STM testing, 
really appreciate it! I've CC'd Yannick until now but I'll also 
CC you sure :) 

It's been over a month since I posted v8 and I was just gearing 
up to address all feedback, rebase & retest to prepare v9 but 
I'll wait a little longer, no problem, it's no rush. 

Small idea, pardon for joining so late: 

Might be a good idea to add inline comment, why the clocks are 
disabled so late.  Effectively a 2 line version of the commit 
summary. 

Feel free to make that a separate/follow-up patch.

Thanks, I'll add the comment to this patch in v9.

-Emil

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Re: [Linux-stm32] [PATCH v8 08/10] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

2020-06-01 Thread Adrian Ratiu


On Fri, 29 May 2020, Philippe CORNU  wrote:
Hi Adrian, and thank you very much for the patchset.  Thank you 
also for having tested it on STM32F769 and STM32MP1.  Sorry for 
the late response, Yannick and I will review it as soon as 
possible and we will keep you posted.  Note: Do not hesitate to 
put us in copy for the next version  (philippe.co...@st.com, 
yannick.fer...@st.com) Regards, Philippe :-) 


Hi Philippe,

Thank you very much for your previous and future STM testing, 
really appreciate it! I've CC'd Yannick until now but I'll also CC 
you sure :)


It's been over a month since I posted v8 and I was just gearing up 
to address all feedback, rebase & retest to prepare v9 but I'll 
wait a little longer, no problem, it's no rush.


Have an awesome day,
Adrian




On 4/27/20 10:19 AM, Adrian Ratiu wrote:

The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.

Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.

The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.

Tested on STM32F769 and STM32MP1.

Cc: linux-st...@st-md-mailman.stormreply.com
Reported-by: Adrian Pop 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 +++-
  1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d0..7218e405d7e2b 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -402,15 +402,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
  
-	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;

-   clk_disable_unprepare(pclk);
-
-   if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
-   ret = -ENODEV;
-   DRM_ERROR("bad dsi hardware version\n");
-   goto err_dsi_probe;
-   }
-
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
  
@@ -423,6 +414,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)

goto err_dsi_probe;
}
  
+	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;

+   clk_disable_unprepare(pclk);
+
return 0;
  
  err_dsi_probe:



___
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Re: [PATCH v7 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-28 Thread Adrian Ratiu


Hi Daniel,

On Tue, 28 Apr 2020, Daniel Vetter  wrote:
On Wed, Apr 22, 2020 at 04:07:27AM +0300, Laurent Pinchart 
wrote: 
Hi Adrian,  On Tue, Apr 21, 2020 at 07:16:06PM +0300, Adrian 
Ratiu wrote: 
> This adds support for the Synopsis DesignWare MIPI DSI v1.01 
> host controller which is embedded in i.MX 6 SoCs.   Based on 
> following patches, but updated/extended to work with existing 
> support found in the kernel:  - drm: imx: Support Synopsys 
> DesignWare MIPI DSI host controller 
>   Signed-off-by: Liu Ying  
>  Cc: Fabio Estevam  Cc: Enric Balletbo 
> Serra  Reviewed-by: Emil Velikov 
>  Tested-by: Adrian Pop 
>  Tested-by: Arnaud Ferraris 
>  Signed-off-by: Sjoerd Simons 
>  Signed-off-by: Martyn Welch 
>  Signed-off-by: Adrian Ratiu 
>  --- Changes since v6: 
>   - Replaced custom noop encoder with the simple drm encoder 
>   (Enric) - Added CONFIG_DRM_IMX6_MIPI_DSI depends on 
>   CONFIG_OF (Enric) - Dropped imx_mipi_dsi_register() because 
>   now it only creates the dummy encoder which can easily be 
>   done directly in imx_dsi_bind() 
>  Changes since v5: 
>   - Reword to remove unrelated device tree patch mention 
>   (Fabio) - Move pllref_clk enable/disable to bind/unbind 
>   (Ezequiel) - Fix freescale.com -> nxp.com email addresses 
>   (Fabio) - Also added myself as module author (Fabio) - Use 
>   DRM_DEV_* macros for consistency, print more error msg 
>  Changes since v4: 
>   - Split off driver-specific configuration of phy timings 
>   due to new upstream API.  - Move regmap infrastructure 
>   logic to separate commit (Ezequiel) - Move dsi v1.01 layout 
>   addition to a separate commit (Ezequiel) - Minor warnings 
>   and driver name fixes 
>  Changes since v3: 
>   - Renamed platform driver to reflect it's i.MX6 
>   only. (Fabio) 
>  Changes since v2: 
>   - Fixed commit tags. (Emil) 
>  Changes since v1: 
>   - Moved register definitions & regmap initialization into 
>   bridge module. Platform drivers get the regmap via 
>   plat_data after calling the bridge probe. (Emil) 
> --- 
>  drivers/gpu/drm/imx/Kconfig|   8 + 
>  drivers/gpu/drm/imx/Makefile   |   1 + 
>  drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 391 
>  + 3 files changed, 400 insertions(+) 
>  create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
>  diff --git a/drivers/gpu/drm/imx/Kconfig 
> b/drivers/gpu/drm/imx/Kconfig index 
> 207bf7409dfba..0dffc72df7922 100644 --- 
> a/drivers/gpu/drm/imx/Kconfig +++ 
> b/drivers/gpu/drm/imx/Kconfig @@ -39,3 +39,11 @@ config 
> DRM_IMX_HDMI 
>  	depends on DRM_IMX help Choose this if you want to use 
>  HDMI on i.MX6. 
> + +config DRM_IMX6_MIPI_DSI +	tristate "Freescale i.MX6 
> DRM MIPI DSI" +	select DRM_DW_MIPI_DSI +	depends on 
> DRM_IMX +	depends on OF +	help +	  Choose this if you want 
> to use MIPI DSI on i.MX6.  diff --git 
> a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile 
> index 21cdcc2faabc8..9a7843c593478 100644 --- 
> a/drivers/gpu/drm/imx/Makefile +++ 
> b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ 
> obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o 
>  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o 
>  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o 
> +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff 
> --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
> b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 
> index 0..f8a0a4fe16e21 --- /dev/null +++ 
> b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,391 @@ 
> +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm 
> driver - MIPI DSI Host Controller + * + * Copyright (C) 
> 2011-2015 Freescale Semiconductor, Inc.  + * Copyright (C) 
> 2019-2020 Collabora, Ltd.  + */ + +#include  
> +#include  +#include  
> +#include  +#include 
>  +#include  +#include 
>  +#include  +#include 
>  +#include  
> +#include  +#include  
> +#include  + +#include "imx-drm.h" + 
> +#define DSI_PWR_UP			0x04 +#define 
> RESET0 +#define POWERUP 
> BIT(0) + +#define DSI_PHY_IF_CTRL			0x5c 
> +#define PHY_IF_CTRL_RESET		0x0 + +#define 
> DSI_PHY_TST_CTRL0		0x64 +#define PHY_TESTCLK 
> BIT(1) +#define PHY_UNTESTCLK			0 +#define 
> PHY_TESTCLR			BIT(0) +#define 
> PHY_UNTESTCLR			0 + +#define 
> DSI_PHY_TST_CTRL1		0x68 +#define PHY_TESTEN 
> BIT(16) +#define PHY_UNTESTEN			0 +#define 
> PHY_TESTDOUT(n)			(((n) & 0xff) << 8) 
> +#define PHY_TESTDIN(n)			(((n) & 0xff) << 
> 0) + +struct imx_mipi_dsi { +	struct drm_encoder 
> encoder; +	struct device *dev; +	struct regmap *mux_sel; + 
> struct dw_mipi_dsi *mipi_dsi; +	struct clk *pllref_clk; + 
> +	void __iomem *base; +	unsigned int lane_mbps; +}; + 
> +struct dphy_pll

Re: [PATCH v8 05/10] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-27 Thread Adrian Ratiu


Hi Enric,

Thank you very much for your review, comments below.

I'll leave this a bit more on review before resending with your 
suggested fixes.


On Mon, 27 Apr 2020, Enric Balletbo i Serra 
 wrote:
Hi Adrian 


Thank you for your patch.




On 27/4/20 10:19, Adrian Ratiu wrote: 
This adds support for the Synopsis DesignWare MIPI DSI v1.01 
host controller which is embedded in i.MX 6 SoCs.   Based on 
following patches, but updated/extended to work with existing 
support found in the kernel:  - drm: imx: Support Synopsys 
DesignWare MIPI DSI host controller 
  Signed-off-by: Liu Ying  
 Cc: Fabio Estevam  Cc: Enric Balletbo 
Serra  Reviewed-by: Emil Velikov 
 Tested-by: Adrian Pop 
 Tested-by: Arnaud Ferraris 
 Signed-off-by: Sjoerd Simons 
 Signed-off-by: Martyn Welch 
 Signed-off-by: Adrian Ratiu 
 --- Changes since v7: 
  - Removed encoder helper ops and added drm_bridge (Laurent) - 
  Brought back drm_simple_encoder_init and dropped dependency 
  on external unify encoder creation patch (Laurent) - Minor 
  typo fixes 
 Changes since v6: 
  - Replaced custom noop encoder with the simple drm encoder 
  (Enric) - Added CONFIG_DRM_IMX6_MIPI_DSI depends on CONFIG_OF 
  (Enric) - Dropped imx_mipi_dsi_register() because now it only 
  creates the dummy encoder which can easily be done directly 
  in imx_dsi_bind() 
 Changes since v5: 
  - Reword to remove unrelated device tree patch mention 
  (Fabio) - Move pllref_clk enable/disable to bind/unbind 
  (Ezequiel) - Fix freescale.com -> nxp.com email addresses 
  (Fabio) - Also added myself as module author (Fabio) - Use 
  DRM_DEV_* macros for consistency, print more error msg 
 Changes since v4: 
  - Split off driver-specific configuration of phy timings due 
  to new upstream API.  - Move regmap infrastructure logic to 
  separate commit (Ezequiel) - Move dsi v1.01 layout addition 
  to a separate commit (Ezequiel) - Minor warnings and driver 
  name fixes 
 Changes since v3: 
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio) 
 Changes since v2: 
  - Fixed commit tags. (Emil) 
 Changes since v1: 
  - Moved register definitions & regmap initialization into 
  bridge module. Platform drivers get the regmap via plat_data 
  after calling the bridge probe. (Emil) 
--- 
 drivers/gpu/drm/imx/Kconfig|   8 + 
 drivers/gpu/drm/imx/Makefile   |   1 + 
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 
 + 3 files changed, 408 insertions(+) 
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
 diff --git a/drivers/gpu/drm/imx/Kconfig 
b/drivers/gpu/drm/imx/Kconfig index 
207bf7409dfba..0dffc72df7922 100644 --- 
a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig 
@@ -39,3 +39,11 @@ config DRM_IMX_HDMI 
 	depends on DRM_IMX help Choose this if you want to use 
 HDMI on i.MX6. 
+ +config DRM_IMX6_MIPI_DSI +	tristate "Freescale i.MX6 
DRM MIPI DSI" +	select DRM_DW_MIPI_DSI +	depends on 
DRM_IMX +	depends on OF +	help +	  Choose this if you want 
to use MIPI DSI on i.MX6.  diff --git 
a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile 
index 21cdcc2faabc8..9a7843c593478 100644 --- 
a/drivers/gpu/drm/imx/Makefile +++ 
b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ 
obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o 
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o 
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff 
--git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 
index 0..492decc418bc3 --- /dev/null +++ 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,399 @@ +// 
SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm driver - 
MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 
Freescale Semiconductor, Inc.  + * Copyright (C) 2019-2020 
Collabora, Ltd.  + */ + +#include  +#include 
 +#include  +#include 
 +#include 
 +#include  +#include 
 +#include  +#include 
 +#include 
 +#include 
 +#include  
+#include  +#include  +#include 
 + +#include "imx-drm.h" + 
+#define DSI_PWR_UP			0x04 +#define RESET 
0 +#define POWERUPBIT(0) + +#define 
DSI_PHY_IF_CTRL			0x5c +#define 
PHY_IF_CTRL_RESET		0x0 + +#define DSI_PHY_TST_CTRL0 
0x64 +#define PHY_TESTCLK			BIT(1) +#define 
PHY_UNTESTCLK			0 +#define PHY_TESTCLR 
BIT(0) +#define PHY_UNTESTCLR			0 + 
+#define DSI_PHY_TST_CTRL1		0x68 +#define PHY_TESTEN 
BIT(16) +#define PHY_UNTESTEN			0 +#define 
PHY_TESTDOUT(n)			(((n) & 0xff) << 8) 
+#define PHY_TESTDIN(n)			(((n) & 0xff) << 
0) + +struct imx_mipi_dsi { +	struct drm_encoder 
encoder; +	struct drm_bridge bridge; +	struct device 
*dev; +	struct regmap *mux_sel; +	struct dw_mipi_dsi 
*mipi_dsi; +	struct clk *pllref_clk; + +	void __iomem 
*base; +	unsigned int lane_mbps; +}; + +struct 
dphy_pll_testdin_map { +	unsigned int max_mbps; +	u8 
testdin; +}; + +/* The table is based on 27MHz DPHY pll 
reference clock. */ +static const struc

[PATCH v8 09/10] drm: bridge: dw-mipi-dsi: split low power cfg register into fields

2020-04-27 Thread Adrian Ratiu

According to the Host Registers documentation for IMX, STM and RK
the LP cfg register should not be written entirely in one go because
some bits are reserved and should be kept to reset values, for eg.
BIT(15) which is reserved in all versions.

This also cleans up the code by removing the the ugly defines
and making field ranges & values written more explicit.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++
 1 file changed, 33 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 140ff40fa1b62..0903ec37289dd 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -120,60 +120,6 @@
 #define DSI_TO_CNT_CFG_V1010x40
 #define DSI_PCKHDL_CFG_V1010x18
 
-#define MAX_RD_PKT_SIZE_LP BIT(24)
-#define DCS_LW_TX_LP   BIT(19)
-#define DCS_SR_0P_TX_LPBIT(18)
-#define DCS_SW_1P_TX_LPBIT(17)
-#define DCS_SW_0P_TX_LPBIT(16)
-#define GEN_LW_TX_LP   BIT(14)
-#define GEN_SR_2P_TX_LPBIT(13)
-#define GEN_SR_1P_TX_LPBIT(12)
-#define GEN_SR_0P_TX_LPBIT(11)
-#define GEN_SW_2P_TX_LPBIT(10)
-#define GEN_SW_1P_TX_LPBIT(9)
-#define GEN_SW_0P_TX_LPBIT(8)
-#define TEAR_FX_EN BIT(0)
-
-#define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
-DCS_LW_TX_LP | \
-DCS_SR_0P_TX_LP | \
-DCS_SW_1P_TX_LP | \
-DCS_SW_0P_TX_LP | \
-GEN_LW_TX_LP | \
-GEN_SR_2P_TX_LP | \
-GEN_SR_1P_TX_LP | \
-GEN_SR_0P_TX_LP | \
-GEN_SW_2P_TX_LP | \
-GEN_SW_1P_TX_LP | \
-GEN_SW_0P_TX_LP)
-
-#define EN_TEAR_FX_V101BIT(14)
-#define DCS_LW_TX_LP_V101  BIT(12)
-#define GEN_LW_TX_LP_V101  BIT(11)
-#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
-#define DCS_SW_2P_TX_LP_V101   BIT(9)
-#define DCS_SW_1P_TX_LP_V101   BIT(8)
-#define DCS_SW_0P_TX_LP_V101   BIT(7)
-#define GEN_SR_2P_TX_LP_V101   BIT(6)
-#define GEN_SR_1P_TX_LP_V101   BIT(5)
-#define GEN_SR_0P_TX_LP_V101   BIT(4)
-#define GEN_SW_2P_TX_LP_V101   BIT(3)
-#define GEN_SW_1P_TX_LP_V101   BIT(2)
-#define GEN_SW_0P_TX_LP_V101   BIT(1)
-
-#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
-GEN_LW_TX_LP_V101 | \
-MAX_RD_PKT_SIZE_LP_V101 | \
-DCS_SW_2P_TX_LP_V101 | \
-DCS_SW_1P_TX_LP_V101 | \
-DCS_SW_0P_TX_LP_V101 | \
-GEN_SR_2P_TX_LP_V101 | \
-GEN_SR_1P_TX_LP_V101 | \
-GEN_SR_0P_TX_LP_V101 | \
-GEN_SW_2P_TX_LP_V101 | \
-GEN_SW_1P_TX_LP_V101 | \
-GEN_SW_0P_TX_LP_V101)
-
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -257,7 +203,11 @@ struct dw_mipi_dsi {
struct regmap_field *field_dpi_vsync_active_low;
struct regmap_field *field_dpi_hsync_active_low;
struct regmap_field *field_cmd_mode_ack_rqst_en;
-   struct regmap_field *field_cmd_mode_all_lp_en;
+   struct regmap_field *field_cmd_mode_gen_sw_sr_en;
+   struct regmap_field *field_cmd_mode_dcs_sw_sr_en;
+   struct regmap_field *field_cmd_mode_gen_lw_en;
+   struct regmap_field *field_cmd_mode_dcs_lw_en;
+   struct regmap_field *field_cmd_mode_max_rd_pkt_size;
struct regmap_field *field_cmd_mode_en;
struct regmap_field *field_cmd_pkt_status;
struct regmap_field *field_vid_mode_en;
@@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant {
struct reg_fieldcfg_dpi_hsync_active_low;
struct reg_fieldcfg_cmd_mode_en;
struct reg_fieldcfg_cmd_mode_ack_rqst_en;
-   struct reg_fieldcfg_cmd_mode_all_lp_en;
+   struct reg_fieldcfg_cmd_mode_gen_sw_sr_en;
+   st

[PATCH v8 03/10] drm: bridge: dw_mipi_dsi: add dsi v1.01 support

2020-04-27 Thread Adrian Ratiu

The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v7:
  - Minor commit msg rewording for consistency

Changes since v5:
  - Fixed cfg_phy_status range from [0,0] to [0,2]

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f453df4eb5072..16fd87055e7b7 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
 #define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10

[PATCH v8 06/10] ARM: dts: imx6qdl: add missing mipi dsi properties

2020-04-27 Thread Adrian Ratiu

Now that we have a proper driver for the imx6 mipi dsi host controller
we can fill in the missing properties to get it working.

Cc: Laurent Pinchart 
Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Signed-off-by: Adrian Ratiu 
---
New in v8.
---
 arch/arm/boot/dts/imx6qdl.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 98da446aa0f27..5f754c3cec052 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1203,7 +1203,15 @@ mipi_csi: mipi@21dc000 {
};
 
mipi_dsi: mipi@21e {
+   compatible = "fsl,imx6-mipi-dsi", 
"snps,dw-mipi-dsi";
+   #address-cells = <1>;
+   #size-cells = <0>;
reg = <0x021e 0x4000>;
+   interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+   fsl,gpr = <>;
+   clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_IPG>;
+   clock-names = "ref", "pclk";
status = "disabled";
 
ports {
-- 
2.26.0

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[PATCH v8 05/10] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-27 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

Cc: Fabio Estevam 
Cc: Enric Balletbo Serra 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v7:
  - Removed encoder helper ops and added drm_bridge (Laurent)
  - Brought back drm_simple_encoder_init and dropped dependency on
  external unify encoder creation patch (Laurent)
  - Minor typo fixes

Changes since v6:
  - Replaced custom noop encoder with the simple drm encoder (Enric)
  - Added CONFIG_DRM_IMX6_MIPI_DSI depends on CONFIG_OF (Enric)
  - Dropped imx_mipi_dsi_register() because now it only creates the
  dummy encoder which can easily be done directly in imx_dsi_bind()

Changes since v5:
  - Reword to remove unrelated device tree patch mention (Fabio)
  - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
  - Fix freescale.com -> nxp.com email addresses (Fabio)
  - Also added myself as module author (Fabio)
  - Use DRM_DEV_* macros for consistency, print more error msg

Changes since v4:
  - Split off driver-specific configuration of phy timings due
  to new upstream API.
  - Move regmap infrastructure logic to separate commit (Ezequiel)
  - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
  - Minor warnings and driver name fixes

Changes since v3:
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio)

Changes since v2:
  - Fixed commit tags. (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after
  calling the bridge probe. (Emil)
---
 drivers/gpu/drm/imx/Kconfig|   8 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +
 3 files changed, 408 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfba..0dffc72df7922 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,11 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+   tristate "Freescale i.MX6 DRM MIPI DSI"
+   select DRM_DW_MIPI_DSI
+   depends on DRM_IMX
+   depends on OF
+   help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc8..9a7843c593478 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index 0..492decc418bc3
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019-2020 Collabora, Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_PHY_IF_CTRL0x5c
+#define PHY_IF_CTRL_RESET  0x0
+
+#define DSI_PHY_TST_CTRL0  0x64
+#define PHY_TESTCLKBIT(1)
+#define PHY_UNTESTCLK  0
+#define PHY_TESTCLRBIT(0)
+#define PHY_UNTESTCLR  0
+
+#define DSI_PHY_TST_CTRL1  0x68
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN   0
+#define PHY_TESTDOUT(n)(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
+
+struct imx_mipi_dsi {
+   struct drm_encoder encoder;
+   struct drm_bridge bridge;
+   struct device *dev;
+   struct regmap *mux_sel;
+   struct dw_mipi_dsi *mipi_dsi;
+   struct clk *pllref_clk;
+
+   void __iomem *base;
+   unsigned int lane_mbps;
+};
+
+struct dphy_pll_testdin_map {
+   unsigned int max_mbps;
+   u8 testdin;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dph

[PATCH v8 04/10] drm: bridge: dw_mipi_dsi: allow bridge daisy chaining

2020-04-27 Thread Adrian Ratiu

Up until now the assumption was that the synopsis dsi bridge will
directly connect to an encoder provided by the platform driver, but
the current practice for drivers is to leave the encoder empty via
the simple encoder API and add their logic to their own drm_bridge.

Thus we need an ablility to connect the DSI bridge to another bridge
provided by the platform driver, so we extend the dw_mipi_dsi bind()
API with a new "previous bridge" arg instead of just hardcoding NULL.

Cc: Laurent Pinchart 
Signed-off-by: Adrian Ratiu 
---
New in v8.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c   | 6 --
 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 2 +-
 include/drm/bridge/dw_mipi_dsi.h| 5 -
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 16fd87055e7b7..140ff40fa1b62 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -1456,11 +1456,13 @@ EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
 /*
  * Bind/unbind API, used from platforms based on the component framework.
  */
-int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
+int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi,
+struct drm_encoder *encoder,
+struct drm_bridge *prev_bridge)
 {
int ret;
 
-   ret = drm_bridge_attach(encoder, >bridge, NULL, 0);
+   ret = drm_bridge_attach(encoder, >bridge, prev_bridge, 0);
if (ret) {
DRM_ERROR("Failed to initialize bridge with drm\n");
return ret;
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 3feff0c45b3f7..83ef43be78135 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -929,7 +929,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
return ret;
}
 
-   ret = dw_mipi_dsi_bind(dsi->dmd, >encoder);
+   ret = dw_mipi_dsi_bind(dsi->dmd, >encoder, NULL);
if (ret) {
DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
return ret;
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
index b0e390b3288e8..699b3531f5b36 100644
--- a/include/drm/bridge/dw_mipi_dsi.h
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -14,6 +14,7 @@
 #include 
 
 struct drm_display_mode;
+struct drm_bridge;
 struct drm_encoder;
 struct dw_mipi_dsi;
 struct mipi_dsi_device;
@@ -62,7 +63,9 @@ struct dw_mipi_dsi *dw_mipi_dsi_probe(struct platform_device 
*pdev,
  const struct dw_mipi_dsi_plat_data
  *plat_data);
 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi);
-int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder);
+int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi,
+struct drm_encoder *encoder,
+struct drm_bridge *prev_bridge);
 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi);
 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave);
 
-- 
2.26.0

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[PATCH v8 07/10] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-27 Thread Adrian Ratiu

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring 
Cc: Neil Armstrong 
Cc: Fabio Estevam 
Cc: Laurent Pinchart 
Cc: devicet...@vger.kernel.org
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v7:
  - Clarified port@0,1 descriptions, marked them as required and
  added missing port@0 in example (Laurent)

Changes since v6:
  - Added ref to the newly created snps,dw-mipi-dsi.yaml (Laurent)
  - Moved *-cells properties outside patternProperties (Laurent)
  - Removed the panel port documentation (Laurent)
  - Wrapped lines at 80 chars, typo fixes, sort includes (Laurent)

Changes since v5:
  - Fixed missing reg warning (Fabio)
  - Updated dt-schema and fixed warnings (Rob)

Changes since v4:
  - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
  and addressed received binding feedback (Rob)

Changes since v3:
  - Added commit message (Neil)
  - Converted to yaml format (Neil)
  - Minor dt node + driver fixes (Rob)
  - Added small panel example to the host controller binding

Changes since v2:
  - Fixed commit tags (Emil)
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 145 ++
 1 file changed, 145 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index 0..c2c3489e63fa3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+  - Adrian Ratiu 
+
+description: |
+  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+  IP block with a companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+allOf:
+  - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
+
+properties:
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+  compatible:
+items:
+  - const: fsl,imx6q-mipi-dsi
+  - const: snps,dw-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module Clock
+  - description: DSI bus clock
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+
+  fsl,gpr:
+description:
+  Phandle to the iomuxc-gpr region containing the multiplexer ctrl 
register.
+$ref: /schemas/types.yaml#/definitions/phandle
+
+  ports:
+type: object
+description: |
+  A node containing DSI input & output port nodes with endpoint
+  definitions as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+  Documentation/devicetree/bindings/graph.txt
+properties:
+  port@0:
+type: object
+description:
+  DSI input port connected to a parallel RGB LTDC output port.
+
+  port@1:
+type: object
+description:
+  DSI serial RGB output port connected to a panel or bridge input port.
+
+required:
+  - port@0
+  - port@1
+
+additionalProperties: false
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+examples:
+  - |+
+#include 
+#include 
+#include 
+
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+mipi_mux_0: endpoint {
+remote-endpoint = <_di0_mipi>;
+};
+};
+port@1 {
+reg = <1>;
+dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+panel@0 {
+compatible = "sharp,ls032b3sx01";
+

[PATCH v8 10/10] drm: bridge: dw-mipi-dsi: fix bad register field offsets

2020-04-27 Thread Adrian Ratiu

According to the DSI Host Registers sections available in the IMX,
STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
are smaller or bigger than what's coded in the driver, leading to
r/w in reserved spaces which might cause undefined behaviours.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +--
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 0903ec37289dd..bf22b04761fdf 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
 static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
.cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
-   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 2),
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 1),
.cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
.cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
.cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
@@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_cmd_mode_dcs_sw_sr_en =REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
.cfg_cmd_mode_dcs_lw_en =   REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
.cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
-   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
-   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
-   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
+   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
+   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
+   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
.cfg_vid_mode_type =REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
.cfg_vid_mode_low_power =   REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
.cfg_vid_mode_vpg_en =  REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
.cfg_vid_mode_vpg_horiz =   REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
-   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
-   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
-   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
-   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
-   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
-   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
-   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
-   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
+   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
+   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
+   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
+   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
+   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
+   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
+   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
.cfg_phy_txrequestclkhs =   REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
-   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
-   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
+   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
.cfg_phy_lp2hs_time =   REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
.cfg_phy_hs2lp_time =   REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
-   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
-   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
-   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
+   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
+   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
.cfg_phy_clklp2hs_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
.cfg_phy_clkhs2lp_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 
31),
.cfg_phy_testclr =  REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
@@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant

[PATCH v8 01/10] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-04-27 Thread Adrian Ratiu

In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.

The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.

Cc: Enric Balletbo Serra 
Suggested-by: Ezequiel Garcia 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Chnages since v7:
  - Minor checkpatch line fix

Changes since v6:
  - Select REGMAP_MMIO in Kconfig (Enric)
  - Drop unnecessary stack variable inits (Enric)
  - Make bridge error ASAP after a bad revision read (Enric)
  - Drop redundant read of hw_version in dphy_timing_config (Enric)

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 210 ++
 2 files changed, 121 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 21a1be3ced0f3..080146093b68e 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -39,3 +39,4 @@ config DRM_DW_MIPI_DSI
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
+   select REGMAP_MMIO
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7bd..34b8668ae24ea 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+   u32 hw_version;
 
 #ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,8 +366,8 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,20 +375,20 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct 
dw_mipi_dsi *dsi, u32 hdr_val)
int ret;
u32 val, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return

[PATCH v8 00/10] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-04-27 Thread Adrian Ratiu

Hello everyone,

The dt-binding added in this series depends on [1] for
"make dt_binding_check" to pass.

The biggest change in v8 is a conversion of the imx6 host controller
driver to drm_bridge and an extension to dw_mipi_dsi.c which allows
platform drivers to daisy-chain bridges between the encoder and the
Synopsis DSI bridge.

Obviously a lot more work can be done on this front, for example to
convert the Rockchip and STM platform drivers to drm_bridge (the STM
driver doesn't even use the current dw_mipi_dsi.c bind API to attach)
or to improve the API itself.

Another kind of related work is refactoring the existng IMX drivers
to drm_bridge and move the empty encoder management to imx-drm-core.

Because this patch is already quite big, I did only the minimum
changes to get the imx6 mipi dsi driver in good shape, all the other
changes should be done in separate patch series.

I also just realized imx6qdl.dtsi was missing some properties to get
the DSI host controller working so I've added them as a new patch.

All received feedback up to this point has been addressed.

Thank you and best wishes,
Adrian

[1] 
https://lore.kernel.org/linux-devicetree/20200423100058.1734009-1-adrian.ra...@collabora.com/

Adrian Ratiu (10):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: dw_mipi_dsi: add dsi v1.01 support
  drm: bridge: dw_mipi_dsi: allow bridge daisy chaining
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  ARM: dts: imx6qdl: add missing mipi dsi properties
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 145 
 arch/arm/boot/dts/imx6qdl.dtsi|   8 +
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 698 +-
 drivers/gpu/drm/imx/Kconfig   |   8 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 399 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |   2 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  12 +-
 include/drm/bridge/dw_mipi_dsi.h  |   5 +-
 10 files changed, 1070 insertions(+), 209 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
2.26.0

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[PATCH v8 08/10] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

2020-04-27 Thread Adrian Ratiu

The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.

Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.

The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.

Tested on STM32F769 and STM32MP1.

Cc: linux-st...@st-md-mailman.stormreply.com
Reported-by: Adrian Pop 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d0..7218e405d7e2b 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -402,15 +402,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
-   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
-   clk_disable_unprepare(pclk);
-
-   if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
-   ret = -ENODEV;
-   DRM_ERROR("bad dsi hardware version\n");
-   goto err_dsi_probe;
-   }
-
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
@@ -423,6 +414,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
+   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+   clk_disable_unprepare(pclk);
+
return 0;
 
 err_dsi_probe:
-- 
2.26.0

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[PATCH v8 02/10] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2020-04-27 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.

The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fix CONFIG_DEBUG_FS build (Adrian)
  - Fix DRM_MODE_FLAG_* test negation (Adrian)
  - Fixed cfg_phy_status range from [0,0] to [0,2]
  - Replace do {} while(0) with GCC extension ({}) (Andrzej)
  - Fixed payload no-op writes on STM devices (Adrian & Arnaud)

Changes since v4:
  - Move regmap infrastructure logic to a separate commit (Ezequiel)
  - Consolidate field infrastructure in this commit (Ezequiel)
  - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)

Changes since v2:
  - Added const declarations to dw_mipi_dsi structs (Emil)
  - Fixed commit tags (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 499 --
 1 file changed, 347 insertions(+), 152 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 34b8668ae24ea..f453df4eb5072 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -47,7 +48,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +56,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +112,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP

RE: [PATCH v4] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-23 Thread Adrian Ratiu


Hi Angelo,

On Thu, 23 Apr 2020, Angelo Ribeiro  
wrote:
Hi Adrian, 

From: Adrian Ratiu  Date: Thu, Apr 
23, 2020 at 11:00:58 

This converts the Synopsis MIPI DSI binding documentation to 
yaml and should be quite straightforward. I've added a missing 
ref clk and also added Philippe as maintainer b/c he's the 
original txt author following the algorithm provided in 
Message-ID 20200420175909.ga5...@ravnborg.org.   Cc: Philippe 
CORNU  Cc: devicet...@vger.kernel.org 
Suggested-by: Laurent Pinchart 
 Reviewed-by: Rob Herring 
 Signed-off-by: Adrian Ratiu 
 --- Changes in v4: 
  - Dropped panel patternProperties (Rob) 
 Changes in v3: 
  - Added ports property and its children which are required 
  (Laurent) - Sorted required list alphabetically 
 Changes in v2: 
  - Removed unnecessary descriptions and maxItems (Rob) - 
  Changed maintainers entry / dropped Mark (Rob) - Added 
  dsi-controller.yaml ref (Rob) 
--- 
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 - 
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 68 
 +++ 2 files changed, 68 insertions(+), 32 
 deletions(-) delete mode 100644 
 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
 create mode 100644 
 Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
 diff --git 
a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
deleted file mode 100644 index b13adf30b8d3b..0 --- 
a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
+++ /dev/null @@ -1,32 +0,0 @@ -Synopsys DesignWare MIPI DSI 
host controller - - 
-This document defines device tree properties for the Synopsys 
DesignWare MIPI -DSI host controller. It doesn't constitue a 
device tree binding specification -by itself but is meant to be 
referenced by platform-specific device tree -bindings.  - -When 
referenced from platform device tree bindings the properties 
defined in -this document are defined as follows. The platform 
device tree bindings are -responsible for defining whether each 
optional property is used or not.  - -- reg: Memory mapped base 
address and length of the DesignWare MIPI DSI -  host 
controller registers. (mandatory) - -- clocks: References to 
all the clocks specified in the clock-names property -  as 
specified in [1]. (mandatory) - -- clock-names: -  - "pclk" is 
the peripheral clock for either AHB and APB. (mandatory) -  - 
"px_clk" is the pixel clock for the DPI/RGB input. (optional) - 
-- resets: References to all the resets specified in the 
reset-names property -  as specified in [2]. (optional) - -- 
reset-names: string reset name, must be "apb" if 
used. (optional) - -- panel or bridge node: see 
[3]. (mandatory) - -[1] 
Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] 
Documentation/devicetree/bindings/reset/reset.txt -[3] 
Documentation/devicetree/bindings/display/mipi-dsi-bus.txt diff 
--git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
new file mode 100644 index 0..012aa8e7cb8cd --- 
/dev/null +++ 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
@@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR 
BSD-2-Clause) +%YAML 1.2 +--- +$id: 
https://urldefense.com/v3/__http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml*__;Iw!!A4F2R9G_pg!Pn0TP0h4QkEcILgH_xBqMjSM4dJxlyU3iCvF4FSbmdQOSIV309ngWu8EKCpP901d$ 
+$schema: 
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!A4F2R9G_pg!Pn0TP0h4QkEcILgH_xBqMjSM4dJxlyU3iCvF4FSbmdQOSIV309ngWu8EKPfhyNgW$ 
+ +title: Synopsys DesignWare MIPI DSI host controller + 
+maintainers: +  - Philippe CORNU  + 
+description: | +  This document defines device tree properties 
for the Synopsys DesignWare MIPI +  DSI host controller. It 
doesn't constitue a device tree binding specification +  by 
itself but is meant to be referenced by platform-specific 
device tree +  bindings.  + +  When referenced from platform 
device tree bindings the properties defined in +  this document 
are defined as follows. The platform device tree bindings are + 
responsible for defining whether each property is required or 
optional.  + +allOf: +  - $ref: ../dsi-controller.yaml# + 
+properties: +  reg: +maxItems: 1 + +  clocks: +items: 
+  - description: Module clock +  - description: DSI 
bus clock for either AHB and APB +  - description: Pixel 
clock for the DPI/RGB input +minItems: 2 + +  clock-names: 
+items: +  - const: ref +  - const: pclk +  - 
const: px_clk +minItems: 2 + +  resets: +maxItems: 1 + 
+  reset-names: +const: apb + +  ports: +type: object + 
+properties: +  port@0: +type: object + 
description: Input node to rece

[PATCH v4] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-23 Thread Adrian Ratiu

This converts the Synopsis MIPI DSI binding documentation to yaml and
should be quite straightforward. I've added a missing ref clk and also
added Philippe as maintainer b/c he's the original txt author following
the algorithm provided in Message-ID 20200420175909.ga5...@ravnborg.org.

Cc: Philippe CORNU 
Cc: devicet...@vger.kernel.org
Suggested-by: Laurent Pinchart 
Reviewed-by: Rob Herring 
Signed-off-by: Adrian Ratiu 
---
Changes in v4:
  - Dropped panel patternProperties (Rob)

Changes in v3:
  - Added ports property and its children which are required (Laurent)
  - Sorted required list alphabetically

Changes in v2:
  - Removed unnecessary descriptions and maxItems (Rob)
  - Changed maintainers entry / dropped Mark (Rob)
  - Added dsi-controller.yaml ref (Rob)
---
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 -
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 68 +++
 2 files changed, 68 insertions(+), 32 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
deleted file mode 100644
index b13adf30b8d3b..0
--- a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Synopsys DesignWare MIPI DSI host controller
-
-
-This document defines device tree properties for the Synopsys DesignWare MIPI
-DSI host controller. It doesn't constitue a device tree binding specification
-by itself but is meant to be referenced by platform-specific device tree
-bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each optional property is used or not.
-
-- reg: Memory mapped base address and length of the DesignWare MIPI DSI
-  host controller registers. (mandatory)
-
-- clocks: References to all the clocks specified in the clock-names property
-  as specified in [1]. (mandatory)
-
-- clock-names:
-  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
-  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
-
-- resets: References to all the resets specified in the reset-names property
-  as specified in [2]. (optional)
-
-- reset-names: string reset name, must be "apb" if used. (optional)
-
-- panel or bridge node: see [3]. (mandatory)
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/reset/reset.txt
-[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
new file mode 100644
index 0..012aa8e7cb8cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare MIPI DSI host controller
+
+maintainers:
+  - Philippe CORNU 
+
+description: |
+  This document defines device tree properties for the Synopsys DesignWare MIPI
+  DSI host controller. It doesn't constitue a device tree binding specification
+  by itself but is meant to be referenced by platform-specific device tree
+  bindings.
+
+  When referenced from platform device tree bindings the properties defined in
+  this document are defined as follows. The platform device tree bindings are
+  responsible for defining whether each property is required or optional.
+
+allOf:
+  - $ref: ../dsi-controller.yaml#
+
+properties:
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module clock
+  - description: DSI bus clock for either AHB and APB
+  - description: Pixel clock for the DPI/RGB input
+minItems: 2
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+  - const: px_clk
+minItems: 2
+
+  resets:
+maxItems: 1
+
+  reset-names:
+const: apb
+
+  ports:
+type: object
+
+properties:
+  port@0:
+type: object
+description: Input node to receive pixel data.
+  port@1:
+type: object
+description: DSI output node to panel.
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - clock-names
+  - clocks
+  - ports
+  - reg
-- 
2.26.0

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Re: [PATCH v7 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-22 Thread Adrian Ratiu

On Wed, 22 Apr 2020, Laurent Pinchart 
 wrote:
Hi Adrian, 

Thank you for the patch. 

On Tue, Apr 21, 2020 at 07:16:07PM +0300, Adrian Ratiu wrote: 
This provides an example DT binding for the MIPI DSI host 
controller present on the i.MX6 SoC based on Synopsis 
DesignWare v1.01 IP.   Cc: Rob Herring  Cc: 
Neil Armstrong  Cc: Fabio Estevam 
 Cc: Laurent Pinchart 
 Cc: 
devicet...@vger.kernel.org Tested-by: Adrian Pop 
 Tested-by: Arnaud Ferraris 
 Signed-off-by: Sjoerd Simons 
 Signed-off-by: Martyn Welch 
 Signed-off-by: Adrian Ratiu 
 --- Changes since v6: 
  - Added ref to the newly created snps,dw-mipi-dsi.yaml 
  (Laurent) - Moved *-cells properties outside 
  patternProperties (Laurent) - Removed the panel port 
  documentation (Laurent) - Wrapped lines at 80 chars, typo 
  fixes, sort includes (Laurent) 
 Changes since v5: 
  - Fixed missing reg warning (Fabio) - Updated dt-schema and 
  fixed warnings (Rob) 
 Changes since v4: 
  - Fixed yaml binding to pass `make dt_binding_check 
  dtbs_check` and addressed received binding feedback (Rob) 
 Changes since v3: 
  - Added commit message (Neil) - Converted to yaml format 
  (Neil) - Minor dt node + driver fixes (Rob) - Added small 
  panel example to the host controller binding 
 Changes since v2: 
  - Fixed commit tags (Emil) 
--- 
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 135 
 ++ 1 file changed, 135 insertions(+) create 
 mode 100644 
 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
 diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
new file mode 100644 index 0..b73e3ae33a852 --- 
/dev/null +++ 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
@@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR 
BSD-2-Clause) +%YAML 1.2 +--- +$id: 
http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml# 
+$schema: http://devicetree.org/meta-schemas/core.yaml# + 
+title: Freescale i.MX6 DW MIPI DSI Host Controller + 
+maintainers: +  - Adrian Ratiu  + 
+description: | +  The i.MX6 DSI host controller is a Synopsys 
DesignWare MIPI DSI v1.01 +  IP block with a companion PHY IP. 
+ +  These DT bindings follow the Synopsys DW MIPI DSI bindings 
defined in + 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
with +  the following device-specific properties.  + +allOf: + 
- $ref: ../bridge/snps,dw-mipi-dsi.yaml# + +properties: + 
'#address-cells': +const: 1 + +  '#size-cells': +const: 
0 + +  compatible: +items: +  - const: 
fsl,imx6q-mipi-dsi +  - const: snps,dw-mipi-dsi + +  reg: + 
maxItems: 1 + +  interrupts: +maxItems: 1 + +  clocks: + 
items: +  - description: Module Clock +  - description: 
DSI bus clock + +  clock-names: +items: +  - const: ref 
+  - const: pclk + +  fsl,gpr: +description: + 
Phandle to the iomuxc-gpr region containing the multiplexer 
ctrl register.  +$ref: 
/schemas/types.yaml#/definitions/phandle + +  ports: +type: 
object +description: | +  A node containing DSI input & 
output port nodes with endpoint +  definitions as 
documented in + 
Documentation/devicetree/bindings/media/video-interfaces.txt + 
Documentation/devicetree/bindings/graph.txt +properties: + 
port@0: +type: object +description: + 
DSI input port node, connected to the ltdc rgb output port.  + 
+  port@1: +type: object +description: + 
RGB output port node, connected to a panel or a bridge input 
port. 


Isn't it the other way around, doesn't the bridge take RGB input 
and output DSI ? And to be precise, it's not about RGB, but 
about the input being parallel interface (DSI will also carry 
RGB). 

I would add 

required: 
  - port@0 - port@1 



Sorry for the confusions and omissions :) Will fix the names to 
avoid ambiguities and also add the required property and the 
missing port@0 in the example below in v8.


Many thanks,
Adrian




+
+additionalProperties: false
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+examples:
+  - |+
+#include 
+#include 
+#include 
+
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;


port@0 is missing.


+

[PATCH v3] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-22 Thread Adrian Ratiu

This converts the Synopsis MIPI DSI binding documentation to yaml and
should be quite straightforward. I've added a missing ref clk and also
added Philippe as maintainer b/c he's the original txt author following
the algorithm provided in Message-ID 20200420175909.ga5...@ravnborg.org.

Cc: Rob Herring 
Cc: Philippe CORNU 
Cc: devicet...@vger.kernel.org
Suggested-by: Laurent Pinchart 
Signed-off-by: Adrian Ratiu 
---
Changes in v3:
  - Added ports property and its children which are required (Laurent)
  - Sorted required list alphabetically

Changes in v2:
  - Removed unnecessary descriptions and maxItems (Rob)
  - Changed maintainers entry / dropped Mark (Rob)
  - Added dsi-controller.yaml ref (Rob)
---
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 -
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 72 +++
 2 files changed, 72 insertions(+), 32 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
deleted file mode 100644
index b13adf30b8d3b..0
--- a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Synopsys DesignWare MIPI DSI host controller
-
-
-This document defines device tree properties for the Synopsys DesignWare MIPI
-DSI host controller. It doesn't constitue a device tree binding specification
-by itself but is meant to be referenced by platform-specific device tree
-bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each optional property is used or not.
-
-- reg: Memory mapped base address and length of the DesignWare MIPI DSI
-  host controller registers. (mandatory)
-
-- clocks: References to all the clocks specified in the clock-names property
-  as specified in [1]. (mandatory)
-
-- clock-names:
-  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
-  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
-
-- resets: References to all the resets specified in the reset-names property
-  as specified in [2]. (optional)
-
-- reset-names: string reset name, must be "apb" if used. (optional)
-
-- panel or bridge node: see [3]. (mandatory)
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/reset/reset.txt
-[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
new file mode 100644
index 0..076567d8d8ec1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare MIPI DSI host controller
+
+maintainers:
+  - Philippe CORNU 
+
+description: |
+  This document defines device tree properties for the Synopsys DesignWare MIPI
+  DSI host controller. It doesn't constitue a device tree binding specification
+  by itself but is meant to be referenced by platform-specific device tree
+  bindings.
+
+  When referenced from platform device tree bindings the properties defined in
+  this document are defined as follows. The platform device tree bindings are
+  responsible for defining whether each property is required or optional.
+
+allOf:
+  - $ref: ../dsi-controller.yaml#
+
+properties:
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module clock
+  - description: DSI bus clock for either AHB and APB
+  - description: Pixel clock for the DPI/RGB input
+minItems: 2
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+  - const: px_clk
+minItems: 2
+
+  resets:
+maxItems: 1
+
+  reset-names:
+const: apb
+
+  ports:
+type: object
+
+properties:
+  port@0:
+type: object
+description: Input node to receive pixel data.
+  port@1:
+type: object
+description: DSI output node to panel.
+
+required:
+  - port@0
+  - port@1
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+
+required:
+  - clock-names
+  - clocks
+  - ports
+  - reg
-- 
2.26.0

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[PATCH v3] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-22 Thread Adrian Ratiu

This converts the Synopsis MIPI DSI binding documentation to yaml and
should be quite straightforward. I've added a missing ref clk and also
added Philippe as maintainer b/c he's the original txt author following
the algorithm provided in Message-ID 20200420175909.ga5...@ravnborg.org.

Cc: Rob Herring 
Cc: Philippe CORNU 
Cc: devicet...@vger.kernel.org
Suggested-by: Laurent Pinchart 
Signed-off-by: Adrian Ratiu 
---
Changes in v3:
  - Added ports property and its children which are required (Laurent)
  - Sorted required list alphabetically

Changes in v2:
  - Removed unnecessary descriptions and maxItems (Rob)
  - Changed maintainers entry / dropped Mark (Rob)
  - Added dsi-controller.yaml ref (Rob)
---
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 -
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 72 +++
 2 files changed, 72 insertions(+), 32 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
deleted file mode 100644
index b13adf30b8d3b..0
--- a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Synopsys DesignWare MIPI DSI host controller
-
-
-This document defines device tree properties for the Synopsys DesignWare MIPI
-DSI host controller. It doesn't constitue a device tree binding specification
-by itself but is meant to be referenced by platform-specific device tree
-bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each optional property is used or not.
-
-- reg: Memory mapped base address and length of the DesignWare MIPI DSI
-  host controller registers. (mandatory)
-
-- clocks: References to all the clocks specified in the clock-names property
-  as specified in [1]. (mandatory)
-
-- clock-names:
-  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
-  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
-
-- resets: References to all the resets specified in the reset-names property
-  as specified in [2]. (optional)
-
-- reset-names: string reset name, must be "apb" if used. (optional)
-
-- panel or bridge node: see [3]. (mandatory)
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/reset/reset.txt
-[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
new file mode 100644
index 0..076567d8d8ec1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare MIPI DSI host controller
+
+maintainers:
+  - Philippe CORNU 
+
+description: |
+  This document defines device tree properties for the Synopsys DesignWare MIPI
+  DSI host controller. It doesn't constitue a device tree binding specification
+  by itself but is meant to be referenced by platform-specific device tree
+  bindings.
+
+  When referenced from platform device tree bindings the properties defined in
+  this document are defined as follows. The platform device tree bindings are
+  responsible for defining whether each property is required or optional.
+
+allOf:
+  - $ref: ../dsi-controller.yaml#
+
+properties:
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module clock
+  - description: DSI bus clock for either AHB and APB
+  - description: Pixel clock for the DPI/RGB input
+minItems: 2
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+  - const: px_clk
+minItems: 2
+
+  resets:
+maxItems: 1
+
+  reset-names:
+const: apb
+
+  ports:
+type: object
+
+properties:
+  port@0:
+type: object
+description: Input node to receive pixel data.
+  port@1:
+type: object
+description: DSI output node to panel.
+
+required:
+  - port@0
+  - port@1
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+
+required:
+  - clock-names
+  - clocks
+  - ports
+  - reg
-- 
2.26.0

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Re: [PATCH v7 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-22 Thread Adrian Ratiu

On Wed, 22 Apr 2020, Laurent Pinchart 
 wrote:
Hi Adrian, 

On Wed, Apr 22, 2020 at 01:15:41PM +0300, Adrian Ratiu wrote: 
On Wed, 22 Apr 2020, Laurent Pinchart wrote: 
> On Wed, Apr 22, 2020 at 03:58:33AM +0300, Laurent Pinchart 
> wrote:  
>> On Tue, Apr 21, 2020 at 07:16:07PM +0300, Adrian Ratiu 
>> wrote:  
>>> This provides an example DT binding for the MIPI DSI host 
>>> controller present on the i.MX6 SoC based on Synopsis 
>>> DesignWare v1.01 IP.   Cc: Rob Herring  
>>> Cc:  Neil Armstrong  Cc: Fabio 
>>> Estevam   Cc: Laurent Pinchart 
>>>  Cc: 
>>> devicet...@vger.kernel.org Tested-by: Adrian Pop 
>>>  Tested-by: Arnaud Ferraris 
>>>  Signed-off-by: Sjoerd 
>>> Simons   Signed-off-by: Martyn 
>>> Welch   Signed-off-by: Adrian 
>>> Ratiu   --- Changes since v6:  
>>>   - Added ref to the newly created snps,dw-mipi-dsi.yaml 
>>>   (Laurent) - Moved *-cells properties outside 
>>>   patternProperties (Laurent) - Removed the panel port 
>>>   documentation (Laurent) - Wrapped lines at 80 chars, typo 
>>>   fixes, sort includes (Laurent)  
>>>  Changes since v5:  
>>>   - Fixed missing reg warning (Fabio) - Updated dt-schema 
>>>   and  fixed warnings (Rob)  
>>>  Changes since v4:  
>>>   - Fixed yaml binding to pass `make dt_binding_check 
>>>   dtbs_check` and addressed received binding feedback (Rob)  
>>>  Changes since v3:  
>>>   - Added commit message (Neil) - Converted to yaml format 
>>>   (Neil) - Minor dt node + driver fixes (Rob) - Added small 
>>>   panel example to the host controller binding  
>>>  Changes since v2:  
>>>   - Fixed commit tags (Emil)  
>>> ---  
>>>  .../display/imx/fsl,mipi-dsi-imx6.yaml| 135 
>>>  ++ 1 file changed, 135 insertions(+) 
>>>  create  mode 100644 
>>>  Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>>>  diff --git  
>>> a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>>> b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>>> new file mode 100644 index 0..b73e3ae33a852 --- 
>>> /dev/null +++ 
>>> b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>>> @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only 
>>> OR BSD-2-Clause) +%YAML 1.2 +--- +$id: 
>>> http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml# 
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# + 
>>> +title: Freescale i.MX6 DW MIPI DSI Host Controller + 
>>> +maintainers: +  - Adrian Ratiu 
>>>   + +description: | +  The 
>>> i.MX6 DSI host controller is a  Synopsys DesignWare MIPI 
>>> DSI v1.01 +  IP block with a  companion PHY IP.  
>  I forgot to mention, if there's a companion PHY, shouldn't 
> it be  referenced from the DT bindings ?  
 I don't think so, that description was copied verbatim from 
the  imx6 ref manual IIRC, the physical layer is the same for 
MIPI DSI  which does TX as for MIPI CSI which does RX, but 
looking at the  ref manual and how drivers are written I don't 
think it's  necessary. 


Does that mean that the PHY is controlled through the registers 
specified by the reg property ? If so then this is fine. 



Yes that is correct, there is just a single set of conf registers 
specified via reg.


This might change if we wanted to unify the DSI and CSI drivers a 
bit, but considering the scope already associated with this patch 
series I'm a bit afraid to open a subject like that =)


That's understandable :-)


>>> +
>>> +  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
>>> +  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
>>> +  the following device-specific properties.
>>> +
>>> +allOf:
>>> +  - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
>>> +
>>> +properties:
>>> +  '#address-cells':
>>> +const: 1
>>> +
>>> +  '#size-cells':
>>> +const: 0
>>> +
>>> +  compatible:
>>> +items:
>>> +  - const: fsl,imx6q-mipi-dsi
>>> +  - const: snps,dw-mipi-dsi
>>> +
>>> +  reg:
>>> +maxItems: 1
>>> +
>>> +  interrupts:
>>> +maxItems: 1
>>> +
>>> +  clocks:
>>> +items:
>>> +  - description: Module Clock
>>> +  - description: DSI bus clock
>>> +
>>> +  clock-names:
>>> +items:
>>> +  -

Re: [PATCH v7 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-22 Thread Adrian Ratiu

On Wed, 22 Apr 2020, Laurent Pinchart 
 wrote:
Hi Adrian, 



Hi Laurent,

On Wed, Apr 22, 2020 at 03:58:33AM +0300, Laurent Pinchart 
wrote: 
On Tue, Apr 21, 2020 at 07:16:07PM +0300, Adrian Ratiu wrote: 
> This provides an example DT binding for the MIPI DSI host 
> controller present on the i.MX6 SoC based on Synopsis 
> DesignWare v1.01 IP.   Cc: Rob Herring  Cc: 
> Neil Armstrong  Cc: Fabio Estevam 
>  Cc: Laurent Pinchart 
>  Cc: 
> devicet...@vger.kernel.org Tested-by: Adrian Pop 
>  Tested-by: Arnaud Ferraris 
>  Signed-off-by: Sjoerd Simons 
>  Signed-off-by: Martyn Welch 
>  Signed-off-by: Adrian Ratiu 
>  --- Changes since v6: 
>   - Added ref to the newly created snps,dw-mipi-dsi.yaml 
>   (Laurent) - Moved *-cells properties outside 
>   patternProperties (Laurent) - Removed the panel port 
>   documentation (Laurent) - Wrapped lines at 80 chars, typo 
>   fixes, sort includes (Laurent) 
>  Changes since v5: 
>   - Fixed missing reg warning (Fabio) - Updated dt-schema and 
>   fixed warnings (Rob) 
>  Changes since v4: 
>   - Fixed yaml binding to pass `make dt_binding_check 
>   dtbs_check` and addressed received binding feedback (Rob) 
>  Changes since v3: 
>   - Added commit message (Neil) - Converted to yaml format 
>   (Neil) - Minor dt node + driver fixes (Rob) - Added small 
>   panel example to the host controller binding 
>  Changes since v2: 
>   - Fixed commit tags (Emil) 
> --- 
>  .../display/imx/fsl,mipi-dsi-imx6.yaml| 135 
>  ++ 1 file changed, 135 insertions(+) create 
>  mode 100644 
>  Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
>  diff --git 
> a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
> b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
> new file mode 100644 index 0..b73e3ae33a852 --- 
> /dev/null +++ 
> b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
> @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only 
> OR BSD-2-Clause) +%YAML 1.2 +--- +$id: 
> http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml# 
> +$schema: http://devicetree.org/meta-schemas/core.yaml# + 
> +title: Freescale i.MX6 DW MIPI DSI Host Controller + 
> +maintainers: +  - Adrian Ratiu  
> + +description: | +  The i.MX6 DSI host controller is a 
> Synopsys DesignWare MIPI DSI v1.01 +  IP block with a 
> companion PHY IP. 


I forgot to mention, if there's a companion PHY, shouldn't it be 
referenced from the DT bindings ? 



I don't think so, that description was copied verbatim from the 
imx6 ref manual IIRC, the physical layer is the same for MIPI DSI 
which does TX as for MIPI CSI which does RX, but looking at the 
ref manual and how drivers are written I don't think it's 
necessary.


This might change if we wanted to unify the DSI and CSI drivers a 
bit, but considering the scope already associated with this patch 
series I'm a bit afraid to open a subject like that =)



> +
> +  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
> +  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
> +  the following device-specific properties.
> +
> +allOf:
> +  - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
> +
> +properties:
> +  '#address-cells':
> +const: 1
> +
> +  '#size-cells':
> +const: 0
> +
> +  compatible:
> +items:
> +  - const: fsl,imx6q-mipi-dsi
> +  - const: snps,dw-mipi-dsi
> +
> +  reg:
> +maxItems: 1
> +
> +  interrupts:
> +maxItems: 1
> +
> +  clocks:
> +items:
> +  - description: Module Clock
> +  - description: DSI bus clock
> +
> +  clock-names:
> +items:
> +  - const: ref
> +  - const: pclk
> +
> +  fsl,gpr:
> +description:
> +  Phandle to the iomuxc-gpr region containing the multiplexer ctrl 
register.
> +$ref: /schemas/types.yaml#/definitions/phandle
> +
> +  ports:
> +type: object
> +description: |
> +  A node containing DSI input & output port nodes with endpoint
> +  definitions as documented in
> +  Documentation/devicetree/bindings/media/video-interfaces.txt
> +  Documentation/devicetree/bindings/graph.txt
> +properties:
> +  port@0:
> +type: object
> +description:
> +  DSI input port node, connected to the ltdc rgb output port.
> +
> +  port@1:
> +type: object
> +description:
> +  RGB output port node, connected to a panel or a bridge input port.

Isn't it the other way around, doesn't the bridge take RGB input and
output DSI ? And to be precise, it's not about RGB, but about the input
being parallel interface (DSI will also car

Re: [PATCH v7 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-22 Thread Adrian Ratiu

On Wed, 22 Apr 2020, Laurent Pinchart 
 wrote:
Hi Adrian, 


Hi Laurent,



On Tue, Apr 21, 2020 at 07:16:06PM +0300, Adrian Ratiu wrote: 
This adds support for the Synopsis DesignWare MIPI DSI v1.01 
host controller which is embedded in i.MX 6 SoCs.   Based on 
following patches, but updated/extended to work with existing 
support found in the kernel:  - drm: imx: Support Synopsys 
DesignWare MIPI DSI host controller 
  Signed-off-by: Liu Ying  
 Cc: Fabio Estevam  Cc: Enric Balletbo 
Serra  Reviewed-by: Emil Velikov 
 Tested-by: Adrian Pop 
 Tested-by: Arnaud Ferraris 
 Signed-off-by: Sjoerd Simons 
 Signed-off-by: Martyn Welch 
 Signed-off-by: Adrian Ratiu 
 --- Changes since v6: 
  - Replaced custom noop encoder with the simple drm encoder 
  (Enric) - Added CONFIG_DRM_IMX6_MIPI_DSI depends on CONFIG_OF 
  (Enric) - Dropped imx_mipi_dsi_register() because now it only 
  creates the dummy encoder which can easily be done directly 
  in imx_dsi_bind() 
 Changes since v5: 
  - Reword to remove unrelated device tree patch mention 
  (Fabio) - Move pllref_clk enable/disable to bind/unbind 
  (Ezequiel) - Fix freescale.com -> nxp.com email addresses 
  (Fabio) - Also added myself as module author (Fabio) - Use 
  DRM_DEV_* macros for consistency, print more error msg 
 Changes since v4: 
  - Split off driver-specific configuration of phy timings due 
  to new upstream API.  - Move regmap infrastructure logic to 
  separate commit (Ezequiel) - Move dsi v1.01 layout addition 
  to a separate commit (Ezequiel) - Minor warnings and driver 
  name fixes 
 Changes since v3: 
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio) 
 Changes since v2: 
  - Fixed commit tags. (Emil) 
 Changes since v1: 
  - Moved register definitions & regmap initialization into 
  bridge module. Platform drivers get the regmap via plat_data 
  after calling the bridge probe. (Emil) 
--- 
 drivers/gpu/drm/imx/Kconfig|   8 + 
 drivers/gpu/drm/imx/Makefile   |   1 + 
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 391 
 + 3 files changed, 400 insertions(+) 
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
 diff --git a/drivers/gpu/drm/imx/Kconfig 
b/drivers/gpu/drm/imx/Kconfig index 
207bf7409dfba..0dffc72df7922 100644 --- 
a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig 
@@ -39,3 +39,11 @@ config DRM_IMX_HDMI 
 	depends on DRM_IMX help Choose this if you want to use 
 HDMI on i.MX6. 
+ +config DRM_IMX6_MIPI_DSI +	tristate "Freescale i.MX6 
DRM MIPI DSI" +	select DRM_DW_MIPI_DSI +	depends on 
DRM_IMX +	depends on OF +	help +	  Choose this if you want 
to use MIPI DSI on i.MX6.  diff --git 
a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile 
index 21cdcc2faabc8..9a7843c593478 100644 --- 
a/drivers/gpu/drm/imx/Makefile +++ 
b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ 
obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o 
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o 
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff 
--git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 
index 0..f8a0a4fe16e21 --- /dev/null +++ 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,391 @@ +// 
SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm driver - 
MIPI DSI Host Controller + * + * Copyright (C) 2011-2015 
Freescale Semiconductor, Inc.  + * Copyright (C) 2019-2020 
Collabora, Ltd.  + */ + +#include  +#include 
 +#include  +#include 
 +#include 
 +#include  +#include 
 +#include  +#include 
 +#include  
+#include  +#include  
+#include  + +#include "imx-drm.h" + +#define 
DSI_PWR_UP			0x04 +#define RESET 
0 +#define POWERUPBIT(0) + +#define 
DSI_PHY_IF_CTRL			0x5c +#define 
PHY_IF_CTRL_RESET		0x0 + +#define DSI_PHY_TST_CTRL0 
0x64 +#define PHY_TESTCLK			BIT(1) +#define 
PHY_UNTESTCLK			0 +#define PHY_TESTCLR 
BIT(0) +#define PHY_UNTESTCLR			0 + 
+#define DSI_PHY_TST_CTRL1		0x68 +#define PHY_TESTEN 
BIT(16) +#define PHY_UNTESTEN			0 +#define 
PHY_TESTDOUT(n)			(((n) & 0xff) << 8) 
+#define PHY_TESTDIN(n)			(((n) & 0xff) << 
0) + +struct imx_mipi_dsi { +	struct drm_encoder 
encoder; +	struct device *dev; +	struct regmap *mux_sel; + 
struct dw_mipi_dsi *mipi_dsi; +	struct clk *pllref_clk; + 
+	void __iomem *base; +	unsigned int lane_mbps; +}; + 
+struct dphy_pll_testdin_map { +	unsigned int max_mbps; + 
u8 testdin; +}; + +/* The table is based on 27MHz DPHY pll 
reference clock. */ +static const struct dphy_pll_testdin_map 
dptdin_map[] = { +	{160, 0x04}, {180, 0x24}, {200, 0x44}, 
{210, 0x06}, +	{240, 0x26}, {250, 0x46}, {270, 0x08}, 
{300, 0x28}, +	{330, 0x48}, {360, 0x2a}, {400, 0x4a}, 
{450, 0x0c}, +	{500, 0x2c}, {550, 0x0e}, {600, 0x2e}, 
{650, 0x10}, +	{700, 0x30}, {750, 0x12}, {800, 0x32}, 
{850, 0x14}, +	{900, 0x34}, {950, 0x54}, {1000, 0x74} +}; 
+ +static inline struct imx_mipi_dsi *enc_to_dsi(struct

[PATCH v7 8/8] drm: bridge: dw-mipi-dsi: fix bad register field offsets

2020-04-21 Thread Adrian Ratiu

According to the DSI Host Registers sections available in the IMX,
STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
are smaller or bigger than what's coded in the driver, leading to
r/w in reserved spaces which might cause undefined behaviours.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +--
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b45a6d19addcc..b6fef4062a0a8 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
 static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
.cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
-   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 2),
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 1),
.cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
.cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
.cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
@@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_cmd_mode_dcs_sw_sr_en =REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
.cfg_cmd_mode_dcs_lw_en =   REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
.cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
-   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
-   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
-   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
+   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
+   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
+   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
.cfg_vid_mode_type =REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
.cfg_vid_mode_low_power =   REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
.cfg_vid_mode_vpg_en =  REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
.cfg_vid_mode_vpg_horiz =   REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
-   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
-   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
-   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
-   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
-   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
-   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
-   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
-   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
+   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
+   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
+   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
+   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
+   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
+   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
+   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
.cfg_phy_txrequestclkhs =   REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
-   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
-   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
+   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
.cfg_phy_lp2hs_time =   REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
.cfg_phy_hs2lp_time =   REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
-   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
-   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
-   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
+   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
+   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
.cfg_phy_clklp2hs_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
.cfg_phy_clkhs2lp_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 
31),
.cfg_phy_testclr =  REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
@@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant

[PATCH v7 7/8] drm: bridge: dw-mipi-dsi: split low power cfg register into fields

2020-04-21 Thread Adrian Ratiu

According to the Host Registers documentation for IMX, STM and RK
the LP cfg register should not be written entirely in one go because
some bits are reserved and should be kept to reset values, for eg.
BIT(15) which is reserved in all versions.

This also cleans up the code by removing the the ugly defines
and making field ranges & values written more explicit.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++
 1 file changed, 33 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f7e71fa5a8c64..b45a6d19addcc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -120,60 +120,6 @@
 #define DSI_TO_CNT_CFG_V1010x40
 #define DSI_PCKHDL_CFG_V1010x18
 
-#define MAX_RD_PKT_SIZE_LP BIT(24)
-#define DCS_LW_TX_LP   BIT(19)
-#define DCS_SR_0P_TX_LPBIT(18)
-#define DCS_SW_1P_TX_LPBIT(17)
-#define DCS_SW_0P_TX_LPBIT(16)
-#define GEN_LW_TX_LP   BIT(14)
-#define GEN_SR_2P_TX_LPBIT(13)
-#define GEN_SR_1P_TX_LPBIT(12)
-#define GEN_SR_0P_TX_LPBIT(11)
-#define GEN_SW_2P_TX_LPBIT(10)
-#define GEN_SW_1P_TX_LPBIT(9)
-#define GEN_SW_0P_TX_LPBIT(8)
-#define TEAR_FX_EN BIT(0)
-
-#define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
-DCS_LW_TX_LP | \
-DCS_SR_0P_TX_LP | \
-DCS_SW_1P_TX_LP | \
-DCS_SW_0P_TX_LP | \
-GEN_LW_TX_LP | \
-GEN_SR_2P_TX_LP | \
-GEN_SR_1P_TX_LP | \
-GEN_SR_0P_TX_LP | \
-GEN_SW_2P_TX_LP | \
-GEN_SW_1P_TX_LP | \
-GEN_SW_0P_TX_LP)
-
-#define EN_TEAR_FX_V101BIT(14)
-#define DCS_LW_TX_LP_V101  BIT(12)
-#define GEN_LW_TX_LP_V101  BIT(11)
-#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
-#define DCS_SW_2P_TX_LP_V101   BIT(9)
-#define DCS_SW_1P_TX_LP_V101   BIT(8)
-#define DCS_SW_0P_TX_LP_V101   BIT(7)
-#define GEN_SR_2P_TX_LP_V101   BIT(6)
-#define GEN_SR_1P_TX_LP_V101   BIT(5)
-#define GEN_SR_0P_TX_LP_V101   BIT(4)
-#define GEN_SW_2P_TX_LP_V101   BIT(3)
-#define GEN_SW_1P_TX_LP_V101   BIT(2)
-#define GEN_SW_0P_TX_LP_V101   BIT(1)
-
-#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
-GEN_LW_TX_LP_V101 | \
-MAX_RD_PKT_SIZE_LP_V101 | \
-DCS_SW_2P_TX_LP_V101 | \
-DCS_SW_1P_TX_LP_V101 | \
-DCS_SW_0P_TX_LP_V101 | \
-GEN_SR_2P_TX_LP_V101 | \
-GEN_SR_1P_TX_LP_V101 | \
-GEN_SR_0P_TX_LP_V101 | \
-GEN_SW_2P_TX_LP_V101 | \
-GEN_SW_1P_TX_LP_V101 | \
-GEN_SW_0P_TX_LP_V101)
-
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -257,7 +203,11 @@ struct dw_mipi_dsi {
struct regmap_field *field_dpi_vsync_active_low;
struct regmap_field *field_dpi_hsync_active_low;
struct regmap_field *field_cmd_mode_ack_rqst_en;
-   struct regmap_field *field_cmd_mode_all_lp_en;
+   struct regmap_field *field_cmd_mode_gen_sw_sr_en;
+   struct regmap_field *field_cmd_mode_dcs_sw_sr_en;
+   struct regmap_field *field_cmd_mode_gen_lw_en;
+   struct regmap_field *field_cmd_mode_dcs_lw_en;
+   struct regmap_field *field_cmd_mode_max_rd_pkt_size;
struct regmap_field *field_cmd_mode_en;
struct regmap_field *field_cmd_pkt_status;
struct regmap_field *field_vid_mode_en;
@@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant {
struct reg_fieldcfg_dpi_hsync_active_low;
struct reg_fieldcfg_cmd_mode_en;
struct reg_fieldcfg_cmd_mode_ack_rqst_en;
-   struct reg_fieldcfg_cmd_mode_all_lp_en;
+   struct reg_fieldcfg_cmd_mode_gen_sw_sr_en;
+   st

[PATCH v7 6/8] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

2020-04-21 Thread Adrian Ratiu

The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.

Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.

The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.

Tested on STM32F769 and STM32MP1.

Cc: linux-st...@st-md-mailman.stormreply.com
Reported-by: Adrian Pop 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d0..7218e405d7e2b 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -402,15 +402,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
-   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
-   clk_disable_unprepare(pclk);
-
-   if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
-   ret = -ENODEV;
-   DRM_ERROR("bad dsi hardware version\n");
-   goto err_dsi_probe;
-   }
-
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
@@ -423,6 +414,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
+   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+   clk_disable_unprepare(pclk);
+
return 0;
 
 err_dsi_probe:
-- 
2.26.0

___
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[PATCH v7 3/8] drm: bridge: synopsis: add dsi v1.01 support

2020-04-21 Thread Adrian Ratiu

The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fixed cfg_phy_status range from [0,0] to [0,2]

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index ed11549326539..f7e71fa5a8c64 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
 #define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
+   .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6

[PATCH v7 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-04-21 Thread Adrian Ratiu

In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.

The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.

Cc: Enric Balletbo Serra 
Suggested-by: Ezequiel Garcia 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v6:
  - Select REGMAP_MMIO in Kconfig (Enric)
  - Drop unnecessary stack variable inits (Enric)
  - Make bridge error ASAP after a bad revision read (Enric)
  - Drop redundant read of hw_version in dphy_timing_config (Enric)

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 211 ++
 2 files changed, 122 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig 
b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 21a1be3ced0f3..080146093b68e 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -39,3 +39,4 @@ config DRM_DW_MIPI_DSI
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
+   select REGMAP_MMIO
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7bd..7803fd6c92d02 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+   u32 hw_version;
 
 #ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,8 +366,8 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,20 +375,20 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct 
dw_mipi_dsi *dsi, u32 hdr_val)
int ret;
u32 val, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -409,18 +409,20 @@ static int dw_m

[PATCH v7 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-21 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

Cc: Fabio Estevam 
Cc: Enric Balletbo Serra 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v6:
  - Replaced custom noop encoder with the simple drm encoder (Enric)
  - Added CONFIG_DRM_IMX6_MIPI_DSI depends on CONFIG_OF (Enric)
  - Dropped imx_mipi_dsi_register() because now it only creates the
  dummy encoder which can easily be done directly in imx_dsi_bind()

Changes since v5:
  - Reword to remove unrelated device tree patch mention (Fabio)
  - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
  - Fix freescale.com -> nxp.com email addresses (Fabio)
  - Also added myself as module author (Fabio)
  - Use DRM_DEV_* macros for consistency, print more error msg

Changes since v4:
  - Split off driver-specific configuration of phy timings due
  to new upstream API.
  - Move regmap infrastructure logic to separate commit (Ezequiel)
  - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
  - Minor warnings and driver name fixes

Changes since v3:
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio)

Changes since v2:
  - Fixed commit tags. (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after
  calling the bridge probe. (Emil)
---
 drivers/gpu/drm/imx/Kconfig|   8 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 391 +
 3 files changed, 400 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfba..0dffc72df7922 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,11 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+   tristate "Freescale i.MX6 DRM MIPI DSI"
+   select DRM_DW_MIPI_DSI
+   depends on DRM_IMX
+   depends on OF
+   help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc8..9a7843c593478 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index 0..f8a0a4fe16e21
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019-2020 Collabora, Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_PHY_IF_CTRL0x5c
+#define PHY_IF_CTRL_RESET  0x0
+
+#define DSI_PHY_TST_CTRL0  0x64
+#define PHY_TESTCLKBIT(1)
+#define PHY_UNTESTCLK  0
+#define PHY_TESTCLRBIT(0)
+#define PHY_UNTESTCLR  0
+
+#define DSI_PHY_TST_CTRL1  0x68
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN   0
+#define PHY_TESTDOUT(n)(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
+
+struct imx_mipi_dsi {
+   struct drm_encoder encoder;
+   struct device *dev;
+   struct regmap *mux_sel;
+   struct dw_mipi_dsi *mipi_dsi;
+   struct clk *pllref_clk;
+
+   void __iomem *base;
+   unsigned int lane_mbps;
+};
+
+struct dphy_pll_testdin_map {
+   unsigned int max_mbps;
+   u8 testdin;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dphy_pll_testdin_map dptdin_map[] = {
+   {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
+   {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
+   {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
+   {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
+

[PATCH v7 2/8] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2020-04-21 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.

The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fix CONFIG_DEBUG_FS build (Adrian)
  - Fix DRM_MODE_FLAG_* test negation (Adrian)
  - Fixed cfg_phy_status range from [0,0] to [0,2]
  - Replace do {} while(0) with GCC extension ({}) (Andrzej)
  - Fixed payload no-op writes on STM devices (Adrian & Arnaud)

Changes since v4:
  - Move regmap infrastructure logic to a separate commit (Ezequiel)
  - Consolidate field infrastructure in this commit (Ezequiel)
  - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)

Changes since v2:
  - Added const declarations to dw_mipi_dsi structs (Emil)
  - Fixed commit tags (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 499 --
 1 file changed, 347 insertions(+), 152 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 7803fd6c92d02..ed11549326539 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -47,7 +48,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +56,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +112,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP

[PATCH v7 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-21 Thread Adrian Ratiu

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring 
Cc: Neil Armstrong 
Cc: Fabio Estevam 
Cc: Laurent Pinchart 
Cc: devicet...@vger.kernel.org
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v6:
  - Added ref to the newly created snps,dw-mipi-dsi.yaml (Laurent)
  - Moved *-cells properties outside patternProperties (Laurent)
  - Removed the panel port documentation (Laurent)
  - Wrapped lines at 80 chars, typo fixes, sort includes (Laurent)

Changes since v5:
  - Fixed missing reg warning (Fabio)
  - Updated dt-schema and fixed warnings (Rob)

Changes since v4:
  - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
  and addressed received binding feedback (Rob)

Changes since v3:
  - Added commit message (Neil)
  - Converted to yaml format (Neil)
  - Minor dt node + driver fixes (Rob)
  - Added small panel example to the host controller binding

Changes since v2:
  - Fixed commit tags (Emil)
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 135 ++
 1 file changed, 135 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index 0..b73e3ae33a852
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+  - Adrian Ratiu 
+
+description: |
+  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+  IP block with a companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+allOf:
+  - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
+
+properties:
+  '#address-cells':
+const: 1
+
+  '#size-cells':
+const: 0
+
+  compatible:
+items:
+  - const: fsl,imx6q-mipi-dsi
+  - const: snps,dw-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module Clock
+  - description: DSI bus clock
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+
+  fsl,gpr:
+description:
+  Phandle to the iomuxc-gpr region containing the multiplexer ctrl 
register.
+$ref: /schemas/types.yaml#/definitions/phandle
+
+  ports:
+type: object
+description: |
+  A node containing DSI input & output port nodes with endpoint
+  definitions as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+  Documentation/devicetree/bindings/graph.txt
+properties:
+  port@0:
+type: object
+description:
+  DSI input port node, connected to the ltdc rgb output port.
+
+  port@1:
+type: object
+description:
+  RGB output port node, connected to a panel or a bridge input port.
+
+additionalProperties: false
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+examples:
+  - |+
+#include 
+#include 
+#include 
+
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@1 {
+reg = <1>;
+dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+panel@0 {
+compatible = "sharp,ls032b3sx01";
+reg = <0>;
+reset-gpios = < 8 GPIO_ACTIVE_LOW>;
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+panel_in: endpoint {
+remote-endpoint = <_out>;
+

[PATCH v7 0/8] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-04-21 Thread Adrian Ratiu

Hello everyone,

v7 addresses the points raised by Enric and Laurent in v6.
Specific details in patch changelogs.

Two new independent patches were derived from this series
and posted for review (now they are dependencies for v7):

Message-ID: 20200421105814.1364900-1-adrian.ra...@collabora.com
Web: 
https://lore.kernel.org/linux-devicetree/20200421105814.1364900-1-adrian.ra...@collabora.com/T/#u

and

Message-ID: 20200420100222.1308898-1-adrian.ra...@collabora.com
Web: 
https://lore.kernel.org/linux-arm-kernel/20200420100222.1308898-1-adrian.ra...@collabora.com/T/#u

Tested on latest linux-next 20200421 with the above two patches
applied.

Thank you,
Adrian

Adrian Ratiu (8):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: synopsis: add dsi v1.01 support
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 135 
 drivers/gpu/drm/bridge/synopsys/Kconfig   |   1 +
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 692 +-
 drivers/gpu/drm/imx/Kconfig   |   8 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 391 ++
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  12 +-
 7 files changed, 1035 insertions(+), 205 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
2.26.0

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[PATCH v2] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-21 Thread Adrian Ratiu

This converts the Synopsis MIPI DSI binding documentation to yaml and
should be quite straightforward. I've added a missing ref clk and also
added Philippe as maintainer b/c he's the original txt author following
the algorithm provided in Message-ID 20200420175909.ga5...@ravnborg.org.

Cc: Rob Herring 
Cc: Philippe CORNU 
Cc: devicet...@vger.kernel.org
Suggested-by: Laurent Pinchart 
Signed-off-by: Adrian Ratiu 
---
Changes in v2:
  - Removed unnecessary descriptions and maxItems (Rob)
  - Changed maintainers entry / dropped Mark (Rob)
  - Added dsi-controller.yaml ref (Rob)
---
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 ---
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 56 +++
 2 files changed, 56 insertions(+), 32 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
deleted file mode 100644
index b13adf30b8d3b..0
--- a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Synopsys DesignWare MIPI DSI host controller
-
-
-This document defines device tree properties for the Synopsys DesignWare MIPI
-DSI host controller. It doesn't constitue a device tree binding specification
-by itself but is meant to be referenced by platform-specific device tree
-bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each optional property is used or not.
-
-- reg: Memory mapped base address and length of the DesignWare MIPI DSI
-  host controller registers. (mandatory)
-
-- clocks: References to all the clocks specified in the clock-names property
-  as specified in [1]. (mandatory)
-
-- clock-names:
-  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
-  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
-
-- resets: References to all the resets specified in the reset-names property
-  as specified in [2]. (optional)
-
-- reset-names: string reset name, must be "apb" if used. (optional)
-
-- panel or bridge node: see [3]. (mandatory)
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/reset/reset.txt
-[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
new file mode 100644
index 0..d9ab464f79ff4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare MIPI DSI host controller
+
+maintainers:
+  - Philippe CORNU 
+
+description: |
+  This document defines device tree properties for the Synopsys DesignWare MIPI
+  DSI host controller. It doesn't constitue a device tree binding specification
+  by itself but is meant to be referenced by platform-specific device tree
+  bindings.
+
+  When referenced from platform device tree bindings the properties defined in
+  this document are defined as follows. The platform device tree bindings are
+  responsible for defining whether each property is required or optional.
+
+allOf:
+  - $ref: ../dsi-controller.yaml#
+
+properties:
+  reg:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module clock
+  - description: DSI bus clock for either AHB and APB
+  - description: Pixel clock for the DPI/RGB input
+minItems: 2
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+  - const: px_clk
+minItems: 2
+
+  resets:
+maxItems: 1
+
+  reset-names:
+const: apb
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+
+required:
+  - reg
+  - clocks
+  - clock-names
-- 
2.26.0

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Rule for bridge yaml dt binding maintainers?

2020-04-20 Thread Adrian Ratiu


Hello,

I got confused while doing the txt -> yaml conversion at [1] and 
it's still not clear to me who should be added in the 
"maintainers" field.  Clearly not the maintainers as returned by 
get_maintainer.pl. :)


Rob mentioned that "owners" should be manintainers but I also have 
trouble picking the persons who should be owners / yaml 
maintainers.


Looking at the completed bridge conversions in the latest 
linux-next, I couldn't find a rule and the majority of bindings 
are still txt: 


$ find ./devicetree/bindings/display/bridge/ -name *txt | wc -l
23
$ find ./devicetree/bindings/display/bridge/ -name *yaml | wc -l
5

So my questions are:
1. Is there a general rule for assigning yaml file 
owners/maintainers?


2. Is this vagueness specific to the bridge dt bindings only?

3. Who should step up and maintain these bindings? Original/new 
authors, SoC, bridge, DRM maintainers etc.?


It would be useful to have a rule to make it easier to do these 
conversions. We (Collabora) are considering doing the conversion 
work.


Thank you,
Adrian

[1] https://patchwork.kernel.org/patch/11493009/
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[PATCH] drm: imx: Unify encoder creation

2020-04-20 Thread Adrian Ratiu

imx drivers don't require drm encoders and they all had empty/no-op
implementations which got converted to simple objects to pacify the
drm core which still requires something to be defined.

The problem now is that each driver duplicates the same encoder
initialization logic and I'm working on adding yet-another driver
(for imx6 mipi-dsi), so instead of copy-pasting the initialization
let's move it from the drivers to a shared function in imx-drm-core.

The imx_drm_encoder_parse_of() logic is made part of the newly added
imx_drm_create_encoder() which was its only caller after the move to
imx-drm-core.

Suggested-by: Laurent Pinchart 
Suggested-by: Enric Balletbo Serra 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/imx/dw_hdmi-imx.c  | 18 ++
 drivers/gpu/drm/imx/imx-drm-core.c | 13 ++---
 drivers/gpu/drm/imx/imx-drm.h  |  2 +-
 drivers/gpu/drm/imx/imx-ldb.c  |  8 
 drivers/gpu/drm/imx/imx-tve.c  |  8 
 drivers/gpu/drm/imx/parallel-display.c | 11 +--
 6 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c 
b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index ba4ca17fd4d8..a710e3d576b4 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -18,7 +18,6 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "imx-drm.h"
 
@@ -218,22 +217,17 @@ static int dw_hdmi_imx_bind(struct device *dev, struct 
device *master,
hdmi->dev = >dev;
encoder = >encoder;
 
-   encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
-   /*
-* If we failed to find the CRTC(s) which this encoder is
-* supposed to be connected to, it's because the CRTC has
-* not been registered yet.  Defer probing, and hope that
-* the required CRTC is added later.
-*/
-   if (encoder->possible_crtcs == 0)
-   return -EPROBE_DEFER;
-
ret = dw_hdmi_imx_parse_dt(hdmi);
if (ret < 0)
return ret;
 
+   ret = imx_drm_create_encoder(drm, encoder, dev->of_node);
+   if (ret) {
+   dev_err(dev, "Failed to create drm encoder\n");
+   return ret;
+   }
+
drm_encoder_helper_add(encoder, _hdmi_imx_encoder_helper_funcs);
-   drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
 
platform_set_drvdata(pdev, hdmi);
 
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c 
b/drivers/gpu/drm/imx/imx-drm-core.c
index 2e38f1a5cf8d..eaf087ed354f 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "imx-drm.h"
@@ -116,11 +117,11 @@ static const struct drm_mode_config_helper_funcs 
imx_drm_mode_config_helpers = {
.atomic_commit_tail = imx_drm_atomic_commit_tail,
 };
 
-
-int imx_drm_encoder_parse_of(struct drm_device *drm,
+int imx_drm_create_encoder(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np)
 {
uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np);
+   int ret;
 
/*
 * If we failed to find the CRTC(s) which this encoder is
@@ -136,9 +137,15 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
/* FIXME: cloning support not clear, disable it all for now */
encoder->possible_clones = 0;
 
+   ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_NONE);
+   if (ret) {
+   DRM_ERROR("Failed to initialize simple drm encoder\n");
+   return ret;
+   }
+
return 0;
 }
-EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
+EXPORT_SYMBOL_GPL(imx_drm_create_encoder);
 
 static const struct drm_ioctl_desc imx_drm_ioctls[] = {
/* none so far */
diff --git a/drivers/gpu/drm/imx/imx-drm.h b/drivers/gpu/drm/imx/imx-drm.h
index c3e1a3f14d30..8573a668a5f5 100644
--- a/drivers/gpu/drm/imx/imx-drm.h
+++ b/drivers/gpu/drm/imx/imx-drm.h
@@ -34,7 +34,7 @@ void imx_drm_mode_config_init(struct drm_device *drm);
 
 struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
 
-int imx_drm_encoder_parse_of(struct drm_device *drm,
+int imx_drm_create_encoder(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np);
 
 void imx_drm_connector_destroy(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index 66ea68e8da87..a37fa325a8c3 100644
--- a/drivers/gpu/drm/imx/imx-ldb.c
+++ b/drivers/gpu/drm/imx/imx-ldb.c
@@ -26,7 +26,6 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "imx-drm.h"
 
@@ -423,9 +422,11 @@ static int imx_ldb_register(struct drm_device *drm,
struct drm_encoder *encoder = _ldb_ch->encoder;
int ret;
 
-   ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
-

Re: [PATCH v6 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-17 Thread Adrian Ratiu


Hi Enric & Laurent,

On Wed, 15 Apr 2020, Laurent Pinchart 
 wrote:
Hi Enric, 

On Wed, Apr 15, 2020 at 07:26:02PM +0200, Enric Balletbo Serra 
wrote: 
Missatge de Adrian Ratiu  del dia 
dt., 14 d’abr. 2020 a les 17:19: 
> 
> This adds support for the Synopsis DesignWare MIPI DSI v1.01 
> host controller which is embedded in i.MX 6 SoCs. 
> 
> Based on following patches, but updated/extended to work with 
> existing support found in the kernel: 
> 
> - drm: imx: Support Synopsys DesignWare MIPI DSI host 
> controller 
>   Signed-off-by: Liu Ying  
> 
> Cc: Fabio Estevam  Reviewed-by: Emil 
> Velikov  Tested-by: Adrian Pop 
>  Tested-by: Arnaud Ferraris 
>  Signed-off-by: Sjoerd Simons 
>  Signed-off-by: Martyn Welch 
>  Signed-off-by: Adrian Ratiu 
>  --- Changes since v5: 
>   - Reword to remove unrelated device tree patch mention 
>   (Fabio) - Move pllref_clk enable/disable to bind/unbind 
>   (Ezequiel) - Fix freescale.com -> nxp.com email addresses 
>   (Fabio) - Also added myself as module author (Fabio) - Use 
>   DRM_DEV_* macros for consistency, print more error msg 
> 
> Changes since v4: 
>   - Split off driver-specific configuration of phy timings 
>   due to new upstream API.  - Move regmap infrastructure 
>   logic to separate commit (Ezequiel) - Move dsi v1.01 layout 
>   addition to a separate commit (Ezequiel) - Minor warnings 
>   and driver name fixes 
> 
> Changes since v3: 
>   - Renamed platform driver to reflect it's i.MX6 
>   only. (Fabio) 
> 
> Changes since v2: 
>   - Fixed commit tags. (Emil) 
> 
> Changes since v1: 
>   - Moved register definitions & regmap initialization into 
>   bridge module. Platform drivers get the regmap via 
>   plat_data after calling the bridge probe. (Emil) 
> --- 
>  drivers/gpu/drm/imx/Kconfig|   7 + 
>  drivers/gpu/drm/imx/Makefile   |   1 + 
>  drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 409 
>  + 3 files changed, 417 insertions(+) 
>  create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
> 
> diff --git a/drivers/gpu/drm/imx/Kconfig 
> b/drivers/gpu/drm/imx/Kconfig index 
> 207bf7409dfb..b49e70e7f0fd 100644 --- 
> a/drivers/gpu/drm/imx/Kconfig +++ 
> b/drivers/gpu/drm/imx/Kconfig @@ -39,3 +39,10 @@ config 
> DRM_IMX_HDMI 
> depends on DRM_IMX help 
>   Choose this if you want to use HDMI on i.MX6. 
> + +config DRM_IMX6_MIPI_DSI +   tristate "Freescale i.MX6 
> DRM MIPI DSI" +   select DRM_DW_MIPI_DSI +   depends 
> on DRM_IMX 
 Should it depend on CONFIG_OF too? I suspect you'll get build 
errors if OF is not selected  
> +   help + Choose this if you want to use MIPI 
> DSI on i.MX6.  diff --git a/drivers/gpu/drm/imx/Makefile 
> b/drivers/gpu/drm/imx/Makefile index 
> 21cdcc2faabc..9a7843c59347 100644 --- 
> a/drivers/gpu/drm/imx/Makefile +++ 
> b/drivers/gpu/drm/imx/Makefile @@ -9,3 +9,4 @@ 
> obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o 
>  obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o 
> 
>  obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o 
> +obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o diff 
> --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
> b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c new file mode 100644 
> index ..6914db8ce8cb --- /dev/null +++ 
> b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c @@ -0,0 +1,409 @@ 
> +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX6 drm 
> driver - MIPI DSI Host Controller + * + * Copyright (C) 
> 2011-2015 Freescale Semiconductor, Inc.  + * Copyright (C) 
> 2019-2020 Collabora, Ltd.  + */ + +#include  
> +#include  +#include  
> +#include  +#include 
>  +#include  +#include 
>  +#include  +#include 
>  +#include  
> +#include  +#include  
> +#include  + +#include "imx-drm.h" + 
> +#define DSI_PWR_UP 0x04 +#define RESET 
> 0 +#define POWERUPBIT(0) + 
> +#define DSI_PHY_IF_CTRL0x5c +#define 
> PHY_IF_CTRL_RESET  0x0 + +#define 
> DSI_PHY_TST_CTRL0  0x64 +#define PHY_TESTCLK 
> BIT(1) +#define PHY_UNTESTCLK  0 +#define 
> PHY_TESTCLRBIT(0) +#define PHY_UNTESTCLR 
> 0 + +#define DSI_PHY_TST_CTRL1  0x68 +#define 
> PHY_TESTEN BIT(16) +#define PHY_UNTESTEN 
> 0 +#define PHY_TESTDOUT(n)(((n) & 
> 0xff) << 8) +#define PHY_TESTDIN(n) (((n) & 
> 0xff) << 0) + +struct imx_mipi_dsi { +   struct 
> drm_encoder encoder; +   struct device *dev; + 
> struct regmap *mux_sel; +   struct dw_mipi_dsi *mipi_dsi; 
> +   struct clk *pllref_clk; + +   void __iomem *base; 
&

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-04-17 Thread Adrian Ratiu

On Thu, 16 Apr 2020, Enric Balletbo Serra  
wrote:
Hi Adrian, 

[snip] 

>> 
>> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi 
>> *dsi) +{ +   regmap_read(dsi->regs, DSI_VERSION, 
>> >hw_version); +   dsi->hw_version &= VERSION; + if 
>> (!dsi->hw_version) +   dev_err(dsi->dev, "Failed 
>> to read DSI hw version register\n"); 
> 
> Is this an error that should be ignored? If you can't get the 
> HW version, probably, there is something wrong with your 
> hardware so, don't you need to return an error? 
> 

After thinking a bit more about it, that error should be a 
warning. 

I added it because in some cases (for eg. if the peripheral 
clock is disabled) the reads can return 0 which is obviously an 
invalid version and the bridge will error in the next step when 
not finding a layout. 

If you'll error anyway, why wait? IIUC at this point the clock 
*must* be enabled, and if not, something is wrong with the 
driver, I don't see any advantage on delay the error. do you 
have a use case where this is called and peripheral clock 
disabled? 

There should be no real use-case (maybe malfunctioning HW), and we 
could error out here to catch driver bugs ASAP, so I'll go this 
route then :)

Thank you, much appreciated!

So I'll make this a warning in v7 and explicitely mention that
reads version == 0 can be caused by a disabled pclk.

-- Enric

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Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-04-16 Thread Adrian Ratiu

On Wed, 15 Apr 2020, Enric Balletbo Serra  
wrote:
Hi Adrian, 

Some few comments/nits below, 

Missatge de Adrian Ratiu  del dia 
dt., 14 d’abr. 2020 a les 17:19: 


In order to support multiple versions of the Synopsis MIPI DSI 
host controller, which have different register layouts but 
almost identical HW protocols, we add a regmap infrastructure 
which can abstract away register accesses for platform drivers 
using the bridge. 

The controller HW revision is detected during bridge probe 
which will be used in future commits to load the relevant 
register layout which the bridge will use transparently to the 
platform drivers. 

Suggested-by: Ezequiel Garcia  
Tested-by: Adrian Pop  Tested-by: 
Arnaud Ferraris  Signed-off-by: 
Adrian Ratiu  --- New in v5.  --- 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 
 ++ 1 file changed, 117 insertions(+), 91 
 deletions(-) 

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
5ef0f154aa7b..6d9e2f21c9cc 100644 --- 
a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7 
@@ 
 #include  #include  
 #include  
+#include  


Should Kconfig select REGMAP for this driver? 

 #include  

 #include  
@@ -227,6 +228,7 @@ struct dw_mipi_dsi { 
struct drm_bridge *panel_bridge; struct device *dev; 
void __iomem *base; 
+   struct regmap *regs; 

struct clk *pclk; 

@@ -235,6 +237,7 @@ struct dw_mipi_dsi { 
u32 lanes; u32 format; unsigned long mode_flags; 
+   u32 hw_version; 

 #ifdef CONFIG_DEBUG_FS 
struct dentry *debugfs; 
@@ -249,6 +252,13 @@ struct dw_mipi_dsi { 
const struct dw_mipi_dsi_plat_data *plat_data; 
 }; 

+static const struct regmap_config dw_mipi_dsi_regmap_cfg = { + 
.reg_bits = 32, +   .val_bits = 32, +   .reg_stride = 
4, +   .name = "dw-mipi-dsi", +}; + 
 /* 
  * Check if either a link to a master or slave is present */ 
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi 
*bridge_to_dsi(struct drm_bridge *bridge) 
return container_of(bridge, struct dw_mipi_dsi, 
bridge); 
 } 

-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, 
u32 val) -{ -   writel(val, dsi->base + reg); -} - -static 
inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ - 
return readl(dsi->base + reg); -} - 
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
   struct mipi_dsi_device 
   *device) 
 { 
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct 
dw_mipi_dsi *dsi, 
if (lpm) 
val |= CMD_MODE_ALL_LP; 

-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); -   dsi_write(dsi, DSI_CMD_MODE_CFG, 
val); +   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); +   regmap_write(dsi->regs, 
DSI_CMD_MODE_CFG, val); 
 } 

 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
 *dsi, u32 hdr_val) { 
int ret; 
-   u32 val, mask; +   u32 val = 0, mask; 



I think that this change is not needed, `val` is an input 
variable that will be overwritten inside the 
regmap_read_poll_timeout.  Initialize here is not needed. 

-   ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, -val, !(val 
& GEN_CMD_FULL), 1000, - 
CMD_PKT_STATUS_TIMEOUT_US); +   ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, !(val & GEN_CMD_FULL), 1000, + 
CMD_PKT_STATUS_TIMEOUT_US); 
if (ret) { 
dev_err(dsi->dev, "failed to get available 
command FIFO\n"); return ret; 
} 

-   dsi_write(dsi, DSI_GEN_HDR, hdr_val); + 
regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); 

mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 
-   ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, -val, (val 
& mask) == mask, -1000, 
CMD_PKT_STATUS_TIMEOUT_US); +   ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, (val & mask) == mask, + 
1000, CMD_PKT_STATUS_TIMEOUT_US); 
if (ret) { 
dev_err(dsi->dev, "failed to write command 
FIFO\n"); return ret; 
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct 
dw_mipi_dsi *dsi, 
const u8 *tx_buf = packet->payload; int len = 
packet->payload_length, pld_data_bytes = sizeof(u32), 
ret; __le32 word; 
-   u32 val; +   u32 val = 0; 



The same here, 'val' is used for the regmap_read_poll_timeout 
and will be overwritten, no need to initialize. 

while (len) { 
if (len < pld_data_bytes) { 
word = 0; memcpy(, tx_buf, len); 
-   dsi_write

Re: [PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-04-16 Thread Adrian Ratiu

On Wed, 15 Apr 2020, Enric Balletbo Serra  
wrote:
Hi Adrian, 

Some few comments/nits below, 



Hi Enric,

Thank you for your review, all your suggested changes will be part 
of v7. I have only one minor comment below.


Missatge de Adrian Ratiu  del dia 
dt., 14 d’abr. 2020 a les 17:19: 


In order to support multiple versions of the Synopsis MIPI DSI 
host controller, which have different register layouts but 
almost identical HW protocols, we add a regmap infrastructure 
which can abstract away register accesses for platform drivers 
using the bridge. 

The controller HW revision is detected during bridge probe 
which will be used in future commits to load the relevant 
register layout which the bridge will use transparently to the 
platform drivers. 

Suggested-by: Ezequiel Garcia  
Tested-by: Adrian Pop  Tested-by: 
Arnaud Ferraris  Signed-off-by: 
Adrian Ratiu  --- New in v5.  --- 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 
 ++ 1 file changed, 117 insertions(+), 91 
 deletions(-) 

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
5ef0f154aa7b..6d9e2f21c9cc 100644 --- 
a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7 
@@ 
 #include  #include  
 #include  
+#include  


Should Kconfig select REGMAP for this driver? 

 #include  

 #include  
@@ -227,6 +228,7 @@ struct dw_mipi_dsi { 
struct drm_bridge *panel_bridge; struct device *dev; 
void __iomem *base; 
+   struct regmap *regs; 

struct clk *pclk; 

@@ -235,6 +237,7 @@ struct dw_mipi_dsi { 
u32 lanes; u32 format; unsigned long mode_flags; 
+   u32 hw_version; 

 #ifdef CONFIG_DEBUG_FS 
struct dentry *debugfs; 
@@ -249,6 +252,13 @@ struct dw_mipi_dsi { 
const struct dw_mipi_dsi_plat_data *plat_data; 
 }; 

+static const struct regmap_config dw_mipi_dsi_regmap_cfg = { + 
.reg_bits = 32, +   .val_bits = 32, +   .reg_stride = 
4, +   .name = "dw-mipi-dsi", +}; + 
 /* 
  * Check if either a link to a master or slave is present */ 
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi 
*bridge_to_dsi(struct drm_bridge *bridge) 
return container_of(bridge, struct dw_mipi_dsi, 
bridge); 
 } 

-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, 
u32 val) -{ -   writel(val, dsi->base + reg); -} - -static 
inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ - 
return readl(dsi->base + reg); -} - 
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
   struct mipi_dsi_device 
   *device) 
 { 
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct 
dw_mipi_dsi *dsi, 
if (lpm) 
val |= CMD_MODE_ALL_LP; 

-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); -   dsi_write(dsi, DSI_CMD_MODE_CFG, 
val); +   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); +   regmap_write(dsi->regs, 
DSI_CMD_MODE_CFG, val); 
 } 

 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
 *dsi, u32 hdr_val) { 
int ret; 
-   u32 val, mask; +   u32 val = 0, mask; 



I think that this change is not needed, `val` is an input 
variable that will be overwritten inside the 
regmap_read_poll_timeout.  Initialize here is not needed. 

-   ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, -val, !(val 
& GEN_CMD_FULL), 1000, - 
CMD_PKT_STATUS_TIMEOUT_US); +   ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, !(val & GEN_CMD_FULL), 1000, + 
CMD_PKT_STATUS_TIMEOUT_US); 
if (ret) { 
dev_err(dsi->dev, "failed to get available 
command FIFO\n"); return ret; 
} 

-   dsi_write(dsi, DSI_GEN_HDR, hdr_val); + 
regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); 

mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 
-   ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, -val, (val 
& mask) == mask, -1000, 
CMD_PKT_STATUS_TIMEOUT_US); +   ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, (val & mask) == mask, + 
1000, CMD_PKT_STATUS_TIMEOUT_US); 
if (ret) { 
dev_err(dsi->dev, "failed to write command 
FIFO\n"); return ret; 
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct 
dw_mipi_dsi *dsi, 
const u8 *tx_buf = packet->payload; int len = 
packet->payload_length, pld_data_bytes = sizeof(u32), 
ret; __le32 word; 
-   u32 val; +   u32 val = 0; 



The same here, 'val' is used for the regmap_read_poll_timeout 
and will be overwritten, no need to initialize. 

while (len) {

Re: [PATCH] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-16 Thread Adrian Ratiu


Hi Rob,

Thank you for the review, I will address all your points in v2, 
however I have a one neclarity below.


On Thu, 16 Apr 2020, Rob Herring  wrote:
On Thu, Apr 16, 2020 at 7:51 AM Adrian Ratiu 
 wrote: 


This converts the Synopsis MIPI DSI binding documentation to 
yaml and should be quite straightforward. I've added a missing 
ref clk and also added Mark and Rob as maintainers based on 
'get_maintainer.pl' results. 

Cc: Rob Herring  Cc: Mark Rutland 
 Cc: devicet...@vger.kernel.org 
Suggested-by: Laurent Pinchart 
 Signed-off-by: Adrian Ratiu 
 --- 
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 - 
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 66 
 +++ 2 files changed, 66 insertions(+), 32 
 deletions(-) delete mode 100644 
 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
 create mode 100644 
 Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 

diff --git 
a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
deleted file mode 100644 index b13adf30b8d3.. --- 
a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
+++ /dev/null @@ -1,32 +0,0 @@ -Synopsys DesignWare MIPI DSI 
host controller - - 
-This document defines device tree properties for the Synopsys 
DesignWare MIPI -DSI host controller. It doesn't constitue a 
device tree binding specification -by itself but is meant to be 
referenced by platform-specific device tree -bindings.  - -When 
referenced from platform device tree bindings the properties 
defined in -this document are defined as follows. The platform 
device tree bindings are -responsible for defining whether each 
optional property is used or not.  - -- reg: Memory mapped base 
address and length of the DesignWare MIPI DSI -  host 
controller registers. (mandatory) - -- clocks: References to 
all the clocks specified in the clock-names property -  as 
specified in [1]. (mandatory) - -- clock-names: -  - "pclk" is 
the peripheral clock for either AHB and APB. (mandatory) -  - 
"px_clk" is the pixel clock for the DPI/RGB input. (optional) - 
-- resets: References to all the resets specified in the 
reset-names property -  as specified in [2]. (optional) - -- 
reset-names: string reset name, must be "apb" if 
used. (optional) - -- panel or bridge node: see 
[3]. (mandatory) - -[1] 
Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] 
Documentation/devicetree/bindings/reset/reset.txt -[3] 
Documentation/devicetree/bindings/display/mipi-dsi-bus.txt diff 
--git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
new file mode 100644 index ..0ab4125eee30 --- 
/dev/null +++ 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
@@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR 
BSD-2-Clause) +%YAML 1.2 +--- +$id: 
http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml# 
+$schema: http://devicetree.org/meta-schemas/core.yaml# + 
+title: Synopsys DesignWare MIPI DSI host controller + 
+maintainers: +  - Rob Herring  


No thanks, I don't know anything about this hardware. It should 
be the owner for this binding, not who applies patches. 



Sorry about that, I just followed what get_maintainer.pl -f 
returned.


I'm not sure I understand the owner vs maintainers difference for 
the "maintainers" entry. How do I find out who is the owner?


Looking at the git log, this file was touched only once when added 
in 88dd1e6f9ad8 ("dt-bindings: display: Add Synopsys DW MIPI DSI 
host controller") by Philippe CORNU .


Is the person who added the file automatically owner?

(cc'd Philippe)

+  - Mark Rutland  


Check current maintainers. Mark is not one anymore. 



Yes, I just noticed he got removed in my latest next-20200416 
tree, thanks.



+
+description: |
+  This document defines device tree properties for the Synopsys DesignWare MIPI
+  DSI host controller. It doesn't constitue a device tree binding specification
+  by itself but is meant to be referenced by platform-specific device tree
+  bindings.
+
+  When referenced from platform device tree bindings the properties defined in
+  this document are defined as follows. The platform device tree bindings are
+  responsible for defining whether each property is required or optional.
+


Need to reference ($ref) dsi-controller.yaml here.


+properties:
+  reg:
+description: |
+  Memory mapped base address and length of the DesignWare MIPI DSI host
+  controller registers.


Drop the description. That's every 'reg'. You need to say how many
regions (maxItems: 1?).


+
+  clocks:
+description: |
+  References to all the clocks specified in the clock-names property as
+  specifie

[PATCH] dt-bindings: display: dw_mipi_dsi.txt: convert to yaml

2020-04-16 Thread Adrian Ratiu

This converts the Synopsis MIPI DSI binding documentation to yaml and
should be quite straightforward. I've added a missing ref clk and also
added Mark and Rob as maintainers based on 'get_maintainer.pl' results.

Cc: Rob Herring 
Cc: Mark Rutland 
Cc: devicet...@vger.kernel.org
Suggested-by: Laurent Pinchart 
Signed-off-by: Adrian Ratiu 
---
 .../bindings/display/bridge/dw_mipi_dsi.txt   | 32 -
 .../display/bridge/snps,dw-mipi-dsi.yaml  | 66 +++
 2 files changed, 66 insertions(+), 32 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
deleted file mode 100644
index b13adf30b8d3..
--- a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Synopsys DesignWare MIPI DSI host controller
-
-
-This document defines device tree properties for the Synopsys DesignWare MIPI
-DSI host controller. It doesn't constitue a device tree binding specification
-by itself but is meant to be referenced by platform-specific device tree
-bindings.
-
-When referenced from platform device tree bindings the properties defined in
-this document are defined as follows. The platform device tree bindings are
-responsible for defining whether each optional property is used or not.
-
-- reg: Memory mapped base address and length of the DesignWare MIPI DSI
-  host controller registers. (mandatory)
-
-- clocks: References to all the clocks specified in the clock-names property
-  as specified in [1]. (mandatory)
-
-- clock-names:
-  - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
-  - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
-
-- resets: References to all the resets specified in the reset-names property
-  as specified in [2]. (optional)
-
-- reset-names: string reset name, must be "apb" if used. (optional)
-
-- panel or bridge node: see [3]. (mandatory)
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/reset/reset.txt
-[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git 
a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
new file mode 100644
index ..0ab4125eee30
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare MIPI DSI host controller
+
+maintainers:
+  - Rob Herring 
+  - Mark Rutland 
+
+description: |
+  This document defines device tree properties for the Synopsys DesignWare MIPI
+  DSI host controller. It doesn't constitue a device tree binding specification
+  by itself but is meant to be referenced by platform-specific device tree
+  bindings.
+
+  When referenced from platform device tree bindings the properties defined in
+  this document are defined as follows. The platform device tree bindings are
+  responsible for defining whether each property is required or optional.
+
+properties:
+  reg:
+description: |
+  Memory mapped base address and length of the DesignWare MIPI DSI host
+  controller registers.
+
+  clocks:
+description: |
+  References to all the clocks specified in the clock-names property as
+  specified in Documentation/devicetree/bindings/clock/clock-bindings.txt
+items:
+  - description: Module clock
+  - description: DSI bus colck for either AHB and APB
+  - description: Pixel clock for the DPI/RGB input
+minItems: 2
+maxItems: 3
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+  - const: px_clk
+minItems: 2
+maxItems: 3
+
+  resets:
+description: |
+  References to all the resets specified in the reset-names property as
+  specified in Documentation/devicetree/bindings/reset/reset.txt
+
+  reset-names:
+const: apb
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+description: |
+  A node containing the panel or bridge description as documented in
+  Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+required:
+  - reg
+  - clocks
+  - clock-names
-- 
2.26.0

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Re: [PATCH v6 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-15 Thread Adrian Ratiu

On Tue, 14 Apr 2020, Laurent Pinchart 
 wrote:
Hi Adrian, 

Thank you for the patch. 


Hi Laurent,

Thank you for the review - you raised some good points which will 
be addressed in the next revision (will leave this on review a bit 
more).


I will also convert the dw_mipi_dsi.txt to yaml as you suggest and 
send that as a separate patch.


Best wishes,
Adrian



On Tue, Apr 14, 2020 at 06:19:52PM +0300, Adrian Ratiu wrote: 
This provides an example DT binding for the MIPI DSI host 
controller present on the i.MX6 SoC based on Synopsis 
DesignWare v1.01 IP.   Cc: Rob Herring  Cc: 
Neil Armstrong  Cc: Fabio Estevam 
 Cc: devicet...@vger.kernel.org Tested-by: 
Adrian Pop  Tested-by: Arnaud Ferraris 
 Signed-off-by: Sjoerd Simons 
 Signed-off-by: Martyn Welch 
 Signed-off-by: Adrian Ratiu 
 --- Changes since v5: 
  - Fixed missing reg warning (Fabio) - Updated dt-schema and 
  fixed warnings (Rob) 
 Changes since v4: 
  - Fixed yaml binding to pass `make dt_binding_check 
  dtbs_check` and addressed received binding feedback (Rob) 
 Changes since v3: 
  - Added commit message (Neil) - Converted to yaml format 
  (Neil) - Minor dt node + driver fixes (Rob) - Added small 
  panel example to the host controller binding 
 Changes since v2: 
  - Fixed commit tags (Emil) 
--- 
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 139 
 ++ 1 file changed, 139 insertions(+) create 
 mode 100644 
 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
 diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
new file mode 100644 index ..10e289ea219a --- 
/dev/null +++ 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
@@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR 
BSD-2-Clause) +%YAML 1.2 +--- +$id: 
http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml# 
+$schema: http://devicetree.org/meta-schemas/core.yaml# + 
+title: Freescale i.MX6 DW MIPI DSI Host Controller + 
+maintainers: +  - Adrian Ratiu  + 
+description: | +  The i.MX6 DSI host controller is a Synopsys 
DesignWare MIPI DSI v1.01 +  IP block with a companion PHY IP. 
+ +  These DT bindings follow the Synopsys DW MIPI DSI bindings 
defined in + 
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt 
with +  the following device-specific properties. 


Not necessarily a prerequisite for this patch, but it would be 
nice to get that converted to yaml, and included here with 

allOf: 
  $ref: ../bridge/snps,dw-mipi-dsi.yaml# 

(assuming that's how the file will be called). 



Yes, I will do this conversion but in a separate patch to avoid 
making this series bigger.


Thanks,
Adrian


+
+properties:
+  compatible:
+items:
+  - const: fsl,imx6q-mipi-dsi
+  - const: snps,dw-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module Clock
+  - description: DSI bus clock
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+
+  fsl,gpr:
+description: Phandle to the iomuxc-gpr region containing the multiplexer 
control register.


Could you please wrap liens at a 80 columns boundary ?


+$ref: /schemas/types.yaml#/definitions/phandle
+
+  ports:
+type: object
+description: |
+  A node containing DSI input & output port nodes with endpoint
+  definitions as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+  Documentation/devicetree/bindings/graph.txt
+properties:


You should add

   '#address-cells':
 const: 1

   '#size-cells':
 const: 0


+  port@0:
+type: object
+description:
+  DSI input port node, connected to the ltdc rgb output port.
+
+  port@1:
+type: object
+description:
+  DSI output port node, connected to a panel or a bridge input port"



Should this be "RGB output port node" ? And s/"/./

And here you should add

   additionalProperties: false


+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+description: |
+  A node containing the panel or bridge description as documented in
+  Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+properties:
+  port:
+type: object
+description:
+  Panel or bridge port node, connected to the DSI output port (port@1)


Does this belong here ? I think the port property for the panel needs to
be described in the panel's binding instead.


+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0


These two properties are not pattern properties, right ? Should they be
listed under the properties above ?


+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+

[PATCH v6 3/8] drm: bridge: synopsis: add dsi v1.01 support

2020-04-14 Thread Adrian Ratiu

The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fixed cfg_phy_status range from [0,0] to [0,2]

New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index f72643e25669..0ce2697d17a3 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
 #define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
+   .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6

[PATCH v6 6/8] drm: stm: dw-mipi-dsi: let the bridge handle the HW version check

2020-04-14 Thread Adrian Ratiu

The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.

Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.

The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.

Tested on STM32F769 and STM32MP1.

Cc: linux-st...@st-md-mailman.stormreply.com
Reported-by: Adrian Pop 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d..7218e405d7e2 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -402,15 +402,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
-   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
-   clk_disable_unprepare(pclk);
-
-   if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
-   ret = -ENODEV;
-   DRM_ERROR("bad dsi hardware version\n");
-   goto err_dsi_probe;
-   }
-
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
 
@@ -423,6 +414,9 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
goto err_dsi_probe;
}
 
+   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+   clk_disable_unprepare(pclk);
+
return 0;
 
 err_dsi_probe:
-- 
2.26.0

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[PATCH v6 4/8] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-04-14 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

Cc: Fabio Estevam 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Reword to remove unrelated device tree patch mention (Fabio)
  - Move pllref_clk enable/disable to bind/unbind (Ezequiel)
  - Fix freescale.com -> nxp.com email addresses (Fabio)
  - Also added myself as module author (Fabio)
  - Use DRM_DEV_* macros for consistency, print more error msg

Changes since v4:
  - Split off driver-specific configuration of phy timings due
  to new upstream API.
  - Move regmap infrastructure logic to separate commit (Ezequiel)
  - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
  - Minor warnings and driver name fixes

Changes since v3:
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio)

Changes since v2:
  - Fixed commit tags. (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after
  calling the bridge probe. (Emil)
---
 drivers/gpu/drm/imx/Kconfig|   7 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 409 +
 3 files changed, 417 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..b49e70e7f0fd 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,10 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+   tristate "Freescale i.MX6 DRM MIPI DSI"
+   select DRM_DW_MIPI_DSI
+   depends on DRM_IMX
+   help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..9a7843c59347 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index ..6914db8ce8cb
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019-2020 Collabora, Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_PHY_IF_CTRL0x5c
+#define PHY_IF_CTRL_RESET  0x0
+
+#define DSI_PHY_TST_CTRL0  0x64
+#define PHY_TESTCLKBIT(1)
+#define PHY_UNTESTCLK  0
+#define PHY_TESTCLRBIT(0)
+#define PHY_UNTESTCLR  0
+
+#define DSI_PHY_TST_CTRL1  0x68
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN   0
+#define PHY_TESTDOUT(n)(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
+
+struct imx_mipi_dsi {
+   struct drm_encoder encoder;
+   struct device *dev;
+   struct regmap *mux_sel;
+   struct dw_mipi_dsi *mipi_dsi;
+   struct clk *pllref_clk;
+
+   void __iomem *base;
+   unsigned int lane_mbps;
+};
+
+struct dphy_pll_testdin_map {
+   unsigned int max_mbps;
+   u8 testdin;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dphy_pll_testdin_map dptdin_map[] = {
+   {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
+   {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
+   {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
+   {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
+   {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14},
+   {900, 0x34}, {950, 0x54}, {1000, 0x74}
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+   return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+

[PATCH v6 7/8] drm: bridge: dw-mipi-dsi: split low power cfg register into fields

2020-04-14 Thread Adrian Ratiu

According to the Host Registers documentation for IMX, STM and RK
the LP cfg register should not be written entirely in one go because
some bits are reserved and should be kept to reset values, for eg.
BIT(15) which is reserved in all versions.

This also cleans up the code by removing the the ugly defines
and making field ranges & values written more explicit.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++
 1 file changed, 33 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 0ce2697d17a3..cbbe31c0dbac 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -120,60 +120,6 @@
 #define DSI_TO_CNT_CFG_V1010x40
 #define DSI_PCKHDL_CFG_V1010x18
 
-#define MAX_RD_PKT_SIZE_LP BIT(24)
-#define DCS_LW_TX_LP   BIT(19)
-#define DCS_SR_0P_TX_LPBIT(18)
-#define DCS_SW_1P_TX_LPBIT(17)
-#define DCS_SW_0P_TX_LPBIT(16)
-#define GEN_LW_TX_LP   BIT(14)
-#define GEN_SR_2P_TX_LPBIT(13)
-#define GEN_SR_1P_TX_LPBIT(12)
-#define GEN_SR_0P_TX_LPBIT(11)
-#define GEN_SW_2P_TX_LPBIT(10)
-#define GEN_SW_1P_TX_LPBIT(9)
-#define GEN_SW_0P_TX_LPBIT(8)
-#define TEAR_FX_EN BIT(0)
-
-#define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
-DCS_LW_TX_LP | \
-DCS_SR_0P_TX_LP | \
-DCS_SW_1P_TX_LP | \
-DCS_SW_0P_TX_LP | \
-GEN_LW_TX_LP | \
-GEN_SR_2P_TX_LP | \
-GEN_SR_1P_TX_LP | \
-GEN_SR_0P_TX_LP | \
-GEN_SW_2P_TX_LP | \
-GEN_SW_1P_TX_LP | \
-GEN_SW_0P_TX_LP)
-
-#define EN_TEAR_FX_V101BIT(14)
-#define DCS_LW_TX_LP_V101  BIT(12)
-#define GEN_LW_TX_LP_V101  BIT(11)
-#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
-#define DCS_SW_2P_TX_LP_V101   BIT(9)
-#define DCS_SW_1P_TX_LP_V101   BIT(8)
-#define DCS_SW_0P_TX_LP_V101   BIT(7)
-#define GEN_SR_2P_TX_LP_V101   BIT(6)
-#define GEN_SR_1P_TX_LP_V101   BIT(5)
-#define GEN_SR_0P_TX_LP_V101   BIT(4)
-#define GEN_SW_2P_TX_LP_V101   BIT(3)
-#define GEN_SW_1P_TX_LP_V101   BIT(2)
-#define GEN_SW_0P_TX_LP_V101   BIT(1)
-
-#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
-GEN_LW_TX_LP_V101 | \
-MAX_RD_PKT_SIZE_LP_V101 | \
-DCS_SW_2P_TX_LP_V101 | \
-DCS_SW_1P_TX_LP_V101 | \
-DCS_SW_0P_TX_LP_V101 | \
-GEN_SR_2P_TX_LP_V101 | \
-GEN_SR_1P_TX_LP_V101 | \
-GEN_SR_0P_TX_LP_V101 | \
-GEN_SW_2P_TX_LP_V101 | \
-GEN_SW_1P_TX_LP_V101 | \
-GEN_SW_0P_TX_LP_V101)
-
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -257,7 +203,11 @@ struct dw_mipi_dsi {
struct regmap_field *field_dpi_vsync_active_low;
struct regmap_field *field_dpi_hsync_active_low;
struct regmap_field *field_cmd_mode_ack_rqst_en;
-   struct regmap_field *field_cmd_mode_all_lp_en;
+   struct regmap_field *field_cmd_mode_gen_sw_sr_en;
+   struct regmap_field *field_cmd_mode_dcs_sw_sr_en;
+   struct regmap_field *field_cmd_mode_gen_lw_en;
+   struct regmap_field *field_cmd_mode_dcs_lw_en;
+   struct regmap_field *field_cmd_mode_max_rd_pkt_size;
struct regmap_field *field_cmd_mode_en;
struct regmap_field *field_cmd_pkt_status;
struct regmap_field *field_vid_mode_en;
@@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant {
struct reg_fieldcfg_dpi_hsync_active_low;
struct reg_fieldcfg_cmd_mode_en;
struct reg_fieldcfg_cmd_mode_ack_rqst_en;
-   struct reg_fieldcfg_cmd_mode_all_lp_en;
+   struct reg_fieldcfg_cmd_mode_gen_sw_sr_en;
+   st

[PATCH v6 0/8] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-04-14 Thread Adrian Ratiu

Hello everyone,

Many thanks to all who have contributed to this new iteration,
especially to Arnaud Ferraris for his stm32mp1 testing and to
Adrian Pop for his stm32f7 testing & debugging help.

Further testing, especially on Rockchip devices, is very much
appreciated.

All reported issues have been addressed and this series should
apply cleanly on latest next-20200414 tree.

Tested on imx6dl, stm32mp1 and stm32f7.

Best wishes,
Adrian

Adrian Ratiu (8):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: synopsis: add dsi v1.01 support
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc
  drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
  drm: bridge: dw-mipi-dsi: split low power cfg register into fields
  drm: bridge: dw-mipi-dsi: fix bad register field offsets

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 139 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 691 +-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 409 +++
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  12 +-
 6 files changed, 1050 insertions(+), 209 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
2.26.0

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[PATCH v6 8/8] drm: bridge: dw-mipi-dsi: fix bad register field offsets

2020-04-14 Thread Adrian Ratiu

According to the DSI Host Registers sections available in the IMX,
STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
are smaller or bigger than what's coded in the driver, leading to
r/w in reserved spaces which might cause undefined behaviours.

Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v6.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +--
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index cbbe31c0dbac..7f6e3d1e2ad2 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
 static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
.cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
-   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 2),
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 1),
.cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
.cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
.cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
@@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_cmd_mode_dcs_sw_sr_en =REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
.cfg_cmd_mode_dcs_lw_en =   REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
.cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
-   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
-   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
-   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
+   .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
+   .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
+   .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
.cfg_vid_mode_type =REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
.cfg_vid_mode_low_power =   REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
.cfg_vid_mode_vpg_en =  REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
.cfg_vid_mode_vpg_horiz =   REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
-   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
-   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
-   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
-   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
-   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
-   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
-   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
-   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+   .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
+   .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
+   .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
+   .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
+   .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
+   .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
+   .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
+   .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
.cfg_phy_txrequestclkhs =   REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
-   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
-   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+   .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
+   .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
.cfg_phy_lp2hs_time =   REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
.cfg_phy_hs2lp_time =   REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
-   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
-   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
-   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+   .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
+   .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
+   .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
.cfg_phy_clklp2hs_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
.cfg_phy_clkhs2lp_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 
31),
.cfg_phy_testclr =  REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
@@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant

[PATCH v6 1/8] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-04-14 Thread Adrian Ratiu

In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.

The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.

Suggested-by: Ezequiel Garcia 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++
 1 file changed, 117 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7b..6d9e2f21c9cc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+   u32 hw_version;
 
 #ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi 
*dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
int ret;
-   u32 val, mask;
+   u32 val = 0, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
const u8 *tx_buf = packet->payload;
int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
__le32 word;
-   u32 val;
+   u32 val = 0;
 
while (len) {
if (len < pld_data_bytes) {
word = 0;
memcpy(, tx_buf, len);
-   dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+   regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+le32_to_cpu(word));
len = 0;
} else {
memcpy(, tx_buf, pld_data_bytes);
-   dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+   regm

[PATCH v6 5/8] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-04-14 Thread Adrian Ratiu

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring 
Cc: Neil Armstrong 
Cc: Fabio Estevam 
Cc: devicet...@vger.kernel.org
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fixed missing reg warning (Fabio)
  - Updated dt-schema and fixed warnings (Rob)

Changes since v4:
  - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
  and addressed received binding feedback (Rob)

Changes since v3:
  - Added commit message (Neil)
  - Converted to yaml format (Neil)
  - Minor dt node + driver fixes (Rob)
  - Added small panel example to the host controller binding

Changes since v2:
  - Fixed commit tags (Emil)
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 139 ++
 1 file changed, 139 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index ..10e289ea219a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+  - Adrian Ratiu 
+
+description: |
+  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+  IP block with a companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+properties:
+  compatible:
+items:
+  - const: fsl,imx6q-mipi-dsi
+  - const: snps,dw-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module Clock
+  - description: DSI bus clock
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+
+  fsl,gpr:
+description: Phandle to the iomuxc-gpr region containing the multiplexer 
control register.
+$ref: /schemas/types.yaml#/definitions/phandle
+
+  ports:
+type: object
+description: |
+  A node containing DSI input & output port nodes with endpoint
+  definitions as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+  Documentation/devicetree/bindings/graph.txt
+properties:
+  port@0:
+type: object
+description:
+  DSI input port node, connected to the ltdc rgb output port.
+
+  port@1:
+type: object
+description:
+  DSI output port node, connected to a panel or a bridge input port"
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+description: |
+  A node containing the panel or bridge description as documented in
+  Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+properties:
+  port:
+type: object
+description:
+  Panel or bridge port node, connected to the DSI output port (port@1)
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |+
+#include 
+#include 
+#include 
+
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@1 {
+reg = <1>;
+dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+panel@0 {
+compatible = "sharp,ls032b3sx01";
+reg = <0>;
+reset-gpios = < 8 GPIO_ACTIVE_LOW>;
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+reg = <0>;
+panel_in: endpoint {
+remote-endpoint = <_out>;
+};
+

[PATCH v6 2/8] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2020-04-14 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.

The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Tested-by: Adrian Pop 
Tested-by: Arnaud Ferraris 
Signed-off-by: Adrian Ratiu 
---
Changes since v5:
  - Fix CONFIG_DEBUG_FS build (Adrian)
  - Fix DRM_MODE_FLAG_* test negation (Adrian)
  - Fixed cfg_phy_status range from [0,0] to [0,2]
  - Replace do {} while(0) with GCC extension ({}) (Andrzej)
  - Fixed payload no-op writes on STM devices (Adrian & Arnaud)

Changes since v4:
  - Move regmap infrastructure logic to a separate commit (Ezequiel)
  - Consolidate field infrastructure in this commit (Ezequiel)
  - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)

Changes since v2:
  - Added const declarations to dw_mipi_dsi structs (Emil)
  - Fixed commit tags (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 503 --
 1 file changed, 347 insertions(+), 156 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6d9e2f21c9cc..f72643e25669 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -47,7 +48,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +56,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +112,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP

Re: [PATCH v5 2/5] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2020-04-10 Thread Adrian Ratiu


Hi Andrzej,

Thank you for the feedback, I really appreciate it, replies are 
below.


On Mon, 06 Apr 2020, Andrzej Hajda  wrote:
W dniu 30.03.2020 o 13:35, Adrian Ratiu pisze: 
Register existence, address/offsets, field layouts, reserved 
bits and so on differ between MIPI-DSI versions and between SoC 
vendor boards.  Despite these differences the hw IP and 
protocols are mostly the same so the generic bridge can be made 
to compensate these differences. 

The current Rockchip and STM drivers hardcoded a lot of their 
common definitions in the bridge code because they're based on 
DSI v1.30 and 1.31 which are relatively close, but in order to 
support older/future versions with more diverging layouts like 
the v1.01 present on imx6, we abstract some of the register 
accesses via the regmap field APIs. 

The bridge detects the DSI core version and initializes the 
required regmap register layout. Other DSI versions / register 
layouts can easily be added in the future by only changing the 
bridge code. 

The platform drivers don't require any changes, DSI register 
layout versioning will be handled transparently by the bridge, 
but if in the future the regmap or layouts needs to be exposed 
to the drivres, it could easily be done via plat_data or a new 
API in dw_mipi_dsi.h. 

Suggested-by: Boris Brezillon  
Reviewed-by: Emil Velikov  
Signed-off-by: Adrian Ratiu  --- 
Changes since v4: 
   - Move regmap infrastructure logic to a separate commit 
   (Ezequiel) - Consolidate field infrastructure in this commit 
   (Ezequiel) - Move the dsi v1.01 layout logic to a separate 
   commit (Ezequiel) 

Changes since v2: 
   - Added const declarations to dw_mipi_dsi structs (Emil) - 
   Fixed commit tags (Emil) 

Changes since v1: 
   - Moved register definitions & regmap initialization into 
   bridge module. Platform drivers get the regmap via plat_data 
   after calling the bridge probe (Emil). 
--- 
  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 510 
  -- 1 file changed, 352 insertions(+), 158 
  deletions(-) 

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
6d9e2f21c9cc..5b78ff925af0 100644 --- 
a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -31,6 +31,7 
@@ 
  #include   #define HWVER_131 
  0x31333100	/* IP version 1.31 */ 
+#define HWVER_130			0x31333000	/* IP 
version 1.30 */ 
   #define DSI_VERSION			0x00 #define 
  VERSIONGENMASK(31, 8) 
@@ -47,7 +48,6 @@ 
  #define DPI_VCID(vcid)			((vcid) & 0x3) 
  #define DSI_DPI_COLOR_CODING		0x10 
-#define LOOSELY18_EN			BIT(8) 
  #define DPI_COLOR_CODING_16BIT_1	0x0 #define 
  DPI_COLOR_CODING_16BIT_2	0x1 #define 
  DPI_COLOR_CODING_16BIT_3	0x2 
@@ -56,11 +56,6 @@ 
  #define DPI_COLOR_CODING_24BIT		0x5  #define 
  DSI_DPI_CFG_POL			0x14 
-#define COLORM_ACTIVE_LOW		BIT(4) -#define 
SHUTD_ACTIVE_LOW		BIT(3) -#define HSYNC_ACTIVE_LOW 
BIT(2) -#define VSYNC_ACTIVE_LOW		BIT(1) -#define 
DATAEN_ACTIVE_LOW		BIT(0) 
   #define DSI_DPI_LP_CMD_TIM		0x18 #define 
  OUTVACT_LPCMD_TIME(p)		(((p) & 0xff) << 16) 
@@ -81,27 +76,19 @@ 
  #define DSI_GEN_VCID			0x30  #define 
  DSI_MODE_CFG			0x34 
-#define ENABLE_VIDEO_MODE		0 -#define ENABLE_CMD_MODE 
BIT(0) 
   #define DSI_VID_MODE_CFG		0x38 
-#define ENABLE_LOW_POWER		(0x3f << 8) -#define 
ENABLE_LOW_POWER_MASK		(0x3f << 8) +#define 
ENABLE_LOW_POWER		0x3f + 
  #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES	0x0 
  #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1 
  #define VID_MODE_TYPE_BURST			0x2 
-#define VID_MODE_TYPE_MASK			0x3 -#define 
VID_MODE_VPG_ENABLE		BIT(16) -#define 
VID_MODE_VPG_HORIZONTAL		BIT(24) 
   #define DSI_VID_PKT_SIZE		0x3c 
-#define VID_PKT_SIZE(p)			((p) & 0x3fff) 
   #define DSI_VID_NUM_CHUNKS		0x40 
-#define VID_NUM_CHUNKS(c)		((c) & 0x1fff) 
   #define DSI_VID_NULL_SIZE		0x44 
-#define VID_NULL_SIZE(b)		((b) & 0x1fff) 
   #define DSI_VID_HSA_TIME		0x48 #define 
  DSI_VID_HBP_TIME		0x4c 
@@ -125,7 +112,6 @@ 
  #define GEN_SW_2P_TX_LP			BIT(10) #define 
  GEN_SW_1P_TX_LP			BIT(9) #define 
  GEN_SW_0P_TX_LP			BIT(8) 
-#define ACK_RQST_EN			BIT(1) 
  #define TEAR_FX_EN			BIT(0)  #define 
  CMD_MODE_ALL_LP			(MAX_RD_PKT_SIZE_LP | \ 
@@ -154,8 +140,6 @@ 
  #define GEN_CMD_EMPTY			BIT(0)  #define 
  DSI_TO_CNT_CFG			0x78 
-#define HSTX_TO_CNT(p)			(((p) & 0x) << 
16) -#define LPRX_TO_CNT(p)			((p) & 0x) 
   #define DSI_HS_RD_TO_CNT		0x7c #define 
  DSI_LP_RD_TO_CNT		0x80 
@@ -164,52 +148,17 @@ 
  #define DSI_BTA_TO_CNT			0x8c  #define 
  DSI_LPCLK_CTRL			0x94 
-#define AUTO_CLKLANE_CTRL		BIT(1) -#define 
PHY_TXREQUESTCLKHS		BIT(0) - 
  #define DSI_PHY_TMR_LPCLK_CFG		0x98 
-#define PHY_CLKHS2LP_TIME(lbcc)		(((lbcc) & 0x3ff) 
<< 16) -#define PHY_CLKLP2HS_TIME(lbcc)		((lbcc) & 
0x3ff) - 
  #define DSI_PHY_TMR_CFG			0x9c 
-#define PHY_HS2LP_TIME(lbcc)		(((lbcc) & 0xff) 
<< 24) -

Re: [PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-03-31 Thread Adrian Ratiu

On Tue, 31 Mar 2020, Ezequiel Garcia  
wrote:
On Tue, 2020-03-31 at 00:31 +0300, Adrian Ratiu wrote: 
On Mon, 30 Mar 2020, Ezequiel Garcia  
wrote: 
> Hello Fabio, Adrian:   On Mon, 2020-03-30 at 08:49 -0300, 
> Fabio Estevam wrote:  
> > Hi Adrian,  On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu 
> >  wrote:  
> > > This adds support for the Synopsis DesignWare MIPI DSI 
> > > v1.01  host controller which is embedded in i.MX 6 SoCs. 
> > > Based on  following patches, but updated/extended to work 
> > > with existing  support found in the kernel:  - drm: imx: 
> > > Support Synopsys  DesignWare MIPI DSI host controller  
> > >   Signed-off-by: Liu Ying   
> > >  - ARM: dtsi: imx6qdl: Add support for MIPI DSI host  
> > > controller  
> > >   Signed-off-by: Liu Ying   
> >  This one looks like a devicetree patch, but this patch 
> >  does  
> > not touch devicetree.   
> > > +   ret = clk_prepare_enable(dsi->pllref_clk); + 
> > > if  (ret) { +   dev_err(dev, "%s: Failed to 
> > > enable  pllref_clk\n", __func__); +   return 
> > > ret; +  } + +   dsi->mux_sel = 
> > > syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); 
> > > +  if (IS_ERR(dsi->mux_sel)) { +   ret = 
> > > PTR_ERR(dsi->mux_sel); +   dev_err(dev, "%s: 
> > > Failed to get GPR regmap: %d\n", +  __func__, ret); + 
> > > return ret;  
> >  You should disable the dsi->pllref_clk clock prior to  
> > returning the error.   
>  Another approach could be moving the clock on and off to to 
> component_ops.{bind,unbind} (as rockhip driver does).What 
> exactly is the PLL clock needed for? Would it make sense to 
> move it some of the PHY power on/off? (Maybe not, but it's 
> worthing checking).Also, it seems the other IP blocks 
> have this PLL clock, so maybe  it could be moved to the 
> dw_mipi_dsi core? This could be  something for a follow-up, 
> to avoid creeping this series. 
 Hi Ezequiel,  pll is the video reference clock which drives 
the data lanes and  yes all drivers have it as it's a basic 
requirement, so moving it  to the common bridge is indeed a 
good idea, however this kind of  driver refactoring is out of 
scope for this specific patch series,  because, for now, I'd 
like to get the regmap and the imx6 driver  in, once that is 
done we can think how to further abstract away  common logic 
and slim down the existing drivers further.   Basically I just 
want to avoid feature creep as I expect v6 to be  ~ 8 patches 
big and the series is already over 1200 lines.  


Oh, absolutely: if there's one thing I try to avoid is feature 
creep -- together with bikeshedding! 

Do note however, that you could move the PLL clock handling to 
component_ops.{bind,unbind} and maybe simplify the error 
handling. 


(BTW, great work!)


Thanks! I'll do the bind/unbind move for the new imx6 driver which 
I'm
adding in this series to make it resemble the existing rockchip 
driver a bit more, then I'll stop short of further driver 
refactorings.




Cheers,
Ezequiel

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Re: [PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-03-30 Thread Adrian Ratiu

On Mon, 30 Mar 2020, Ezequiel Garcia  
wrote:
Hello Fabio, Adrian: 

On Mon, 2020-03-30 at 08:49 -0300, Fabio Estevam wrote: 
Hi Adrian,  On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu 
 wrote: 
> This adds support for the Synopsis DesignWare MIPI DSI v1.01 
> host controller which is embedded in i.MX 6 SoCs.   Based on 
> following patches, but updated/extended to work with existing 
> support found in the kernel:  - drm: imx: Support Synopsys 
> DesignWare MIPI DSI host controller 
>   Signed-off-by: Liu Ying  
>  - ARM: dtsi: imx6qdl: Add support for MIPI DSI host 
> controller 
>   Signed-off-by: Liu Ying  
 This one looks like a devicetree patch, but this patch does 
not touch devicetree.  
> +   ret = clk_prepare_enable(dsi->pllref_clk); +   if 
> (ret) { +   dev_err(dev, "%s: Failed to enable 
> pllref_clk\n", __func__); +   return ret; + 
> } + +   dsi->mux_sel = 
> syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); + 
> if (IS_ERR(dsi->mux_sel)) { +   ret = 
> PTR_ERR(dsi->mux_sel); +   dev_err(dev, "%s: 
> Failed to get GPR regmap: %d\n", + 
> __func__, ret); +   return ret; 
 You should disable the dsi->pllref_clk clock prior to 
returning the error.  

Another approach could be moving the clock on and off to to 
component_ops.{bind,unbind} (as rockhip driver does). 

What exactly is the PLL clock needed for? Would it make sense to 
move it some of the PHY power on/off? (Maybe not, but it's 
worthing checking). 

Also, it seems the other IP blocks have this PLL clock, so maybe 
it could be moved to the dw_mipi_dsi core? This could be 
something for a follow-up, to avoid creeping this series.

Hi Ezequiel,

pll is the video reference clock which drives the data lanes and 
yes all drivers have it as it's a basic requirement, so moving it 
to the common bridge is indeed a good idea, however this kind of 
driver refactoring is out of scope for this specific patch series, 
because, for now, I'd like to get the regmap and the imx6 driver 
in, once that is done we can think how to further abstract away 
common logic and slim down the existing drivers further.

Basically I just want to avoid feature creep as I expect v6 to be 
~ 8 patches big and the series is already over 1200 lines.

Thank you,
Adrian

Thanks,
Ezequiel

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Re: [PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-03-30 Thread Adrian Ratiu


On Mon, 30 Mar 2020, Fabio Estevam  wrote:
Hi Adrian, 

On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu 
 wrote: 


This adds support for the Synopsis DesignWare MIPI DSI v1.01 
host controller which is embedded in i.MX 6 SoCs. 

Based on following patches, but updated/extended to work with 
existing support found in the kernel: 

- drm: imx: Support Synopsys DesignWare MIPI DSI host 
controller 
  Signed-off-by: Liu Ying  

- ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller 
  Signed-off-by: Liu Ying  


This one looks like a devicetree patch, but this patch does not 
touch devicetree. 

+   ret = clk_prepare_enable(dsi->pllref_clk); +   if 
(ret) { +   dev_err(dev, "%s: Failed to enable 
pllref_clk\n", __func__); +   return ret; +   } 
+ +   dsi->mux_sel = 
syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); + 
if (IS_ERR(dsi->mux_sel)) { +   ret = 
PTR_ERR(dsi->mux_sel); +   dev_err(dev, "%s: Failed 
to get GPR regmap: %d\n", +   __func__, 
ret); +   return ret; 


You should disable the dsi->pllref_clk clock prior to returning 
the error. 

+   dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata); + 
if (IS_ERR(dsi->mipi_dsi)) { +   ret = 
PTR_ERR(dsi->mipi_dsi); +   dev_dbg(dev, "%s: 
Unable to probe DW DSI host device: %d\n", + 
__func__, ret); +   return -ENODEV; 


Same here. You should disable the clock. Shouldn't you return 
'ret' here instead of -ENODEV? 

+module_platform_driver(imx_mipi_dsi_driver); + 
+MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver"); 
+MODULE_AUTHOR("Liu Ying "); 


The freescale.com domain is no longer functional. 

Ying Liu's NXP address is victor@nxp.com. You could probably 
add your entry as well. 


Hi Fabio,

All the issues you pointed out are valid and will be addressed in 
v6 (including the device tree ones).


Thank you, much appreciated,
Adrian
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Re: [PATCH v5 3/5] drm: bridge: synopsis: add dsi v1.01 support

2020-03-30 Thread Adrian Ratiu


On Mon, 30 Mar 2020, adrian61  wrote:
Hello Adrian, 

Here i get a compile error: 


I neglected to test with CONFIG_DEBUG_FS, oops!

Will fix in v6, thanks!



On Mon, Mar 30, 2020 at 2:36 PM Adrian Ratiu  wrote:


The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Signed-off-by: Adrian Ratiu 
---
New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5b78ff925af0..fb9dbc4fd0f5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@

 #define HWVER_131  0x31333100  /* IP version 1.31 */
 #define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */

 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64

 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)

+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70

@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8

+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4

 #define PHY_STATUS_TIMEOUT_US  1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };

+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10

Re: [PATCH v5 1/5] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-03-30 Thread Adrian Ratiu


On Mon, 30 Mar 2020, adrian61  wrote:
Hello Adrian, 

I am testing hese changes on my STM32F769-DISCO and i found 
that: 

On Mon, Mar 30, 2020 at 2:35 PM Adrian Ratiu 
 wrote: 


In order to support multiple versions of the Synopsis MIPI DSI 
host controller, which have different register layouts but 
almost identical HW protocols, we add a regmap infrastructure 
which can abstract away register accesses for platform drivers 
using the bridge. 

The controller HW revision is detected during bridge probe 
which will be used in future commits to load the relevant 
register layout which the bridge will use transparently to the 
platform drivers. 

Signed-off-by: Adrian Ratiu  --- 
New in v5.  --- 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 
 ++ 1 file changed, 117 insertions(+), 91 
 deletions(-) 

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
5ef0f154aa7b..6d9e2f21c9cc 100644 --- 
a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7 
@@ 
 #include  #include  
 #include  
+#include  
 #include  

 #include  
@@ -227,6 +228,7 @@ struct dw_mipi_dsi { 
struct drm_bridge *panel_bridge; struct device *dev; 
void __iomem *base; 
+   struct regmap *regs; 

struct clk *pclk; 

@@ -235,6 +237,7 @@ struct dw_mipi_dsi { 
u32 lanes; u32 format; unsigned long mode_flags; 
+   u32 hw_version; 

 #ifdef CONFIG_DEBUG_FS 
struct dentry *debugfs; 
@@ -249,6 +252,13 @@ struct dw_mipi_dsi { 
const struct dw_mipi_dsi_plat_data *plat_data; 
 }; 

+static const struct regmap_config dw_mipi_dsi_regmap_cfg = { + 
.reg_bits = 32, +   .val_bits = 32, +   .reg_stride = 
4, +   .name = "dw-mipi-dsi", +}; + 
 /* 
  * Check if either a link to a master or slave is present */ 
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi 
*bridge_to_dsi(struct drm_bridge *bridge) 
return container_of(bridge, struct dw_mipi_dsi, 
bridge); 
 } 

-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, 
u32 val) -{ -   writel(val, dsi->base + reg); -} - -static 
inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ - 
return readl(dsi->base + reg); -} - 
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
   struct mipi_dsi_device 
   *device) 
 { 
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct 
dw_mipi_dsi *dsi, 
if (lpm) 
val |= CMD_MODE_ALL_LP; 

-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); -   dsi_write(dsi, DSI_CMD_MODE_CFG, 
val); +   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); +   regmap_write(dsi->regs, 
DSI_CMD_MODE_CFG, val); 
 } 

 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
 *dsi, u32 hdr_val) { 
int ret; 
-   u32 val, mask; +   u32 val = 0, mask; 

-   ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, -val, !(val 
& GEN_CMD_FULL), 1000, - 
CMD_PKT_STATUS_TIMEOUT_US); +   ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, !(val & GEN_CMD_FULL), 1000, + 
CMD_PKT_STATUS_TIMEOUT_US); 
if (ret) { 
dev_err(dsi->dev, "failed to get available 
command FIFO\n"); return ret; 
} 

-   dsi_write(dsi, DSI_GEN_HDR, hdr_val); + 
regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); 

mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 
-   ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, -val, (val 
& mask) == mask, -1000, 
CMD_PKT_STATUS_TIMEOUT_US); +   ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, (val & mask) == mask, + 
1000, CMD_PKT_STATUS_TIMEOUT_US); 
if (ret) { 
dev_err(dsi->dev, "failed to write command 
FIFO\n"); return ret; 
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct 
dw_mipi_dsi *dsi, 
const u8 *tx_buf = packet->payload; int len = 
packet->payload_length, pld_data_bytes = sizeof(u32), 
ret; __le32 word; 
-   u32 val; +   u32 val = 0; 

while (len) { 
if (len < pld_data_bytes) { 
word = 0; memcpy(, tx_buf, len); 
-   dsi_write(dsi, DSI_GEN_PLD_DATA, 
le32_to_cpu(word)); + 
regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
le32_to_cpu(word)); 
len = 0; 
} else { 
memcpy(, tx_buf, pld_data_bytes); 
-   dsi_write(dsi, DSI_GEN_PLD_DATA, 
le32_to_cpu(word)); + 
regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
le32_to_cpu(word));

[PATCH v5 5/5] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2020-03-30 Thread Adrian Ratiu

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring 
Cc: Neil Armstrong 
Cc: devicet...@vger.kernel.org
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v4:
  - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
  and addressed received binding feedback (Rob)

Changes since v3:
  - Added commit message (Neil)
  - Converted to yaml format (Neil)
  - Minor dt node + driver fixes (Rob)
  - Added small panel example to the host controller binding

Changes since v2:
  - Fixed commit tags (Emil)
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 134 ++
 1 file changed, 134 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index ..59146df11510
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+  - Adrian Ratiu 
+
+description: |
+  The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+  IP block with a companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+properties:
+  compatible:
+items:
+  - const: fsl,imx6q-mipi-dsi
+  - const: snps,dw-mipi-dsi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module Clock
+  - description: DSI bus clock
+
+  clock-names:
+items:
+  - const: ref
+  - const: pclk
+
+  fsl,gpr:
+description: Phandle to the iomuxc-gpr region containing the multiplexer 
control register.
+$ref: /schemas/types.yaml#/definitions/phandle
+
+  ports:
+type: object
+description: |
+  A node containing DSI input & output port nodes with endpoint
+  definitions as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+  Documentation/devicetree/bindings/graph.txt
+properties:
+  port@0:
+type: object
+description:
+  DSI input port node, connected to the ltdc rgb output port.
+
+  port@1:
+type: object
+description:
+  DSI output port node, connected to a panel or a bridge input port"
+
+patternProperties:
+  "^panel@[0-3]$":
+type: object
+description: |
+  A node containing the panel or bridge description as documented in
+  Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+properties:
+  port:
+type: object
+description:
+  Panel or bridge port node, connected to the DSI output port (port@1)
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |+
+#include 
+#include 
+#include 
+
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+port@1 {
+reg = <1>;
+dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+panel@0 {
+compatible = "sharp,ls032b3sx01";
+reg = <0>;
+reset-gpios = < 8 GPIO_ACTIVE_LOW>;
+ports {
+port@0 {
+panel_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+};
+};
+
+...
-- 
2.26.0

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[PATCH v5 4/5] drm: imx: Add i.MX 6 MIPI DSI host platform driver

2020-03-30 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

- ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
  Signed-off-by: Liu Ying 

Cc: Fabio Estevam 
Reviewed-by: Emil Velikov 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
Changes since v4:
  - Split off driver-specific configuration of phy timings due
  to new upstream API.
  - Move regmap infrastructure logic to separate commit (Ezequiel)
  - Move dsi v1.01 layout addition to a separate commit (Ezequiel)
  - Minor warnings and driver name fixes

Changes since v3:
  - Renamed platform driver to reflect it's i.MX6 only. (Fabio)

Changes since v2:
  - Fixed commit tags. (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after
  calling the bridge probe. (Emil)
---
 drivers/gpu/drm/imx/Kconfig|   7 +
 drivers/gpu/drm/imx/Makefile   |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +
 3 files changed, 407 insertions(+)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..b49e70e7f0fd 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,10 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
  Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+   tristate "Freescale i.MX6 DRM MIPI DSI"
+   select DRM_DW_MIPI_DSI
+   depends on DRM_IMX
+   help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..9a7843c59347 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
 
 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c 
b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index ..56b17d8670a2
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_PHY_IF_CTRL0x5c
+#define PHY_IF_CTRL_RESET  0x0
+
+#define DSI_PHY_TST_CTRL0  0x64
+#define PHY_TESTCLKBIT(1)
+#define PHY_UNTESTCLK  0
+#define PHY_TESTCLRBIT(0)
+#define PHY_UNTESTCLR  0
+
+#define DSI_PHY_TST_CTRL1  0x68
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN   0
+#define PHY_TESTDOUT(n)(((n) & 0xff) << 8)
+#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
+
+struct imx_mipi_dsi {
+   struct drm_encoder encoder;
+   struct device *dev;
+   struct regmap *mux_sel;
+   struct dw_mipi_dsi *mipi_dsi;
+   struct clk *pllref_clk;
+
+   void __iomem *base;
+   unsigned int lane_mbps;
+};
+
+struct dphy_pll_testdin_map {
+   unsigned int max_mbps;
+   u8 testdin;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dphy_pll_testdin_map dptdin_map[] = {
+   {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
+   {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
+   {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
+   {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
+   {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14},
+   {900, 0x34}, {950, 0x54}, {1000, 0x74}
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+   return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+   regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3,
+  IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
+  ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
+}
+
+static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
+   .destroy = imx_drm_encoder_destroy,
+};
+
+static bo

[PATCH v5 0/5] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2020-03-30 Thread Adrian Ratiu

Hello everyone,

The v5 series is a significantly cleaned up version from v4,
started by Ezequiel Garcia's suggestion of splitting out the
regmap infrastructure from the drivers (thank you!).

Turns out no changes are required to the existing drivers and
the bridge can transparently take care of the layout logic,
so there's no need to expose the regmap via plat_data anymore.

Starting from this version I also opted to add per-patch
changelogs. All review comments up to now have been addressed.

Tested on IMX6DL.

Adrian Ratiu (5):
  drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: bridge: synopsis: add dsi v1.01 support
  drm: imx: Add i.MX 6 MIPI DSI host platform driver
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 134 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 683 +-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 399 ++
 5 files changed, 1049 insertions(+), 175 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
2.26.0

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[PATCH v5 2/5] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2020-03-30 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.

The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
Changes since v4:
  - Move regmap infrastructure logic to a separate commit (Ezequiel)
  - Consolidate field infrastructure in this commit (Ezequiel)
  - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)

Changes since v2:
  - Added const declarations to dw_mipi_dsi structs (Emil)
  - Fixed commit tags (Emil)

Changes since v1:
  - Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 510 --
 1 file changed, 352 insertions(+), 158 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6d9e2f21c9cc..5b78ff925af0 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -47,7 +48,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +56,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +112,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +140,6 @@
 #define GEN_CMD_EMPTY  BIT(0)
 
 #define DSI_TO_CNT_CFG 0x78
-#define HSTX_TO_CNT(p) (((p) & 0x) << 16)
-#define LPRX_TO_CNT(p) ((p) & 0x)
 
 #define DSI_HS_RD_TO_CNT   0x7c
 #define DSI_LP_RD_TO_CNT

[PATCH v5 1/5] drm: bridge: dw_mipi_dsi: add initial regmap infrastructure

2020-03-30 Thread Adrian Ratiu

In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.

The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.

Signed-off-by: Adrian Ratiu 
---
New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++
 1 file changed, 117 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7b..6d9e2f21c9cc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+   u32 hw_version;
 
 #ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi 
*dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
int ret;
-   u32 val, mask;
+   u32 val = 0, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
const u8 *tx_buf = packet->payload;
int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
__le32 word;
-   u32 val;
+   u32 val = 0;
 
while (len) {
if (len < pld_data_bytes) {
word = 0;
memcpy(, tx_buf, len);
-   dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+   regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+le32_to_cpu(word));
len = 0;
} else {
memcpy(, tx_buf, pld_data_bytes);
-   dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+   regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+le3

[PATCH v5 3/5] drm: bridge: synopsis: add dsi v1.01 support

2020-03-30 Thread Adrian Ratiu

The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.

Signed-off-by: Adrian Ratiu 
---
New in v5.
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
 1 file changed, 119 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5b78ff925af0..fb9dbc4fd0f5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
 #define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -100,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -127,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -165,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
+   .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6),
+   .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7),
+   .cfg_cmd_mode_en =  REG_FIELD

Re: [Linux-stm32] [PATCH v4 0/4] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2019-12-10 Thread Adrian Ratiu


On Fri, 06 Dec 2019, Philippe CORNU  wrote:
Hi Adrian, 

And sorry for this late reply.  Your patches look good and we 
("stm guys") understand that v1.01 is very  different to 
v1.30/31. 

We are doing our best to review & test your patches and we will 
go back  to you asap.  Many thanks, Philippe :-) 


Hi Philippe,

Thank you for taking the time to test this, I really appreciate 
it.


Adrian




On 12/2/19 8:33 PM, Adrian Ratiu wrote:

Having a generic Synopsis DesignWare MIPI-DSI host controller bridge
driver is a very good idea, however the current implementation has
hardcoded quite a lot of the register layouts used by the two supported
SoC vendors, STM and Rockchip, which use IP cores v1.30 and v1.31.

This makes it hard to support other SoC vendors like the FSL/NXP i.MX 6
which use older v1.01 cores or future versions because, based on history,
layout changes should also be expected in new DSI versions / SoCs.

This patch series converts the bridge and platform drivers to access
registers via generic regmap APIs and allows each platform driver to
configure its register layout via struct reg_fields, then adds support
for the host controller found on i.MX 6.

I only have i.MX hardware with MIPI-DSI panel and relevant documentation
available for testing so I'll really appreciate it if someone could test
the series on Rockchip and STM... eyeballing register fields could only
get me so far, so sorry in advance for any breakage!

Many thanks to Boris Brezillon  for
suggesting the regmap solution and to Liu Ying 
for doing the initial i.MX platform driver implementation.

This series applies on top of latest linux-next tree, next-20191202.

v3 -> v4:
   * Added commmit message to dt-binding patch (Neil)
   * Converted the dt-binding to yaml dt-schema format (Neil)
   * Small DT node + driver fixes (Rob)
   * Renamed platform driver to reflect it's only for i.MX v6 (Fabio)
   * Added small panel example to the host controller DT binding

v2 -> v3:
   * Added const declarations to dw-mipi-dsi.c structs (Emil)
   * Fixed Reviewed-by tags and cc'd some more relevant ML (Emil)

v1 -> v2:
   * Moved register definitions & regmap initialization into bridge
   module. Platform drivers get the regmap via plat_data after calling
   the bridge probe (Emil).

Adrian Ratiu (4):
   drm: bridge: dw_mipi_dsi: access registers via a regmap
   drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
   drm: imx: Add i.MX 6 MIPI DSI host driver
   dt-bindings: display: add i.MX6 MIPI DSI host controller doc

  .../display/imx/fsl,mipi-dsi-imx6.yaml| 136 
  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 699 +-
  drivers/gpu/drm/imx/Kconfig   |   7 +
  drivers/gpu/drm/imx/Makefile  |   1 +
  drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 378 ++
  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 +-
  include/drm/bridge/dw_mipi_dsi.h  |   2 +-
  8 files changed, 1067 insertions(+), 207 deletions(-)
  create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
  create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c


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Re: [Linux-stm32] [PATCH v4 0/4] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2019-12-10 Thread Adrian Ratiu

On Mon, 02 Dec 2019, Adrian Ratiu  
wrote:
Having a generic Synopsis DesignWare MIPI-DSI host controller 
bridge driver is a very good idea, however the current 
implementation has hardcoded quite a lot of the register layouts 
used by the two supported SoC vendors, STM and Rockchip, which 
use IP cores v1.30 and v1.31. 

This makes it hard to support other SoC vendors like the FSL/NXP 
i.MX 6 which use older v1.01 cores or future versions because, 
based on history, layout changes should also be expected in new 
DSI versions / SoCs. 

This patch series converts the bridge and platform drivers to 
access registers via generic regmap APIs and allows each 
platform driver to configure its register layout via struct 
reg_fields, then adds support for the host controller found on 
i.MX 6. 

I only have i.MX hardware with MIPI-DSI panel and relevant 
documentation available for testing so I'll really appreciate it 
if someone could test the series on Rockchip and 
STM... eyeballing register fields could only get me so far, so 
sorry in advance for any breakage! 

Many thanks to Boris Brezillon  
for suggesting the regmap solution and to Liu Ying 
 for doing the initial i.MX platform 
driver implementation. 

This series applies on top of latest linux-next tree, 
next-20191202. 

v3 -> v4: 
  * Added commmit message to dt-binding patch (Neil) * Converted 
  the dt-binding to yaml dt-schema format (Neil) * Small DT node 
  + driver fixes (Rob) * Renamed platform driver to reflect it's 
  only for i.MX v6 (Fabio) * Added small panel example to the 
  host controller DT binding 

v2 -> v3: 
  * Added const declarations to dw-mipi-dsi.c structs (Emil) * 
  Fixed Reviewed-by tags and cc'd some more relevant ML (Emil) 

v1 -> v2: 
  * Moved register definitions & regmap initialization into 
  bridge module. Platform drivers get the regmap via plat_data 
  after calling the bridge probe (Emil). 


I've been told I forgot to explicitly CC some of the maintainers, 
sorry about that! Added a few more persons to CC.




Adrian Ratiu (4):
  drm: bridge: dw_mipi_dsi: access registers via a regmap
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: imx: Add i.MX 6 MIPI DSI host driver
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 136 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 699 +-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 378 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 +-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 8 files changed, 1067 insertions(+), 207 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

--
2.24.0

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[PATCH v4 2/4] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2019-12-02 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic driver can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout, so platform drivers will continue to use the
regmap as before. Other DSI versions / register layouts can easily be
added in the future by only changing the bridge code.

An additional benefit of using the reg_field API is that much of the
bit-shifting and masking boilerplate is removed because it's now
handled automatically by the regmap subsystem.

Not all register accesses have been converted: only the minimum diff
between the three host controller versions supported by the current
vendor platform drivers (rockchip, stm and now imx), more can be added
in the future as needed.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 504 --
 1 file changed, 346 insertions(+), 158 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6cb57807f3f9..a41a630302b6 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -47,7 +47,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +55,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +75,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +111,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +139,6 @@
 #define GEN_CMD_EMPTY  BIT(0)
 
 #define DSI_TO_CNT_CFG 0x78
-#define HSTX_TO_CNT(p) (((p) & 0x) << 16)
-#define LPRX_TO_CNT(p) ((p) & 0x)
 
 #define DSI_HS_RD_TO_CNT   0x7c
 #define DSI_LP_RD_TO_CNT   0x80
@@ -164,52 +147,17 @@
 #define DSI_BTA_TO_CNT 0x8c
 
 #define DSI_LPCLK_CTRL 0x94
-#define AUTO_CLKLANE_CTRL  BIT(1)
-#define PHY_TXREQUESTCLKHS BIT(0)
-
 #define DSI_PHY_TMR_LPCLK_CFG  0x98
-#define PHY_CLKHS2LP_TIME(lbcc)(((lbcc) & 0x3ff) << 16)
-#define PHY_CLKLP2HS_TIME(lbcc)((lbcc) & 0x3ff)
-
 #define DSI_PHY_TMR_CFG0x9c
-#define PHY_HS2LP_TIME(lbcc)   (((lbcc) & 0xff) << 24)
-#define PHY_LP2HS_TIME(lbcc)   (((lbcc) &

[PATCH v4 0/4] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2019-12-02 Thread Adrian Ratiu

Having a generic Synopsis DesignWare MIPI-DSI host controller bridge
driver is a very good idea, however the current implementation has
hardcoded quite a lot of the register layouts used by the two supported
SoC vendors, STM and Rockchip, which use IP cores v1.30 and v1.31.

This makes it hard to support other SoC vendors like the FSL/NXP i.MX 6
which use older v1.01 cores or future versions because, based on history,
layout changes should also be expected in new DSI versions / SoCs.

This patch series converts the bridge and platform drivers to access
registers via generic regmap APIs and allows each platform driver to
configure its register layout via struct reg_fields, then adds support
for the host controller found on i.MX 6.

I only have i.MX hardware with MIPI-DSI panel and relevant documentation
available for testing so I'll really appreciate it if someone could test
the series on Rockchip and STM... eyeballing register fields could only
get me so far, so sorry in advance for any breakage!

Many thanks to Boris Brezillon  for
suggesting the regmap solution and to Liu Ying 
for doing the initial i.MX platform driver implementation.

This series applies on top of latest linux-next tree, next-20191202.

v3 -> v4:
  * Added commmit message to dt-binding patch (Neil)
  * Converted the dt-binding to yaml dt-schema format (Neil)
  * Small DT node + driver fixes (Rob)
  * Renamed platform driver to reflect it's only for i.MX v6 (Fabio)
  * Added small panel example to the host controller DT binding

v2 -> v3:
  * Added const declarations to dw-mipi-dsi.c structs (Emil)
  * Fixed Reviewed-by tags and cc'd some more relevant ML (Emil)

v1 -> v2:
  * Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).

Adrian Ratiu (4):
  drm: bridge: dw_mipi_dsi: access registers via a regmap
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: imx: Add i.MX 6 MIPI DSI host driver
  dt-bindings: display: add i.MX6 MIPI DSI host controller doc

 .../display/imx/fsl,mipi-dsi-imx6.yaml| 136 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 699 +-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 378 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 +-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 8 files changed, 1067 insertions(+), 207 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

-- 
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[PATCH v4 4/4] dt-bindings: display: add i.MX6 MIPI DSI host controller doc

2019-12-02 Thread Adrian Ratiu

This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.

Cc: Rob Herring 
Cc: Neil Armstrong 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
 .../display/imx/fsl,mipi-dsi-imx6.yaml| 136 ++
 1 file changed, 136 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml 
b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index ..8c9603c28240
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+description:
+  The DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 IP with a 
companion PHY IP.
+
+  These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+  Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+  the following device-specific properties.
+
+properties:
+  compatible:
+const: [ "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi" ]
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+items:
+  - description: Module Clock
+  - description: DSI bus clock
+minItems: 2
+maxItems: 2
+
+  clock-names:
+items:
+  - const: pclk
+  - const: ref
+minItems: 2
+maxItems: 2
+
+  fsl,gpr:
+description: Phandle to the iomuxc-gpr region containing the multiplexer 
control register.
+const: *gpr
+
+  ports:
+type: object
+description:
+  A node containing DSI input & output port nodes with endpoint
+  definitions as documented in
+  Documentation/devicetree/bindings/media/video-interfaces.txt
+  Documentation/devicetree/bindings/graph.txt
+properties:
+  port@0:
+type: object
+description:
+  DSI input port node, connected to the ltdc rgb output port.
+
+  port@1:
+type: object
+description:
+  DSI output port node, connected to a panel or a bridge input port"
+
+patternProperties:
+  "^(panel|panel-dsi)@[0-9]$":
+type: object
+description:
+  A node containing the panel or bridge description as documented in
+  Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+properties:
+  port:
+type: object
+description:
+  Panel or bridge port node, connected to the DSI output port (port@1)
+
+  "#address-cells":
+const: 1
+
+  "#size-cells":
+const: 0
+
+required:
+  - "#address-cells"
+  - "#size-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+dsi: dsi@21e {
+#address-cells = <1>;
+#size-cells = <0>;
+compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+reg = <0x021e 0x4000>;
+interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+fsl,gpr = <>;
+clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+ < IMX6QDL_CLK_MIPI_IPG>;
+clock-names = "ref", "pclk";
+
+ports {
+port@0 {
+reg = <0>;
+dsi_in: endpoint {
+remote-endpoint = <_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+dsi_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+panel@0 {
+compatible = "sharp,ls032b3sx01";
+reg = <0>;
+reset-gpios = < 8 GPIO_ACTIVE_LOW>;
+
+ports {
+port@0 {
+panel_in: endpoint {
+remote-endpoint = <_out>;
+};
+};
+};
+};
+};
+
+...
-- 
2.24.0

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[PATCH v4 1/4] drm: bridge: dw_mipi_dsi: access registers via a regmap

2019-12-02 Thread Adrian Ratiu

Convert the common bridge code and the two rockchip & stm drivers
which currently use it to the regmap API in anticipation for further
changes to make it more generic and add older DSI host controller
support as found on i.mx6 based devices.

The regmap becomes an internal state of the bridge. No functional
changes other than requiring the platform drivers to use the
pre-configured regmap supplied by the bridge after its probe() call
instead of ioremp'ing the registers themselves.

In subsequent commits the bridge will become able to detect the
DSI host core version and init the regmap with different register
layouts. The platform drivers will continue to use the regmap without
modifications or worrying about the specific layout in use (in other
words the layout is abstracted away via the regmap).

Suggested-by: Boris Brezillon 
Reviewed-by: Neil Armstrong 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 215 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 ++-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 4 files changed, 145 insertions(+), 123 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b6e793bb653c..6cb57807f3f9 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -226,7 +227,7 @@ struct dw_mipi_dsi {
struct mipi_dsi_host dsi_host;
struct drm_bridge *panel_bridge;
struct device *dev;
-   void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -249,6 +250,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +288,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,29 +364,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi 
*dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
int ret;
-   u32 val, mask;
+   u32 val = 0, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -403,24 +401,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
const u8 *tx_buf = packet->payload;
int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
__le32 word;
-   u32 val;
+   u32 val = 0;
 
while (len) {
if (len < pld_data_bytes) {
word = 0;
memcpy(, tx_buf, len);
-   dsi_write(dsi, DSI_GEN_PL

[PATCH v4 3/4] drm: imx: Add i.MX 6 MIPI DSI host driver

2019-12-02 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

- ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
  Signed-off-by: Liu Ying 

Cc: Fabio Estevam 
Reviewed-by: Emil Velikov 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 146 ++-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c| 378 ++
 4 files changed, 523 insertions(+), 9 deletions(-)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index a41a630302b6..5f2fa467734c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,8 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -99,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -126,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -164,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -357,6 +410,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD

Re: [PATCH v3 4/4] dt-bindings: display: add IMX MIPI DSI host controller doc

2019-11-20 Thread Adrian Ratiu

On Wed, 20 Nov 2019, Neil Armstrong  
wrote:
Hi, 

On 18/11/2019 16:25, Adrian Ratiu wrote: 

A small commit log would be welcome here. 

Signed-off-by: Sjoerd Simons  
Signed-off-by: Martyn Welch  
Signed-off-by: Adrian Ratiu  --- 
 .../bindings/display/imx/mipi-dsi.txt | 56 
 +++ 1 file changed, 56 insertions(+) create 
 mode 100644 
 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt 
 diff --git 
a/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt 
b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt 
new file mode 100644 index ..3f05c32ef963 --- 
/dev/null +++ 
b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt 


New bindings should use the yaml dt-schema format, could you 
convert it ?


Yes, I will convert to yaml and add a commit log in the next 
version.


Will leave the current patches a little more on review to give 
others a chance to see them.


Thank you!



Neil


@@ -0,0 +1,56 @@
+Freescale i.MX6 DW MIPI DSI Host Controller
+===
+
+The DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+the following device-specific properties.
+
+Required properties:
+
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi".
+- reg: See dw_mipi_dsi.txt.
+- interrupts: The controller's CPU interrupt.
+- clocks, clock-names: Phandles to the controller's pll reference
+  clock(ref) and APB clock(pclk), as described in [1].
+- ports: a port node with endpoint definitions as defined in [2].
+- gpr: Should be <>.
+   Phandle to the iomuxc-gpr region containing the multiplexer
+   control register.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   mipi_dsi: mipi@21e {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+   reg = <0x021e 0x4000>;
+   interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+   gpr = <>;
+   clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_IPG>;
+   clock-names = "ref", "pclk";
+   status = "okay";
+
+   ports {
+   port@0 {
+   reg = <0>;
+   mipi_mux_0: endpoint {
+   remote-endpoint = <_di0_mipi>;
+   };
+   };
+   port@1 {
+   reg = <1>;
+   mipi_mux_1: endpoint {
+   remote-endpoint = <_di1_mipi>;
+   };
+   };
+   };
+};




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Re: [PATCH v3 3/4] drm: imx: Add i.MX 6 MIPI DSI host driver

2019-11-19 Thread Adrian Ratiu


On Tue, 19 Nov 2019, Fabio Estevam  wrote:
Hi Adrian, 


Hi Fabio,



On Mon, Nov 18, 2019 at 12:25 PM Adrian Ratiu 
 wrote: 

Some nitpicks: 

+ +config DRM_IMX_MIPI_DSI +   tristate "Freescale i.MX DRM 
MIPI DSI" 


This text seems too generic as there are i.MX SoCs that use 
different MIPI DSI IP. 

Maybe "Freescale i.MX6 DRM MIPI DSI" instead? 


Yes, this is a good idea, will update in a newer version to make 
it more specific. I'll let this version sit a little more on 
review so others also have time to review.


Thank you!



+module_platform_driver(imx_mipi_dsi_driver); + 
+MODULE_DESCRIPTION("i.MX MIPI DSI host controller driver"); 


i.MX6 MIPI DSI, please.

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[PATCH v3 4/4] dt-bindings: display: add IMX MIPI DSI host controller doc

2019-11-18 Thread Adrian Ratiu

Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
 .../bindings/display/imx/mipi-dsi.txt | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt

diff --git a/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt 
b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt
new file mode 100644
index ..3f05c32ef963
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt
@@ -0,0 +1,56 @@
+Freescale i.MX6 DW MIPI DSI Host Controller
+===
+
+The DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+the following device-specific properties.
+
+Required properties:
+
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi".
+- reg: See dw_mipi_dsi.txt.
+- interrupts: The controller's CPU interrupt.
+- clocks, clock-names: Phandles to the controller's pll reference
+  clock(ref) and APB clock(pclk), as described in [1].
+- ports: a port node with endpoint definitions as defined in [2].
+- gpr: Should be <>.
+   Phandle to the iomuxc-gpr region containing the multiplexer
+   control register.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   mipi_dsi: mipi@21e {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+   reg = <0x021e 0x4000>;
+   interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+   gpr = <>;
+   clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_IPG>;
+   clock-names = "ref", "pclk";
+   status = "okay";
+
+   ports {
+   port@0 {
+   reg = <0>;
+   mipi_mux_0: endpoint {
+   remote-endpoint = <_di0_mipi>;
+   };
+   };
+   port@1 {
+   reg = <1>;
+   mipi_mux_1: endpoint {
+   remote-endpoint = <_di1_mipi>;
+   };
+   };
+   };
+};
-- 
2.24.0

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[PATCH v3 3/4] drm: imx: Add i.MX 6 MIPI DSI host driver

2019-11-18 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

- ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
  Signed-off-by: Liu Ying 

Reviewed-by: Emil Velikov 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 146 ++-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 378 ++
 4 files changed, 523 insertions(+), 9 deletions(-)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index a41a630302b6..5f2fa467734c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,8 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -99,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -126,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -164,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -357,6 +410,49 @@ static const struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4

[PATCH v3 1/4] drm: bridge: dw_mipi_dsi: access registers via a regmap

2019-11-18 Thread Adrian Ratiu

Convert the common bridge code and the two rockchip & stm drivers
which currently use it to the regmap API in anticipation for further
changes to make it more generic and add older DSI host controller
support as found on i.mx6 based devices.

The regmap becomes an internal state of the bridge. No functional
changes other than requiring the platform drivers to use the
pre-configured regmap supplied by the bridge after its probe() call
instead of ioremp'ing the registers themselves.

In subsequent commits the bridge will become able to detect the
DSI host core version and init the regmap with different register
layouts. The platform drivers will continue to use the regmap without
modifications or worrying about the specific layout in use (in other
words the layout is abstracted away via the regmap).

Suggested-by: Boris Brezillon 
Reviewed-by: Neil Armstrong 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 215 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 ++-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 4 files changed, 145 insertions(+), 123 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b6e793bb653c..6cb57807f3f9 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -226,7 +227,7 @@ struct dw_mipi_dsi {
struct mipi_dsi_host dsi_host;
struct drm_bridge *panel_bridge;
struct device *dev;
-   void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -249,6 +250,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +288,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,29 +364,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi 
*dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
int ret;
-   u32 val, mask;
+   u32 val = 0, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -403,24 +401,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
const u8 *tx_buf = packet->payload;
int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
__le32 word;
-   u32 val;
+   u32 val = 0;
 
while (len) {
if (len < pld_data_bytes) {
word = 0;
memcpy(, tx_buf, len);
-   dsi_write(dsi, DSI_GEN_PL

[PATCH v3 2/4] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2019-11-18 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic driver can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout, so platform drivers will continue to use the
regmap as before. Other DSI versions / register layouts can easily be
added in the future by only changing the bridge code.

An additional benefit of using the reg_field API is that much of the
bit-shifting and masking boilerplate is removed because it's now
handled automatically by the regmap subsystem.

Not all register accesses have been converted: only the minimum diff
between the three host controller versions supported by the current
vendor platform drivers (rockchip, stm and now imx), more can be added
in the future as needed.

Suggested-by: Boris Brezillon 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 504 --
 1 file changed, 346 insertions(+), 158 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6cb57807f3f9..a41a630302b6 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -47,7 +47,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +55,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +75,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +111,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +139,6 @@
 #define GEN_CMD_EMPTY  BIT(0)
 
 #define DSI_TO_CNT_CFG 0x78
-#define HSTX_TO_CNT(p) (((p) & 0x) << 16)
-#define LPRX_TO_CNT(p) ((p) & 0x)
 
 #define DSI_HS_RD_TO_CNT   0x7c
 #define DSI_LP_RD_TO_CNT   0x80
@@ -164,52 +147,17 @@
 #define DSI_BTA_TO_CNT 0x8c
 
 #define DSI_LPCLK_CTRL 0x94
-#define AUTO_CLKLANE_CTRL  BIT(1)
-#define PHY_TXREQUESTCLKHS BIT(0)
-
 #define DSI_PHY_TMR_LPCLK_CFG  0x98
-#define PHY_CLKHS2LP_TIME(lbcc)(((lbcc) & 0x3ff) << 16)
-#define PHY_CLKLP2HS_TIME(lbcc)((lbcc) & 0x3ff)
-
 #define DSI_PHY_TMR_CFG0x9c
-#define PHY_HS2LP_TIME(lbcc)   (((lbcc) & 0xff) << 24)
-#define PHY_LP2HS_TIME(lbcc)   (((lbcc) &

[PATCH v3 0/4] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2019-11-18 Thread Adrian Ratiu

Having a generic Synopsis DesignWare MIPI-DSI host controller bridge
driver is a very good idea, however the current implementation has
hardcoded quite a lot of the register layouts used by the two supported
SoC vendors, STM and Rockchip, which use IP cores v1.30 and v1.31.

This makes it hard to support other SoC vendors like the FSL/NXP i.MX 6
which use older v1.01 cores or future versions because, based on history,
layout changes should also be expected in new DSI versions / SoCs.

This patch series converts the bridge and platform drivers to access
registers via generic regmap APIs and allows each platform driver to
configure its register layout via struct reg_fields, then adds support
for the host controller found on i.MX 6.

I only have i.MX hardware with MIPI-DSI panel and relevant documentation
available for testing so I'll really appreciate it if someone could test
the series on Rockchip and STM... eyeballing register fields could only
get me so far, so sorry in advance for any breakage!

Many thanks to Boris Brezillon  for
suggesting the regmap solution and to Liu Ying 
for doing the initial i.MX platform driver implementation.

This series applies on top of latest linux-next tree, next-20191118.

v2 -> v3:
  * Added const declarations to dw-mipi-dsi.c structs (Emil)
  * Fixed Reviewed-by tags and cc'd some more relevant ML (Emil)

v1 -> v2:
  * Moved register definitions & regmap initialization into bridge
  module. Platform drivers get the regmap via plat_data after calling
  the bridge probe (Emil).

Adrian Ratiu (4):
  drm: bridge: dw_mipi_dsi: access registers via a regmap
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: imx: Add i.MX 6 MIPI DSI host driver
  dt-bindings: display: add IMX MIPI DSI host controller doc

 .../bindings/display/imx/mipi-dsi.txt |  56 ++
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 699 +-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 378 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 +-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 8 files changed, 987 insertions(+), 207 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c

-- 
2.24.0

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Re: [PATCH v2 1/4] drm: bridge: dw_mipi_dsi: access registers via a regmap

2019-11-13 Thread Adrian Ratiu

On Wed, 13 Nov 2019, Emil Velikov  
wrote:
On Wed, 6 Nov 2019 at 16:30, Adrian Ratiu 
 wrote: 


Convert the common bridge code and the two rockchip & stm 
drivers which currently use it to the regmap API in 
anticipation for further changes to make it more generic and 
add older DSI host controller support as found on i.mx6 based 
devices. 

The regmap becomes an internal state of the bridge. No 
functional changes other than requiring the platform drivers to 
use the pre-configured regmap supplied by the bridge after its 
probe() call instead of ioremp'ing the registers themselves. 

In subsequent commits the bridge will become able to detect the 
DSI host core version and init the regmap with different 
register layouts. The platform drivers will continue to use the 
regmap without modifications or worrying about the specific 
layout in use (in other words the layout is abstracted away via 
the regmap). 

Suggested-by: Boris Brezillon  
Reviewed-by: Neil Armstrong  
Reviewed-by: Emil Velikov  


I should have been clearer earlier - I didn't quite review the 
patch.  Is is now though.  Reviewed-by: Emil Velikov 



Sorry about that, I got confused and thought you reviewed it all.



Admittedly a couple of nitpicks (DRIVER_NAME, zero initialize of 
val) could have been left out.  It's not a big deal, there's no 
need to polish those.


I'll address them in v3 as well as updating your mail address.

Thanks for reviewing!



-Emil

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[PATCH v2 3/4] drm: imx: Add i.MX 6 MIPI DSI host driver

2019-11-06 Thread Adrian Ratiu

This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.

Based on following patches, but updated/extended to work with existing
support found in the kernel:

- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
  Signed-off-by: Liu Ying 

- ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
  Signed-off-by: Liu Ying 

Reviewed-by: Neil Armstrong 
Reviewed-by: Emil Velikov 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 146 ++-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 378 ++
 4 files changed, 523 insertions(+), 9 deletions(-)
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index a0637328fbc1..d88363cc2681 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,8 @@
 #include 
 
 #define HWVER_131  0x31333100  /* IP version 1.31 */
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_101  0x31303000  /* IP version 1.01 */
 
 #define DSI_VERSION0x00
 #define VERSIONGENMASK(31, 8)
@@ -99,6 +101,25 @@
 #define DSI_EDPI_CMD_SIZE  0x64
 
 #define DSI_CMD_MODE_CFG   0x68
+
+#define DSI_DPI_CFG0x0c
+#define DSI_TMR_LINE_CFG   0x28
+#define DSI_VTIMING_CFG0x2c
+#define DSI_PHY_TMR_CFG_V101   0x30
+#define DSI_PHY_IF_CFG_V1010x58
+#define DSI_PHY_IF_CTRL0x5c
+#define DSI_PHY_RSTZ_V101  0x54
+#define DSI_PHY_STATUS_V1010x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101   0x34
+#define DSI_GEN_PLD_DATA_V101  0x38
+#define DSI_CMD_MODE_CFG_V101  0x24
+#define DSI_CMD_PKT_STATUS_V1010x3c
+#define DSI_VID_PKT_CFG0x20
+#define DSI_VID_MODE_CFG_V101  0x1c
+#define DSI_TO_CNT_CFG_V1010x40
+#define DSI_PCKHDL_CFG_V1010x18
+
 #define MAX_RD_PKT_SIZE_LP BIT(24)
 #define DCS_LW_TX_LP   BIT(19)
 #define DCS_SR_0P_TX_LPBIT(18)
@@ -126,6 +147,33 @@
 GEN_SW_1P_TX_LP | \
 GEN_SW_0P_TX_LP)
 
+#define EN_TEAR_FX_V101BIT(14)
+#define DCS_LW_TX_LP_V101  BIT(12)
+#define GEN_LW_TX_LP_V101  BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101BIT(10)
+#define DCS_SW_2P_TX_LP_V101   BIT(9)
+#define DCS_SW_1P_TX_LP_V101   BIT(8)
+#define DCS_SW_0P_TX_LP_V101   BIT(7)
+#define GEN_SR_2P_TX_LP_V101   BIT(6)
+#define GEN_SR_1P_TX_LP_V101   BIT(5)
+#define GEN_SR_0P_TX_LP_V101   BIT(4)
+#define GEN_SW_2P_TX_LP_V101   BIT(3)
+#define GEN_SW_1P_TX_LP_V101   BIT(2)
+#define GEN_SW_0P_TX_LP_V101   BIT(1)
+
+#define CMD_MODE_ALL_LP_V101   (DCS_LW_TX_LP_V101 | \
+GEN_LW_TX_LP_V101 | \
+MAX_RD_PKT_SIZE_LP_V101 | \
+DCS_SW_2P_TX_LP_V101 | \
+DCS_SW_1P_TX_LP_V101 | \
+DCS_SW_0P_TX_LP_V101 | \
+GEN_SR_2P_TX_LP_V101 | \
+GEN_SR_1P_TX_LP_V101 | \
+GEN_SR_0P_TX_LP_V101 | \
+GEN_SW_2P_TX_LP_V101 | \
+GEN_SW_1P_TX_LP_V101 | \
+GEN_SW_0P_TX_LP_V101)
+
 #define DSI_GEN_HDR0x6c
 #define DSI_GEN_PLD_DATA   0x70
 
@@ -164,6 +212,11 @@
 #define DSI_INT_MSK0   0xc4
 #define DSI_INT_MSK1   0xc8
 
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V1010x4c
+#define DSI_ERROR_MSK1_V1010x50
+
 #define DSI_PHY_TMR_RD_CFG 0xf4
 
 #define PHY_STATUS_TIMEOUT_US  1
@@ -357,6 +410,49 @@ static struct dw_mipi_dsi_variant 
dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
 };
 
+static struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+   .cfg_dpi_vid =  REG_FIELD(DSI_DPI_CFG, 0, 1),
+   .cfg_dpi_color_coding = REG_FIELD

[PATCH v2 2/4] drm: bridge: dw_mipi_dsi: abstract register access using reg_fields

2019-11-06 Thread Adrian Ratiu

Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic driver can be made to compensate these differences.

The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.

The bridge detects the DSI core version and initializes the required
regmap register layout, so platform drivers will continue to use the
regmap as before. Other DSI versions / register layouts can easily be
added in the future by only changing the bridge code.

An additional benefit of using the reg_field API is that much of the
bit-shifting and masking boilerplate is removed because it's now
handled automatically by the regmap subsystem.

Not all register accesses have been converted: only the minimum diff
between the three host controller versions supported by the current
vendor platform drivers (rockchip, stm and now imx), more can be added
in the future as needed.

Suggested-by: Boris Brezillon 
Reviewed-by: Neil Armstrong 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 504 --
 1 file changed, 346 insertions(+), 158 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6cb57807f3f9..a0637328fbc1 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -47,7 +47,6 @@
 #define DPI_VCID(vcid) ((vcid) & 0x3)
 
 #define DSI_DPI_COLOR_CODING   0x10
-#define LOOSELY18_EN   BIT(8)
 #define DPI_COLOR_CODING_16BIT_1   0x0
 #define DPI_COLOR_CODING_16BIT_2   0x1
 #define DPI_COLOR_CODING_16BIT_3   0x2
@@ -56,11 +55,6 @@
 #define DPI_COLOR_CODING_24BIT 0x5
 
 #define DSI_DPI_CFG_POL0x14
-#define COLORM_ACTIVE_LOW  BIT(4)
-#define SHUTD_ACTIVE_LOW   BIT(3)
-#define HSYNC_ACTIVE_LOW   BIT(2)
-#define VSYNC_ACTIVE_LOW   BIT(1)
-#define DATAEN_ACTIVE_LOW  BIT(0)
 
 #define DSI_DPI_LP_CMD_TIM 0x18
 #define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
@@ -81,27 +75,19 @@
 #define DSI_GEN_VCID   0x30
 
 #define DSI_MODE_CFG   0x34
-#define ENABLE_VIDEO_MODE  0
-#define ENABLE_CMD_MODEBIT(0)
 
 #define DSI_VID_MODE_CFG   0x38
-#define ENABLE_LOW_POWER   (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define ENABLE_LOW_POWER   0x3f
+
 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLEBIT(16)
-#define VID_MODE_VPG_HORIZONTALBIT(24)
 
 #define DSI_VID_PKT_SIZE   0x3c
-#define VID_PKT_SIZE(p)((p) & 0x3fff)
 
 #define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c)  ((c) & 0x1fff)
 
 #define DSI_VID_NULL_SIZE  0x44
-#define VID_NULL_SIZE(b)   ((b) & 0x1fff)
 
 #define DSI_VID_HSA_TIME   0x48
 #define DSI_VID_HBP_TIME   0x4c
@@ -125,7 +111,6 @@
 #define GEN_SW_2P_TX_LPBIT(10)
 #define GEN_SW_1P_TX_LPBIT(9)
 #define GEN_SW_0P_TX_LPBIT(8)
-#define ACK_RQST_ENBIT(1)
 #define TEAR_FX_EN BIT(0)
 
 #define CMD_MODE_ALL_LP(MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +139,6 @@
 #define GEN_CMD_EMPTY  BIT(0)
 
 #define DSI_TO_CNT_CFG 0x78
-#define HSTX_TO_CNT(p) (((p) & 0x) << 16)
-#define LPRX_TO_CNT(p) ((p) & 0x)
 
 #define DSI_HS_RD_TO_CNT   0x7c
 #define DSI_LP_RD_TO_CNT   0x80
@@ -164,52 +147,17 @@
 #define DSI_BTA_TO_CNT 0x8c
 
 #define DSI_LPCLK_CTRL 0x94
-#define AUTO_CLKLANE_CTRL  BIT(1)
-#define PHY_TXREQUESTCLKHS BIT(0)
-
 #define DSI_PHY_TMR_LPCLK_CFG  0x98
-#define PHY_CLKHS2LP_TIME(lbcc)(((lbcc) & 0x3ff) << 16)
-#define PHY_CLKLP2HS_TIME(lbcc)((lbcc) & 0x3ff)
-
 #define DSI_PHY_TMR_CFG0x9c
-#define PHY_HS2LP_TIME(lbcc)   (((lbcc) & 0xff) << 24)
-#define PHY_LP2HS_TIME(lbcc)   (((l

[PATCH v2 0/4] Genericize DW MIPI DSI bridge and add i.MX 6 driver

2019-11-06 Thread Adrian Ratiu

Having a generic Synopsis DesignWare MIPI-DSI host controller bridge
driver is a very good idea, however the current implementation has
hardcoded quite a lot of the register layouts used by the two supported
SoC vendors, STM and Rockchip, which use IP cores v1.30 and v1.31.

This makes it hard to support other SoC vendors like the FSL/NXP i.MX 6
which use older v1.01 cores or future versions because, based on history,
layout changes should also be expected in new DSI versions / SoCs.

This patch series converts the bridge and platform drivers to access
registers via generic regmap APIs then, adds support for the host
controller found on i.MX 6.

I only have i.MX hardware with MIPI-DSI panel and relevant documentation
available for testing so I'll really appreciate it if someone could test
the series on Rockchip and STM... eyeballing register fields could only
get me so far, so sorry in advance for any breakage!

Many thanks to Boris Brezillon  for
suggesting the regmap solution and to Liu Ying 
for doing the initial i.MX platform driver implementation.

This series applies on top of latest linux-next tree, next-20191106.

v1 -> v2:
  * Moved the register definitions & regmap initialization into the
  bridge module as suggested by Emil. Platform drivers can get the
  regmap via their plat_data after calling the bridge probe() without
  worrying at all about layouts, which are handled by the bridge now.

Adrian Ratiu (4):
  drm: bridge: dw_mipi_dsi: access registers via a regmap
  drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
  drm: imx: Add i.MX 6 MIPI DSI host driver
  dt-bindings: display: add IMX MIPI DSI host controller doc

 .../bindings/display/imx/mipi-dsi.txt |  56 ++
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 699 +-
 drivers/gpu/drm/imx/Kconfig   |   7 +
 drivers/gpu/drm/imx/Makefile  |   1 +
 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c | 378 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 +-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 8 files changed, 987 insertions(+), 207 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt
 create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx.c

-- 
2.23.0

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[PATCH v2 1/4] drm: bridge: dw_mipi_dsi: access registers via a regmap

2019-11-06 Thread Adrian Ratiu

Convert the common bridge code and the two rockchip & stm drivers
which currently use it to the regmap API in anticipation for further
changes to make it more generic and add older DSI host controller
support as found on i.mx6 based devices.

The regmap becomes an internal state of the bridge. No functional
changes other than requiring the platform drivers to use the
pre-configured regmap supplied by the bridge after its probe() call
instead of ioremp'ing the registers themselves.

In subsequent commits the bridge will become able to detect the
DSI host core version and init the regmap with different register
layouts. The platform drivers will continue to use the regmap without
modifications or worrying about the specific layout in use (in other
words the layout is abstracted away via the regmap).

Suggested-by: Boris Brezillon 
Reviewed-by: Neil Armstrong 
Reviewed-by: Emil Velikov 
Signed-off-by: Adrian Ratiu 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 215 ++
 .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  17 +-
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  34 ++-
 include/drm/bridge/dw_mipi_dsi.h  |   2 +-
 4 files changed, 145 insertions(+), 123 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index b6e793bb653c..6cb57807f3f9 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -226,7 +227,7 @@ struct dw_mipi_dsi {
struct mipi_dsi_host dsi_host;
struct drm_bridge *panel_bridge;
struct device *dev;
-   void __iomem *base;
+   struct regmap *regs;
 
struct clk *pclk;
 
@@ -249,6 +250,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
 };
 
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+   .reg_bits = 32,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .name = "dw-mipi-dsi",
+};
+
 /*
  * Check if either a link to a master or slave is present
  */
@@ -280,16 +288,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct 
drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
 }
 
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
-   writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
-   return readl(dsi->base + reg);
-}
-
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
   struct mipi_dsi_device *device)
 {
@@ -366,29 +364,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi 
*dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
-   dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+   regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+   regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 {
int ret;
-   u32 val, mask;
+   u32 val = 0, mask;
 
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, !(val & GEN_CMD_FULL), 1000,
-CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, !(val & GEN_CMD_FULL), 1000,
+  CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
 
-   dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+   regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
 
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-   ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
-val, (val & mask) == mask,
-1000, CMD_PKT_STATUS_TIMEOUT_US);
+   ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+  val, (val & mask) == mask,
+  1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -403,24 +401,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
const u8 *tx_buf = packet->payload;
int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
__le32 word;
-   u32 val;
+   u32 val = 0;
 
while (len) {
if (len < pld_data_bytes) {
word = 0;
memcpy(, tx_buf, len);
-   dsi_write(dsi, DSI_GEN_PL

[PATCH v2 4/4] dt-bindings: display: add IMX MIPI DSI host controller doc

2019-11-06 Thread Adrian Ratiu

Reviewed-by: Neil Armstrong 
Reviewed-by: Emil Velikov 
Signed-off-by: Sjoerd Simons 
Signed-off-by: Martyn Welch 
Signed-off-by: Adrian Ratiu 
---
 .../bindings/display/imx/mipi-dsi.txt | 56 +++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt

diff --git a/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt 
b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt
new file mode 100644
index ..3f05c32ef963
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt
@@ -0,0 +1,56 @@
+Freescale i.MX6 DW MIPI DSI Host Controller
+===
+
+The DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+the following device-specific properties.
+
+Required properties:
+
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi".
+- reg: See dw_mipi_dsi.txt.
+- interrupts: The controller's CPU interrupt.
+- clocks, clock-names: Phandles to the controller's pll reference
+  clock(ref) and APB clock(pclk), as described in [1].
+- ports: a port node with endpoint definitions as defined in [2].
+- gpr: Should be <>.
+   Phandle to the iomuxc-gpr region containing the multiplexer
+   control register.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   mipi_dsi: mipi@21e {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+   reg = <0x021e 0x4000>;
+   interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+   gpr = <>;
+   clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_IPG>;
+   clock-names = "ref", "pclk";
+   status = "okay";
+
+   ports {
+   port@0 {
+   reg = <0>;
+   mipi_mux_0: endpoint {
+   remote-endpoint = <_di0_mipi>;
+   };
+   };
+   port@1 {
+   reg = <1>;
+   mipi_mux_1: endpoint {
+   remote-endpoint = <_di1_mipi>;
+   };
+   };
+   };
+};
-- 
2.23.0

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Re: [PATCH 1/4] drm: bridge: dw_mipi_dsi: access registers via a regmap

2019-11-04 Thread Adrian Ratiu

On Mon, 04 Nov 2019, Neil Armstrong  
wrote:
On 31/10/2019 15:26, Adrian Ratiu wrote: 
Convert the common bridge code and the two rockchip & stm 
drivers which currently use it to the regmap API in 
anticipation for further changes to make it more generic and 
add older DSI host controller support as found on i.mx6 based 
devices.   No functional changes other than requiring the 
platform drivers to provide a regmap via their plat_data. Going 
further each platform driver can also add its own regmap 
configuration like for maximum write offsets, r/w callbacks or 
different register layouts.   Suggested-by: Boris Brezillon 
 Signed-off-by: Adrian Ratiu 
 --- 
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 189 
 +- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 
 |  36 +++- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c |  44 
 ++-- include/drm/bridge/dw_mipi_dsi.h  |   2 +- 4 
 files changed, 155 insertions(+), 116 deletions(-) 
 diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 
b6e793bb653c..4ef3e9038cc2 100644 --- 
a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7 
@@ 
 #include  #include  
 #include  
+#include  
 #include   #include  
@@ -226,7 +227,7 @@ struct dw_mipi_dsi { 
 	struct mipi_dsi_host dsi_host; struct drm_bridge 
 *panel_bridge; struct device *dev; 
-	void __iomem *base; +	struct regmap *regs; 
  struct clk *pclk;  
@@ -280,16 +281,6 @@ static inline struct dw_mipi_dsi 
*bridge_to_dsi(struct drm_bridge *bridge) 
 	return container_of(bridge, struct dw_mipi_dsi, bridge); }  
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, 
u32 val) -{ -	writel(val, dsi->base + reg); -} - -static 
inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ - 
return readl(dsi->base + reg); -} - 
 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 
 struct mipi_dsi_device *device) { 
@@ -366,29 +357,29 @@ static void dw_mipi_message_config(struct 
dw_mipi_dsi *dsi, 
 	if (lpm) val |= CMD_MODE_ALL_LP;  
-	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); -	dsi_write(dsi, DSI_CMD_MODE_CFG, 
val); +	regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : 
PHY_TXREQUESTCLKHS); +	regmap_write(dsi->regs, 
DSI_CMD_MODE_CFG, val); 
 }  static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi 
 *dsi, u32 hdr_val) { int ret; 
-	u32 val, mask; +	u32 val = 0, mask; 
  
-	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, - 
val, !(val & GEN_CMD_FULL), 1000, - 
CMD_PKT_STATUS_TIMEOUT_US); +	ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, !(val & GEN_CMD_FULL), 1000, + 
CMD_PKT_STATUS_TIMEOUT_US); 
 	if (ret) { dev_err(dsi->dev, "failed to get available 
 command FIFO\n"); return ret; }  
-	dsi_write(dsi, DSI_GEN_HDR, hdr_val); + 
regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); 
  mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 
-	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, - 
val, (val & mask) == mask, - 1000, 
CMD_PKT_STATUS_TIMEOUT_US); +	ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, (val & mask) == mask, + 
1000, CMD_PKT_STATUS_TIMEOUT_US); 
 	if (ret) { dev_err(dsi->dev, "failed to write command 
 FIFO\n"); return ret; 
@@ -403,24 +394,26 @@ static int dw_mipi_dsi_write(struct 
dw_mipi_dsi *dsi, 
 	const u8 *tx_buf = packet->payload; int len = 
 packet->payload_length, pld_data_bytes = sizeof(u32), ret; 
 __le32 word; 
-	u32 val; +	u32 val = 0; 
  while (len) { if (len < pld_data_bytes) { word = 0; 
 memcpy(, tx_buf, len); 
-			dsi_write(dsi, DSI_GEN_PLD_DATA, 
le32_to_cpu(word)); + 
regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
le32_to_cpu(word)); 
 			len = 0; } else { memcpy(, tx_buf, 
 pld_data_bytes); 
-			dsi_write(dsi, DSI_GEN_PLD_DATA, 
le32_to_cpu(word)); + 
regmap_write(dsi->regs, DSI_GEN_PLD_DATA, + 
le32_to_cpu(word)); 
 			tx_buf += pld_data_bytes; len -= 
 pld_data_bytes; }  
-		ret = readl_poll_timeout(dsi->base + 
DSI_CMD_PKT_STATUS, - 
val, !(val & GEN_PLD_W_FULL), 1000, - 
CMD_PKT_STATUS_TIMEOUT_US); +		ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, !(val & GEN_PLD_W_FULL), + 
1000, CMD_PKT_STATUS_TIMEOUT_US); 
 		if (ret) { dev_err(dsi->dev, "failed to get 
 available write payload FIFO\n"); 
@@ -438,12 +431,12 @@ static int dw_mipi_dsi_read(struct 
dw_mipi_dsi *dsi, 
 { int i, j, ret, len = msg->rx_len; u8 *buf = msg->rx_buf; 
-	u32 val; +	u32 val = 0; 
  /* Wait end of the read operation */ 
-	ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, - 
val, !(val & GEN_RD_CMD_BUSY), - 
1000, CMD_PKT_STATUS_TIMEOUT_US); +	ret = 
regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, + 
val, !(val & GEN_RD_CMD_BUSY), + 
1000, CMD_PKT_STATUS_TIMEOUT_US); 
 	if (ret) { dev_err(dsi->dev, "

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