[PATCH] drm/edid: use for_each_displayid_db where applicable
Replace the duplicated versions of the while loop with the new macro.
Signed-off-by: Andres Rodriguez
Cc: Dave Airlie
---
This patch depends on "drm/edid: parse CEA blocks embedded in DisplayID"
I didn't send them together to avoid grouping the portion that
was cc:stable and the "touch ups" into the same series.
drivers/gpu/drm/drm_edid.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a4e3f6b22dbb..5ff046175478 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4730,11 +4730,7 @@ static int add_displayid_detailed_modes(struct
drm_connector *connector,
return 0;
idx += sizeof(struct displayid_hdr);
- while (block = (struct displayid_block *)&displayid[idx],
- idx + sizeof(struct displayid_block) <= length &&
- idx + sizeof(struct displayid_block) + block->num_bytes <=
length &&
- block->num_bytes > 0) {
- idx += block->num_bytes + sizeof(struct displayid_block);
+ for_each_displayid_db(displayid, block, idx, length) {
switch (block->tag) {
case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
num_modes += add_displayid_detailed_1_modes(connector,
block);
@@ -5279,11 +5275,7 @@ static int drm_parse_display_id(struct drm_connector
*connector,
return ret;
idx += sizeof(struct displayid_hdr);
- while (block = (struct displayid_block *)&displayid[idx],
- idx + sizeof(struct displayid_block) <= length &&
- idx + sizeof(struct displayid_block) + block->num_bytes <=
length &&
- block->num_bytes > 0) {
- idx += block->num_bytes + sizeof(struct displayid_block);
+ for_each_displayid_db(displayid, block, idx, length) {
DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
block->tag, block->rev, block->num_bytes);
--
2.19.1
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[PATCH] drm/edid: parse CEA blocks embedded in DisplayID
DisplayID blocks allow embedding of CEA blocks. The payloads are
identical to traditional top level CEA extension blocks, but the header
is slightly different.
This change allows the CEA parser to find a CEA block inside a DisplayID
block. Additionally, it adds support for parsing the embedded CTA
header. No further changes are necessary due to payload parity.
This change fixes audio support for the Valve Index HMD.
Signed-off-by: Andres Rodriguez
Cc: Dave Airlie
Cc: Jani Nikula
Cc: # v4.15
---
drivers/gpu/drm/drm_edid.c | 81 -
include/drm/drm_displayid.h | 10 +
2 files changed, 80 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 649cfd8b4200..a4e3f6b22dbb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1339,6 +1339,7 @@ MODULE_PARM_DESC(edid_fixup,
static void drm_get_displayid(struct drm_connector *connector,
struct edid *edid);
+static int validate_displayid(u8 *displayid, int length, int idx);
static int drm_edid_block_checksum(const u8 *raw_edid)
{
@@ -2883,16 +2884,46 @@ static u8 *drm_find_edid_extension(const struct edid
*edid, int ext_id)
return edid_ext;
}
-static u8 *drm_find_cea_extension(const struct edid *edid)
-{
- return drm_find_edid_extension(edid, CEA_EXT);
-}
static u8 *drm_find_displayid_extension(const struct edid *edid)
{
return drm_find_edid_extension(edid, DISPLAYID_EXT);
}
+static u8 *drm_find_cea_extension(const struct edid *edid)
+{
+ int ret;
+ int idx = 1;
+ int length = EDID_LENGTH;
+ struct displayid_block *block;
+ u8 *cea;
+ u8 *displayid;
+
+ /* Look for a top level CEA extension block */
+ cea = drm_find_edid_extension(edid, CEA_EXT);
+ if (cea)
+ return cea;
+
+ /* CEA blocks can also be found embedded in a DisplayID block */
+ displayid = drm_find_displayid_extension(edid);
+ if (!displayid)
+ return NULL;
+
+ ret = validate_displayid(displayid, length, idx);
+ if (ret)
+ return NULL;
+
+ idx += sizeof(struct displayid_hdr);
+ for_each_displayid_db(displayid, block, idx, length) {
+ if (block->tag == DATA_BLOCK_CTA) {
+ cea = (u8 *)block;
+ break;
+ }
+ }
+
+ return cea;
+}
+
/*
* Calculate the alternate clock for the CEA mode
* (60Hz vs. 59.94Hz etc.)
@@ -3616,13 +3647,38 @@ cea_revision(const u8 *cea)
static int
cea_db_offsets(const u8 *cea, int *start, int *end)
{
- /* Data block offset in CEA extension block */
- *start = 4;
- *end = cea[2];
- if (*end == 0)
- *end = 127;
- if (*end < 4 || *end > 127)
- return -ERANGE;
+
+ /* DisplayID CTA extension blocks and top-level CEA EDID
+* block header definitions differ in the following bytes:
+* 1) Byte 2 of the header specifies length differently,
+* 2) Byte 3 is only present in the CEA top level block.
+*
+* The different definitions for byte 2 follow.
+*
+* DisplayID CTA extension block defines byte 2 as:
+* Number of payload bytes
+*
+* CEA EDID block defines byte 2 as:
+* Byte number (decimal) within this block where the 18-byte
+* DTDs begin. If no non-DTD data is present in this extension
+* block, the value should be set to 04h (the byte after next).
+* If set to 00h, there are no DTDs present in this block and
+* no non-DTD data.
+*/
+ if (cea[0] == DATA_BLOCK_CTA) {
+ *start = 3;
+ *end = *start + cea[2];
+ } else if (cea[0] == CEA_EXT) {
+ /* Data block offset in CEA extension block */
+ *start = 4;
+ *end = cea[2];
+ if (*end == 0)
+ *end = 127;
+ if (*end < 4 || *end > 127)
+ return -ERANGE;
+ } else
+ return -ENOTSUPP;
+
return 0;
}
@@ -5240,6 +5296,9 @@ static int drm_parse_display_id(struct drm_connector
*connector,
case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
/* handled in mode gathering code. */
break;
+ case DATA_BLOCK_CTA:
+ /* handled in the cea parser code. */
+ break;
default:
DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n",
block->tag);
break;
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index c0d4df6a606f..9d3b745c3107 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -40,6 +40,7 @@
#define DATA_BLOCK_DIS
[PATCH v2] drm/edid: parse CEA blocks embedded in DisplayID
DisplayID blocks allow embedding of CEA blocks. The payloads are
identical to traditional top level CEA extension blocks, but the header
is slightly different.
This change allows the CEA parser to find a CEA block inside a DisplayID
block. Additionally, it adds support for parsing the embedded CTA
header. No further changes are necessary due to payload parity.
This change enables audio support for the Valve Index HMD.
Signed-off-by: Andres Rodriguez
---
v2: Review feedback from Jani.
drivers/gpu/drm/drm_edid.c | 75 +
include/drm/drm_displayid.h | 10 +
2 files changed, 77 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 649cfd8b4200..8ecd7f70825d 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1339,6 +1339,8 @@ MODULE_PARM_DESC(edid_fixup,
static void drm_get_displayid(struct drm_connector *connector,
struct edid *edid);
+static u8 *drm_find_displayid_extension(const struct edid *edid);
+static int validate_displayid(u8 *displayid, int length, int idx);
static int drm_edid_block_checksum(const u8 *raw_edid)
{
@@ -2885,7 +2887,36 @@ static u8 *drm_find_edid_extension(const struct edid
*edid, int ext_id)
static u8 *drm_find_cea_extension(const struct edid *edid)
{
- return drm_find_edid_extension(edid, CEA_EXT);
+ int ret;
+ int idx = 1;
+ int length = EDID_LENGTH;
+ struct displayid_block *block;
+ u8 *cea;
+ u8 *displayid;
+
+ /* Look for a top level CEA extension block */
+ cea = drm_find_edid_extension(edid, CEA_EXT);
+ if (cea)
+ return cea;
+
+ /* CEA blocks can also be found embedded in a DisplayID block */
+ displayid = drm_find_displayid_extension(edid);
+ if (!displayid)
+ return NULL;
+
+ ret = validate_displayid(displayid, length, idx);
+ if (ret)
+ return NULL;
+
+ idx += sizeof(struct displayid_hdr);
+ for_each_displayid_db(displayid, block, idx, length) {
+ if (block->tag == DATA_BLOCK_CTA) {
+ cea = (u8 *)block;
+ break;
+ }
+ }
+
+ return cea;
}
static u8 *drm_find_displayid_extension(const struct edid *edid)
@@ -3616,13 +3647,38 @@ cea_revision(const u8 *cea)
static int
cea_db_offsets(const u8 *cea, int *start, int *end)
{
- /* Data block offset in CEA extension block */
- *start = 4;
- *end = cea[2];
- if (*end == 0)
- *end = 127;
- if (*end < 4 || *end > 127)
- return -ERANGE;
+
+ /* DisplayID CTA extension blocks and top-level CEA EDID
+* block header definitions differ in the following bytes:
+* 1) Byte 2 of the header specifies length differently,
+* 2) Byte 3 is only present in the CEA top level block.
+*
+* The different definitions for byte 2 follow.
+*
+* DisplayID CTA extension block defines byte 2 as:
+* Number of payload bytes
+*
+* CEA EDID block defines byte 2 as:
+* Byte number (decimal) within this block where the 18-byte
+* DTDs begin. If no non-DTD data is present in this extension
+* block, the value should be set to 04h (the byte after next).
+* If set to 00h, there are no DTDs present in this block and
+* no non-DTD data.
+*/
+ if (cea[0] == DATA_BLOCK_CTA) {
+ *start = 3;
+ *end = *start + cea[2];
+ } else if (cea[0] == CEA_EXT) {
+ /* Data block offset in CEA extension block */
+ *start = 4;
+ *end = cea[2];
+ if (*end == 0)
+ *end = 127;
+ if (*end < 4 || *end > 127)
+ return -ERANGE;
+ } else
+ return -ENOTSUPP;
+
return 0;
}
@@ -5240,6 +5296,9 @@ static int drm_parse_display_id(struct drm_connector
*connector,
case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
/* handled in mode gathering code. */
break;
+ case DATA_BLOCK_CTA:
+ /* handled in the cea parser code. */
+ break;
default:
DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n",
block->tag);
break;
diff --git a/include/drm/drm_displayid.h b/include/drm/drm_displayid.h
index c0d4df6a606f..9d3b745c3107 100644
--- a/include/drm/drm_displayid.h
+++ b/include/drm/drm_displayid.h
@@ -40,6 +40,7 @@
#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
#define DATA_BLOCK_TILED_DISPLAY 0x12
+#define DATA_BLOCK_CTA 0x81
#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
[PATCH] drm/edid: parse CEA blocks embedded in DisplayID
DisplayID blocks allow embedding of CEA blocks. The payloads are
identical to traditional top level CEA extension blocks, but the header
is slightly different.
This change allows the CEA parser to find a CEA block inside a DisplayID
block. Additionally, it adds support for parsing the embedded CTA
header. No further changes are necessary due to payload parity.
This change enables audio support for the Valve Index HMD.
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/drm_edid.c | 79 +
include/drm/drm_displayid.h | 1 +
2 files changed, 72 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 649cfd8b4200..3e71c6ae48d4 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1339,6 +1339,8 @@ MODULE_PARM_DESC(edid_fixup,
static void drm_get_displayid(struct drm_connector *connector,
struct edid *edid);
+static u8 *drm_find_displayid_extension(const struct edid *edid);
+static int validate_displayid(u8 *displayid, int length, int idx);
static int drm_edid_block_checksum(const u8 *raw_edid)
{
@@ -2885,7 +2887,40 @@ static u8 *drm_find_edid_extension(const struct edid
*edid, int ext_id)
static u8 *drm_find_cea_extension(const struct edid *edid)
{
- return drm_find_edid_extension(edid, CEA_EXT);
+ int ret;
+ int idx = 1;
+ int length = EDID_LENGTH;
+ struct displayid_block *block;
+ u8 *cea = NULL;
+ u8 *displayid = NULL;
+
+ cea = drm_find_edid_extension(edid, CEA_EXT);
+
+ /* CEA blocks can also be found embedded in a DisplayID block */
+ if (!cea) {
+ displayid = drm_find_displayid_extension(edid);
+ if (!displayid)
+ return NULL;
+
+ ret = validate_displayid(displayid, length, idx);
+ if (ret)
+ return NULL;
+
+ idx += sizeof(struct displayid_hdr);
+ while (block = (struct displayid_block *)&displayid[idx],
+ idx + sizeof(struct displayid_block) <= length &&
+ idx + sizeof(struct displayid_block) + block->num_bytes
<= length &&
+ block->num_bytes > 0) {
+ idx += block->num_bytes + sizeof(struct
displayid_block);
+ switch (block->tag) {
+ case DATA_BLOCK_CTA:
+ cea = (u8 *)block;
+ break;
+ }
+ }
+ }
+
+ return cea;
}
static u8 *drm_find_displayid_extension(const struct edid *edid)
@@ -3616,13 +3651,38 @@ cea_revision(const u8 *cea)
static int
cea_db_offsets(const u8 *cea, int *start, int *end)
{
- /* Data block offset in CEA extension block */
- *start = 4;
- *end = cea[2];
- if (*end == 0)
- *end = 127;
- if (*end < 4 || *end > 127)
- return -ERANGE;
+
+ /* DisplayID CTA extension blocks and top-level CEA EDID
+* blocks headers differ in two byte definitions:
+* 1) Byte 2 of the header specifies length differently,
+* 2) Byte 3 is only present in the CEA top level block.
+*
+* The different definitions for byte 2 follow.
+*
+* DisplayID CTA extension block defines byte 2 as:
+* Number of payload bytes
+*
+* CEA EDID block defines byte 2 as:
+* Byte number (decimal) within this block where the 18-byte
+* DTDs begin. If no non-DTD data is present in this extension
+* block, the value should be set to 04h (the byte after next).
+* If set to 00h, there are no DTDs present in this block and
+* no non-DTD data.
+*/
+ if (cea[0] == DATA_BLOCK_CTA) {
+ *start = 3;
+ *end = *start + cea[2];
+ } else if (cea[0] == CEA_EXT) {
+ *start = 4;
+ *end = cea[2];
+ /* Data block offset in CEA extension block */
+ if (*end == 0)
+ *end = 127;
+ if (*end < 4 || *end > 127)
+ return -ERANGE;
+ } else
+ return -ENOTSUPP;
+
return 0;
}
@@ -5240,6 +5300,9 @@ static int drm_parse_display_id(struct drm_connector
*connector,
case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
/* handled in mode gathering code. */
break;
+ case DATA_BLOCK_CTA:
+ /* handled in the cea parser code. */
+ break;
default:
DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n",
block->tag);
break;
diff --git a/include/drm/drm_displayid.h b/include
[PATCH] drm: add non-desktop quirk for Valve HMDs
Add vendor/product pairs for the Valve Index HMDs.
Signed-off-by: Andres Rodriguez
Cc: Dave Airlie
Cc: # v4.15
---
drivers/gpu/drm/drm_edid.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 2c22ea446075..649cfd8b4200 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -162,6 +162,25 @@ static const struct edid_quirk {
/* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
{ "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
+ /* Valve Index Headset */
+ { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
+ { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
+
/* HTC Vive and Vive Pro VR Headsets */
{ "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
{ "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
--
2.19.1
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Re: [PATCH libdrm] amdgpu: Add context priority override function.
On 2019-04-17 2:33 p.m., Bas Nieuwenhuizen wrote:
This way we can override the priority of a single context using a
master fd.
Since we cannot usefully create an amdgpu device of a master fd
without the fd deduplication kicking in this takes a plain fd.
This can be used by e.g. radv to get high priority contexts using
a master fd from the primary node or a lease
---
amdgpu/amdgpu-symbol-check | 1 +
amdgpu/amdgpu.h| 15 +++
amdgpu/amdgpu_cs.c | 25 +
3 files changed, 41 insertions(+)
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 96a44b40..4d806922 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -38,6 +38,7 @@ amdgpu_cs_create_syncobj2
amdgpu_cs_ctx_create
amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
+amdgpu_cs_ctx_override_priority
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index d6de3b8d..3d838e08 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -911,6 +911,21 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
*/
int amdgpu_cs_ctx_free(amdgpu_context_handle context);
+/**
+ * Override the submission priority for the given context using a master fd.
+ *
+ * \param dev - \c [in] device handle
Minor indentation misalignment here.
+ * \param context- \c [in] context handle for context id
+ * \param master_fd - \c [in] The master fd to authorize the override.
+ * \param priority - \c [in] The priority to assign to the context.
+ *
+ * \return 0 on success or a a negative Posix error code on failure.
+ */
+int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
+amdgpu_context_handle context,
+int master_fd,
+unsigned priority);
+
/**
* Query reset state for the specific GPU Context
*
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 5bedf748..7ee844fb 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -142,6 +142,31 @@ drm_public int amdgpu_cs_ctx_free(amdgpu_context_handle
context)
return r;
}
+drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
+ amdgpu_context_handle context,
+ int master_fd,
+ unsigned priority)
+{
+ int r;
+
+ if (!dev || !context || master_fd < 0)
+ return -EINVAL;
+
+ union drm_amdgpu_sched args;
+ memset(&args, 0, sizeof(args));
+
+ args.in.op = AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE;
+ args.in.fd = dev->fd;
+ args.in.priority = priority;
+ args.in.ctx_id = context->id;
+
+ r = drmCommandWrite(master_fd, DRM_AMDGPU_SCHED, &args, sizeof(args));
I'm assuming there is no other initialization required before this
command can be executed on the master_fd.
If so, this changed is:
Reviewed-by: Andres Rodriguez
+ if (r)
+ return r;
+
+ return 0;
+}
+
drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
uint32_t *state, uint32_t *hangs)
{
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[PATCH] drm/amdgpu: fix drm leases being broken on radv
After a recent commit, access to the DRM_AUTH ioctls become more
permissive. This resulted in a buggy check for drm_master capabilities
inside radv stop working.
This commit adds a backwards compatibility workaround so that the radv
drm_master check keeps working as previously expected.
This fixes SteamVR and other drm lease based apps being broken since
v5.1-rc1
From the usermode side, radv will also be fixed to properly test for
master capabilities:
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/669
Fixes: 8059add0478e ("drm: allow render capable master with DRM_AUTH ioctls")
Signed-off-by: Andres Rodriguez
Cc: Daniel Vetter
Cc: David Airlie
Cc: Emil Velikov
Cc: Alex Deucher
Cc: Keith Packard
Reviewed-by: Keith Packard
Reviewed-by: Daniel Vetter
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 22 ++
3 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8d0d7f3dd5fb..e67bfee8d411 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -409,6 +409,9 @@ struct amdgpu_fpriv {
struct mutexbo_list_lock;
struct idr bo_list_handles;
struct amdgpu_ctx_mgr ctx_mgr;
+
+ /* Part of a backwards compatibility hack */
+ boolis_first_ioctl;
};
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7419ea8a388b..cd438afa7092 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1128,6 +1128,7 @@ long amdgpu_drm_ioctl(struct file *filp,
unsigned int cmd, unsigned long arg)
{
struct drm_file *file_priv = filp->private_data;
+ struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct drm_device *dev;
long ret;
dev = file_priv->minor->dev;
@@ -1136,6 +1137,7 @@ long amdgpu_drm_ioctl(struct file *filp,
return ret;
ret = drm_ioctl(filp, cmd, arg);
+ fpriv->is_first_ioctl = false;
pm_runtime_mark_last_busy(dev->dev);
pm_runtime_put_autosuspend(dev->dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e860412043bb..00c0a2fb2a69 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -455,6 +455,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct
drm_file *filp)
{
struct amdgpu_device *adev = dev->dev_private;
+ struct amdgpu_fpriv *fpriv = filp->driver_priv;
struct drm_amdgpu_info *info = data;
struct amdgpu_mode_info *minfo = &adev->mode_info;
void __user *out = (void __user *)(uintptr_t)info->return_pointer;
@@ -470,6 +471,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
switch (info->query) {
case AMDGPU_INFO_ACCEL_WORKING:
+ /* HACK: radv has a fragile open-coded check for drm master
+* The pattern for the call is:
+* open(DRM_NODE_PRIMARY)
+* drmModeCommandWrite( query=AMDGPU_INFO_ACCEL_WORKING )
+*
+* After commit 8059add04 this check stopped working due to
+* operations on a primary node from non-master clients becoming
+* more permissive.
+*
+* This backwards compatibility hack targets the calling pattern
+* above to fail radv from thinking it has master access to the
+* display system ( without reverting 8059add04 ).
+*
+* Users of libdrm will not be affected as some other ioctls are
+* performed between open() and the AMDGPU_INFO_ACCEL_WORKING
+* query.
+*/
+ if (fpriv->is_first_ioctl && !filp->is_master)
+ return -EACCES;
+
ui32 = adev->accel_working;
return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
case AMDGPU_INFO_CRTC_FROM_ID:
@@ -987,6 +1008,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct
drm_file *file_priv)
goto error_vm;
}
+ fpriv->is_first_ioctl = true;
mutex_init(&fpriv->bo_list_lock);
idr_init(&fpriv->bo_list_handles);
--
2.19.1
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Re: [PATCH] drm/amdgpu: cleanup firmware requests v2
Ping.
On 2018-04-17 06:12 PM, Andres Rodriguez wrote:
Add a new function amdgpu_ucode_request_firmware() that encapsulates a
lot of the common behaviour we have around firmware requests.
This is the first step in my quest to get rid of the following annoying
messages when my polaris10 boots up:
[0.558537] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_pfp_2.bin failed with error -2
[0.558551] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_me_2.bin failed with error -2
[0.558562] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_ce_2.bin failed with error -2
[0.558580] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_mec_2.bin failed with error -2
[0.558619] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_mec2_2.bin failed with error -2
v2: make amdgpu_ucode_validate file scope only
add kernel-doc for amdgpu_ucode_request_firmware()
Signed-off-by: Andres Rodriguez
---
Sorry for the quick V2, noticed some docs might help and that
_validate() could be reduced in scope. Pasting my old message
again just in case.
Hey Christian,
Wanted to go through a cleanup of the ucode loading in amdgpu
to facilitate some of our heated discussions :)
For now, functionality should remain the same. Once _nowarn()
lands we can change amdgpu_ucode_request_firmware() with either:
Alternative A:
- err = request_firmware(&loaded_fw, name, adev->dev);
+ err = request_firmware_nowarn(&loaded_fw, name, adev->dev);
Alternative B:
- err = request_firmware(&loaded_fw, name, adev->dev);
+ if (optional)
+ err = request_firmware_nowarn(&loaded_fw, name, adev->dev);
+ else
+ err = request_firmware(&loaded_fw, name, adev->dev);
I prefer A, but I'm not opposed to B. I'll leave it up to you.
Regards,
Andres
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 14 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 74 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c| 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 16 +
drivers/gpu/drm/amd/amdgpu/ci_dpm.c| 15 +---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 112 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 17 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 18 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 15 +---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c| 16 +
22 files changed, 164 insertions(+), 325 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a8a942c60ea2..347ab1710523 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -402,19 +402,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device
*cgs_device,
return -EINVAL;
}
- err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
- if (err) {
- DRM_ERROR("Failed to request firmware\n");
+ err = amdgpu_ucode_request_firmware(adev, &adev->pm.fw,
fw_name, false);
+ if (err)
return err;
- }
-
- err = amdgpu_ucode_validate(adev->pm.fw);
- if (err) {
- DRM_ERROR("Failed to load firmware \"%s\"",
fw_name);
- release_firmware(adev->pm.fw);
- adev->pm.fw = NULL;
- return err;
- }
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
ucode =
&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abc33464959e..967e14f14abc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1355,20 +1355,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
}
snprintf(fw_name, siz
[PATCH] drm/amdgpu: cleanup firmware requests v2
Add a new function amdgpu_ucode_request_firmware() that encapsulates a
lot of the common behaviour we have around firmware requests.
This is the first step in my quest to get rid of the following annoying
messages when my polaris10 boots up:
[0.558537] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_pfp_2.bin failed with error -2
[0.558551] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_me_2.bin failed with error -2
[0.558562] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_ce_2.bin failed with error -2
[0.558580] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_mec_2.bin failed with error -2
[0.558619] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_mec2_2.bin failed with error -2
v2: make amdgpu_ucode_validate file scope only
add kernel-doc for amdgpu_ucode_request_firmware()
Signed-off-by: Andres Rodriguez
---
Sorry for the quick V2, noticed some docs might help and that
_validate() could be reduced in scope. Pasting my old message
again just in case.
Hey Christian,
Wanted to go through a cleanup of the ucode loading in amdgpu
to facilitate some of our heated discussions :)
For now, functionality should remain the same. Once _nowarn()
lands we can change amdgpu_ucode_request_firmware() with either:
Alternative A:
- err = request_firmware(&loaded_fw, name, adev->dev);
+ err = request_firmware_nowarn(&loaded_fw, name, adev->dev);
Alternative B:
- err = request_firmware(&loaded_fw, name, adev->dev);
+ if (optional)
+ err = request_firmware_nowarn(&loaded_fw, name, adev->dev);
+ else
+ err = request_firmware(&loaded_fw, name, adev->dev);
I prefer A, but I'm not opposed to B. I'll leave it up to you.
Regards,
Andres
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 14 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 74 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c| 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 16 +
drivers/gpu/drm/amd/amdgpu/ci_dpm.c| 15 +---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 112 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 17 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 18 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 15 +---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c| 16 +
22 files changed, 164 insertions(+), 325 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a8a942c60ea2..347ab1710523 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -402,19 +402,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device
*cgs_device,
return -EINVAL;
}
- err = request_firmware(&adev->pm.fw, fw_name,
adev->dev);
- if (err) {
- DRM_ERROR("Failed to request firmware\n");
+ err = amdgpu_ucode_request_firmware(adev, &adev->pm.fw,
fw_name, false);
+ if (err)
return err;
- }
-
- err = amdgpu_ucode_validate(adev->pm.fw);
- if (err) {
- DRM_ERROR("Failed to load firmware \"%s\"",
fw_name);
- release_firmware(adev->pm.fw);
- adev->pm.fw = NULL;
- return err;
- }
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
ucode =
&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abc33464959e..967e14f14abc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1355,20 +1355,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
}
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_inf
[PATCH] drm/amdgpu: cleanup firmware requests
Add a new function amdgpu_ucode_request_firmware() that encapsulates a
lot of the common behaviour we have around firmware requests.
This is the first step in my quest to get rid of the following annoying
messages when my polaris10 boots up:
[0.558537] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_pfp_2.bin failed with error -2
[0.558551] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_me_2.bin failed with error -2
[0.558562] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_ce_2.bin failed with error -2
[0.558580] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_mec_2.bin failed with error -2
[0.558619] amdgpu :01:00.0: Direct firmware load for
amdgpu/polaris10_mec2_2.bin failed with error -2
Signed-off-by: Andres Rodriguez
---
Hey Christian,
Wanted to go through a cleanup of the ucode loading in amdgpu
to facilitate some of our heated discussions :)
For now, functionality should remain the same. Once _nowarn()
lands we can change amdgpu_ucode_request_firmware() with either:
Alternative A:
- err = request_firmware(&loaded_fw, name, adev->dev);
+ err = request_firmware_nowarn(&loaded_fw, name, adev->dev);
Alternative B:
- err = request_firmware(&loaded_fw, name, adev->dev);
+ if (optional)
+ err = request_firmware_nowarn(&loaded_fw, name, adev->dev);
+ else
+ err = request_firmware(&loaded_fw, name, adev->dev);
I prefer A, but I'm not opposed to B. I'll leave it up to you.
Regards,
Andres
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c| 14 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 39 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c| 16 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c| 16 +
drivers/gpu/drm/amd/amdgpu/ci_dpm.c| 15 +---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 +-
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 30 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 112 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 17 +
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 18 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 15 +---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +-
drivers/gpu/drm/amd/amdgpu/si_dpm.c| 16 +
22 files changed, 139 insertions(+), 314 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a8a942c60ea2..347ab1710523 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -402,19 +402,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device
*cgs_device,
return -EINVAL;
}
- err = request_firmware(&adev->pm.fw, fw_name,
adev->dev);
- if (err) {
- DRM_ERROR("Failed to request firmware\n");
+ err = amdgpu_ucode_request_firmware(adev, &adev->pm.fw,
fw_name, false);
+ if (err)
return err;
- }
-
- err = amdgpu_ucode_validate(adev->pm.fw);
- if (err) {
- DRM_ERROR("Failed to load firmware \"%s\"",
fw_name);
- release_firmware(adev->pm.fw);
- adev->pm.fw = NULL;
- return err;
- }
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
ucode =
&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index abc33464959e..967e14f14abc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1355,20 +1355,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
}
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
- err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
- if (err) {
- dev_err(adev->dev,
- "Failed to load g
[PATCH libdrm 1/2] headers: Sync amdgpu_drm.h with drm-next
Generated using make headers_install from:
airlied/drm-next 282dc83 Merge tag 'drm-intel-next-2017-10-12' ...
Signed-off-by: Andres Rodriguez
---
include/drm/amdgpu_drm.h | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 4c6e8c4..ff01818 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -53,6 +53,7 @@ extern "C" {
#define DRM_AMDGPU_WAIT_FENCES 0x12
#define DRM_AMDGPU_VM 0x13
#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
+#define DRM_AMDGPU_SCHED 0x15
#define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -69,6 +70,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
#define DRM_IOCTL_AMDGPU_VMDRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
+#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE +
DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -91,6 +93,8 @@ extern "C" {
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
+/* Flag that BO sharing will be explicitly synchronized */
+#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC(1 << 7)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -166,13 +170,22 @@ union drm_amdgpu_bo_list {
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
+/* Context priority level */
+#define AMDGPU_CTX_PRIORITY_UNSET -2048
+#define AMDGPU_CTX_PRIORITY_VERY_LOW-1023
+#define AMDGPU_CTX_PRIORITY_LOW -512
+#define AMDGPU_CTX_PRIORITY_NORMAL 0
+/* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
+#define AMDGPU_CTX_PRIORITY_HIGH512
+#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
+
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
/** For future use, no flags defined so far */
__u32 flags;
__u32 ctx_id;
- __u32 _pad;
+ __s32 priority;
};
union drm_amdgpu_ctx_out {
@@ -216,6 +229,21 @@ union drm_amdgpu_vm {
struct drm_amdgpu_vm_out out;
};
+/* sched ioctl */
+#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
+
+struct drm_amdgpu_sched_in {
+ /* AMDGPU_SCHED_OP_* */
+ __u32 op;
+ __u32 fd;
+ __s32 priority;
+ __u32 flags;
+};
+
+union drm_amdgpu_sched {
+ struct drm_amdgpu_sched_in in;
+};
+
/*
* This is not a reliable API and you should expect it to fail for any
* number of reasons and have fallback path that do not use userptr to
@@ -629,6 +657,7 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
+#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
--
2.9.3
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[PATCH libdrm 2/2] amdgpu: implement context priority for amdgpu_cs_ctx_create2 v3
Add a new context creation function that allows specifying the context
priority.
A high priority context has the potential of starving lower priority
contexts. The current kernel driver implementation allows only apps
that hold CAP_SYS_NICE or DRM_MASTER to acquire a priority above
AMDGPU_CTX_PRIORITY_NORMAL.
v2: corresponding changes for kernel patch v2
v3: Fixed 'make check' symbol error
Signed-off-by: Andres Rodriguez
---
amdgpu/amdgpu-symbol-check | 1 +
amdgpu/amdgpu.h| 17 +++--
amdgpu/amdgpu_cs.c | 17 +
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index d9f89ef..095c3a0 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -30,6 +30,7 @@ amdgpu_cs_chunk_fence_to_dep
amdgpu_cs_create_semaphore
amdgpu_cs_create_syncobj
amdgpu_cs_ctx_create
+amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 23cde10..ecc975f 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -798,8 +798,9 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
* context will always be executed in order (first come, first serve).
*
*
- * \param dev- \c [in] Device handle. See
#amdgpu_device_initialize()
- * \param context - \c [out] GPU Context handle
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ * \param priority - \c [in] Context creation flags. See
AMDGPU_CTX_PRIORITY_*
+ * \param context - \c [out] GPU Context handle
*
* \return 0 on success\n
* <0 - Negative POSIX Error code
@@ -807,6 +808,18 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
* \sa amdgpu_cs_ctx_free()
*
*/
+int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
+uint32_t priority,
+amdgpu_context_handle *context);
+/**
+ * Create GPU execution Context
+ *
+ * Refer to amdgpu_cs_ctx_create2 for full documentation. This call
+ * is missing the priority parameter.
+ *
+ * \sa amdgpu_cs_ctx_create2()
+ *
+*/
int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
amdgpu_context_handle *context);
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 9577d5c..b9fc01e 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -46,13 +46,14 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
/**
* Create command submission context
*
- * \param dev - \c [in] amdgpu device handle
- * \param context - \c [out] amdgpu context handle
+ * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
+ * \param priority - \c [in] Context creation flags. See
AMDGPU_CTX_PRIORITY_*
+ * \param context - \c [out] GPU Context handle
*
* \return 0 on success otherwise POSIX Error code
*/
-int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
-amdgpu_context_handle *context)
+int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, uint32_t priority,
+ amdgpu_context_handle
*context)
{
struct amdgpu_context *gpu_context;
union drm_amdgpu_ctx args;
@@ -75,6 +76,8 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
/* Create the context */
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
+ args.in.priority = priority;
+
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
if (r)
goto error;
@@ -94,6 +97,12 @@ error:
return r;
}
+int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
+amdgpu_context_handle *context)
+{
+ return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context);
+}
+
/**
* Release command submission context
*
--
2.9.3
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Re: XDC 2017 feedback
Hi, A small piece of feedback from those of us watching remotely. It would be nice to have a simple to access index for the long livestream videos. I think the XDC 2017 wiki page would be a good place for this information. A brief example: Presentation Title | Presenter Name | Link with timestamp ---||- ...| ...| youtu.be/video-id?t=XhYmZs Or alternatively, a list of hyperlinks with the presentation title as text that point to the correct timestamp in the video would also be sufficient. Really enjoyed the talks, and would like them to be slightly easier to access and share with others. Regards, Andres On 2017-09-26 12:57 PM, Daniel Vetter wrote: Hi all, First again big thanks to Stéphane and Jennifer for organizing a great XDC. Like last year we'd like to hear feedback on how this year's XDC went, both the good (and what you'd like to see more of) and the not so good. Talk selection, organization, location, scheduling of talks, anything really. Here's a few things we took into account from Helsinki and tried to apply: - More breaks for more hallway track. - Try to schedule the hot topics on the first day (did we pick the right ones) for better hallway track. - More lightning talk time to give all the late/rejected submissions some place to give a quick showcase. Things that didn't work out perfectly this year and that we'll try to get better at next year: - Lots of people missed the submission deadline and their talks were rejected only because of that. We'll do better PR by sending out a pile of reminders. - Comparitively few people asked for travel assistance. No idea whether this was a year with more budget around, or whether this isn't all that well know and we need to make more PR in maybe the call for papers about it. But that's just the stuff we've gathered already, we'd like to hear more feedback. Just reply to this mail or send a mail to bo...@foundation.x.org if you don't want the entire world to read it. And if you want to send at pseudonymous feedback, drop a pastebin onto the #xf-bod channel on the OFTC irc server. Thanks, Daniel ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] gpu: drm: amd: amdgpu: remove dead code
On 2017-05-09 08:53 AM, Alex Deucher wrote:
On Mon, May 8, 2017 at 1:01 PM, Gustavo A. R. Silva
wrote:
Local variable use_doorbell is assigned to a constant value and it is never
updated again. Remove this variable and the dead code it guards.
Addresses-Coverity-ID: 1401828
Signed-off-by: Gustavo A. R. Silva
This code is already removed in the latest code queued for the next
kernel for gfx8. For gfx7, I think Andres' priority patch set fixes
this up for gfx7.
Yeah, on gfx7 it should use ring->use_doorbell instead of the hard-coded
local variable.
Andres
Alex
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 53 +--
1 file changed, 20 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 67afc90..e824c2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4991,7 +4991,6 @@ static int gfx_v8_0_cp_compute_resume(struct
amdgpu_device *adev)
{
int r, i, j;
u32 tmp;
- bool use_doorbell = true;
u64 hqd_gpu_addr;
u64 mqd_gpu_addr;
u64 eop_gpu_addr;
@@ -5079,11 +5078,7 @@ static int gfx_v8_0_cp_compute_resume(struct
amdgpu_device *adev)
/* enable doorbell? */
tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
- if (use_doorbell) {
- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_EN, 1);
- } else {
- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_EN, 0);
- }
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_EN, 1);
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
mqd->cp_hqd_pq_doorbell_control = tmp;
@@ -5157,29 +5152,23 @@ static int gfx_v8_0_cp_compute_resume(struct
amdgpu_device *adev)
mqd->cp_hqd_pq_wptr_poll_addr_hi);
/* enable the doorbell if requested */
- if (use_doorbell) {
- if ((adev->asic_type == CHIP_CARRIZO) ||
- (adev->asic_type == CHIP_FIJI) ||
- (adev->asic_type == CHIP_STONEY) ||
- (adev->asic_type == CHIP_POLARIS11) ||
- (adev->asic_type == CHIP_POLARIS10) ||
- (adev->asic_type == CHIP_POLARIS12)) {
- WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
- AMDGPU_DOORBELL_KIQ << 2);
- WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
- AMDGPU_DOORBELL_MEC_RING7 << 2);
- }
- tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
- DOORBELL_OFFSET,
ring->doorbell_index);
- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_EN, 1);
- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_SOURCE, 0);
- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_HIT, 0);
- mqd->cp_hqd_pq_doorbell_control = tmp;
-
- } else {
- mqd->cp_hqd_pq_doorbell_control = 0;
+ if ((adev->asic_type == CHIP_CARRIZO) ||
+ (adev->asic_type == CHIP_FIJI) ||
+ (adev->asic_type == CHIP_STONEY) ||
+ (adev->asic_type == CHIP_POLARIS11) ||
+ (adev->asic_type == CHIP_POLARIS10) ||
+ (adev->asic_type == CHIP_POLARIS12)) {
+ WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ
<< 2);
+ WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
AMDGPU_DOORBELL_MEC_RING7 << 2);
}
+ tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
+ DOORBELL_OFFSET, ring->doorbell_index);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_EN, 1);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_SOURCE, 0);
+ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
DOORBELL_HIT, 0);
+ mqd->cp_hqd_pq_doorbell_control = tmp;
+
WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
mqd->cp_hqd_pq_doorbell_control);
@@ -5217,11 +5206,9 @@ static int gfx_v8_0_cp_compute_resume(struct
amdgpu_device *adev)
amdgpu_bo_unreserve(ring->mqd_obj);
}
- if (use_doorbell) {
- tmp = RREG32(mmCP_PQ_STATUS);
- tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
- WREG32(mmCP_PQ_STATUS, tmp);
- }
+ tmp
[PATCH] dma-buf: avoid scheduling on fence status query v2
When a timeout of zero is specified, the caller is only interested in
the fence status.
In the current implementation, dma_fence_default_wait will always call
schedule_timeout() at least once for an unsignaled fence. This adds a
significant overhead to a fence status query.
Avoid this overhead by returning early if a zero timeout is specified.
v2: move early return after enable_signaling
Signed-off-by: Andres Rodriguez
---
If I'm understanding correctly, I don't think we need to register the
default wait callback. But if that isn't the case please let me know.
This patch has the same perf improvements as v1.
drivers/dma-buf/dma-fence.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 0918d3f..57da14c 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -402,6 +402,11 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr,
signed long timeout)
}
}
+ if (!timeout) {
+ ret = 0;
+ goto out;
+ }
+
cb.base.func = dma_fence_default_wait_cb;
cb.task = current;
list_add(&cb.base.node, &fence->cb_list);
--
2.9.3
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Re: [PATCH] dma-buf: avoid scheduling on fence status query
On 2017-04-26 06:13 AM, Christian König wrote: Am 26.04.2017 um 11:59 schrieb Dave Airlie: On 26 April 2017 at 17:20, Christian König wrote: NAK, I'm wondering how often I have to reject that change. We should probably add a comment here. Even with a zero timeout we still need to enable signaling, otherwise some fence will never signal if userspace just polls on them. If a caller is only interested in the fence status without enabling the signaling it should call dma_fence_is_signaled() instead. Can we not move the return 0 (with spin unlock) down after we enabling signalling, but before we enter the schedule_timeout(1)? Yes, that would be an option. I was actually arguing with Dave about this on IRC yesterday. Seems like I owe him a beer now. -Andres Christian. Dave. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] dma-buf: avoid scheduling on fence status query
CC a few extra lists I missed.
Regards,
Andres
On 2017-04-25 09:36 PM, Andres Rodriguez wrote:
When a timeout of zero is specified, the caller is only interested in
the fence status.
In the current implementation, dma_fence_default_wait will always call
schedule_timeout() at least once for an unsignaled fence. This adds a
significant overhead to a fence status query.
Avoid this overhead by returning early if a zero timeout is specified.
Signed-off-by: Andres Rodriguez
---
This heavily affects the performance of the Source2 engine running on
radv.
This patch improves dota2(radv) perf on a i7-6700k+RX480 system from
72fps->81fps.
drivers/dma-buf/dma-fence.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 0918d3f..348e9e2 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -380,6 +380,9 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr,
signed long timeout)
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
return ret;
+ if (!timeout)
+ return 0;
+
spin_lock_irqsave(fence->lock, flags);
if (intr && signal_pending(current)) {
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[PATCH] dma-buf: avoid scheduling on fence status query
When a timeout of zero is specified, the caller is only interested in
the fence status.
In the current implementation, dma_fence_default_wait will always call
schedule_timeout() at least once for an unsignaled fence. This adds a
significant overhead to a fence status query.
Avoid this overhead by returning early if a zero timeout is specified.
Signed-off-by: Andres Rodriguez
---
This heavily affects the performance of the Source2 engine running on
radv.
This patch improves dota2(radv) perf on a i7-6700k+RX480 system from
72fps->81fps.
drivers/dma-buf/dma-fence.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c
index 0918d3f..348e9e2 100644
--- a/drivers/dma-buf/dma-fence.c
+++ b/drivers/dma-buf/dma-fence.c
@@ -380,6 +380,9 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr,
signed long timeout)
if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))
return ret;
+ if (!timeout)
+ return 0;
+
spin_lock_irqsave(fence->lock, flags);
if (intr && signal_pending(current)) {
--
2.9.3
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Re: [PATCH] drm: Fix get_property logic fumble
On 2017-04-10 08:40 AM, Maarten Lankhorst wrote:
Op 10-04-17 om 13:54 schreef Daniel Vetter:
Yet again I've proven that I can't negate conditions :(
Fixes: eb8eb02ed850 ("drm: Drop modeset_lock_all from the getproperty ioctl")
Cc: Maarten Lankhorst
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Sean Paul
Reported-by: Tvrtko Ursulin
Cc: Tvrtko Ursulin
Signed-off-by: Daniel Vetter
---
drivers/gpu/drm/drm_property.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c
index 3feef0659940..3e88fa24eab3 100644
--- a/drivers/gpu/drm/drm_property.c
+++ b/drivers/gpu/drm/drm_property.c
@@ -476,7 +476,7 @@ int drm_mode_getproperty_ioctl(struct drm_device *dev,
drm_property_type_is(property, DRM_MODE_PROP_BITMASK)) {
list_for_each_entry(prop_enum, &property->enum_list, head) {
enum_count++;
- if (out_resp->count_enum_blobs <= enum_count)
+ if (out_resp->count_enum_blobs < enum_count)
continue;
if (copy_to_user(&enum_ptr[copied].value,
Neither can I, glanced over it while looking why the bisect pointed at this
commit.
Same.
Tested-by: Andres Rodriguez
Fixes segfaults on xorg-video-amdgpu-1.1.2
Reviewed-by: Maarten Lankhorst
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gputool: a tool for debugging AMD GPUs
Hey Everyone, I started a small project called gputool to help me debug issues on AMD platforms. I think it may be useful to other driver devs, so I've made it available on github: https://github.com/lostgoat/gputool Mainly I wanted something that could read and decode registers, so that is what is currently supported. Example operation: |gputool> read CB_HW_CONTROL CB_HW_CONTROL: 0x7208 FORCE_NEEDS_DST: 0x0 DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED: 0x0 DISABLE_BLEND_OPT_DISCARD_PIXEL: 0x0 DISABLE_BLEND_OPT_DONT_RD_DST: 0x0 PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT: 0x0 DISABLE_FULL_WRITE_MASK: 0x0 DISABLE_BLEND_OPT_RESULT_EQ_DEST: 0x0 DISABLE_INTNORM_LE11BPC_CLAMPING: 0x0 DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE: 0x0 ALLOW_MRT_WITH_DUAL_SOURCE: 0x0 DISABLE_CC_IB_SERIALIZER_STATE_OPT: 0x0 PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT: 0x0 FORCE_ALWAYS_TOGGLE: 0x0 FC_CACHE_EVICT_POINT: 0x8 CC_CACHE_EVICT_POINT: 0x7 DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG: 0x0 DISABLE_BLEND_OPT_BYPASS: 0x0 CM_CACHE_EVICT_POINT: 0x8 ||gputool> read PA_SC_RASTER_CONFIG PA_SC_RASTER_CONFIG: 0x1612 RB_XSEL: 0x0 SC_YSEL: 0x0 SC_MAP: 0x0 SC_XSEL: 0x0 SE_YSEL: 0x1 SE_XSEL: 0x1 PKR_YSEL: 0x0 RB_YSEL: 0x0 PKR_XSEL: 0x0 RB_XSEL2: 0x1 PKR_XSEL2: 0x0 SE_MAP: 0x2 RB_MAP_PKR0: 0x2 RB_MAP_PKR1: 0x0 PKR_MAP: 0x0| One of the other things I'm considering adding is register write support, and also dumping textures from vram for inspection. Regards, Andres || ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] amdgpu: fix asic initialization for virtualized environments
When executing in a PCI passthrough based virtuzliation environemnt, the
hypervisor will usually attempt to send a PCIe bus reset signal to the
ASIC when the VM reboots. In this scenario, the card is not correctly
initialized, but we still consider it to be posted. Therefore, in a
passthrough based environemnt we should always post the card to guarantee
it is in a good state for driver initialization.
However, if we are operating in SR-IOV mode it is up to the GIM driver
to manage the asic state, therefore we should not post the card (and
shouldn't be able to do it either).
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++
drivers/gpu/drm/amd/amdgpu/vi.c| 15 +++
4 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 26fe670..fe71dea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1835,6 +1835,8 @@ struct amdgpu_asic_funcs {
/* MM block clocks */
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
+ /* query virtual capabilities */
+ u32 (*get_virtual_caps)(struct amdgpu_device *adev);
};
/*
@@ -1932,8 +1934,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device);
/* GPU virtualization */
+#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
+#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
struct amdgpu_virtualization {
bool supports_sr_iov;
+ bool is_virtual;
+ u32 caps;
};
/*
@@ -2226,6 +2232,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
#define amdgpu_asic_set_uvd_clocks(adev, v, d)
(adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
#define amdgpu_asic_set_vce_clocks(adev, ev, ec)
(adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
+#define amdgpu_asic_get_virtual_caps(adev)
((adev)->asic_funcs->get_virtual_caps((adev)))
#define amdgpu_asic_get_gpu_clock_counter(adev)
(adev)->asic_funcs->get_gpu_clock_counter((adev))
#define amdgpu_asic_read_disabled_bios(adev)
(adev)->asic_funcs->read_disabled_bios((adev))
#define amdgpu_asic_read_bios_from_rom(adev, b, l)
(adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b494212..b98ebac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1392,6 +1392,14 @@ static int amdgpu_resume(struct amdgpu_device *adev)
return 0;
}
+static bool amdgpu_device_is_virtual(void)
+{
+#ifdef CONFIG_X86
+ return boot_cpu_has(X86_FEATURE_HYPERVISOR);
+#else
+ return false;
+#endif
+}
/**
* amdgpu_device_has_dal_support - check if dal is supported
@@ -1560,8 +1568,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->virtualization.supports_sr_iov =
amdgpu_atombios_has_gpu_virtualization_table(adev);
+ /* Check if we are executing in a virtualized environment */
+ adev->virtualization.is_virtual = amdgpu_device_is_virtual();
+ adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
+
/* Post card if necessary */
- if (!amdgpu_card_posted(adev)) {
+ if (!amdgpu_card_posted(adev) ||
+ (adev->virtualization.is_virtual &&
+!adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) {
if (!adev->bios) {
dev_err(adev->dev, "Card not posted and no BIOS -
ignoring\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 40f4fda..907bb28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -963,6 +963,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device
*adev,
return true;
}
+static u32 cik_get_virtual_caps(struct amdgpu_device *adev)
+{
+ /* CIK does not support SR-IOV */
+ return 0;
+}
+
static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[]
= {
{mmGRBM_STATUS, false},
{mmGB_ADDR_CONFIG, false},
@@ -2176,6 +2182,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
.get_xclk = &cik_get_xclk,
.set_uvd_clocks = &cik_set_uvd_clocks,
.set_vce_clocks = &cik_set_vce_clocks,
+ .get_virtual_caps = &cik_get_virtual_caps,
/* these should be moved to their own ip modules */
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
[PATCH] amdgpu: fix asic initialization for virtualized environments
When executing in a PCI passthrough based virtuzliation environemnt, the
hypervisor will usually attempt to send a PCIe bus reset signal to the
ASIC when the VM reboots. In this scenario, the card is not correctly
initialized, but we still consider it to be posted. Therefore, in a
passthrough based environemnt we should always post the card to guarantee
it is in a good state for driver initialization.
However, if we are operating in SR-IOV mode it is up to the GIM driver
to manage the asic state, therefore we should not post the card (and
shouldn't be able to do it either).
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++
drivers/gpu/drm/amd/amdgpu/vi.c| 15 +++
4 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 26fe670..fe71dea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1835,6 +1835,8 @@ struct amdgpu_asic_funcs {
/* MM block clocks */
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
+ /* query virtual capabilities */
+ u32 (*get_virtual_caps)(struct amdgpu_device *adev);
};
/*
@@ -1932,8 +1934,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device);
/* GPU virtualization */
+#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
+#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
struct amdgpu_virtualization {
bool supports_sr_iov;
+ bool is_virtual;
+ u32 caps;
};
/*
@@ -2226,6 +2232,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
#define amdgpu_asic_set_uvd_clocks(adev, v, d)
(adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
#define amdgpu_asic_set_vce_clocks(adev, ev, ec)
(adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
+#define amdgpu_asic_get_virtual_caps(adev)
((adev)->asic_funcs->get_virtual_caps((adev)))
#define amdgpu_asic_get_gpu_clock_counter(adev)
(adev)->asic_funcs->get_gpu_clock_counter((adev))
#define amdgpu_asic_read_disabled_bios(adev)
(adev)->asic_funcs->read_disabled_bios((adev))
#define amdgpu_asic_read_bios_from_rom(adev, b, l)
(adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b494212..629e4e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1392,6 +1392,14 @@ static int amdgpu_resume(struct amdgpu_device *adev)
return 0;
}
+static bool amdgpu_device_is_virtual(void)
+{
+#ifdef CONFIG_X86
+ return boot_cpu_has(X86_FEATURE_HYPERVISOR);
+#else
+ return false
+#endif
+}
/**
* amdgpu_device_has_dal_support - check if dal is supported
@@ -1560,8 +1568,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->virtualization.supports_sr_iov =
amdgpu_atombios_has_gpu_virtualization_table(adev);
+ /* Check if we are executing in a virtualized environment */
+ adev->virtualization.is_virtual = amdgpu_device_is_virtual();
+ adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
+
/* Post card if necessary */
- if (!amdgpu_card_posted(adev)) {
+ if (!amdgpu_card_posted(adev) ||
+ (adev->virtualization.is_virtual &&
+!adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) {
if (!adev->bios) {
dev_err(adev->dev, "Card not posted and no BIOS -
ignoring\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 40f4fda..907bb28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -963,6 +963,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device
*adev,
return true;
}
+static u32 cik_get_virtual_caps(struct amdgpu_device *adev)
+{
+ /* CIK does not support SR-IOV */
+ return 0;
+}
+
static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[]
= {
{mmGRBM_STATUS, false},
{mmGB_ADDR_CONFIG, false},
@@ -2176,6 +2182,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
.get_xclk = &cik_get_xclk,
.set_uvd_clocks = &cik_set_uvd_clocks,
.set_vce_clocks = &cik_set_vce_clocks,
+ .get_virtual_caps = &cik_get_virtual_caps,
/* these should be moved to their own ip modules */
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
[PATCH] amdgpu: fix asic initialization for virtualized environments
When executing in a PCI passthrough based virtuzliation environemnt, the
hypervisor will usually attempt to send a PCIe bus reset signal to the
ASIC when the VM reboots. In this scenario, the card is not correctly
initialized, but we still consider it to be posted. Therefore, in a
passthrough based environemnt we should always post the card to guarantee
it is in a good state for driver initialization.
However, if we are operating in SR-IOV mode it is up to the GIM driver
to manage the asic state, therefore we should not post the card (and
shouldn't be able to do it either).
Signed-off-by: Andres Rodriguez
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++
drivers/gpu/drm/amd/amdgpu/vi.c| 15 +++
4 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 26fe670..fe71dea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1835,6 +1835,8 @@ struct amdgpu_asic_funcs {
/* MM block clocks */
int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
+ /* query virtual capabilities */
+ u32 (*get_virtual_caps)(struct amdgpu_device *adev);
};
/*
@@ -1932,8 +1934,12 @@ void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device);
/* GPU virtualization */
+#define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
+#define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
struct amdgpu_virtualization {
bool supports_sr_iov;
+ bool is_virtual;
+ u32 caps;
};
/*
@@ -2226,6 +2232,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
#define amdgpu_asic_set_uvd_clocks(adev, v, d)
(adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
#define amdgpu_asic_set_vce_clocks(adev, ev, ec)
(adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
+#define amdgpu_asic_get_virtual_caps(adev)
((adev)->asic_funcs->get_virtual_caps((adev)))
#define amdgpu_asic_get_gpu_clock_counter(adev)
(adev)->asic_funcs->get_gpu_clock_counter((adev))
#define amdgpu_asic_read_disabled_bios(adev)
(adev)->asic_funcs->read_disabled_bios((adev))
#define amdgpu_asic_read_bios_from_rom(adev, b, l)
(adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b494212..629e4e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1392,6 +1392,14 @@ static int amdgpu_resume(struct amdgpu_device *adev)
return 0;
}
+static bool amdgpu_device_is_virtual(void)
+{
+#ifdef CONFIG_X86
+ return boot_cpu_has(X86_FEATURE_HYPERVISOR);
+#else
+ return false
+#endif
+}
/**
* amdgpu_device_has_dal_support - check if dal is supported
@@ -1560,8 +1568,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->virtualization.supports_sr_iov =
amdgpu_atombios_has_gpu_virtualization_table(adev);
+ /* Check if we are executing in a virtualized environment */
+ adev->virtualization.is_virtual = amdgpu_device_is_virtual();
+ adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
+
/* Post card if necessary */
- if (!amdgpu_card_posted(adev)) {
+ if (!amdgpu_card_posted(adev) ||
+ (adev->virtualization.is_virtual &&
+!adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN)) {
if (!adev->bios) {
dev_err(adev->dev, "Card not posted and no BIOS -
ignoring\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 40f4fda..907bb28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -963,6 +963,12 @@ static bool cik_read_bios_from_rom(struct amdgpu_device
*adev,
return true;
}
+static u32 cik_get_virtual_caps(struct amdgpu_device *adev)
+{
+ /* CIK does not support SR-IOV */
+ return 0;
+}
+
static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[]
= {
{mmGRBM_STATUS, false},
{mmGB_ADDR_CONFIG, false},
@@ -2176,6 +2182,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
.get_xclk = &cik_get_xclk,
.set_uvd_clocks = &cik_set_uvd_clocks,
.set_vce_clocks = &cik_set_vce_clocks,
+ .get_virtual_caps = &cik_get_virtual_caps,
/* these should be moved to their own ip modules */
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
