from:"Cédric Cano"

R600 definition error for interrupt handler swap

2012-02-02 Thread Cédric Cano

Hi Alex,

We don't have the documentation that contains this register definition.

We try to use the Linux 3.0.0 on our PowerPC board and M96 GPU (RV730): 
it doesn't work as is. We need to revert this definition like it was 
before 2.6.39.4 
(http://lists.freedesktop.org/archives/dri-devel/2011-July/012811.html).

Are you sure the documentation is correct?

Cedric

Le 01/02/2012 20:46, Alex Deucher a ?crit :
> On Wed, Feb 1, 2012 at 4:33 AM, C?dric Cano  
> wrote:
>> Hello,
>>
>> We're trying to use R600 DRM driver with big endian architecture. We find
>> the following error in R600 definition of interrupt handler swap.
>>
>> Perhaps there's the same error in the evergreen definitions header file.
> The definition in the register header is correct according to the
> register spec.  It's bits 2:1 on both r6xx and evergreen.
>
> 0 = no swap
> 1 = 16 bit swap (0xaabb becomes 0xbbaa)
> 2 = 32 bit swap (0xaabbccdd becomes 0xddccbbaa)
> 3 = 64 bit swap (0xaabbccddeeff0011 becomes 0x1100ffeeddccbbaa))
>
> Alex
>
>> Cedric
>>
>> Signed-off-by: C?dric Cano
>> Signed-off-by: Thomas Jourdan
>> ---
>> diff -Naur linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
>> linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
>> --- linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-01-26
>> 01:39:32.0 +0100
>> +++ linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-02-01
>> 10:25:04.0 +0100
>> @@ -552,7 +552,7 @@
>>   #define IH_RB_WPTR_ADDR_LO0x3e14
>>   #define IH_CNTL   0x3e18
>>   #   define ENABLE_INTR(1<<  0)
>> -#   define IH_MC_SWAP(x)  ((x)<<  1)
>> +#   define IH_MC_SWAP(x)  ((x)<<  2)
>>   #   define IH_MC_SWAP_NONE0
>>   #   define IH_MC_SWAP_16BIT   1
>>   #   define IH_MC_SWAP_32BIT   2
>> --
>>
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: R600 definition error for interrupt handler swap

2012-02-02 Thread Cédric Cano


Hi Alex,

We don't have the documentation that contains this register definition.

We try to use the Linux 3.0.0 on our PowerPC board and M96 GPU (RV730): 
it doesn't work as is. We need to revert this definition like it was 
before 2.6.39.4 
(http://lists.freedesktop.org/archives/dri-devel/2011-July/012811.html).


Are you sure the documentation is correct?

Cedric

Le 01/02/2012 20:46, Alex Deucher a écrit :

On Wed, Feb 1, 2012 at 4:33 AM, Cédric Canocc...@interfaceconcept.com  wrote:

Hello,

We're trying to use R600 DRM driver with big endian architecture. We find
the following error in R600 definition of interrupt handler swap.

Perhaps there's the same error in the evergreen definitions header file.

The definition in the register header is correct according to the
register spec.  It's bits 2:1 on both r6xx and evergreen.

0 = no swap
1 = 16 bit swap (0xaabb becomes 0xbbaa)
2 = 32 bit swap (0xaabbccdd becomes 0xddccbbaa)
3 = 64 bit swap (0xaabbccddeeff0011 becomes 0x1100ffeeddccbbaa))

Alex


Cedric

Signed-off-by: Cédric Canocc...@interfaceconcept.com
Signed-off-by: Thomas Jourdantjour...@interfaceconcept.com
---
diff -Naur linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
--- linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-01-26
01:39:32.0 +0100
+++ linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-02-01
10:25:04.0 +0100
@@ -552,7 +552,7 @@
  #define IH_RB_WPTR_ADDR_LO0x3e14
  #define IH_CNTL   0x3e18
  #   define ENABLE_INTR(1  0)
-#   define IH_MC_SWAP(x)  ((x)  1)
+#   define IH_MC_SWAP(x)  ((x)  2)
  #   define IH_MC_SWAP_NONE0
  #   define IH_MC_SWAP_16BIT   1
  #   define IH_MC_SWAP_32BIT   2
--


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R600 definition error for interrupt handler swap

2012-02-01 Thread Cédric Cano

Hello,

We're trying to use R600 DRM driver with big endian architecture. We 
find the following error in R600 definition of interrupt handler swap.

Perhaps there's the same error in the evergreen definitions header file.

Cedric

Signed-off-by: C?dric Cano 
Signed-off-by: Thomas Jourdan 
---
diff -Naur linux-3.2.2/drivers/gpu/drm/radeon/r600d.h 
linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
--- linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-01-26 
01:39:32.0 +0100
+++ linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-02-01 
10:25:04.0 +0100
@@ -552,7 +552,7 @@
  #define IH_RB_WPTR_ADDR_LO0x3e14
  #define IH_CNTL   0x3e18
  #   define ENABLE_INTR(1 << 0)
-#   define IH_MC_SWAP(x)  ((x) << 1)
+#   define IH_MC_SWAP(x)  ((x) << 2)
  #   define IH_MC_SWAP_NONE0
  #   define IH_MC_SWAP_16BIT   1
  #   define IH_MC_SWAP_32BIT   2
--

R600 definition error for interrupt handler swap

2012-02-01 Thread Cédric Cano


Hello,

We're trying to use R600 DRM driver with big endian architecture. We 
find the following error in R600 definition of interrupt handler swap.


Perhaps there's the same error in the evergreen definitions header file.

Cedric

Signed-off-by: Cédric Cano cc...@interfaceconcept.com
Signed-off-by: Thomas Jourdan tjour...@interfaceconcept.com
---
diff -Naur linux-3.2.2/drivers/gpu/drm/radeon/r600d.h 
linux-3.2.2/drivers/gpu/drm/radeon/r600d.h
--- linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-01-26 
01:39:32.0 +0100
+++ linux-3.2.2/drivers/gpu/drm/radeon/r600d.h2012-02-01 
10:25:04.0 +0100

@@ -552,7 +552,7 @@
 #define IH_RB_WPTR_ADDR_LO0x3e14
 #define IH_CNTL   0x3e18
 #   define ENABLE_INTR(1  0)
-#   define IH_MC_SWAP(x)  ((x)  1)
+#   define IH_MC_SWAP(x)  ((x)  2)
 #   define IH_MC_SWAP_NONE0
 #   define IH_MC_SWAP_16BIT   1
 #   define IH_MC_SWAP_32BIT   2
--


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[PATCH] radeon: Fix KMS CP writeback on big endian machines.

2011-04-19 Thread Cédric Cano

Hi,

Sorry, I've done a patch in reverse mode :(.

I repost the patch for r600 and evergreen write back correction for big 
endian platforms.

Cedric

Signed-off-by: Cedric Cano 
---
diff -Nuar linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c 
linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c
--- linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c2011-03-27 
20:37:20.0 +0200
+++ linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c2011-04-19 
11:39:39.0 +0200
@@ -2587,7 +2587,7 @@
  u32 wptr, tmp;

  if (rdev->wb.enabled)
-wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
+wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
  else
  wptr = RREG32(IH_RB_WPTR);


diff -Nuar linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c 
linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c
--- linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-03-27 
20:37:20.0 +0200
+++ linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-04-19 
09:52:13.0 +0200
@@ -3227,7 +3227,7 @@
  u32 wptr, tmp;

  if (rdev->wb.enabled)
-wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
+wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
  else
  wptr = RREG32(IH_RB_WPTR);




Le 19/04/2011 10:54, Michel D?nzer a ?crit :
>  On Die, 2011-04-19 at 10:23 +0200, C?dric Cano wrote:
> >
> > The following patch fixes interrupt acknowledge when write-back is
> > enabled on big endian platform.
> >
> > The same should be applied on evergreen.
>
>  Can you include that in the patch? I somehow managed to miss these in
>  my previous patch for older chips. :(
>
>

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[PATCH] radeon: Fix KMS CP writeback on big endian machines.

2011-04-19 Thread Cédric Cano

Signed-off-by: Cedric Cano

---
--- linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c2011-04-19 
11:39:39.0 +0200
+++ /home/cec/tmp/linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c
2011-03-27 20:37:20.0 +0200
@@ -2587,7 +2587,7 @@
  u32 wptr, tmp;

  if (rdev->wb.enabled)
-wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
+wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
  else
  wptr = RREG32(IH_RB_WPTR);


Le 19/04/2011 10:54, Michel D?nzer a ?crit :
> On Die, 2011-04-19 at 10:23 +0200, C?dric Cano wrote:
>> The following patch fixes interrupt acknowledge when write-back is
>> enabled on big endian platform.
>>
>> The same should be applied on evergreen.
> Can you include that in the patch? I somehow managed to miss these in my
> previous patch for older chips. :(
>
>

[PATCH] radeon: Fix KMS CP writeback on big endian machines.

2011-04-19 Thread Cédric Cano

Hi,

The following patch fixes interrupt acknowledge when write-back is 
enabled on big endian platform.

The same should be applied on evergreen.

Cedric

Signed-off-by: Cedric Cano
---
diff -Naur linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c 
linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c
--- linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-04-19 
09:52:13.0 +0200
+++ linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-03-27 
20:37:20.0 +0200
@@ -3227,7 +3227,7 @@
  u32 wptr, tmp;

  if (rdev->wb.enabled)
-wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
+wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
  else
  wptr = RREG32(IH_RB_WPTR);

[PATCH] radeon: Fix KMS CP writeback on big endian machines.

2011-04-19 Thread Cédric Cano


Hi,

The following patch fixes interrupt acknowledge when write-back is 
enabled on big endian platform.


The same should be applied on evergreen.

Cedric

Signed-off-by: Cedric Canoccano at interfaceconcept.com
---
diff -Naur linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c 
linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c
--- linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-04-19 
09:52:13.0 +0200
+++ linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-03-27 
20:37:20.0 +0200

@@ -3227,7 +3227,7 @@
 u32 wptr, tmp;

 if (rdev-wb.enabled)
-wptr = le32_to_cpu(rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
+wptr = rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4];
 else
 wptr = RREG32(IH_RB_WPTR);


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Re: [PATCH] radeon: Fix KMS CP writeback on big endian machines.

2011-04-19 Thread Cédric Cano


Signed-off-by: Cedric Canoccano at interfaceconcept.com

---
--- linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c2011-04-19 
11:39:39.0 +0200
+++ /home/cec/tmp/linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c
2011-03-27 20:37:20.0 +0200

@@ -2587,7 +2587,7 @@
 u32 wptr, tmp;

 if (rdev-wb.enabled)
-wptr = le32_to_cpu(rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
+wptr = rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4];
 else
 wptr = RREG32(IH_RB_WPTR);


Le 19/04/2011 10:54, Michel Dänzer a écrit :

On Die, 2011-04-19 at 10:23 +0200, Cédric Cano wrote:

The following patch fixes interrupt acknowledge when write-back is
enabled on big endian platform.

The same should be applied on evergreen.

Can you include that in the patch? I somehow managed to miss these in my
previous patch for older chips. :(



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Re: [PATCH] radeon: Fix KMS CP writeback on big endian machines.

2011-04-19 Thread Cédric Cano


Hi,

Sorry, I've done a patch in reverse mode :(.

I repost the patch for r600 and evergreen write back correction for big 
endian platforms.


Cedric

Signed-off-by: Cedric Cano ccano at interfaceconcept.com
---
diff -Nuar linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c 
linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c
--- linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c2011-03-27 
20:37:20.0 +0200
+++ linux-2.6.38.2/drivers/gpu/drm/radeon/evergreen.c2011-04-19 
11:39:39.0 +0200

@@ -2587,7 +2587,7 @@
 u32 wptr, tmp;

 if (rdev-wb.enabled)
-wptr = rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4];
+wptr = le32_to_cpu(rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
 else
 wptr = RREG32(IH_RB_WPTR);


diff -Nuar linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c 
linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c
--- linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-03-27 
20:37:20.0 +0200
+++ linux-2.6.38.2/drivers/gpu/drm/radeon/r600.c2011-04-19 
09:52:13.0 +0200

@@ -3227,7 +3227,7 @@
 u32 wptr, tmp;

 if (rdev-wb.enabled)
-wptr = rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4];
+wptr = le32_to_cpu(rdev-wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
 else
 wptr = RREG32(IH_RB_WPTR);




Le 19/04/2011 10:54, Michel Dänzer a écrit :

 On Die, 2011-04-19 at 10:23 +0200, Cédric Cano wrote:

 The following patch fixes interrupt acknowledge when write-back is
 enabled on big endian platform.

 The same should be applied on evergreen.

 Can you include that in the patch? I somehow managed to miss these in
 my previous patch for older chips. :(




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[PATCH] Big endian support for RV730 (Gallium r600g)

2011-04-15 Thread Cédric Cano

Hi

Here you are a patch that adds big endian support for rv730 in r600 
gallium driver.

I used the mesa-demos to test the driver status on big endian platform. 
Except with demos using accumulation buffer, the rendering is the same 
as on Intel platform. Albeit there are still some artefacts with some 
demos.

I manage to fix accumulation buffer demos but then, glReadPixels demos 
won't work. I still can figure out (like with r600c) what and when I 
must enable swap. It will depends on object's domains. That's what I 
tried to do in r600_cb and r600_create_sampler_view.

Reviewing of the patch would be greatly appreciated.

Regards,
Cedric
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[PATCH] Big endian support for RV730 (Gallium r600g)

2011-04-15 Thread Cédric Cano


Hi

Here you are a patch that adds big endian support for rv730 in r600 
gallium driver.


I used the mesa-demos to test the driver status on big endian platform. 
Except with demos using accumulation buffer, the rendering is the same 
as on Intel platform. Albeit there are still some artefacts with some 
demos.


I manage to fix accumulation buffer demos but then, glReadPixels demos 
won't work. I still can figure out (like with r600c) what and when I 
must enable swap. It will depends on object's domains. That's what I 
tried to do in r600_cb and r600_create_sampler_view.


Reviewing of the patch would be greatly appreciated.

Regards,
Cedric
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index c22bd8e..7e854b1 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -22,6 +22,7 @@
  */
 #include stdio.h
 #include errno.h
+#include byteswap.h
 #include util/u_format.h
 #include util/u_memory.h
 #include pipe/p_shader_tokens.h
@@ -32,6 +33,12 @@
 #include r600_formats.h
 #include r600d.h
 
+#ifdef PIPE_ARCH_BIG_ENDIAN
+#define CPU_TO_LE32(x)	bswap_32(x)
+#else
+#define CPU_TO_LE32(x)	(x)
+#endif
+
 #define NUM_OF_CYCLES 3
 #define NUM_OF_COMPONENTS 4
 
@@ -1383,6 +1390,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx-srf_mode_all) |
 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx-dst_gpr);
 	bc-bytecode[id++] = S_SQ_VTX_WORD2_OFFSET(vtx-offset) |
+	   			S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx-endian) |
 S_SQ_VTX_WORD2_MEGA_FETCH(1);
 	bc-bytecode[id++] = 0;
 	return 0;
@@ -1917,6 +1925,7 @@ void r600_bc_dump(struct r600_bc *bc)
 			fprintf(stderr, MODE:%d)\n, vtx-srf_mode_all);
 			id++;
 			fprintf(stderr, %04d %08X   , id, bc-bytecode[id]);
+			fprintf(stderr, ENDIAN:%d , vtx-endian);
 			fprintf(stderr, OFFSET:%d\n, vtx-offset);
 			//TODO
 			id++;
@@ -1929,7 +1938,7 @@ void r600_bc_dump(struct r600_bc *bc)
 }
 
 static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
-unsigned *num_format, unsigned *format_comp)
+unsigned *num_format, unsigned *format_comp, unsigned *endian)
 {
 	const struct util_format_description *desc;
 	unsigned i;
@@ -1937,6 +1946,7 @@ static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
 	*format = 0;
 	*num_format = 0;
 	*format_comp = 0;
+	*endian = ENDIAN_NONE;
 
 	desc = util_format_description(pformat);
 	if (desc-layout != UTIL_FORMAT_LAYOUT_PLAIN) {
@@ -1967,6 +1977,9 @@ static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
 *format = FMT_16_16_16_16_FLOAT;
 break;
 			}
+#ifdef PIPE_ARCH_BIG_ENDIAN
+			*endian = ENDIAN_8IN16;
+#endif
 			break;
 		case 32:
 			switch (desc-nr_channels) {
@@ -1983,6 +1996,9 @@ static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
 *format = FMT_32_32_32_32_FLOAT;
 break;
 			}
+#ifdef PIPE_ARCH_BIG_ENDIAN
+			*endian = ENDIAN_8IN32;
+#endif
 			break;
 		default:
 			goto out_unknown;
@@ -2020,6 +2036,9 @@ static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
 *format = FMT_16_16_16_16;
 break;
 			}
+#ifdef PIPE_ARCH_BIG_ENDIAN
+			*endian = ENDIAN_8IN16;
+#endif
 			break;
 		case 32:
 			switch (desc-nr_channels) {
@@ -2036,6 +2055,9 @@ static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
 *format = FMT_32_32_32_32;
 break;
 			}
+#ifdef PIPE_ARCH_BIG_ENDIAN
+			*endian = ENDIAN_8IN32;
+#endif
 			break;
 		default:
 			goto out_unknown;
@@ -2067,7 +2089,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 	struct pipe_vertex_element *elements = ve-elements;
 	const struct util_format_description *desc;
 	unsigned fetch_resource_start = rctx-family = CHIP_CEDAR ? 0 : 160;
-	unsigned format, num_format, format_comp;
+	unsigned format, num_format, format_comp, endian;
 	u32 *bytecode;
 	int i, r;
 
@@ -2114,7 +2136,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 
 	for (i = 0; i  ve-count; i++) {
 		unsigned vbuffer_index;
-		r600_vertex_data_type(ve-elements[i].src_format, format, num_format, format_comp);
+		r600_vertex_data_type(ve-elements[i].src_format, format, num_format, format_comp, endian);
 		desc = util_format_description(ve-elements[i].src_format);
 		if (desc == NULL) {
 			r600_bc_clear(bc);
@@ -2140,6 +2162,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 		vtx.format_comp_all = format_comp;
 		vtx.srf_mode_all = 1;
 		vtx.offset = elements[i].src_offset;
+		vtx.endian = endian;
 
 		if ((r = r600_bc_add_vtx(bc, vtx))) {
 			r600_bc_clear(bc);
@@ -2179,7 +2202,9 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 		return -ENOMEM;
 	}
 
-	memcpy(bytecode, bc.bytecode, ve-fs_size);
+	for(i = 0; i  ve-fs_size / 4; i++) {
+		*(bytecode + i) = CPU_TO_LE32(*(bc.bytecode

[PATCH] Big Endian support for RV730 (Mesa r600)

2011-04-14 Thread Cédric Cano

Le 13/04/2011 14:10, Benjamin Herrenschmidt a ?crit :
> On Wed, 2011-04-13 at 22:05 +1000, Benjamin Herrenschmidt wrote:
>> On Tue, 2011-04-12 at 10:01 +0200, C?dric Cano wrote:
>>> Hi
>>>
>>> Here you are a patch that adds big endian support for rv730 in r600
>>> classic mesa driver. The BE modifications are almost the same as the DRM
>>> / DDX driver modifications
>>> (http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).
>>>
>>> I used the mesa-demos to test the driver status on big endian platform.
>>> Nearly all demos renders the same as on Intel architecture.
>>> Nevertheless, there are still some issues in glReadPixels (r600_blit)
>>> with some formats. I can't figure out exactly what and when data must be
>>> swapped (set_tex_resoures, set_render_target...). Review of the patch
>>> would be greatly appreciated.
>>>
>>> It seems that r600g will be the default for Mesa 7.11 so I'll try to
>>> enable big endian support for Gallium now.
>> Cool stuff !
>>
>> I'll try to test that one of these days on various ppc's
> BTW. I see you used some FSL embedded board. Do you have your PCIe MMIO
> space above 32-bit ? Last I looked, there was a bunch of fixing needing
> to be done, among others in the TTM, to make that work.
>
> I had some preliminary patches but they bitrot... mostly the issue is to
> make sure than a phys_addr_t is used instead of an unsigned long
> whenever it tries to store the physical address of an object.
>
> Ben.
>
>
>
Hi Ben,

I don't use Freescale eval boards but our custom PowerPC design. We 
didn't enable the 36-bit addressing mode yet.

C?dric

Re: [PATCH] Big Endian support for RV730 (Mesa r600)

2011-04-14 Thread Cédric Cano


Le 13/04/2011 14:10, Benjamin Herrenschmidt a écrit :

On Wed, 2011-04-13 at 22:05 +1000, Benjamin Herrenschmidt wrote:

On Tue, 2011-04-12 at 10:01 +0200, Cédric Cano wrote:

Hi

Here you are a patch that adds big endian support for rv730 in r600
classic mesa driver. The BE modifications are almost the same as the DRM
/ DDX driver modifications
(http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).

I used the mesa-demos to test the driver status on big endian platform.
Nearly all demos renders the same as on Intel architecture.
Nevertheless, there are still some issues in glReadPixels (r600_blit)
with some formats. I can't figure out exactly what and when data must be
swapped (set_tex_resoures, set_render_target...). Review of the patch
would be greatly appreciated.

It seems that r600g will be the default for Mesa 7.11 so I'll try to
enable big endian support for Gallium now.

Cool stuff !

I'll try to test that one of these days on various ppc's

BTW. I see you used some FSL embedded board. Do you have your PCIe MMIO
space above 32-bit ? Last I looked, there was a bunch of fixing needing
to be done, among others in the TTM, to make that work.

I had some preliminary patches but they bitrot... mostly the issue is to
make sure than a phys_addr_t is used instead of an unsigned long
whenever it tries to store the physical address of an object.

Ben.




Hi Ben,

I don't use Freescale eval boards but our custom PowerPC design. We 
didn't enable the 36-bit addressing mode yet.


Cédric


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[PATCH] Big Endian support for RV730 (Mesa r600)

2011-04-12 Thread Cédric Cano

Hi

Here you are a patch that adds big endian support for rv730 in r600 
classic mesa driver. The BE modifications are almost the same as the DRM 
/ DDX driver modifications 
(http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).

I used the mesa-demos to test the driver status on big endian platform. 
Nearly all demos renders the same as on Intel architecture. 
Nevertheless, there are still some issues in glReadPixels (r600_blit) 
with some formats. I can't figure out exactly what and when data must be 
swapped (set_tex_resoures, set_render_target...). Review of the patch 
would be greatly appreciated.

It seems that r600g will be the default for Mesa 7.11 so I'll try to 
enable big endian support for Gallium now.

Regards
C?dric Cano
-- next part --
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[PATCH] Big Endian support for RV730 (Mesa r600)

2011-04-12 Thread Cédric Cano


Hi

Here you are a patch that adds big endian support for rv730 in r600 
classic mesa driver. The BE modifications are almost the same as the DRM 
/ DDX driver modifications 
(http://lists.freedesktop.org/archives/dri-devel/2011-February/008151.html).


I used the mesa-demos to test the driver status on big endian platform. 
Nearly all demos renders the same as on Intel architecture. 
Nevertheless, there are still some issues in glReadPixels (r600_blit) 
with some formats. I can't figure out exactly what and when data must be 
swapped (set_tex_resoures, set_render_target...). Review of the patch 
would be greatly appreciated.


It seems that r600g will be the default for Mesa 7.11 so I'll try to 
enable big endian support for Gallium now.


Regards
Cédric Cano
diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h
--- Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h	2010-02-05 01:10:40.0 +0100
+++ Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h	2011-04-07 16:19:50.0 +0200
@@ -29,8 +29,8 @@
 #define _DEFINEENDIAN_H_
 
 //We have to choose a reg bits orientation if there is no compile flag for it.
-#if defined(LITTLEENDIAN_CPU)
-#elif defined(BIGENDIAN_CPU)
+#ifdef MESA_BIG_ENDIAN
+#define BIGENDIAN_CPU
 #else
 #define LITTLEENDIAN_CPU
 #endif
diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c
--- Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c	2010-12-14 22:43:15.0 +0100
+++ Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c	2011-04-11 16:43:40.0 +0200
@@ -94,17 +94,17 @@
 {
 uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
 int id = 0;
-uint32_t comp_swap, format;
+uint32_t endian, comp_swap, format;
 BATCH_LOCALS(context-radeon);
 
 cb_color0_base = dst_offset / 256;
+	endian = ENDIAN_NONE;
 
 SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
  PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
 SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
  SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
 
-SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
 SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
  CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 
@@ -112,24 +112,36 @@
 
 switch(mesa_format) {
 case MESA_FORMAT_RGBA:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD_REV;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 	SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_SIGNED_RGBA:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD_REV;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 	SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_RGBA_REV:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 	SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_SIGNED_RGBA_REV:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -137,6 +149,9 @@
 break;
 case MESA_FORMAT_ARGB:
 case MESA_FORMAT_XRGB:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_ALT;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -144,54 +159,81 @@
 break;
 case MESA_FORMAT_ARGB_REV:
 case MESA_FORMAT_XRGB_REV:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_ALT_REV;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 	SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_RGB565:
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN16;
+#endif
+		comp_swap = SWAP_STD_REV;	
 format = COLOR_5_6_5;
-comp_swap = SWAP_STD_REV;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 	SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_RGB565_REV:
-format = COLOR_5_6_5;
+#ifdef MESA_BIG_ENDIAN
+			endian = ENDIAN_8IN16;
+#endif
 comp_swap = SWAP_STD;
+format = COLOR_5_6_5;
 	SETbit(cb_color0_info, SOURCE_FORMAT_bit);
 	SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 break

[PATCH] Big endian support for RV730

2011-02-11 Thread Cédric Cano

Signed-off-by: Cedric Cano 
---
diff -Naur xf86-video-ati-6.13.2/src/drmmode_display.c 
xf86-video-ati-6.13.2/src/drmmode_display.c
--- xf86-video-ati-6.13.2/src/drmmode_display.c2010-09-28 
00:20:53.0 +0200
+++ xf86-video-ati-6.13.2/src/drmmode_display.c2011-02-10 
14:27:56.0 +0100
@@ -385,12 +385,15 @@
  drmmode_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
  {
  drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
-void *ptr;
+int i;
+uint32_t *ptr;

  /* cursor should be mapped already */
-ptr = drmmode_crtc->cursor_bo->ptr;
+ptr = (uint32_t *)(drmmode_crtc->cursor_bo->ptr);

-memcpy (ptr, image, 64 * 64 * 4);
+for(i = 0; i < 64 * 64; i++) {
+ptr[i] = cpu_to_le32(image[i]);
+}

  return;
  }
diff -Naur xf86-video-ati-6.13.2/src/r600_exa.c 
xf86-video-ati-6.13.2/src/r600_exa.c
--- xf86-video-ati-6.13.2/src/r600_exa.c2010-09-28 
00:20:53.0 +0200
+++ xf86-video-ati-6.13.2/src/r600_exa.c2011-02-10 
14:29:03.0 +0100
@@ -247,9 +247,15 @@
  } else if (accel_state->dst_obj.bpp == 16) {
  cb_conf.format = COLOR_5_6_5;
  cb_conf.comp_swap = 2; /* RGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+cb_conf.endian = ENDIAN_8IN16;
+#endif
  } else {
  cb_conf.format = COLOR_8_8_8_8;
  cb_conf.comp_swap = 1; /* ARGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+cb_conf.endian = ENDIAN_8IN32;
+#endif
  }
  cb_conf.source_format = 1;
  cb_conf.blend_clamp = 1;
@@ -942,7 +948,18 @@
  tex_res.bo  = accel_state->src_obj[unit].bo;
  tex_res.mip_bo  = accel_state->src_obj[unit].bo;
  tex_res.request_size= 1;
-
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+switch(accel_state->src_obj[unit].bpp) {
+case 16:
+tex_res.endian = SQ_ENDIAN_8IN16;
+break;
+case 32:
+tex_res.endian = SQ_ENDIAN_8IN32;
+break;
+default :
+break;
+}
+#endif
  /* component swizzles */
  switch (pPict->format) {
  case PICT_a1r5g5b5:
@@ -1405,6 +1422,18 @@
  }
  cb_conf.source_format = 1;
  cb_conf.blend_clamp = 1;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+switch(dst_obj.bpp) {
+case 16:
+cb_conf.endian = ENDIAN_8IN16;
+break;
+case 32:
+cb_conf.endian = ENDIAN_8IN32;
+break;
+default:
+break;
+}
+#endif
  set_render_target(pScrn, accel_state->ib, _conf, 
accel_state->dst_obj.domain);

  BEGIN_BATCH(24);
@@ -2116,6 +2145,15 @@
  accel_state->xv_ps_offset = 3584;
  R600_xv_ps(ChipSet, shader + accel_state->xv_ps_offset / 4);

+#if X_BYTE_ORDER == X_BIG_ENDIAN
+{
+int i;
+for(i = 0; i < (4096 / 4); i++) {
+shader[i] = cpu_to_le32(shader[i]);
+}
+}
+#endif
+
  #ifdef XF86DRM_MODE
  #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4)
  if (info->cs) {
diff -Naur xf86-video-ati-6.13.2/src/r600_shader.c 
xf86-video-ati-6.13.2/src/r600_shader.c
--- xf86-video-ati-6.13.2/src/r600_shader.c2010-09-28 
00:20:53.0 +0200
+++ xf86-video-ati-6.13.2/src/r600_shader.c2011-02-10 
14:30:10.0 +0100
@@ -111,7 +111,11 @@
   FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
   SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
  shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
   CONST_BUF_NO_STRIDE(0),
   MEGA_FETCH(1));
  shader[i++] = VTX_DWORD_PAD;
@@ -341,7 +345,11 @@
   FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
   SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
  shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
   CONST_BUF_NO_STRIDE(0),
   MEGA_FETCH(1));
  shader[i++] = VTX_DWORD_PAD;
@@ -366,7 +374,11 @@
   FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
   SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
  shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
   CONST_BUF_NO_STRIDE(0),
   MEGA_FETCH(0));
  shader[i++] = VTX_DWORD_PAD;
@@ -596,7 +608,11 @@
   FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),

SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
  shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+

[PATCH] Big endian support for RV730

2011-02-11 Thread Cédric Cano

Signed-off-by: Cedric Cano 
---
diff -Naur linux-2.6.35.6/drivers/gpu/drm/radeon/atombios_crtc.c 
linux-2.6.35.6/drivers/gpu/drm/radeon/atombios_crtc.c
--- linux-2.6.35.6/drivers/gpu/drm/radeon/atombios_crtc.c2010-09-27 
02:19:16.0 +0200
+++ linux-2.6.35.6/drivers/gpu/drm/radeon/atombios_crtc.c2011-01-27 
15:03:46.0 +0100
@@ -808,6 +808,7 @@
  struct radeon_bo *rbo;
  uint64_t fb_location;
  uint32_t fb_format, fb_pitch_pixels, tiling_flags;
+u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
  int r;

  /* no fb bound */
@@ -844,11 +845,17 @@
  case 16:
  fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
   EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
+#ifdef __BIG_ENDIAN
+fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
+#endif
  break;
  case 24:
  case 32:
  fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
   EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB));
+#ifdef __BIG_ENDIAN
+fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
  break;
  default:
  DRM_ERROR("Unsupported screen depth %d\n",
@@ -888,6 +895,7 @@
  WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + 
radeon_crtc->crtc_offset,
 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
  WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
+WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, 
fb_swap);

  WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
  WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
@@ -942,6 +950,7 @@
  struct radeon_bo *rbo;
  uint64_t fb_location;
  uint32_t fb_format, fb_pitch_pixels, tiling_flags;
+u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
  int r;

  /* no fb bound */
@@ -981,12 +990,18 @@
  fb_format =
  AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
  AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+#ifdef __BIG_ENDIAN
+fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
+#endif
  break;
  case 24:
  case 32:
  fb_format =
  AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
  AVIVO_D1GRPH_CONTROL_32BPP_ARGB;
+#ifdef __BIG_ENDIAN
+fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
+#endif
  break;
  default:
  DRM_ERROR("Unsupported screen depth %d\n",
@@ -1019,6 +1034,8 @@
  WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
 radeon_crtc->crtc_offset, (u32) fb_location);
  WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
+if (rdev->family >= CHIP_R600)
+WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, 
fb_swap);

  WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
  WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
diff -Naur linux-2.6.35.6/drivers/gpu/drm/radeon/r600_blit.c 
linux-2.6.35.6/drivers/gpu/drm/radeon/r600_blit.c
--- linux-2.6.35.6/drivers/gpu/drm/radeon/r600_blit.c2010-09-27 
02:19:16.0 +0200
+++ linux-2.6.35.6/drivers/gpu/drm/radeon/r600_blit.c2011-02-10 
10:25:32.0 +0100
@@ -53,7 +53,9 @@
  if (h < 8)
  h = 8;

-cb_color_info = ((format << 2) | (1 << 27));
+cb_color_info = (0 |
+(format << 2) |
+(1 << 27));
  pitch = (w / 8) - 1;
  slice = ((w * h) / 64) - 1;

@@ -137,9 +139,9 @@
  ps = (u32 *) ((char *)dev->agp_buffer_map->handle + 
dev_priv->blit_vb->offset + 256);

  for (i = 0; i < r6xx_vs_size; i++)
-vs[i] = r6xx_vs[i];
+vs[i] = cpu_to_le32(r6xx_vs[i]);
  for (i = 0; i < r6xx_ps_size; i++)
-ps[i] = r6xx_ps[i];
+ps[i] = cpu_to_le32(r6xx_ps[i]);

  dev_priv->blit_vb->used = 512;

@@ -191,7 +193,12 @@
  RING_LOCALS;
  DRM_DEBUG("\n");

-sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
+sq_vtx_constant_word2 = (0 |
+#ifdef __BIG_ENDIAN
+(2 << 30) |
+#endif
+((gpu_addr >> 32) & 0xff) |
+(16 << 8));

  BEGIN_RING(9);
  OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
@@ -235,7 +242,8 @@
  sq_tex_resource_word1 = (format << 26);
  sq_tex_resource_word1 |= ((h - 1) << 0);

-sq_tex_resource_word4 = ((1 << 14) |
+sq_tex_resource_word4 = (0 |
+ (1 << 14) |
   (0 << 16) |
   (1 << 19) |
   (2 << 22) |
@@ -291,7 +299,11 @@
  OUT_RING(DI_PT_RECTLIST);

  OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+#ifdef __BIG_ENDIAN
+OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
+#else
  OUT_RING(DI_INDEX_SIZE_16_BIT);
+#endif

  OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
  OUT_RING(1);
diff -Naur linux-2.6.35.6/drivers/gpu/drm/radeon/r600_blit_kms.c

[PATCH] Big endian support for RV730

2011-02-11 Thread Cédric Cano

Hi

Here are a couple of patches that enable support for RV730 on big endian 
architectures. The following items will work :
* KMS
   - correct color in framebuffer
   - interrupts
   - kms blit
   - power management
* DDX
   - kms enabled
   - exa
   - video textures
   - hardware cursor

For the BE modifications, the AMD Linux Engineering team advised me to focus on 
:
- make sure all the atombios data table accesses are endian safe
- set the display controller swappers 
properly(http://lists.freedesktop.org/archives/dri-devel/2011-January/007486.html)
- make sure the appropriate endian swapper is enabled in the texture and vertex 
fetch constants (see SQ_TEX_RESOURCE_WORD* and SQ_VTX_RESOURCE_WORD* regs)
- make sure the shaders are stored in LE order
- make sure shader constant buffers are stored in LE order
- endian swap IH (interrupt handler) packets
- endian swap the CP command buffers
- endian swap WB (write back) buffers

That's what I tried to do and so far, I have KMS and DDX (with EXA) drivers 
working. Drivers have been tested on a MPC8640 custom design, with a custom 
graphics board based on E4690 (RV730). I'm using a custom linux distribution 
with Xorg 7.6 (xf86-video-ati 6.13.2). The latest kernel available for my board 
is 2.6.35.6 so I haven't tested with upstream kernel.

I'd also like to test more the ddx driver in order to check the EXA functions 
do a correct rendering. Is there a driver framework testing, or some kind of 
unit test you, ddx driver writers, are using ?

Regards,
Cedric Cano

Re: [PATCH] Big endian support for RV730

2011-02-11 Thread Cédric Cano


Signed-off-by: Cedric Cano ccano at interfaceconcept.com
---
diff -Naur xf86-video-ati-6.13.2/src/drmmode_display.c 
xf86-video-ati-6.13.2/src/drmmode_display.c
--- xf86-video-ati-6.13.2/src/drmmode_display.c2010-09-28 
00:20:53.0 +0200
+++ xf86-video-ati-6.13.2/src/drmmode_display.c2011-02-10 
14:27:56.0 +0100

@@ -385,12 +385,15 @@
 drmmode_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
 {
 drmmode_crtc_private_ptr drmmode_crtc = crtc-driver_private;
-void *ptr;
+int i;
+uint32_t *ptr;

 /* cursor should be mapped already */
-ptr = drmmode_crtc-cursor_bo-ptr;
+ptr = (uint32_t *)(drmmode_crtc-cursor_bo-ptr);

-memcpy (ptr, image, 64 * 64 * 4);
+for(i = 0; i  64 * 64; i++) {
+ptr[i] = cpu_to_le32(image[i]);
+}

 return;
 }
diff -Naur xf86-video-ati-6.13.2/src/r600_exa.c 
xf86-video-ati-6.13.2/src/r600_exa.c
--- xf86-video-ati-6.13.2/src/r600_exa.c2010-09-28 
00:20:53.0 +0200
+++ xf86-video-ati-6.13.2/src/r600_exa.c2011-02-10 
14:29:03.0 +0100

@@ -247,9 +247,15 @@
 } else if (accel_state-dst_obj.bpp == 16) {
 cb_conf.format = COLOR_5_6_5;
 cb_conf.comp_swap = 2; /* RGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+cb_conf.endian = ENDIAN_8IN16;
+#endif
 } else {
 cb_conf.format = COLOR_8_8_8_8;
 cb_conf.comp_swap = 1; /* ARGB */
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+cb_conf.endian = ENDIAN_8IN32;
+#endif
 }
 cb_conf.source_format = 1;
 cb_conf.blend_clamp = 1;
@@ -942,7 +948,18 @@
 tex_res.bo  = accel_state-src_obj[unit].bo;
 tex_res.mip_bo  = accel_state-src_obj[unit].bo;
 tex_res.request_size= 1;
-
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+switch(accel_state-src_obj[unit].bpp) {
+case 16:
+tex_res.endian = SQ_ENDIAN_8IN16;
+break;
+case 32:
+tex_res.endian = SQ_ENDIAN_8IN32;
+break;
+default :
+break;
+}
+#endif
 /* component swizzles */
 switch (pPict-format) {
 case PICT_a1r5g5b5:
@@ -1405,6 +1422,18 @@
 }
 cb_conf.source_format = 1;
 cb_conf.blend_clamp = 1;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+switch(dst_obj.bpp) {
+case 16:
+cb_conf.endian = ENDIAN_8IN16;
+break;
+case 32:
+cb_conf.endian = ENDIAN_8IN32;
+break;
+default:
+break;
+}
+#endif
 set_render_target(pScrn, accel_state-ib, cb_conf, 
accel_state-dst_obj.domain);


 BEGIN_BATCH(24);
@@ -2116,6 +2145,15 @@
 accel_state-xv_ps_offset = 3584;
 R600_xv_ps(ChipSet, shader + accel_state-xv_ps_offset / 4);

+#if X_BYTE_ORDER == X_BIG_ENDIAN
+{
+int i;
+for(i = 0; i  (4096 / 4); i++) {
+shader[i] = cpu_to_le32(shader[i]);
+}
+}
+#endif
+
 #ifdef XF86DRM_MODE
 #if (EXA_VERSION_MAJOR == 2  EXA_VERSION_MINOR = 4)
 if (info-cs) {
diff -Naur xf86-video-ati-6.13.2/src/r600_shader.c 
xf86-video-ati-6.13.2/src/r600_shader.c
--- xf86-video-ati-6.13.2/src/r600_shader.c2010-09-28 
00:20:53.0 +0200
+++ xf86-video-ati-6.13.2/src/r600_shader.c2011-02-10 
14:30:10.0 +0100

@@ -111,7 +111,11 @@
  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
  SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
 shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
  CONST_BUF_NO_STRIDE(0),
  MEGA_FETCH(1));
 shader[i++] = VTX_DWORD_PAD;
@@ -341,7 +345,11 @@
  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
  SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
 shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
  CONST_BUF_NO_STRIDE(0),
  MEGA_FETCH(1));
 shader[i++] = VTX_DWORD_PAD;
@@ -366,7 +374,11 @@
  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
  SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));
 shader[i++] = VTX_DWORD2(OFFSET(8),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+ ENDIAN_SWAP(SQ_ENDIAN_NONE),
+#endif
  CONST_BUF_NO_STRIDE(0),
  MEGA_FETCH(0));
 shader[i++] = VTX_DWORD_PAD;
@@ -596,7 +608,11 @@
  FORMAT_COMP_ALL(SQ_FORMAT_COMP_SIGNED),
  
SRF_MODE_ALL(SRF_MODE_ZERO_CLAMP_MINUS_ONE));

 shader[i++] = VTX_DWORD2(OFFSET(0),
- ENDIAN_SWAP(ENDIAN_NONE),
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ ENDIAN_SWAP(SQ_ENDIAN_8IN32),
+#else
+

R600 definition error for interrupt handler swap

Re: R600 definition error for interrupt handler swap

R600 definition error for interrupt handler swap

R600 definition error for interrupt handler swap

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Re: [PATCH] radeon: Fix KMS CP writeback on big endian machines.

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[PATCH] Big endian support for RV730

[PATCH] Big endian support for RV730

Re: [PATCH] Big endian support for RV730

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