[v1 PATCH 0/4] Rockchip Type-C and DispplayPort driver
Hi all This series patch is for rockchip Type-C phy and DisplayPort controller driver. The USB Type-C PHY is designed to support the USB3 and DP applications. The PHY basically has two main components: USB3 and DisplyPort. USB3 operates in SuperSpeed mode and the DP can operate at RBR, HBR and HBR2 data rates. The Type-C cable orientation detection and Power Delivery (PD) is accomplished using a PD PHY or a exernal PD chip. The DP controller is compliant with DisplayPort Specification, Version 1.3, This IP is compatible with the rockchip type-c PHY IP. There is a uCPU in DP controller, it need a firmware to work, please put the firmware file to /lib/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The PHY driver has register a notification with extcon API, to get the alt mode from PD, the PD driver need call the devm_extcon_dev_allocate to create a extcon device and use extcon_set_state to notify PHY and DP controller. About the DP audio, cdn-dp registered 2 DAIs: 0 is I2S, 1 is SPDIF. We can reference them in simple-card. This series is based on Mark Yao's branch: https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23 I test this patches on the rk3399-evb board, with a fusb302 driver, this branch has no rk3399.dtsi, so the patch about dts is not included in this series. Changes in v1: - add extcon node description - move the registers in phy driver - remove the suffix of reset - update the licence note - init core clock to 50MHz - use extcon API - remove unused global - add some comments for magic num - change usleep_range(1000, 2000) tousleep_range(1000, 1050) - remove __func__ from dev_err - return err number when get clk failed - remove ADDR_ADJ define - use devm_clk_get(>dev, "tcpdcore") - add extcon node description - add #sound-dai-cells description - use extcon API - use hdmi-codec for the DP Asoc - do not initialize the "ret" - printk a err log when drm_of_encoder_active_endpoint_id - modify the dclk pin_pol to a single line Chris Zhong (4): Documentation: bindings: add dt doc for Rockchip USB Type-C PHY phy: Add USB Type-C PHY driver for rk3399 Documentation: bindings: add dt documentation for cdn DP controller drm/rockchip: cdn-dp: add cdn DP support for rk3399 .../bindings/display/rockchip/cdn-dp-rockchip.txt | 62 ++ .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 + drivers/gpu/drm/rockchip/Kconfig | 9 + drivers/gpu/drm/rockchip/Makefile | 1 + drivers/gpu/drm/rockchip/cdn-dp-core.c | 709 drivers/gpu/drm/rockchip/cdn-dp-core.h | 110 +++ drivers/gpu/drm/rockchip/cdn-dp-reg.c | 721 drivers/gpu/drm/rockchip/cdn-dp-reg.h | 404 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 6 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.h| 2 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 2 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-typec.c | 942 + include/linux/phy/phy-rockchip-typec.h | 20 + 15 files changed, 3041 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h create mode 100644 drivers/phy/phy-rockchip-typec.c create mode 100644 include/linux/phy/phy-rockchip-typec.h -- 2.6.3
[RESEND PATCH 4/6] Documentation: bindings: add dt documentation for cdn DP controller
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
---
.../bindings/display/rockchip/cdn-dp-rockchip.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
new file mode 100644
index 000..60795c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
@@ -0,0 +1,57 @@
+Rockchip RK3399 specific extensions to the cdn Display Port
+
+
+Required properties:
+- compatible: "rockchip,cdn-dp"
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+
+- clock-names: from common clock binding:
+ Required elements: "core_clk" "pclk" "spdif"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port nodes with endpoint definitions as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+contained 2 endpoints, connecting to the output of vop.
+
+- phys: from general PHY binding: the phandle for the PHY device.
+
+---
+
+Example:
+ cdn_dp: dp at fec0 {
+ compatible = "rockchip,cdn-dp";
+ reg = <0x0 0xfec0 0x0 0x10>;
+ interrupts = ;
+ clocks = < SCLK_DP_CORE>, < PCLK_DP_CTRL>,
+< SCLK_SPDIF_REC_DPTX>;
+ clock-names = "core_clk", "pclk", "spdif";
+ phys = <>;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <_out_dp>;
+ };
+
+ dp_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <_out_dp>;
+ };
+ };
+ };
+ };
--
2.6.3
[RESEND PATCH 3/6] drm/rockchip: vop: add cdn DP support for rk3399
Add support for cdn DP controller which is embedded in the rk3399
SoCs. The DP is compliant with DisplayPort Specification,
Version 1.3, This IP is compatible with the rockchip type-c PHY IP.
There is a uCPU in DP controller, it need a firmware to work,
please put the firmware file to /lib/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/cdn-dp-core.c | 620 +++
drivers/gpu/drm/rockchip/cdn-dp-core.h | 95
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 730
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 404 +++
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 9 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 +
include/sound/cdn-dp-audio.h| 51 ++
10 files changed, 1922 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h
create mode 100644 include/sound/cdn-dp-audio.h
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index d30bdc3..20da9a8 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,6 +25,15 @@ config ROCKCHIP_ANALOGIX_DP
for the Analogix Core DP driver. If you want to enable DP
on RK3288 based SoC, you should selet this option.
+config ROCKCHIP_CDN_DP
+tristate "Rockchip cdn DP"
+depends on DRM_ROCKCHIP
+help
+ This selects support for Rockchip SoC specific extensions
+ for the cdn Dp driver. If you want to enable Dp on
+ RK3399 based SoC, you should selet this
+ option.
+
config ROCKCHIP_DW_HDMI
tristate "Rockchip specific extensions for Synopsys DW HDMI"
depends on DRM_ROCKCHIP
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index 05d0713..abdecd5 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
+obj-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
new file mode 100644
index 000..fdf99f5
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -0,0 +1,620 @@
+/*
+ * cdn dp controller core driver
+ *
+ * Copyright (C) 2016 Chris Zhong
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+#include "rockchip_drm_vop.h"
+#include "cdn-dp-reg.h"
+#include "cdn-dp-core.h"
+
+#define connector_to_dp(c) \
+ container_of(c, struct cdn_dp_device, connector)
+
+#define encoder_to_dp(c) \
+ container_of(c, struct cdn_dp_device, encoder)
+
+/* dp grf register offset */
+#define DP_VOP_SEL 0x6224
+#define DP_SEL_VOP_LIT BIT(12)
+
+static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
+{
+ int ret = 0;
+ int clk_rate = 2;
+
+ ret = clk_prepare_enable(dp->pclk);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot enable dp pclk %d\n", ret);
+ goto err_pclk;
+ }
+
+ ret = clk_prepare_enable(dp->core_clk);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot enable core_clk %d\n", ret);
+ goto err_core_clk;
+ }
+
+ ret = clk_set_rate(dp->core_clk, clk_rate);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set dp core clk to %d %d\n",
+
[RESEND PATCH 0/6] Rockchip Type-C and DispplayPort driver
Sorry, forgot a head file in patch 1, so resend. Hi all This series patch is for rockchip Type-C phy and DisplayPort controller driver. The USB Type-C PHY is designed to support the USB3 and DP applications. The PHY basically has two main components: USB3 and DisplyPort. USB3 operates in SuperSpeed mode and the DP can operate at RBR, HBR and HBR2 data rates. The Type-C cable orientation detection and Power Delivery (PD) is accomplished using a PD PHY or a exernal PD chip. The DP controller is compliant with DisplayPort Specification, Version 1.3, This IP is compatible with the rockchip type-c PHY IP. There is a uCPU in DP controller, it need a firmware to work, please put the firmware file to /lib/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The PHY driver has register a notification, to get the alt mode from PD, the PD driver need call the tcphy_notifier_call_chain to notify PHY and DP controller. This series is based on Mark Yao's branch: https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23 I test this patches on the rk3399-evb board, with a fusb302 driver, this branch has no rk3399.dtsi, so the patch about dts is not included in this series. Chris Zhong (6): phy: Add USB Type-C PHY driver for rk3399 Documentation: bindings: add dt doc for Rockchip USB Type-C PHY drm/rockchip: vop: add cdn DP support for rk3399 Documentation: bindings: add dt documentation for cdn DP controller ASoC: cdn-dp: Add cdn DP codec driver ASoC: rockchip: Add machine driver for cdn dp codec .../bindings/display/rockchip/cdn-dp-rockchip.txt | 57 ++ .../devicetree/bindings/phy/phy-rockchip-typec.txt | 55 ++ .../bindings/sound/rockchip-cdn-dp-audio.txt | 12 + drivers/gpu/drm/rockchip/Kconfig | 9 + drivers/gpu/drm/rockchip/Makefile | 1 + drivers/gpu/drm/rockchip/cdn-dp-core.c | 620 drivers/gpu/drm/rockchip/cdn-dp-core.h | 95 +++ drivers/gpu/drm/rockchip/cdn-dp-reg.c | 730 ++ drivers/gpu/drm/rockchip/cdn-dp-reg.h | 404 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 9 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.h| 2 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 2 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-typec.c | 823 + include/linux/phy/phy-rockchip-typec.h | 72 ++ include/sound/cdn-dp-audio.h | 51 ++ sound/soc/codecs/Kconfig | 3 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cdn-dp-audio.c| 246 ++ sound/soc/rockchip/Kconfig | 9 + sound/soc/rockchip/Makefile| 2 + sound/soc/rockchip/rockchip-cdn-dp-audio.c | 167 + 23 files changed, 3378 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt create mode 100644 Documentation/devicetree/bindings/sound/rockchip-cdn-dp-audio.txt create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h create mode 100644 drivers/phy/phy-rockchip-typec.c create mode 100644 include/linux/phy/phy-rockchip-typec.h create mode 100644 include/sound/cdn-dp-audio.h create mode 100644 sound/soc/codecs/cdn-dp-audio.c create mode 100644 sound/soc/rockchip/rockchip-cdn-dp-audio.c -- 2.6.3
[PATCH 4/6] Documentation: bindings: add dt documentation for cdn DP controller
This patch adds a binding that describes the cdn DP controller for
rk3399.
Signed-off-by: Chris Zhong
---
.../bindings/display/rockchip/cdn-dp-rockchip.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
new file mode 100644
index 000..60795c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt
@@ -0,0 +1,57 @@
+Rockchip RK3399 specific extensions to the cdn Display Port
+
+
+Required properties:
+- compatible: "rockchip,cdn-dp"
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+
+- clock-names: from common clock binding:
+ Required elements: "core_clk" "pclk" "spdif"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port nodes with endpoint definitions as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+contained 2 endpoints, connecting to the output of vop.
+
+- phys: from general PHY binding: the phandle for the PHY device.
+
+---
+
+Example:
+ cdn_dp: dp at fec0 {
+ compatible = "rockchip,cdn-dp";
+ reg = <0x0 0xfec0 0x0 0x10>;
+ interrupts = ;
+ clocks = < SCLK_DP_CORE>, < PCLK_DP_CTRL>,
+< SCLK_SPDIF_REC_DPTX>;
+ clock-names = "core_clk", "pclk", "spdif";
+ phys = <>;
+ rockchip,grf = <>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <_out_dp>;
+ };
+
+ dp_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <_out_dp>;
+ };
+ };
+ };
+ };
--
2.6.3
[PATCH 3/6] drm/rockchip: vop: add cdn DP support for rk3399
Add support for cdn DP controller which is embedded in the rk3399
SoCs. The DP is compliant with DisplayPort Specification,
Version 1.3, This IP is compatible with the rockchip type-c PHY IP.
There is a uCPU in DP controller, it need a firmware to work,
please put the firmware file to /lib/firmware/cdn/dptx.bin. The
uCPU in charge of aux communication and link training, the host use
mailbox to communicate with the ucpu.
The dclk pin_pol of vop must not be invert for DP.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/cdn-dp-core.c | 620 +++
drivers/gpu/drm/rockchip/cdn-dp-core.h | 95
drivers/gpu/drm/rockchip/cdn-dp-reg.c | 730
drivers/gpu/drm/rockchip/cdn-dp-reg.h | 404 +++
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 9 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 +
include/sound/cdn-dp-audio.h| 51 ++
10 files changed, 1922 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c
create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h
create mode 100644 include/sound/cdn-dp-audio.h
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index d30bdc3..20da9a8 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,6 +25,15 @@ config ROCKCHIP_ANALOGIX_DP
for the Analogix Core DP driver. If you want to enable DP
on RK3288 based SoC, you should selet this option.
+config ROCKCHIP_CDN_DP
+tristate "Rockchip cdn DP"
+depends on DRM_ROCKCHIP
+help
+ This selects support for Rockchip SoC specific extensions
+ for the cdn Dp driver. If you want to enable Dp on
+ RK3399 based SoC, you should selet this
+ option.
+
config ROCKCHIP_DW_HDMI
tristate "Rockchip specific extensions for Synopsys DW HDMI"
depends on DRM_ROCKCHIP
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index 05d0713..abdecd5 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
+obj-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
b/drivers/gpu/drm/rockchip/cdn-dp-core.c
new file mode 100644
index 000..fdf99f5
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -0,0 +1,620 @@
+/*
+ * cdn dp controller core driver
+ *
+ * Copyright (C) 2016 Chris Zhong
+ * Copyright (C) 2016 ROCKCHIP, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+#include "rockchip_drm_vop.h"
+#include "cdn-dp-reg.h"
+#include "cdn-dp-core.h"
+
+#define connector_to_dp(c) \
+ container_of(c, struct cdn_dp_device, connector)
+
+#define encoder_to_dp(c) \
+ container_of(c, struct cdn_dp_device, encoder)
+
+/* dp grf register offset */
+#define DP_VOP_SEL 0x6224
+#define DP_SEL_VOP_LIT BIT(12)
+
+static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
+{
+ int ret = 0;
+ int clk_rate = 2;
+
+ ret = clk_prepare_enable(dp->pclk);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot enable dp pclk %d\n", ret);
+ goto err_pclk;
+ }
+
+ ret = clk_prepare_enable(dp->core_clk);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot enable core_clk %d\n", ret);
+ goto err_core_clk;
+ }
+
+ ret = clk_set_rate(dp->core_clk, clk_rate);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set dp core clk to %d %d\n",
+
[PATCH 0/6] Rockchip Type-C and DispplayPort driver
Hi all This series patch is for rockchip Type-C phy and DisplayPort controller driver. The USB Type-C PHY is designed to support the USB3 and DP applications. The PHY basically has two main components: USB3 and DisplyPort. USB3 operates in SuperSpeed mode and the DP can operate at RBR, HBR and HBR2 data rates. The Type-C cable orientation detection and Power Delivery (PD) is accomplished using a PD PHY or a exernal PD chip. The DP controller is compliant with DisplayPort Specification, Version 1.3, This IP is compatible with the rockchip type-c PHY IP. There is a uCPU in DP controller, it need a firmware to work, please put the firmware file to /lib/firmware/cdn/dptx.bin. The uCPU in charge of aux communication and link training, the host use mailbox to communicate with the ucpu. The PHY driver has register a notification, to get the alt mode from PD, the PD driver need call the tcphy_notifier_call_chain to notify PHY and DP controller. This series is based on Mark Yao's branch: https://github.com/markyzq/kernel-drm-rockchip/tree/drm-rockchip-next-2016-05-23 I test this patches on the rk3399-evb board, with a fusb302 driver, this branch has no rk3399.dtsi, so the patch about dts is not included in this series. Chris Zhong (6): phy: Add USB Type-C PHY driver for rk3399 Documentation: bindings: add dt doc for Rockchip USB Type-C PHY drm/rockchip: vop: add cdn DP support for rk3399 Documentation: bindings: add dt documentation for cdn DP controller ASoC: cdn-dp: Add cdn DP codec driver ASoC: rockchip: Add machine driver for cdn dp codec .../bindings/display/rockchip/cdn-dp-rockchip.txt | 57 ++ .../devicetree/bindings/phy/phy-rockchip-typec.txt | 55 ++ .../bindings/sound/rockchip-cdn-dp-audio.txt | 12 + drivers/gpu/drm/rockchip/Kconfig | 9 + drivers/gpu/drm/rockchip/Makefile | 1 + drivers/gpu/drm/rockchip/cdn-dp-core.c | 620 drivers/gpu/drm/rockchip/cdn-dp-core.h | 95 +++ drivers/gpu/drm/rockchip/cdn-dp-reg.c | 730 ++ drivers/gpu/drm/rockchip/cdn-dp-reg.h | 404 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c| 9 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.h| 2 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c| 2 + drivers/phy/Kconfig| 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-typec.c | 823 + include/sound/cdn-dp-audio.h | 51 ++ sound/soc/codecs/Kconfig | 3 + sound/soc/codecs/Makefile | 2 + sound/soc/codecs/cdn-dp-audio.c| 246 ++ sound/soc/rockchip/Kconfig | 9 + sound/soc/rockchip/Makefile| 2 + sound/soc/rockchip/rockchip-cdn-dp-audio.c | 167 + 22 files changed, 3306 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/cdn-dp-rockchip.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt create mode 100644 Documentation/devicetree/bindings/sound/rockchip-cdn-dp-audio.txt create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.c create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-core.h create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.c create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-reg.h create mode 100644 drivers/phy/phy-rockchip-typec.c create mode 100644 include/sound/cdn-dp-audio.h create mode 100644 sound/soc/codecs/cdn-dp-audio.c create mode 100644 sound/soc/rockchip/rockchip-cdn-dp-audio.c -- 2.6.3
[PATCH] drm/rockchip/dsi: fix handling mipi_dsi_pixel_format_to_bpp result
Hi Andrzej
On 01/14/2016 04:59 PM, Andrzej Hajda wrote:
> The function can return negative value so it should be assigned to signed
> variable.
>
> The problem has been detected using patch
> scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci.
>
> Signed-off-by: Andrzej Hajda
> ---
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 7bfe243..f8f8f29 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -461,10 +461,11 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
>
> static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
> {
> - unsigned int bpp, i, pre;
> + unsigned int i, pre;
> unsigned long mpclk, pllref, tmp;
> unsigned int m = 1, n = 1, target_mbps = 1000;
> unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps;
> + int bpp;
>
> bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> if (bpp < 0) {
Reviewed-by: Chris Zhong
Thanks
[PATCH v7.2 3/5] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong Acked-by: Mark Yao --- Changes in v7.2: - make sure disable clk when drm_panel_prepare err (Mark Yao) Changes in v7: - modify the config to tristate for modules build (Mark Yao) - Pass NULL 'name' to drm_encoder_init() to fix compile err (Mark Yao) Changes in v6: - move the mipi_en gate to ockchip_drm_crtc_mode_config - Remove the atomic feature check (Mark Yao) - Add atomic API support (Heiko Stübne) - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1194 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1208 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..8573985 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI for the Synopsys DesignWare HDMI driver. If you want to enable HDMI on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + tristate "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index a9d380f..d1dc0f7 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ rockchip_drm_gem.o obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o \ rockchip_vop_reg.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..7bfe243 --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1194 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX
[PATCH v7.1 3/5] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong Acked-by: Mark Yao --- Changes in v7.1: - make sure disable clk when drm_panel_prepare err (Mark Yao) Changes in v7: - modify the config to tristate for modules build (Mark Yao) - Pass NULL 'name' to drm_encoder_init() to fix compile err (Mark Yao) Changes in v6: - move the mipi_en gate to ockchip_drm_crtc_mode_config - Remove the atomic feature check (Mark Yao) - Add atomic API support (Heiko Stübne) - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1197 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1211 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..8573985 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI for the Synopsys DesignWare HDMI driver. If you want to enable HDMI on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + tristate "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index a9d380f..d1dc0f7 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ rockchip_drm_gem.o obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o \ rockchip_vop_reg.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..a36cf60 --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1197 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX
[PATCH v6.3 4/6] drm: rockchip: Support Synopsys DW MIPI DSI
Hi Mark
On 01/06/2016 09:48 AM, Mark yao wrote:
> On 2015å¹´12æ23æ¥ 11:43, Chris Zhong wrote:
>> +static int dw_mipi_dsi_register(struct drm_device *drm,
>> + struct dw_mipi_dsi *dsi)
>> +{
>> +struct drm_encoder *encoder = >encoder;
>> +struct drm_connector *connector = >connector;
>> +struct device *dev = dsi->dev;
>> +int ret;
>> +
>> +encoder->possible_crtcs = drm_of_find_possible_crtcs(drm,
>> + dev->of_node);
>> +/*
>> + * If we failed to find the CRTC(s) which this encoder is
>> + * supposed to be connected to, it's because the CRTC has
>> + * not been registered yet. Defer probing, and hope that
>> + * the required CRTC is added later.
>> + */
>> +if (encoder->possible_crtcs == 0)
>> +return -EPROBE_DEFER;
>> +
>> +drm_encoder_helper_add(>encoder,
>> + _mipi_dsi_encoder_helper_funcs);
>> +ret = drm_encoder_init(drm, >encoder,
>> _mipi_dsi_encoder_funcs,
>> + DRM_MODE_ENCODER_DSI);
>> +if (ret) {
>> +dev_err(dev, "Failed to initialize encoder with drm\n");
>> +return ret;
>> +}
>> +
>> +drm_connector_helper_add(connector,
>> +_mipi_dsi_connector_helper_funcs);
>> +
>> +drm_connector_init(drm, >connector,
>> + _mipi_dsi_atomic_connector_funcs,
>> + DRM_MODE_CONNECTOR_DSI);
>> +
> Hi Chris
>
> I try to pick your patches, but found following issues:
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c:
> å¨å½æ°âdw_mipi_dsi_registerâä¸:
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c:1024:5: éè¯¯ï¼ æä¾ç»å½æ°
> âdrm_encoder_initâçå®å太å°
> include/drm/drm_crtc.h:2220:5: éæ³¨ï¼ å¨æ¤å£°æ
> make[4]: *** [drivers/gpu/drm/rockchip/dw-mipi-dsi.o] é误 1
>
> Can you rebase to newest Dave's drm-next and fix this problem?
Thanks Mark.
I have post the v7 serial, fix this this compile err and modify the
config to tristate for modules build
>
> Thanks.
>
[PATCH v7 3/5] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong Acked-by: Mark Yao --- Changes in v7: - modify the config to tristate for modules build (Mark Yao) - Pass NULL 'name' to drm_encoder_init() to fix compile err (Mark Yao) Changes in v6: - move the mipi_en gate to ockchip_drm_crtc_mode_config - Remove the atomic feature check (Mark Yao) - Add atomic API support (Heiko Stübne) - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1196 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1210 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..8573985 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI for the Synopsys DesignWare HDMI driver. If you want to enable HDMI on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + tristate "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index a9d380f..d1dc0f7 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ rockchip_drm_gem.o obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o \ rockchip_vop_reg.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..b170f9d --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1196 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) +
[PATCH v7 1/5] drm/rockchip: return a true clock rate to adjusted_mode
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- use clk_round_rate to check the clock rate in vop_crtc_mode_fixup
Changes in v3: None
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index f5b3da2..056cac3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -878,9 +878,14 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
+ struct vop *vop = to_vop(crtc);
+
if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
return false;
+ adjusted_mode->clock =
+ clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+
return true;
}
--
2.6.3
[PATCH v7 0/5] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM driver. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel chrome_v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> According to the suggestion from Thierry, I have get rid of the bridge, and register the encoder & connecter in drm/rockchip/dw-mipi-dsi.c. After backport below patches from linux-next, I can merge this serial into Dave's drm-next branch. 94d5d6a0fbf3 clk: rockchip: add an id for rk3288 crypto clk c6d49fbcfcc4 clk: rockchip: add id for mipidsi sclk on rk3288 a2f4c560f18e clk: rockchip: add mipidsi clock on rk3288 69c923743640 ARM: dts: rockchip: correct the name of REG8 for rk3288-evb-act8846 662513a14c9d ARM: dts: rockchip: add 2 regulators for rk3288-evb-act8846 b04061e6599b ARM: dts: rockchip: move the public part to rk3288-evb common Changes in v7: - modify the config to tristate for modules build (Mark Yao) - Pass NULL 'name' to drm_encoder_init() to fix compile err (Mark Yao) - Move the lcd_en control to act8846 dts Changes in v6: - update the document, since the bridge device has been deleted. - move the mipi_en gate to ockchip_drm_crtc_mode_config - Remove the atomic feature check (Mark Yao) - Add atomic API support (Heiko Stübne) - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup Changes in v3: - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Chris Zhong (5): drm/rockchip: return a true clock rate to adjusted_mode Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver drm: rockchip: Support Synopsys DW MIPI DSI ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 + arch/arm/boot/dts/rk3288-evb-act8846.dts |2 + arch/arm/boot/dts/rk3288-evb.dtsi | 12 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1196 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + 8 files changed, 1327 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c -- 2.6.3
[PATCH v6.3 4/6] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong --- Changes in v6.3: - move the mipi_en gate to ockchip_drm_crtc_mode_config Changes in v6.2: - Remove the atomic feature check (Mark Yao) Changes in v6.1: - Add atomic API support (Heiko Stübne) Changes in v6: - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1196 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1210 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 686cb49..1db1b86 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -34,3 +34,13 @@ config ROCKCHIP_ANALOGIX_DP This selects support for Rockchip SoC specific extensions for the Analogix Core DP driver. If you want to enable DP on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + bool "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 8ad01fb..c5c2d61 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -7,5 +7,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..1fe631e --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1196 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#def
[PATCH v6.2 4/6] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong --- Changes in v6.2: - Remove the atomic feature check (Mark Yao) Changes in v6.1: - Add atomic API support (Heiko Stübne) Changes in v6: - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1196 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1210 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 686cb49..1db1b86 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -34,3 +34,13 @@ config ROCKCHIP_ANALOGIX_DP This selects support for Rockchip SoC specific extensions for the Analogix Core DP driver. If you want to enable DP on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + bool "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 8ad01fb..c5c2d61 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -7,5 +7,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..1fe631e --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1196 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_
[PATCH v6 0/6] Add mipi dsi support for rk3288
Hi Heiko Thanks for your reminder. I have post the v6.1 mipi patch with the atomic support. <https://patchwork.kernel.org/patch/7881781/> On 12/17/2015 05:29 PM, Heiko Stübner wrote: > Hi Chris, > > Am Mittwoch, 16. Dezember 2015, 18:10:10 schrieb Chris Zhong: >> The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller >> IP. This series adds support for a Synopsys DesignWare MIPI DSI host >> controller DRM driver. >> >> The MIPI DSI feature is tested on rk3288 evb board, backport them to >> chrome os kernel chrome_v3.14, and it can display normally. >> >> This patchset is base on the patchset from Ying.liu at freescale.com. >> <http://www.spinics.net/lists/dri-devel/msg77181.html> >> >> According to the suggestion from Thierry, I have get rid of the bridge, >> and register the encoder & connecter in drm/rockchip/dw-mipi-dsi.c. > from my point it looks good (although I cannot really speak on the drm-related > internals). > > But I do think we'll be doing atomic modesetting conversion first (last > version posted from Mark today), so you should probably make sure your dsi > driver still works after that conversion and make changes if needed. > > > Heiko > >> >> Changes in v6: >> - update the document, since the bridge device has been deleted. >> - Do not use bridge driver (Thierry Reding) >> - Optimization the phy init sequence >> >> Changes in v5: >> - modify the clk name to SCLK_MIPIDSI_24M >> - add a blank line befor lcd_en >> >> Changes in v4: >> - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup >> >> Changes in v3: >> - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ >> >> Chris Zhong (5): >>drm/rockchip: return a true clock rate to adjusted_mode >>Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver >>drm: rockchip: Support Synopsys DW MIPI DSI >>ARM: dts: rockchip: add rk3288 mipi_dsi nodes >>ARM: dts: rockchip: add support mipi panel tv080wum-nl0 >> >> Liu Ying (1): >>drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format >> >> .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 + >> arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- >> arch/arm/boot/dts/rk3288.dtsi | 39 + >> drivers/gpu/drm/rockchip/Kconfig | 10 + >> drivers/gpu/drm/rockchip/Makefile |1 + >> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1200 >> drivers/gpu/drm/rockchip/rockchip_drm_vop.c| >> 8 + >> include/drm/drm_mipi_dsi.h | 14 + >> 8 files changed, 1351 insertions(+), 1 deletion(-) >> create mode 100644 >> Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt >> create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > >
[PATCH v6.1 4/6] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong --- Changes in v6.1: - Add atomic API support (Heiko Stübne) Changes in v6: - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1208 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1222 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 686cb49..1db1b86 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -34,3 +34,13 @@ config ROCKCHIP_ANALOGIX_DP This selects support for Rockchip SoC specific extensions for the Analogix Core DP driver. If you want to enable DP on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + bool "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 8ad01fb..c5c2d61 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -7,5 +7,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..8413cb0 --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1208 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK
[PATCH v6 4/6] drm: rockchip: Support Synopsys DW MIPI DSI
Add support for Synopsys DesignWare MIPI DSI controller which is embedded in the rk3288 SoCs. Signed-off-by: Chris Zhong --- Changes in v6: - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/rockchip/Kconfig| 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1200 +++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c |3 + 4 files changed, 1214 insertions(+) create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 686cb49..1db1b86 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -34,3 +34,13 @@ config ROCKCHIP_ANALOGIX_DP This selects support for Rockchip SoC specific extensions for the Analogix Core DP driver. If you want to enable DP on RK3288 based SoC, you should selet this option. + +config ROCKCHIP_DW_MIPI_DSI + bool "Rockchip specific extensions for Synopsys DW MIPI DSI" + depends on DRM_ROCKCHIP + select DRM_MIPI_DSI + help +This selects support for Rockchip SoC specific extensions +for the Synopsys DesignWare HDMI driver. If you want to +enable MIPI DSI on RK3288 based SoC, you should selet this +option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index 8ad01fb..c5c2d61 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -7,5 +7,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o +obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c new file mode 100644 index 000..e38ae3f --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -0,0 +1,1200 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define DRIVER_NAME"dw-mipi-dsi" + +#define GRF_SOC_CON60x025c +#define DSI0_SEL_VOP_LIT(1 << 6) +#define DSI1_SEL_VOP_LIT(1 << 9) + +#define DSI_VERSION0x00 +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK BIT(14) +#define ENABLE_LOW_POWER (0x3f << 8) +#define
[PATCH v6 2/6] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.6.3
[PATCH v6 1/6] drm/rockchip: return a true clock rate to adjusted_mode
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- use clk_round_rate to check the clock rate in vop_crtc_mode_fixup
Changes in v3: None
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 696e977..d9ec780 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1146,9 +1146,14 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
+ struct vop *vop = to_vop(crtc);
+
if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
return false;
+ adjusted_mode->clock =
+ clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+
return true;
}
--
2.6.3
[PATCH v6 0/6] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM driver. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel chrome_v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> According to the suggestion from Thierry, I have get rid of the bridge, and register the encoder & connecter in drm/rockchip/dw-mipi-dsi.c. Changes in v6: - update the document, since the bridge device has been deleted. - Do not use bridge driver (Thierry Reding) - Optimization the phy init sequence Changes in v5: - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup Changes in v3: - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Chris Zhong (5): drm/rockchip: return a true clock rate to adjusted_mode Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver drm: rockchip: Support Synopsys DW MIPI DSI ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 Liu Ying (1): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format .../display/rockchip/dw_mipi_dsi_rockchip.txt | 60 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 1200 drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + include/drm/drm_mipi_dsi.h | 14 + 8 files changed, 1351 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/rockchip/dw-mipi-dsi.c -- 2.6.3
[PATCH v4 06/13] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
On 11/26/2015 04:04 PM, Thierry Reding wrote:
> On Thu, Nov 26, 2015 at 03:03:54PM +0800, Chris Zhong wrote:
>> Hi Thierry
>>
>> Thanks for your feedback.
>>
>>
>> On 11/21/2015 12:07 AM, Thierry Reding wrote:
>>> On Fri, Nov 20, 2015 at 04:15:32PM +0800, Chris Zhong wrote:
>>>> add Synopsys DesignWare MIPI DSI host controller driver support.
>>>>
>>>> Signed-off-by: Chris Zhong
>>>> ---
>>>>
>>>> Changes in v4:
>>>> eliminate some warnning
>>>>
>>>> Changes in v3: None
>>>> Changes in v2: None
>>>>
>>>> drivers/gpu/drm/bridge/Kconfig | 11 +
>>>> drivers/gpu/drm/bridge/Makefile |1 +
>>>> drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1056
>>>> ++
>>>> include/drm/bridge/dw_mipi_dsi.h | 27 +
>>>> 4 files changed, 1095 insertions(+)
>>>> create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c
>>>> create mode 100644 include/drm/bridge/dw_mipi_dsi.h
>>>>
>>>>
>>>> +struct dw_mipi_dsi {
>>>> + struct mipi_dsi_host dsi_host;
>>>> + struct drm_connector connector;
>>>> + struct drm_encoder *encoder;
>>> struct drm_bridge already has a pointer to an encoder, can't you reuse
>>> that instead?
>>>
>>>> + struct drm_bridge *bridge;
>>> Typically you'd embed the bridge into the driver structure.
>> I'm almost done with all the modifications according to your comments.
>> Remaining this point I can not understand, the dsi is a pointer of
>> drm_bridge,
>> hence I can not get the bridge by container_of.
>> Although, the "bridge->driver_private = dsi" have done in
>> dw_mipi_dsi_register.
> I don't understand. If you don't make bridge a pointer, but rather embed
> it within the structure, then you can use container_of(), can't you? You
> get it allocated automatically as part of allocating the dw_mipi_dsi
> structure. See for example the ps8622 and ptn3460 bridge drivers.
Yeah, got it, thanks. :)
I am going to modify it in next version patch.
>
> On a slightly unrelated note, I'm not sure if we discussed this already
> or if it was in another thread, but why is this even a bridge driver? A
> bridge is typically some IC outside of the SoC, whereas this clearly is
> IP designed into the SoC. So it's really more of an encoder rather than
> a bridge.
I guess you mean this thread <https://patchwork.kernel.org/patch/5816991/>
I think the bridge is beneficial to share the dw-mipi driver for
different soc
with same version dw-mipi IP.
>
> Thierry
[PATCH v5 08/11] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c | 249
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +
4 files changed, 263 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..24395f3 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_DW_MIPI_DSI
+ bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+ depends on DRM_ROCKCHIP
+ select DRM_DW_MIPI_DSI
+ help
+This selects support for Rockchip SoC specific extensions
+for the Synopsys DesignWare HDMI driver. If you want to
+enable MIPI DSI on RK3288 based SoC, you should selet this
+option.
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..6a97059 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi_rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
new file mode 100644
index 000..a0bb4eb
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define DRIVER_NAME"rockchip-mipi-dsi"
+
+#define GRF_SOC_CON60x025c
+#define DSI0_SEL_VOP_LIT(1 << 6)
+#define DSI1_SEL_VOP_LIT(1 << 9)
+
+struct rockchip_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct rockchip_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct rockchip_mipi_dsi, encoder);
+}
+
+static struct drm_encoder_funcs rockchip_mipi_dsi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int rockchip_mipi_parse_dt(struct rockchip_mipi_dsi *dsi)
+{
+ struct device_node *np = dsi->dev->of_node;
+
+ dsi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dsi->regmap)) {
+ dev_err(dsi->dev, "Unable to get rockchip,grf\n");
+ return PTR_ERR(dsi->regmap);
+ }
+
+ return 0;
+}
+
+static bool rockchip_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void rockchip_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(encoder);
+
+ switch (encoder_pix_fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P565;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
+ rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_DSI,
+ interface_pix_fmt);
+}
+
+static void rockchip_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
[PATCH v5 07/11] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
add Synopsys DesignWare MIPI DSI host controller driver support. Signed-off-by: Chris Zhong Signed-off-by: Liu Ying --- Changes in v5: Adviced by Thierry - use hyphens instead of underscore - use encoder in drm_bridge - reformatting the dptdin table - use readx_poll_timeout to check register - use msleep to wait - add a comment to explain how to program phy - change the program code to symbolic names - check this for validity of find_panel and clk_prepare_enable - eliminate the configuration clock - some optimization for coding style Changes in v4: - eliminate some warnning Changes in v3: None Changes in v2: None drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw-mipi-dsi.c | 1084 ++ include/drm/bridge/dw_mipi_dsi.h | 28 + 4 files changed, 1123 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw-mipi-dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 639..d9ca7b4 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -22,6 +22,16 @@ config DRM_DW_HDMI_AHB_AUDIO Designware HDMI block. This is used in conjunction with the i.MX6 HDMI driver. +config DRM_DW_MIPI_DSI + tristate "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. If M is selected, the module will be + called dw-mipi-dsi. config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d4e28be..96c54af 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,5 +2,6 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw_hdmi-ahb-audio.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o diff --git a/drivers/gpu/drm/bridge/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/dw-mipi-dsi.c new file mode 100644 index 000..26b96e8 --- /dev/null +++ b/drivers/gpu/drm/bridge/dw-mipi-dsi.c @@ -0,0 +1,1084 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK BIT(14) +#define ENABLE_LOW_POWER (0x3f << 8) +#define ENABLE_LOW_POWER_MASK (0x3f << 8) +#define VI
[PATCH v5 05/11] drm: bridge: allow some funcs to be optional
Check the validity of post_disable/pre_enable in bridge->funcs before call them. Signed-off-by: Chris Zhong --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None drivers/gpu/drm/drm_bridge.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 6b8f721..8f29330 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -223,7 +223,8 @@ void drm_bridge_post_disable(struct drm_bridge *bridge) if (!bridge) return; - bridge->funcs->post_disable(bridge); + if (bridge->funcs->post_disable) + bridge->funcs->post_disable(bridge); drm_bridge_post_disable(bridge->next); } @@ -273,7 +274,8 @@ void drm_bridge_pre_enable(struct drm_bridge *bridge) drm_bridge_pre_enable(bridge->next); - bridge->funcs->pre_enable(bridge); + if (bridge->funcs->pre_enable) + bridge->funcs->pre_enable(bridge); } EXPORT_SYMBOL(drm_bridge_pre_enable); -- 2.6.3
[PATCH v5 04/11] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.6.3
[PATCH v5 03/11] drm/rockchip: return a true clock rate to adjusted_mode
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
Acked-by: Mark Yao
---
Changes in v5: None
Changes in v4:
- use clk_round_rate to check the clock rate in vop_crtc_mode_fixup
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..eff545b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1136,9 +1136,14 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
+ struct vop *vop = to_vop(crtc);
+
if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
return false;
+ adjusted_mode->clock =
+ clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+
return true;
}
--
2.6.3
[PATCH v5 0/11] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v5: - change the mipidsi clk to SCLK_MIPIDSI_24M - modify the mipidsi clk name to SCLK_MIPIDSI_24M Adviced by Thierry - use hyphens instead of underscore - use encoder in drm_bridge - reformatting the dptdin table - use readx_poll_timeout to check register - use msleep to wait - add a comment to explain how to program phy - change the program code to symbolic names - check this for validity of find_panel and clk_prepare_enable - eliminate the configuration clock - some optimization for coding style - modify the clk name to SCLK_MIPIDSI_24M - add a blank line befor lcd_en Changes in v4: - use clk_round_rate to check the clock rate in vop_crtc_mode_fixup - remove the cfg clk - remove gpr property from example, since it is noused now. - add the description about ports - eliminate some warnning Changes in v3: - move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge - move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ Changes in v2: - add the mipi clk id in a single patch Chris Zhong (9): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm: bridge: allow some funcs to be optional drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for DW MIPI DSI .../bindings/display/bridge/dw_mipi_dsi.txt| 74 ++ .../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw-mipi-dsi.c | 1084 drivers/gpu/drm/drm_bridge.c |6 +- drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + include/drm/bridge/dw_mipi_dsi.h | 28 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 16 files changed, 1599 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw-mipi-dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.3
[PATCH v4 06/13] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
Hi Thierry
Thanks for your feedback.
On 11/21/2015 12:07 AM, Thierry Reding wrote:
> On Fri, Nov 20, 2015 at 04:15:32PM +0800, Chris Zhong wrote:
>> add Synopsys DesignWare MIPI DSI host controller driver support.
>>
>> Signed-off-by: Chris Zhong
>> ---
>>
>> Changes in v4:
>> eliminate some warnning
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>> drivers/gpu/drm/bridge/Kconfig | 11 +
>> drivers/gpu/drm/bridge/Makefile |1 +
>> drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1056
>> ++
>> include/drm/bridge/dw_mipi_dsi.h | 27 +
>> 4 files changed, 1095 insertions(+)
>> create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c
>> create mode 100644 include/drm/bridge/dw_mipi_dsi.h
>>
>>
>> +struct dw_mipi_dsi {
>> +struct mipi_dsi_host dsi_host;
>> +struct drm_connector connector;
>> +struct drm_encoder *encoder;
> struct drm_bridge already has a pointer to an encoder, can't you reuse
> that instead?
>
>> +struct drm_bridge *bridge;
> Typically you'd embed the bridge into the driver structure.
I'm almost done with all the modifications according to your comments.
Remaining this point I can not understand, the dsi is a pointer of
drm_bridge,
hence I can not get the bridge by container_of.
Although, the "bridge->driver_private = dsi" have done in
dw_mipi_dsi_register.
>
>> +struct drm_panel *panel;
>> +struct device *dev;
>> +
>> +void __iomem *base;
>> +
>> +struct clk *pllref_clk;
>> +struct clk *cfg_clk;
>> +struct clk *pclk;
>> +
>> +unsigned int lane_mbps; /* per lane */
>> +u32 channel;
>> +u32 lanes;
>> +u32 format;
>> +u16 input_div;
>> +u16 feedback_div;
>> +struct drm_display_mode *mode;
>> +
>> +const struct dw_mipi_dsi_plat_data *pdata;
>> +
>> +bool enabled;
>> +};
>> +
>>
>>
>> Thierry
[PATCH v4 13/13] ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boot/dts/rk3288-evb.dtsi
index f6d2e78..d04878f 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,7 +47,7 @@
reg = <0x0 0x8000>;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
@@ -177,6 +177,21 @@
status = "okay";
};
+_dsi {
+ status = "okay";
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = < 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_en>;
+ backlight = <>;
+ status = "okay";
+ };
+};
+
{
bus-width = <4>;
cap-mmc-highspeed;
@@ -247,6 +262,9 @@
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO _pull_none>;
};
+ lcd_en: lcd-en {
+ rockchip,pins = <7 3 RK_FUNC_GPIO _pull_none>;
+ };
};
buttons {
--
2.6.3
[PATCH v4 12/13] drm/panel: simple: Add boe, tv080wum-nl0 simple panel device tree binding
This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v4: None Changes in v3: move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: As Thierry.Reding comment, add a documentation for this panel. .../devicetree/bindings/display/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.3
[PATCH v4 11/13] drm/panel: simple: Add support for BOE TV080WUM-NL0
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
Changes in v4:
Alphabetically arranged the name
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index f97b73e..e3ac2de 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1263,6 +1263,36 @@ static const struct panel_desc_dsi auo_b080uan01 = {
.lanes = 4,
};
+static const struct drm_display_mode boe_tv080wum_nl0_mode = {
+ .clock = 16,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 120,
+ .hsync_end = 1200 + 120 + 20,
+ .htotal = 1200 + 120 + 20 + 21,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 21,
+ .vsync_end = 1920 + 21 + 3,
+ .vtotal = 1920 + 21 + 3 + 18,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc_dsi boe_tv080wum_nl0 = {
+ .desc = {
+ .modes = _tv080wum_nl0_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 107,
+ .height = 172,
+ },
+ },
+ .flags = MIPI_DSI_MODE_VIDEO |
+MIPI_DSI_MODE_VIDEO_BURST |
+MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
+ .format = MIPI_DSI_FMT_RGB888,
+ .lanes = 4,
+};
+
static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
.clock = 71000,
.hdisplay = 800,
@@ -1348,11 +1378,15 @@ static const struct panel_desc_dsi
panasonic_vvx10f004b00 = {
.lanes = 4,
};
+
static const struct of_device_id dsi_of_match[] = {
{
.compatible = "auo,b080uan01",
.data = _b080uan01
}, {
+ .compatible = "boe,tv080wum-nl0",
+ .data = _tv080wum_nl0
+ }, {
.compatible = "lg,ld070wx3-sl01",
.data = _ld070wx3_sl01
}, {
--
2.6.3
[PATCH v4 10/13] of: add vendor prefix for boe
Signed-off-by: Chris Zhong Acked-by: Rob Herring --- Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 55df1d4..0f88d6f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -33,6 +33,7 @@ auo AU Optronics Corporation avago Avago Technologies avic Shanghai AVIC Optoelectronics Co., Ltd. axis Axis Communications AB +boeBOE Technology Group Co., Ltd. bosch Bosch Sensortec GmbH boundary Boundary Devices Inc. brcm Broadcom Corporation -- 2.6.3
[PATCH v4 09/13] ARM: dts: rockchip: add rk3288 mipi_dsi nodes
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6a79c9c..a5c5670 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -798,6 +798,10 @@
reg = <0>;
remote-endpoint = <_in_vopb>;
};
+ vopb_out_mipi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <_in_vopb>;
+ };
};
};
@@ -831,6 +835,10 @@
reg = <0>;
remote-endpoint = <_in_vopl>;
};
+ vopl_out_mipi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <_in_vopl>;
+ };
};
};
@@ -871,6 +879,37 @@
};
};
+ mipi_dsi: mipi at ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = < SCLK_MIPI_24M>, < PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <_out_mipi>;
+ };
+ mipi_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <_out_mipi>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller at ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
--
2.6.3
[PATCH v4 08/13] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
Acked-by: Rob Herring
---
Changes in v4: None
Changes in v3:
move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/
Changes in v2: None
.../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
new file mode 100644
index 000..acd9ec9
--- /dev/null
+++
b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -0,0 +1,56 @@
+Rockchip specific extensions to the Synopsys Designware MIPI DSI
+
+
+Required properties:
+- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+- ports: contain a port node with endpoint definitions as defined in [1].
+ For vopb,set the reg = <0> and set the reg = <1> for vopl.
+
+For more required properties, please refer to [2].
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+[2] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+
+Example:
+ mipi_dsi: mipi at ff96 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0xff96 0x4000>;
+ interrupts = ;
+ clocks = < SCLK_MIPI_24M>, < PCLK_MIPI_DSI0>;
+ clock-names = "ref", "pclk";
+ rockchip,grf = <>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mipi_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <_out_mipi>;
+ };
+ mipi_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <_out_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible ="boe,tv080wum-nl0";
+ reg = <0>;
+
+ enable-gpios = < 3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_en>;
+ backlight = <>;
+ status = "okay";
+ };
+ };
--
2.6.3
[PATCH v4 07/13] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c | 249
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +
4 files changed, 263 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..24395f3 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_DW_MIPI_DSI
+ bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+ depends on DRM_ROCKCHIP
+ select DRM_DW_MIPI_DSI
+ help
+This selects support for Rockchip SoC specific extensions
+for the Synopsys DesignWare HDMI driver. If you want to
+enable MIPI DSI on RK3288 based SoC, you should selet this
+option.
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..6a97059 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi_rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
new file mode 100644
index 000..a0bb4eb
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define DRIVER_NAME"rockchip-mipi-dsi"
+
+#define GRF_SOC_CON60x025c
+#define DSI0_SEL_VOP_LIT(1 << 6)
+#define DSI1_SEL_VOP_LIT(1 << 9)
+
+struct rockchip_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct rockchip_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct rockchip_mipi_dsi, encoder);
+}
+
+static struct drm_encoder_funcs rockchip_mipi_dsi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int rockchip_mipi_parse_dt(struct rockchip_mipi_dsi *dsi)
+{
+ struct device_node *np = dsi->dev->of_node;
+
+ dsi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dsi->regmap)) {
+ dev_err(dsi->dev, "Unable to get rockchip,grf\n");
+ return PTR_ERR(dsi->regmap);
+ }
+
+ return 0;
+}
+
+static bool rockchip_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void rockchip_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(encoder);
+
+ switch (encoder_pix_fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P565;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
+ rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_DSI,
+ interface_pix_fmt);
+}
+
+static void rockchip_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void rockchip_
[PATCH v4 06/13] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
add Synopsys DesignWare MIPI DSI host controller driver support. Signed-off-by: Chris Zhong --- Changes in v4: eliminate some warnning Changes in v3: None Changes in v2: None drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1056 ++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1095 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 639..c0900e0 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -22,6 +22,17 @@ config DRM_DW_HDMI_AHB_AUDIO Designware HDMI block. This is used in conjunction with the i.MX6 HDMI driver. +config DRM_DW_MIPI_DSI + tristate "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. If M is selected, the module will be + called dw_mipi_dsi. DRM_MIPI_DSI support is required for this driver + to work. config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d4e28be..d908c4b 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,5 +2,6 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw_hdmi-ahb-audio.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..23b612d --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,1056 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK BIT(14) +#define ENABLE_LOW_POWER (0x3f << 8) +#define ENABLE_LOW_POWER_MASK (0x3f << 8) +#define VID_MODE_TYPE_BURST_SYNC_PULSES0x2 +#define VID_MODE_TYPE_MASK 0x3 + +#define DSI_VID_PKT_SIZE 0x3c +#define VID_PKT_SIZE(p)(((p) & 0x3fff) << 0) +#define VID_PKT_MAX_SIZE 0x3fff + +#define DSI_VID_HSA_TIME 0x48 +#define DSI_VID_HBP_TIME 0x4c +#define DSI
[PATCH v4 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver
From: Liu Ying <ying@freescale.com>
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
Changes in v4:
remove gpr property from example, since it is noused now.
add the description about ports
Changes in v3:
move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge
Changes in v2: None
.../bindings/display/bridge/dw_mipi_dsi.txt| 80 ++
1 file changed, 80 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000..8572ab3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,80 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+ for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific
+ device tree binding documentations. A common compatible string
+ "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref), configuration clock(cfg) and APB clock(pclk), as
+ described in [1].
+ - port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+*
Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi-rockchip.txt
+
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+example:
+ gpr: iomuxc-gpr at 020e {
+ /* ... */
+ };
+
+ mipi_dsi: mipi at 021e {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = < IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_CORE_CFG>,
+< IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "cfg", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <_di0_mipi>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <_di1_mipi>;
+ };
+ };
+ };
+
+ panel {
+ compatible = "truly,tft480800-16-e-dsi";
+ reg = <0>;
+ /* ... */
+ };
+ };
--
2.6.3
[PATCH v4 04/13] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.6.3
[PATCH v4 03/13] drm/rockchip: return a true clock rate to adjusted_mode
Since the mipi dsi driver need to use the clock of vop to make the
calculation of Blanking. But sometimes the clock driver can not set a
accurate clock_rate for vop, get it by clk_round_rate before mode_set,
so we can get the true value.
Signed-off-by: Chris Zhong
---
Changes in v4:
use clk_round_rate to check the clock rate in vop_crtc_mode_fixup
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..eff545b 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1136,9 +1136,14 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
+ struct vop *vop = to_vop(crtc);
+
if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
return false;
+ adjusted_mode->clock =
+ clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+
return true;
}
--
2.6.3
[PATCH v4 02/13] clk: rockchip: add mipidsi clocks on rk3288
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/clk/rockchip/clk-rk3288.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 9040878..c7d7ebf 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
__initdata = {
GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0,
RK3288_CLKGATE_CON(13), 11, GFLAGS),
GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0,
RK3288_CLKGATE_CON(5), 9, GFLAGS),
GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
RK3288_CLKGATE_CON(5), 10, GFLAGS),
- GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15,
GFLAGS),
+ GATE(SCLK_MIPI_24M, "sclk_mipidsi_24m", "xin24m", 0,
RK3288_CLKGATE_CON(5), 15, GFLAGS),
/* sclk_gpu gates */
GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0,
GFLAGS),
--
2.6.3
[PATCH v4 01/13] clk: rockchip: add id for mipidsi sclk on rk3288
Adds a new id for the sclk supplying the mipidsi on rk3288 socs. Signed-off-by: Chris Zhong --- Changes in v4: None Changes in v3: None Changes in v2: add the mipi clk id in a single patch include/dt-bindings/clock/rk3288-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index c719aac..b07cdd3 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -86,6 +86,7 @@ #define SCLK_USBPHY480M_SRC122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_MIPI_24M 125 #define SCLK_MAC 151 #define SCLK_MACREF_OUT152 -- 2.6.3
[PATCH v4 0/13] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v4: use clk_round_rate to check the clock rate in vop_crtc_mode_fixup remove gpr property from example, since it is noused now. add the description about ports eliminate some warnning Alphabetically arranged the name Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: add the mipi clk id in a single patch As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (11): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes of: add vendor prefix for boe drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../bindings/display/bridge/dw_mipi_dsi.txt| 80 ++ .../bindings/display/panel/boe,tv080wum-nl0.txt|7 + .../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++ .../devicetree/bindings/vendor-prefixes.txt|1 + arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1056 drivers/gpu/drm/panel/panel-simple.c | 34 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|8 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 18 files changed, 1615 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.3
[PATCH v3 00/12] Add mipi dsi support for rk3288
Hi Emil On 11/19/2015 10:41 PM, Emil Velikov wrote: > On 19 November 2015 at 03:35, Chris Zhong wrote: >> The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller >> IP. This series adds support for a Synopsys DesignWare MIPI DSI host >> controller DRM bridge driver and a rockchip MIPI DSI specific DRM >> driver. >> >> This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. >> This panel only use the MIPI DSI video mode. >> >> The MIPI DSI feature is tested on rk3288 evb board, backport them to >> chrome os kernel v3.14, and it can display normally. >> >> This patchset is base on the patchset from Ying.liu at freescale.com. >> <http://www.spinics.net/lists/dri-devel/msg77181.html> >> >> >> Changes in v3: >> move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge >> move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ >> move boe,tv080wum-nl0.txt to bindings/display/panel/ >> >> Changes in v2: >> add the mipi clk id in a single patch >> As Thierry.Reding comment, add a documentation for this panel. >> >> Chris Zhong (10): >>clk: rockchip: add id for mipidsi sclk on rk3288 >>clk: rockchip: add mipidsi clocks on rk3288 >>drm/rockchip: return a true clock rate to adjusted_mode >>drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver > Did you actually rewrite the patch from Liu Ying ? I modify the dw_mipi_dsi.c based on the patch from Liu Ying. > Out of curiosity what was the obstacle of this work getting merged ? There are different version dw controller, and it is too hard to merge them, since most registers are different. > >>drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller >>Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver >>ARM: dts: rockchip: add rk3288 mipi_dsi nodes >>drm/panel: simple: Add support for BOE TV080WUM-NL0 >>drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree >> binding > As the DT people will tell you - there is no BOE vendor in > bindings/vendor-prefixes.txt. Yes, I have post a verdor patch in v2 series, <https://patchwork.kernel.org/patch/7530791/> Maybe I should add it back to series with Acked-by: Rob Herring > >>ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb >> >> Liu Ying (2): >>drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format >>Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM >> bridge driver >> > >From the above 12 patches only ~6 reached this mailing list is that > intentional ? Previously I've seen people CC dri-devel for their > panel/bridge DT patches. I use the patman to post the series, forgot to add you and Thierry to the to-list. I will fix in next version series. Thanks for your reply. > > Regards, > Emil > > >
[PATCH v3 03/12] drm/rockchip: return a true clock rate to adjusted_mode
On 11/19/2015 03:08 PM, Mark yao wrote:
> On 2015å¹´11æ19æ¥ 11:35, Chris Zhong wrote:
>> +
>> +/*
>> + * Sometimes the clock driver can not set a accurate clock_rate
>> for vop,
>> + * get the true rate of vop_dclk and set it back to adjusted_mode.
>> + */
>> +adjusted_mode->clock = clk_get_rate(vop->dclk) / 1000;
>> out:
>> ret_clk = clk_enable(vop->dclk);
>> if (ret_clk < 0) {
> Hi Chris
> How about use clk_round_rate to check the clock rate first?
> I think we can check it on vop_crtc_mode_fixup.
Hi Mark
Nice advice, I'll modify it in next version. Thanks.
>
> Thanks.
> - ï¼ark Yao
>
>
>
[PATCH v3 11/12] drm/panel: simple: Add boe, tv080wum-nl0 simple panel device tree binding
This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong --- Changes in v3: move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: As Thierry.Reding comment, add a documentation for this panel. .../devicetree/bindings/display/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.3
[PATCH v3 10/12] drm/panel: simple: Add support for BOE TV080WUM-NL0
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index f97b73e..3610e1c 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1348,6 +1348,36 @@ static const struct panel_desc_dsi
panasonic_vvx10f004b00 = {
.lanes = 4,
};
+static const struct drm_display_mode boe_tv080wum_nl0_mode = {
+ .clock = 16,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 120,
+ .hsync_end = 1200 + 120 + 20,
+ .htotal = 1200 + 120 + 20 + 21,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 21,
+ .vsync_end = 1920 + 21 + 3,
+ .vtotal = 1920 + 21 + 3 + 18,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc_dsi boe_tv080wum_nl0 = {
+ .desc = {
+ .modes = _tv080wum_nl0_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 107,
+ .height = 172,
+ },
+ },
+ .flags = MIPI_DSI_MODE_VIDEO |
+MIPI_DSI_MODE_VIDEO_BURST |
+MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
+ .format = MIPI_DSI_FMT_RGB888,
+ .lanes = 4,
+};
+
static const struct of_device_id dsi_of_match[] = {
{
.compatible = "auo,b080uan01",
@@ -1362,6 +1392,9 @@ static const struct of_device_id dsi_of_match[] = {
.compatible = "panasonic,vvx10f004b00",
.data = _vvx10f004b00
}, {
+ .compatible = "boe,tv080wum-nl0",
+ .data = _tv080wum_nl0
+ }, {
/* sentinel */
}
};
--
2.6.3
[PATCH v3 07/12] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c | 249
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +
4 files changed, 263 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..24395f3 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_DW_MIPI_DSI
+ bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+ depends on DRM_ROCKCHIP
+ select DRM_DW_MIPI_DSI
+ help
+This selects support for Rockchip SoC specific extensions
+for the Synopsys DesignWare HDMI driver. If you want to
+enable MIPI DSI on RK3288 based SoC, you should selet this
+option.
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..6a97059 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi_rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
new file mode 100644
index 000..a0bb4eb
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define DRIVER_NAME"rockchip-mipi-dsi"
+
+#define GRF_SOC_CON60x025c
+#define DSI0_SEL_VOP_LIT(1 << 6)
+#define DSI1_SEL_VOP_LIT(1 << 9)
+
+struct rockchip_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct rockchip_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct rockchip_mipi_dsi, encoder);
+}
+
+static struct drm_encoder_funcs rockchip_mipi_dsi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int rockchip_mipi_parse_dt(struct rockchip_mipi_dsi *dsi)
+{
+ struct device_node *np = dsi->dev->of_node;
+
+ dsi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dsi->regmap)) {
+ dev_err(dsi->dev, "Unable to get rockchip,grf\n");
+ return PTR_ERR(dsi->regmap);
+ }
+
+ return 0;
+}
+
+static bool rockchip_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void rockchip_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(encoder);
+
+ switch (encoder_pix_fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P565;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
+ rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_DSI,
+ interface_pix_fmt);
+}
+
+static void rockchip_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void rockchip_mipi_dsi_encoder_comm
[PATCH v3 06/12] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
add Synopsys DesignWare MIPI DSI host controller driver support. Signed-off-by: Chris Zhong --- Changes in v3: None Changes in v2: None drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 ++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1094 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 639..c0900e0 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -22,6 +22,17 @@ config DRM_DW_HDMI_AHB_AUDIO Designware HDMI block. This is used in conjunction with the i.MX6 HDMI driver. +config DRM_DW_MIPI_DSI + tristate "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + help + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. If M is selected, the module will be + called dw_mipi_dsi. DRM_MIPI_DSI support is required for this driver + to work. config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d4e28be..d908c4b 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,5 +2,6 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw_hdmi-ahb-audio.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..442fc7c --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,1055 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK BIT(14) +#define ENABLE_LOW_POWER (0x3f << 8) +#define ENABLE_LOW_POWER_MASK (0x3f << 8) +#define VID_MODE_TYPE_BURST_SYNC_PULSES0x2 +#define VID_MODE_TYPE_MASK 0x3 + +#define DSI_VID_PKT_SIZE 0x3c +#define VID_PKT_SIZE(p)(((p) & 0x3fff) << 0) +#define VID_PKT_MAX_SIZE 0x3fff + +#define DSI_VID_HSA_TIME 0x48 +#define DSI_VID_HBP_TIME 0x4c +#define DSI_VID_HLINE_TIME 0x50 +#define DSI
[PATCH v3 04/12] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.6.3
[PATCH v3 03/12] drm/rockchip: return a true clock rate to adjusted_mode
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9986b311ed 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1232,6 +1232,12 @@ static int vop_crtc_mode_set(struct drm_crtc *crtc,
reset_control_deassert(vop->dclk_rst);
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
+
+ /*
+* Sometimes the clock driver can not set a accurate clock_rate for vop,
+* get the true rate of vop_dclk and set it back to adjusted_mode.
+*/
+ adjusted_mode->clock = clk_get_rate(vop->dclk) / 1000;
out:
ret_clk = clk_enable(vop->dclk);
if (ret_clk < 0) {
--
2.6.3
[PATCH v3 00/12] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge move dw_mipi_dsi_rockchip.txt to bindings/display/rockchip/ move boe,tv080wum-nl0.txt to bindings/display/panel/ Changes in v2: add the mipi clk id in a single patch As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (10): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add boe,tv080wum-nl0 simple panel device tree binding ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../bindings/display/bridge/dw_mipi_dsi.txt| 76 ++ .../bindings/display/panel/boe,tv080wum-nl0.txt|7 + .../display/rockchip/dw_mipi_dsi_rockchip.txt | 56 ++ arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 11 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 drivers/gpu/drm/panel/panel-simple.c | 33 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|9 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 17 files changed, 1609 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/display/panel/boe,tv080wum-nl0.txt create mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.3
[PATCH v2 12/13] drm/panel: simple: Add simple panel device tree binding
Hi Rob On 11/02/2015 11:06 PM, Rob Herring wrote: > On Sat, Oct 31, 2015 at 7:56 AM, Chris Zhong wrote: > > Your subject should be more specific with the panel name. I'll write more specific in subject next version. > >> This binding specifies a set of common properties for display panels. It >> can be used as a basis by bindings for specific panels. >> Bindings for three specific panels are provided to show how the >> simple panel binding can be used. >> >> Signed-off-by: Chris Zhong >> >> --- >> >> Changes in v2: >> As Thierry.Reding comment, add a documentation for this panel. >> >> Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt | 7 +++ >> 1 file changed, 7 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt > Please move to bindings/display/panel/ Okay. > >> diff --git a/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt >> b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt >> new file mode 100644 >> index 000..50be5e2 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt >> @@ -0,0 +1,7 @@ >> +Boe Corporation 8.0" WUXGA TFT LCD panel >> + >> +Required properties: >> +- compatible: should be "boe,tv080wum-nl0" >> + >> +This binding is compatible with the simple-panel binding, which is specified >> +in simple-panel.txt in this directory. >> -- >> 2.6.2 >> > >
[PATCH v2 12/13] drm/panel: simple: Add simple panel device tree binding
This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Signed-off-by: Chris Zhong --- Changes in v2: As Thierry.Reding comment, add a documentation for this panel. Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt diff --git a/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt new file mode 100644 index 000..50be5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt @@ -0,0 +1,7 @@ +Boe Corporation 8.0" WUXGA TFT LCD panel + +Required properties: +- compatible: should be "boe,tv080wum-nl0" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. -- 2.6.2
[PATCH v2 11/13] drm/panel: simple: Add support for BOE TV080WUM-NL0
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index f97b73e..3610e1c 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1348,6 +1348,36 @@ static const struct panel_desc_dsi
panasonic_vvx10f004b00 = {
.lanes = 4,
};
+static const struct drm_display_mode boe_tv080wum_nl0_mode = {
+ .clock = 16,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 120,
+ .hsync_end = 1200 + 120 + 20,
+ .htotal = 1200 + 120 + 20 + 21,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 21,
+ .vsync_end = 1920 + 21 + 3,
+ .vtotal = 1920 + 21 + 3 + 18,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc_dsi boe_tv080wum_nl0 = {
+ .desc = {
+ .modes = _tv080wum_nl0_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 107,
+ .height = 172,
+ },
+ },
+ .flags = MIPI_DSI_MODE_VIDEO |
+MIPI_DSI_MODE_VIDEO_BURST |
+MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
+ .format = MIPI_DSI_FMT_RGB888,
+ .lanes = 4,
+};
+
static const struct of_device_id dsi_of_match[] = {
{
.compatible = "auo,b080uan01",
@@ -1362,6 +1392,9 @@ static const struct of_device_id dsi_of_match[] = {
.compatible = "panasonic,vvx10f004b00",
.data = _vvx10f004b00
}, {
+ .compatible = "boe,tv080wum-nl0",
+ .data = _tv080wum_nl0
+ }, {
/* sentinel */
}
};
--
2.6.2
[PATCH v2 07/13] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c | 249
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +
4 files changed, 263 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..24395f3 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_DW_MIPI_DSI
+ bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+ depends on DRM_ROCKCHIP
+ select DRM_DW_MIPI_DSI
+ help
+This selects support for Rockchip SoC specific extensions
+for the Synopsys DesignWare HDMI driver. If you want to
+enable MIPI DSI on RK3288 based SoC, you should selet this
+option.
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..6a97059 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi_rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
new file mode 100644
index 000..a0bb4eb
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define DRIVER_NAME"rockchip-mipi-dsi"
+
+#define GRF_SOC_CON60x025c
+#define DSI0_SEL_VOP_LIT(1 << 6)
+#define DSI1_SEL_VOP_LIT(1 << 9)
+
+struct rockchip_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct rockchip_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct rockchip_mipi_dsi, encoder);
+}
+
+static struct drm_encoder_funcs rockchip_mipi_dsi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int rockchip_mipi_parse_dt(struct rockchip_mipi_dsi *dsi)
+{
+ struct device_node *np = dsi->dev->of_node;
+
+ dsi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dsi->regmap)) {
+ dev_err(dsi->dev, "Unable to get rockchip,grf\n");
+ return PTR_ERR(dsi->regmap);
+ }
+
+ return 0;
+}
+
+static bool rockchip_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void rockchip_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(encoder);
+
+ switch (encoder_pix_fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P565;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
+ rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_DSI,
+ interface_pix_fmt);
+}
+
+static void rockchip_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void rockchip_mipi_dsi_encoder_commit(struct drm_enco
[PATCH v2 06/13] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
add Synopsys DesignWare MIPI DSI host controller driver support. Signed-off-by: Chris Zhong --- Changes in v2: None drivers/gpu/drm/bridge/Kconfig |9 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 ++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1092 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 639..d6bde0d 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -22,6 +22,15 @@ config DRM_DW_HDMI_AHB_AUDIO Designware HDMI block. This is used in conjunction with the i.MX6 HDMI driver. +config DRM_DW_MIPI_DSI + tristate "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d4e28be..d908c4b 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -2,5 +2,6 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw_hdmi-ahb-audio.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..442fc7c --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,1055 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK BIT(14) +#define ENABLE_LOW_POWER (0x3f << 8) +#define ENABLE_LOW_POWER_MASK (0x3f << 8) +#define VID_MODE_TYPE_BURST_SYNC_PULSES0x2 +#define VID_MODE_TYPE_MASK 0x3 + +#define DSI_VID_PKT_SIZE 0x3c +#define VID_PKT_SIZE(p)(((p) & 0x3fff) << 0) +#define VID_PKT_MAX_SIZE 0x3fff + +#define DSI_VID_HSA_TIME 0x48 +#define DSI_VID_HBP_TIME 0x4c +#define DSI_VID_HLINE_TIME 0x50 +#define DSI_VID_VSA_LINES 0x54 +#define DSI_VID_VBP_LINES 0x58 +#define DSI_VID_VFP_LINES 0x5c +#define DSI_VID_VACTIVE_LINES
[PATCH v2 04/13] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
Changes in v2: None
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.6.2
[PATCH v2 03/13] drm/rockchip: return a true clock rate to adjusted_mode
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
Changes in v2: None
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9986b311ed 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1232,6 +1232,12 @@ static int vop_crtc_mode_set(struct drm_crtc *crtc,
reset_control_deassert(vop->dclk_rst);
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
+
+ /*
+* Sometimes the clock driver can not set a accurate clock_rate for vop,
+* get the true rate of vop_dclk and set it back to adjusted_mode.
+*/
+ adjusted_mode->clock = clk_get_rate(vop->dclk) / 1000;
out:
ret_clk = clk_enable(vop->dclk);
if (ret_clk < 0) {
--
2.6.2
[PATCH v2 00/13] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Changes in v2: add the mipi clk id in a single patch add vendor prefix for boe As Thierry.Reding comment, add a documentation for this panel. Chris Zhong (11): clk: rockchip: add id for mipidsi sclk on rk3288 clk: rockchip: add mipidsi clocks on rk3288 drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes of: add vendor prefix for boe drm/panel: simple: Add support for BOE TV080WUM-NL0 drm/panel: simple: Add simple panel device tree binding ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++ .../devicetree/bindings/panel/boe,tv080wum-nl0.txt |7 + .../devicetree/bindings/vendor-prefixes.txt|1 + .../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++ arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig |9 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 drivers/gpu/drm/panel/panel-simple.c | 33 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|9 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 18 files changed, 1608 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/panel/boe,tv080wum-nl0.txt create mode 100644 Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.2
[PATCH 09/10] drm/panel: simple: Add support for BOE TV080WUM-NL0
This adds support for the BOE TV080WUM-NL0 1200x1920 mipi panel to the
DRM simple panel driver.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/panel/panel-simple.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index f97b73e..3610e1c 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1348,6 +1348,36 @@ static const struct panel_desc_dsi
panasonic_vvx10f004b00 = {
.lanes = 4,
};
+static const struct drm_display_mode boe_tv080wum_nl0_mode = {
+ .clock = 16,
+ .hdisplay = 1200,
+ .hsync_start = 1200 + 120,
+ .hsync_end = 1200 + 120 + 20,
+ .htotal = 1200 + 120 + 20 + 21,
+ .vdisplay = 1920,
+ .vsync_start = 1920 + 21,
+ .vsync_end = 1920 + 21 + 3,
+ .vtotal = 1920 + 21 + 3 + 18,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc_dsi boe_tv080wum_nl0 = {
+ .desc = {
+ .modes = _tv080wum_nl0_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 107,
+ .height = 172,
+ },
+ },
+ .flags = MIPI_DSI_MODE_VIDEO |
+MIPI_DSI_MODE_VIDEO_BURST |
+MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
+ .format = MIPI_DSI_FMT_RGB888,
+ .lanes = 4,
+};
+
static const struct of_device_id dsi_of_match[] = {
{
.compatible = "auo,b080uan01",
@@ -1362,6 +1392,9 @@ static const struct of_device_id dsi_of_match[] = {
.compatible = "panasonic,vvx10f004b00",
.data = _vvx10f004b00
}, {
+ .compatible = "boe,tv080wum-nl0",
+ .data = _tv080wum_nl0
+ }, {
/* sentinel */
}
};
--
2.6.1
[PATCH 06/10] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller
Add support for Synopsys DesignWare MIPI DSI host controller which is
embedded in the rk3288 SoCs.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c | 249
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +
4 files changed, 263 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..24395f3 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,13 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_DW_MIPI_DSI
+ bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+ depends on DRM_ROCKCHIP
+ select DRM_DW_MIPI_DSI
+ help
+This selects support for Rockchip SoC specific extensions
+for the Synopsys DesignWare HDMI driver. If you want to
+enable MIPI DSI on RK3288 based SoC, you should selet this
+option.
diff --git a/drivers/gpu/drm/rockchip/Makefile
b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..6a97059 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o
rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi_rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
new file mode 100644
index 000..a0bb4eb
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define DRIVER_NAME"rockchip-mipi-dsi"
+
+#define GRF_SOC_CON60x025c
+#define DSI0_SEL_VOP_LIT(1 << 6)
+#define DSI1_SEL_VOP_LIT(1 << 9)
+
+struct rockchip_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *regmap;
+};
+
+static inline struct rockchip_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct rockchip_mipi_dsi, encoder);
+}
+
+static struct drm_encoder_funcs rockchip_mipi_dsi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int rockchip_mipi_parse_dt(struct rockchip_mipi_dsi *dsi)
+{
+ struct device_node *np = dsi->dev->of_node;
+
+ dsi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dsi->regmap)) {
+ dev_err(dsi->dev, "Unable to get rockchip,grf\n");
+ return PTR_ERR(dsi->regmap);
+ }
+
+ return 0;
+}
+
+static bool rockchip_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void rockchip_mipi_dsi_encoder_prepare(struct drm_encoder *encoder)
+{
+ u32 encoder_pix_fmt, interface_pix_fmt;
+
+ encoder_pix_fmt = dw_mipi_dsi_get_encoder_pixel_format(encoder);
+
+ switch (encoder_pix_fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P888;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P666;
+ break;
+ case MIPI_DSI_FMT_RGB565:
+ interface_pix_fmt = ROCKCHIP_OUT_MODE_P565;
+ break;
+ default:
+ WARN_ON(1);
+ return;
+ }
+
+ rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_DSI,
+ interface_pix_fmt);
+}
+
+static void rockchip_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void rockchip_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
+{
[PATCH 05/10] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver
add Synopsys DesignWare MIPI DSI host controller driver support. Signed-off-by: Chris Zhong --- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile |1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 ++ include/drm/bridge/dw_mipi_dsi.h | 27 + 4 files changed, 1093 insertions(+) create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 2de52a5..9d1bd04 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -11,6 +11,16 @@ config DRM_DW_HDMI tristate select DRM_KMS_HELPER +config DRM_DW_MIPI_DSI + tristate "Synopsys DesignWare MIPI DSI host controller bridge" + depends on DRM + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL + ---help--- + Choose this if you want to use the Synopsys DesignWare MIPI DSI host + controller bridge. + config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index e2eef1c..6f22942 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -1,5 +1,6 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o +obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o diff --git a/drivers/gpu/drm/bridge/dw_mipi_dsi.c b/drivers/gpu/drm/bridge/dw_mipi_dsi.c new file mode 100644 index 000..c30e0ca --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_mipi_dsi.c @@ -0,0 +1,1055 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define DSI_VERSION0x00 + +#define DSI_PWR_UP 0x04 +#define RESET 0 +#define POWERUPBIT(0) + +#define DSI_CLKMGR_CFG 0x08 +#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8) +#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0) + +#define DSI_DPI_VCID 0x0c +#define DPI_VID(vid) (((vid) & 0x3) << 0) + +#define DSI_DPI_COLOR_CODING 0x10 +#define EN18_LOOSELY BIT(8) +#define DPI_COLOR_CODING_16BIT_1 0x0 +#define DPI_COLOR_CODING_16BIT_2 0x1 +#define DPI_COLOR_CODING_16BIT_3 0x2 +#define DPI_COLOR_CODING_18BIT_1 0x3 +#define DPI_COLOR_CODING_18BIT_2 0x4 +#define DPI_COLOR_CODING_24BIT 0x5 + +#define DSI_DPI_CFG_POL0x14 +#define COLORM_ACTIVE_LOW BIT(4) +#define SHUTD_ACTIVE_LOW BIT(3) +#define HSYNC_ACTIVE_LOW BIT(2) +#define VSYNC_ACTIVE_LOW BIT(1) +#define DATAEN_ACTIVE_LOW BIT(0) + +#define DSI_DPI_LP_CMD_TIM 0x18 +#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) +#define INVACT_LPCMD_TIME(p) ((p) & 0xff) + +#define DSI_DBI_CFG0x20 +#define DSI_DBI_CMDSIZE0x28 + +#define DSI_PCKHDL_CFG 0x2c +#define EN_CRC_RX BIT(4) +#define EN_ECC_RX BIT(3) +#define EN_BTA BIT(2) +#define EN_EOTP_RX BIT(1) +#define EN_EOTP_TX BIT(0) + +#define DSI_MODE_CFG 0x34 +#define ENABLE_VIDEO_MODE 0 +#define ENABLE_CMD_MODEBIT(0) + +#define DSI_VID_MODE_CFG 0x38 +#define FRAME_BTA_ACK BIT(14) +#define ENABLE_LOW_POWER (0x3f << 8) +#define ENABLE_LOW_POWER_MASK (0x3f << 8) +#define VID_MODE_TYPE_BURST_SYNC_PULSES0x2 +#define VID_MODE_TYPE_MASK 0x3 + +#define DSI_VID_PKT_SIZE 0x3c +#define VID_PKT_SIZE(p)(((p) & 0x3fff) << 0) +#define VID_PKT_MAX_SIZE 0x3fff + +#define DSI_VID_HSA_TIME 0x48 +#define DSI_VID_HBP_TIME 0x4c +#define DSI_VID_HLINE_TIME 0x50 +#define DSI_VID_VSA_LINES 0x54 +#define DSI_VID_VBP_LINES 0x58 +#define DSI_VID_VFP_LINES 0x5c +#define DSI_VID_VACTIVE_LINES 0x60 +#define DSI_CMD_MODE_CFG 0x68 +#define MAX_RD_PKT_SIZE_LP BIT(24) +#define DCS_LW_
[PATCH 03/10] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format
From: Liu Ying <ying@freescale.com>
Signed-off-by: Liu Ying
Acked-by: Thierry Reding
Signed-off-by: Chris Zhong
---
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index f1d8d0d..3662021 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -163,6 +163,20 @@ static inline struct mipi_dsi_device
*to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+ switch (fmt) {
+ case MIPI_DSI_FMT_RGB888:
+ case MIPI_DSI_FMT_RGB666:
+ return 24;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ return 18;
+ case MIPI_DSI_FMT_RGB565:
+ return 16;
+ }
+ return -EINVAL;
+}
+
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node
*np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
--
2.6.1
[PATCH 02/10] drm/rockchip: return a true clock rate to adjusted_mode
Sometimes the clock driver can not set a accurate clock_rate for vop,
get the true rate of vop_dclk and set it back to adjusted_mode, since
the mipi dsi driver need to use the clock to make the calculation of
Blanking.
Signed-off-by: Chris Zhong
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9986b311ed 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1232,6 +1232,12 @@ static int vop_crtc_mode_set(struct drm_crtc *crtc,
reset_control_deassert(vop->dclk_rst);
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
+
+ /*
+* Sometimes the clock driver can not set a accurate clock_rate for vop,
+* get the true rate of vop_dclk and set it back to adjusted_mode.
+*/
+ adjusted_mode->clock = clk_get_rate(vop->dclk) / 1000;
out:
ret_clk = clk_enable(vop->dclk);
if (ret_clk < 0) {
--
2.6.1
[PATCH 00/10] Add mipi dsi support for rk3288
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and a rockchip MIPI DSI specific DRM driver. This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel. This panel only use the MIPI DSI video mode. The MIPI DSI feature is tested on rk3288 evb board, backport them to chrome os kernel v3.14, and it can display normally. This patchset is base on the patchset from Ying.liu at freescale.com. <http://www.spinics.net/lists/dri-devel/msg77181.html> Chris Zhong (8): clk: rockchip: Add sclk_mipidsi_24m for mipi dsi drm/rockchip: return a true clock rate to adjusted_mode drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver ARM: dts: rockchip: add rk3288 mipi_dsi nodes drm/panel: simple: Add support for BOE TV080WUM-NL0 ARM: dts: rockchip: add support mipi panel tv080wum-nl0 for rk3288-evb Liu Ying (2): drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++ .../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++ arch/arm/boot/dts/rk3288-evb.dtsi | 20 +- arch/arm/boot/dts/rk3288.dtsi | 39 + drivers/clk/rockchip/clk-rk3288.c |2 +- drivers/gpu/drm/bridge/Kconfig | 10 + drivers/gpu/drm/bridge/Makefile|1 + drivers/gpu/drm/bridge/dw_mipi_dsi.c | 1055 drivers/gpu/drm/panel/panel-simple.c | 33 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile |1 + drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c| 249 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c|9 + include/drm/bridge/dw_mipi_dsi.h | 27 + include/drm/drm_mipi_dsi.h | 14 + include/dt-bindings/clock/rk3288-cru.h |1 + 16 files changed, 1601 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt create mode 100644 Documentation/devicetree/bindings/video/dw_mipi_dsi_rockchip.txt create mode 100644 drivers/gpu/drm/bridge/dw_mipi_dsi.c create mode 100644 drivers/gpu/drm/rockchip/dw_mipi_dsi_rockchip.c create mode 100644 include/drm/bridge/dw_mipi_dsi.h -- 2.6.1
