[REGRESSION] GM20B pmu timeout
Hello, Somewhere between 6.11-rc4 and 6.11-rc5 the following error message is displayed when trying to initialize a nvc0_screen on the Tegra X1's GM20B: [ 34.431210] nouveau 5700.gpu: pmu:hpq: timeout waiting for queue ready [ 34.438145] nouveau 5700.gpu: gr: init failed, -110 nvc0_screen_create:1075 - Error allocating PGRAPH context for M2MF: -110 failed to create GPU screen If we then try a second time we get a more detailed error message: [ 27.432391] [ cut here ] [ 27.437019] nouveau 5700.gpu: timeout [ 27.441083] WARNING: CPU: 2 PID: 307 at drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c:840 gf100_gr_fecs_bind_pointer+0x140/0x158 [nouveau] [ 27.453897] Modules linked in: nouveau drm_ttm_helper ttm backlight gpu_sched i2c_algo_bit drm_gpuvm drm_exec efivarfs [ 27.464592] CPU: 2 UID: 0 PID: 307 Comm: loadjpeg Not tainted 6.11.0-rc4+ #1 [ 27.471628] Hardware name: nvidia NVIDIA P2371-2180/NVIDIA P2371-2180, BIOS 2024.10-rc5-00018-g56b47b8b6a09 10/01/2024 [ 27.482303] pstate: 6005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 27.489251] pc : gf100_gr_fecs_bind_pointer+0x140/0x158 [nouveau] [ 27.495535] lr : gf100_gr_fecs_bind_pointer+0x140/0x158 [nouveau] [ 27.501794] sp : ffc082473810 [ 27.505100] x29: ffc082473840 x28: ff80c56fe500 x27: ff80c6f3be40 [ 27.512227] x26: 804001ea x25: 0001 x24: [ 27.519351] x23: ff80c5516808 x22: ffc079d08350 x21: ff80c16bae40 [ 27.526476] x20: 00409800 x19: ff80c5516808 x18: [ 27.533599] x17: x16: x15: 0006 [ 27.540724] x14: ffc0817defc8 x13: 74756f656d697420 x12: 3a7570672e303030 [ 27.547848] x11: ffc0817defc8 x10: 03f1 x9 : ffc081836fc8 [ 27.554972] x8 : 00017fe8 x7 : f000 x6 : 0001 [ 27.562096] x5 : x4 : x3 : [ 27.569218] x2 : x1 : x0 : ff80d578c600 [ 27.576341] Call trace: [ 27.578780] gf100_gr_fecs_bind_pointer+0x140/0x158 [nouveau] [ 27.584698] gf100_grctx_generate+0x54c/0x6f4 [nouveau] [ 27.590093] gf100_gr_chan_new+0x3f8/0x430 [nouveau] [ 27.595223] nvkm_gr_cclass_new+0x34/0x48 [nouveau] [ 27.600269] nvkm_cgrp_ectx_get+0x134/0x224 [nouveau] [ 27.605485] nvkm_cgrp_vctx_get+0x11c/0x300 [nouveau] [ 27.610704] nvkm_chan_cctx_get+0x144/0x25c [nouveau] [ 27.615920] nvkm_uchan_object_new+0xd8/0x1e0 [nouveau] [ 27.621311] nvkm_ioctl_new+0x14c/0x24c [nouveau] [ 27.626167] nvkm_ioctl+0xd0/0x280 [nouveau] [ 27.630590] nvkm_client_ioctl+0x10/0x1c [nouveau] [ 27.635551] nvif_client_ioctl+0x20/0x2c [nouveau] [ 27.640493] usif_ioctl+0x294/0x420 [nouveau] [ 27.645021] nouveau_drm_ioctl+0xb0/0xe0 [nouveau] [ 27.649982] __arm64_sys_ioctl+0xac/0xf0 [ 27.653900] invoke_syscall+0x48/0x104 [ 27.657645] el0_svc_common.constprop.0+0x40/0xe0 [ 27.662341] do_el0_svc+0x1c/0x28 [ 27.665650] el0_svc+0x3c/0x108 [ 27.668787] el0t_64_sync_handler+0x120/0x12c [ 27.673133] el0t_64_sync+0x190/0x194 [ 27.676789] ---[ end trace ]--- [ 27.681937] nouveau 5700.gpu: gr: failed to construct context [ 27.688126] nouveau 5700.gpu: fifo:00:0002:[loadjpeg[307]] ectx 0[gr]: -110 [ 27.695786] nouveau 5700.gpu: fifo:00:0002:0002:[loadjpeg[307]] vctx 0[gr]: -110 nvc0_screen_create:1075 - Error allocating PGRAPH context for M2MF: -110 failed to create GPU screen but I am not sure if this is connected to the fact that the first attempt failed or not. When trying to bissect the issue the "bad" commit I obtained was 9b340aeb26d5. However, checking out this commit and compiling the kernel leads to a different error where we have a boot regression: [ 19.146693] nouveau 5700.gpu: Adding to iommu group 3 [ 19.155581] nouveau 5700.gpu: NVIDIA GM20B (12b000a1) [ 19.161025] nouveau 5700.gpu: imem: using IOMMU [ 22.451833] [ cut here ] [ 22.456460] nouveau 5700.gpu: timeout [ 22.460508] WARNING: CPU: 0 PID: 201 at drivers/gpu/drm/nouveau/nvkm/falcon/gm200.c:231 gm200_flcn_fw_boot+0x2a4/0x428 [nouveau] [ 22.472384] Modules linked in: nouveau(+) drm_ttm_helper ttm backlight gpu_sched i2c_algo_bit drm_gpuvm drm_exec efivarfs [ 22.483342] CPU: 0 UID: 0 PID: 201 Comm: (udev-worker) Not tainted 6.11.0-rc1+ #4 [ 22.490811] Hardware name: nvidia NVIDIA P2371-2180/NVIDIA P2371-2180, BIOS 2024.10-rc5-00018-g56b47b8b6a09 10/01/2024 [ 22.501485] pstate: 6005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 22.508434] pc : gm200_flcn_fw_boot+0x2a4/0x428 [nouveau] [ 22.514063] lr : gm200_flcn_fw_boot+0x2a4/0x428 [nouveau] [ 22.519656] sp : ffc0822fb3e0 [ 22.522961] x29: ffc0822fb410 x28: ff80c7bf0008 x27: ff80d5625208 [ 22.530088] x26: 0001 x25: 000
[PATCH v3 1/5] dt-bindings: display: Add bindings for JDI LPM102A188A
The LPM102A188A is a 10.2" 2560x1800 IPS panel found in
the Google Pixel C.
Signed-off-by: Diogo Ivo
Reviewed-by: Krzysztof Kozlowski
---
Changes in v2:
- removed the touch screen property
Changes in v3:
- add Reviewed-by from Krzysztof Kozlowski
.../display/panel/jdi,lpm102a188a.yaml| 94 +++
1 file changed, 94 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
b/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
new file mode 100644
index ..2f4d27a309a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/jdi,lpm102a188a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
+
+maintainers:
+ - Diogo Ivo
+
+description: |
+ This panel requires a dual-channel DSI host to operate. It supports two
modes:
+ - left-right: each channel drives the left or right half of the screen
+ - even-odd: each channel drives the even or odd lines of the screen
+
+ Each of the DSI channels controls a separate DSI peripheral. The peripheral
+ driven by the first link (DSI-LINK1) is considered the primary peripheral
+ and controls the device. The 'link2' property contains a phandle to the
+ peripheral driven by the second link (DSI-LINK2).
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: jdi,lpm102a188a
+
+ reg: true
+ enable-gpios: true
+ reset-gpios: true
+ power-supply: true
+ backlight: true
+
+ ddi-supply:
+description: The regulator that provides IOVCC (1.8V).
+
+ link2:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the DSI peripheral on the secondary link. Note that the
+ presence of this property marks the containing node as DSI-LINK1.
+
+required:
+ - compatible
+ - reg
+
+if:
+ required:
+- link2
+then:
+ required:
+- power-supply
+- ddi-supply
+- enable-gpios
+- reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+dsia: dsi@5430 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x0 0x5430 0x0 0x0004>;
+
+link2: panel@0 {
+compatible = "jdi,lpm102a188a";
+reg = <0>;
+};
+};
+
+dsib: dsi@5440{
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x0 0x5440 0x0 0x0004>;
+nvidia,ganged-mode = <&dsia>;
+
+link1: panel@0 {
+compatible = "jdi,lpm102a188a";
+reg = <0>;
+power-supply = <&pplcd_vdd>;
+ddi-supply = <&pp1800_lcdio>;
+enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+link2 = <&link2>;
+backlight = <&backlight>;
+};
+};
+
+...
--
2.41.0
[PATCH v3 2/5] drm/panel: Add driver for JDI LPM102A188A
The JDI LPM102A188A is a 2560x1800 IPS panel found in the Google Pixel C.
This driver is based on the downstream GPLv2 driver released by Google
written by Sean Paul [1], which was then adapted to the newer kernel APIs.
[1]:
https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
Signed-off-by: Diogo Ivo
---
Changes in v2:
- tuned backlight delays
Changed in v3:
- removed "-dsi" from driver name, renamed "control"->"command" (Rayyan Ansari)
- fix error handling
- remove enabled/prepared booleans
- add dc/dc setting function
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 551 ++
3 files changed, 563 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 203c0ef0bbfd..787e6ac6f1e7 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -244,6 +244,17 @@ config DRM_PANEL_JDI_LT070ME05000
The panel has a 1200(RGB)×1920 (WUXGA) resolution and uses
24 bit per pixel.
+config DRM_PANEL_JDI_LPM102A188A
+ tristate "JDI LPM102A188A DSI panel"
+ depends on OF && GPIOLIB
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for JDI LPM102A188A DSI
+ command mode panel as found in Google Pixel C devices.
+ The panel has a 2560×1800 resolution. It provides a MIPI DSI interface
+ to the host.
+
config DRM_PANEL_JDI_R63452
tristate "JDI R63452 Full HD DSI panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 30cf553c8d1d..e5a235017c86 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) +=
panel-innolux-ej030na.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
obj-$(CONFIG_DRM_PANEL_JADARD_JD9365DA_H3) += panel-jadard-jd9365da-h3.o
obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
+obj-$(CONFIG_DRM_PANEL_JDI_LPM102A188A) += panel-jdi-lpm102a188a.o
obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o
obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o
obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
diff --git a/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
new file mode 100644
index ..5b5082efb282
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
@@ -0,0 +1,551 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * Copyright (C) 2022 Diogo Ivo
+ *
+ * Adapted from the downstream Pixel C driver written by Sean Paul
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+#define MCS_CMD_ACS_PROT 0xB0
+#define MCS_CMD_ACS_PROT_OFF (0 << 0)
+
+#define MCS_PWR_CTRL_FUNC 0xD0
+#define MCS_PWR_CTRL_PARAM1_DEFAULT(2 << 0)
+#define MCS_PWR_CTRL_PARAM1_VGH_210_DIV(1 << 4)
+#define MCS_PWR_CTRL_PARAM1_VGH_240_DIV(2 << 4)
+#define MCS_PWR_CTRL_PARAM1_VGH_280_DIV(3 << 4)
+#define MCS_PWR_CTRL_PARAM1_VGH_330_DIV(4 << 4)
+#define MCS_PWR_CTRL_PARAM1_VGH_410_DIV(5 << 4)
+#define MCS_PWR_CTRL_PARAM2_DEFAULT(9 << 4)
+#define MCS_PWR_CTRL_PARAM2_VGL_210_DIV(1 << 0)
+#define MCS_PWR_CTRL_PARAM2_VGL_240_DIV(2 << 0)
+#define MCS_PWR_CTRL_PARAM2_VGL_280_DIV(3 << 0)
+#define MCS_PWR_CTRL_PARAM2_VGL_330_DIV(4 << 0)
+#define MCS_PWR_CTRL_PARAM2_VGL_410_DIV(5 << 0)
+
+struct jdi_panel {
+ struct drm_panel base;
+ struct mipi_dsi_device *link1;
+ struct mipi_dsi_device *link2;
+
+ struct regulator *supply;
+ struct regulator *ddi_supply;
+ struct backlight_device *backlight;
+
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+
+ const struct drm_display_mode *mode;
+};
+
+static inline struct jdi_panel *to_panel_jdi(struct drm_panel *panel)
+{
+ return container_of(panel, struct jdi_panel, base);
+}
+
+static void jdi_wait_frames(struct jdi_panel *jdi, unsigned int frames)
+{
+ unsigned int refresh = drm_mode_vrefresh(jdi->mode);
+
+ if (WARN_ON(frames > refresh))
+ return;
+
+ msleep(1000 / (refresh / frames));
+}
+
+static int jdi_panel_disable(struct drm
[PATCH v3 0/5] Add JDI LPM102A188A display panel support
Hello, These patches add support for the JDI LPM102A188A display panel, found in the Google Pixel C. Patch 1 adds the DT bindings for the panel. Patch 2 adds the panel driver, which is based on the downstream kernel driver published by Google and developed by Sean Paul. Patches 3-5 add DT nodes for the regulator, backlight controller and display panel. The first version of this patch series can be found at: https://lore.kernel.org/all/20220929170502.1034040-1-diogo@tecnico.ulisboa.pt/ The first submission of v2 can be found at: https://lore.kernel.org/all/20221025153746.101278-1-diogo@tecnico.ulisboa.pt/ Changes in v2: - Patch 1: remove touchscreen reset gpio property - Patch 2: clear register based on its value rather than a DT property - Patch 3: tune backlight delay values - Patch 4: add generic node names, remove underscores Changes in v3: - Patch 1: add Reviewed-by - Patch 2: fix error handling, remove enabled/prepared booleans, add dc/dc setting - Patches 3-5: Split previous patch 3 into three different patches, each adding a separate node - removed previous patch 2 pertaining to Tegra DSI reset as it was upstreamed Diogo Ivo (5): dt-bindings: display: Add bindings for JDI LPM102A188A drm/panel: Add driver for JDI LPM102A188A arm64: dts: smaug: Add DSI/CSI regulator arm64: dts: smaug: Add backlight node arm64: dts: smaug: Add display panel node .../display/panel/jdi,lpm102a188a.yaml| 94 +++ arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 66 +++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 551 ++ 5 files changed, 723 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c -- 2.41.0
Re: [PATCH v2 0/2] Enable GPU on Smaug
On Tue, May 16, 2023 at 09:28:27AM +0100, Diogo Ivo wrote: > Hello, > > This patch series enables the use of the GM20B GPU in the > Google Pixel C. > > Patch 1 adds the needed regulator DT node for the GPU. > > Patch 2 enables the GPU in the DT. Hello, Gentle ping on these patches. Thank you, Diogo Ivo
[PATCH v2 1/2] arm64: dts: tegra: smaug: add GPU power rail regulator
Add the GPU power rail regulator node for the Pixel C.
Signed-off-by: Diogo Ivo
---
V1 -> V2: Use generic DT node name and GPIO flag
defines (Krzysztof Kozlowski)
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index e55bff859692..929372f24339 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1406,6 +1406,23 @@ max77621_cpu: max77621@1b {
maxim,externally-enable;
};
+ max77621_gpu: regulator@1c {
+ compatible = "maxim,max77621";
+ reg = <0x1c>;
+ interrupt-parent = <&gpio>;
+ interrupts = ;
+ regulator-min-microvolt = <84>;
+ regulator-max-microvolt = <115>;
+ regulator-name = "PPVAR_GPU";
+ regulator-ramp-delay = <12500>;
+ maxim,dvs-default-state = <1>;
+ maxim,enable-active-discharge;
+ maxim,enable-bias-control;
+ maxim,disable-etr;
+ maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+ maxim,externally-enable;
+ };
+
pmic: pmic@3c {
compatible = "maxim,max77620";
reg = <0x3c>;
--
2.40.1
[PATCH v2 2/2] arm64: dts: tegra: smaug: add GPU node
Enable the GPU on the Pixel C.
Signed-off-by: Diogo Ivo
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 929372f24339..db25f3ae8e0b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -67,6 +67,11 @@ dpaux: dpaux@545c {
};
};
+ gpu@5700 {
+ vdd-supply = <&max77621_gpu>;
+ status = "okay";
+ };
+
pinmux: pinmux@78d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
--
2.40.1
[PATCH v2 0/2] Enable GPU on Smaug
Hello, This patch series enables the use of the GM20B GPU in the Google Pixel C. Patch 1 adds the needed regulator DT node for the GPU. Patch 2 enables the GPU in the DT. The first version of these patches can be found at: https://lore.kernel.org/linux-tegra/20230511083101.78516-1-diogo@tecnico.ulisboa.pt/ V1 -> V2: - Patch 1: Use generic DT node name for regulator and GPIO flag defines. Best regards, Diogo Ivo (2): arm64: dts: tegra: smaug: add GPU power rail regulator arm64: dts: tegra: smaug: add GPU node arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 22 +++ 1 file changed, 22 insertions(+) -- 2.40.1
Re: [PATCH 0/2] drm/tegra: handle implicit scanout modifiers
On Tue, Jan 24, 2023 at 03:25:09PM +0100, Thierry Reding wrote: > On Fri, Jan 20, 2023 at 10:58:56AM +0000, Diogo Ivo wrote: > > Hello! > > > > This patch series adds support for correctly displaying tiled > > framebuffers when no modifiers are reported by userspace. > > > > Patch 1 adds the sector_layout parameter to the SET/GET_TILING > > IOCTLs so that userspace can set this field appropriately. > > > > Patch 2 adds handling of the case where the buffer object > > passed to create a framebuffer is allocated with non-linear > > tiling but no modifier is reported. > > > > Diogo Ivo (2): > > drm/tegra: add sector layout to SET/GET_TILING IOCTLs > > drm/tegra: add scanout support for implicit tiling parameters > > > > drivers/gpu/drm/tegra/drm.c | 29 ++ > > drivers/gpu/drm/tegra/fb.c | 59 ++-- > > include/uapi/drm/tegra_drm.h | 16 ++ > > 3 files changed, 96 insertions(+), 8 deletions(-) > > We really don't want to use SET_TILING and GET_TILING IOCTLs anymore. > These only exist for backwards compatibility with very old userspace. > New code should use standard DRM/KMS mechanisms to deal with > framebuffer modifiers. Hello, Thank you for your review! This implementation is basically a copy of what vc4 already does when importing resources with no modifiers specified by userspace. I looked into the DRM/KMS infrastructure and did not find a mechanism to do this, but perhaps I am missing something; if this is the case, I would be happy to submit a more fitting implementation, since handling these implicit modifiers allows us to lift the restriction of linear scanout buffers. Best regards, Diogo
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Mon, Jan 30, 2023 at 08:36:06AM +1000, Ben Skeggs wrote: > On Fri, 27 Jan 2023 at 20:42, Diogo Ivo wrote: > > > > On Fri, Jan 27, 2023 at 04:00:59PM +1000, Ben Skeggs wrote: > > > On Fri, 20 Jan 2023 at 21:37, Diogo Ivo > > > wrote: > > > > > > > > On Wed, Jan 18, 2023 at 11:28:49AM +1000, Ben Skeggs wrote: > > > > > On Mon, 16 Jan 2023 at 22:27, Diogo Ivo > > > > > wrote: > > > > > > On Mon, Jan 16, 2023 at 07:45:05AM +1000, David Airlie wrote: > > > > > > > As a quick check can you try changing > > > > > > > > > > > > > > drivers/gpu/drm/nouveau/nvkm/core/firmware.c:nvkm_firmware_mem_target > > > > > > > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? > > > > > > > > > In addition to Dave's change, can you try changing the > > > > > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > > > > > > > > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > > > > > sizeof(args), 0, false); > > > > > > > > Chiming in just to say that with this change I see the same as Nicolas > > > > except that the init message size is 255 instead of 0: > > > > > > > > [2.196934] nouveau 5700.gpu: pmu: unexpected init message size > > > > 255 vs 42 > > > I've attached an entirely untested patch (to go on top of the other > > > hacks/fixes so far), that will hopefully get us a little further. > > > > Hello, > > > > Thank you for the patch! I can confirm that it fixes the problem > > on the Pixel C, and everything works as before the regression. > > With this, for the combination of patches > > > > Tested-by: Diogo Ivo > > > > which I can resend after testing the final patch version. > Thank you (both!) for testing! > > I've attached a "final" version of a patch that I'll send (assuming it > still works ;)) after re-testing. There's only a minor change to > avoid breaking the non-Tegra path, so I expect it should be fine. Hello! I have tested this new version and everything is working as before, so Tested-by: Diogo Ivo Thank you, Diogo
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Fri, Jan 27, 2023 at 10:03:17AM +0100, Nicolas Chauvet wrote: > I've tried to run glmark2-wayland under weston with DRI_PRIME=1, it > seems to work at the beginning, but then I have the following error: > > [ 1510.861730] nouveau 5700.gpu: gr: DATA_ERROR 0003 > [INVALID_OPERATION] ch 3 [04002a2000 glmark2-wayland[2753]] subc 0 > class b197 mthd 19d0 data 003d > [ 1510.952000] nouveau 5700.gpu: gr: DATA_ERROR 0003 > [INVALID_OPERATION] ch 3 [04002a2000 glmark2-wayland[2753]] subc 0 > class b197 mthd 19d0 data 003d > [ 1510.952060] nouveau 5700.gpu: gr: DATA_ERROR 009c [] ch 3 > [04002a2000 glmark2-wayland[2753]] subc 0 class b197 mthd 0d78 data > 0006 > I think it's a separate error as I think I can reproduce on kernel > 6.1x (I will open a separate thread). Hello, Would you mind testing this Mesa merge request (and the kernel patches mentioned there) to see if it fixes this error: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20811 Thanks, Diogo
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Fri, Jan 27, 2023 at 04:00:59PM +1000, Ben Skeggs wrote: > On Fri, 20 Jan 2023 at 21:37, Diogo Ivo wrote: > > > > On Wed, Jan 18, 2023 at 11:28:49AM +1000, Ben Skeggs wrote: > > > On Mon, 16 Jan 2023 at 22:27, Diogo Ivo > > > wrote: > > > > On Mon, Jan 16, 2023 at 07:45:05AM +1000, David Airlie wrote: > > > > > As a quick check can you try changing > > > > > > > > > > drivers/gpu/drm/nouveau/nvkm/core/firmware.c:nvkm_firmware_mem_target > > > > > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? > > > > > In addition to Dave's change, can you try changing the > > > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > > > > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > > > sizeof(args), 0, false); > > > > Chiming in just to say that with this change I see the same as Nicolas > > except that the init message size is 255 instead of 0: > > > > [2.196934] nouveau 5700.gpu: pmu: unexpected init message size 255 > > vs 42 > I've attached an entirely untested patch (to go on top of the other > hacks/fixes so far), that will hopefully get us a little further. Hello, Thank you for the patch! I can confirm that it fixes the problem on the Pixel C, and everything works as before the regression. With this, for the combination of patches Tested-by: Diogo Ivo which I can resend after testing the final patch version. Thanks, Diogo
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Wed, Jan 18, 2023 at 11:28:49AM +1000, Ben Skeggs wrote: > On Mon, 16 Jan 2023 at 22:27, Diogo Ivo wrote: > > On Mon, Jan 16, 2023 at 07:45:05AM +1000, David Airlie wrote: > > > As a quick check can you try changing > > > > > > drivers/gpu/drm/nouveau/nvkm/core/firmware.c:nvkm_firmware_mem_target > > > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? > In addition to Dave's change, can you try changing the > nvkm_falcon_load_dmem() call in gm20b_pmu_init() to: > > nvkm_falcon_pio_wr(falcon, (u8 *)&args, 0, 0, DMEM, addr_args, > sizeof(args), 0, false); Hello! Chiming in just to say that with this change I see the same as Nicolas except that the init message size is 255 instead of 0: [2.196934] nouveau 5700.gpu: pmu: unexpected init message size 255 vs 42
[PATCH 1/2] drm/tegra: add sector layout to SET/GET_TILING IOCTLs
Commit 7b6f846785f4 ("drm/tegra: Support sector layout on Tegra194")
updated struct tegra_bo_tiling with a new field conveying information
about the sector layout of the buffer object. Update the
SET/GET_TILING IOCTLs with this field so that userspace can set it
appropriately.
Signed-off-by: Diogo Ivo
---
drivers/gpu/drm/tegra/drm.c | 29 +
include/uapi/drm/tegra_drm.h | 16 ++--
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 6748ec1e0005..27afb7fa6259 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -612,6 +612,7 @@ static int tegra_gem_set_tiling(struct drm_device *drm,
void *data,
enum tegra_bo_tiling_mode mode;
struct drm_gem_object *gem;
unsigned long value = 0;
+ enum tegra_bo_sector_layout layout;
struct tegra_bo *bo;
switch (args->mode) {
@@ -644,6 +645,19 @@ static int tegra_gem_set_tiling(struct drm_device *drm,
void *data,
return -EINVAL;
}
+ switch (args->sector_layout) {
+ case DRM_TEGRA_GEM_SECTOR_LAYOUT_TEGRA:
+ layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA;
+ break;
+
+ case DRM_TEGRA_GEM_SECTOR_LAYOUT_GPU:
+ layout = TEGRA_BO_SECTOR_LAYOUT_GPU;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
gem = drm_gem_object_lookup(file, args->handle);
if (!gem)
return -ENOENT;
@@ -652,6 +666,7 @@ static int tegra_gem_set_tiling(struct drm_device *drm,
void *data,
bo->tiling.mode = mode;
bo->tiling.value = value;
+ bo->tiling.sector_layout = layout;
drm_gem_object_put(gem);
@@ -693,6 +708,20 @@ static int tegra_gem_get_tiling(struct drm_device *drm,
void *data,
break;
}
+ switch (bo->tiling.sector_layout) {
+ case TEGRA_BO_SECTOR_LAYOUT_TEGRA:
+ args->sector_layout = DRM_TEGRA_GEM_SECTOR_LAYOUT_TEGRA;
+ break;
+
+ case TEGRA_BO_SECTOR_LAYOUT_GPU:
+ args->sector_layout = DRM_TEGRA_GEM_SECTOR_LAYOUT_GPU;
+ break;
+
+ default:
+ err = -EINVAL;
+ break;
+ }
+
drm_gem_object_put(gem);
return err;
diff --git a/include/uapi/drm/tegra_drm.h b/include/uapi/drm/tegra_drm.h
index 94cfc306d50a..811e21b1a60e 100644
--- a/include/uapi/drm/tegra_drm.h
+++ b/include/uapi/drm/tegra_drm.h
@@ -508,6 +508,9 @@ struct drm_tegra_submit {
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
+#define DRM_TEGRA_GEM_SECTOR_LAYOUT_TEGRA 0
+#define DRM_TEGRA_GEM_SECTOR_LAYOUT_GPU 1
+
/**
* struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
*/
@@ -543,11 +546,11 @@ struct drm_tegra_gem_set_tiling {
__u32 value;
/**
-* @pad:
+* @sector_layout:
*
-* Structure padding that may be used in the future. Must be 0.
+* Specify low-level sector layout.
*/
- __u32 pad;
+ __u32 sector_layout;
};
/**
@@ -578,11 +581,12 @@ struct drm_tegra_gem_get_tiling {
__u32 value;
/**
-* @pad:
+* @sector_layout:
*
-* Structure padding that may be used in the future. Must be 0.
+* The sector layout parameter currently associated with the GEM object.
+* Set by the kernel upon successful completion of the IOCTL.
*/
- __u32 pad;
+ __u32 sector_layout;
};
#define DRM_TEGRA_GEM_BOTTOM_UP(1 << 0)
--
2.39.1
[PATCH 2/2] drm/tegra: add scanout support for implicit tiling parameters
When importing buffers from the GPU to scan out, it may happen
that the buffer object has non-trivial tiling parameters, which
currently go by undetected. This leads to the framebuffer being
read and displayed in the wrong order. Explicitly check for this
case and reconstruct the adequate modifier so that the framebuffer
is correctly scanned out.
Signed-off-by: Diogo Ivo
---
drivers/gpu/drm/tegra/fb.c | 59 --
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
index 9291209154a7..31f381262345 100644
--- a/drivers/gpu/drm/tegra/fb.c
+++ b/drivers/gpu/drm/tegra/fb.c
@@ -116,11 +116,63 @@ static struct drm_framebuffer *tegra_fb_alloc(struct
drm_device *drm,
struct drm_framebuffer *fb;
unsigned int i;
int err;
+ struct drm_mode_fb_cmd2 mode_cmd_local;
fb = kzalloc(sizeof(*fb), GFP_KERNEL);
if (!fb)
return ERR_PTR(-ENOMEM);
+ /* Check for implicitly defined modifiers using
+* the state defined by tegra_gem_set_tiling().
+*/
+ if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
+ uint64_t modifier;
+
+ mode_cmd_local = *mode_cmd;
+
+ switch (planes[0]->tiling.mode) {
+ case TEGRA_BO_TILING_MODE_PITCH:
+ modifier = DRM_FORMAT_MOD_LINEAR;
+ break;
+
+ case TEGRA_BO_TILING_MODE_TILED:
+ modifier = DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED;
+ break;
+
+ /* With all rigour this reconstruction of the modifier is
+* incomplete, as it skips some fields (like page kind).
+* However, along with the sector layout below it should
+* contain all the bits of information needed by the
+* scanout hardware.
+*/
+ case TEGRA_BO_TILING_MODE_BLOCK:
+ unsigned long height = planes[0]->tiling.value;
+
+ if (height > 5) {
+ dev_err(drm->dev, "invalid block height value:
%ld\n",
+ height);
+
+ err = -EINVAL;
+ goto cleanup;
+ }
+
+ modifier = DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(height);
+ break;
+
+ default:
+ dev_err(drm->dev, "invalid tiling mode\n");
+ err = -EINVAL;
+ goto cleanup;
+ }
+
+ if (planes[0]->tiling.sector_layout ==
DRM_TEGRA_GEM_SECTOR_LAYOUT_GPU)
+ modifier |= DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT;
+
+ mode_cmd_local.modifier[0] = modifier;
+
+ mode_cmd = &mode_cmd_local;
+ }
+
drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd);
for (i = 0; i < fb->format->num_planes; i++)
@@ -130,11 +182,14 @@ static struct drm_framebuffer *tegra_fb_alloc(struct
drm_device *drm,
if (err < 0) {
dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
err);
- kfree(fb);
- return ERR_PTR(err);
+ goto cleanup;
}
return fb;
+
+cleanup:
+ kfree(fb);
+ return ERR_PTR(err);
}
struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
--
2.39.1
[PATCH 0/2] drm/tegra: handle implicit scanout modifiers
Hello! This patch series adds support for correctly displaying tiled framebuffers when no modifiers are reported by userspace. Patch 1 adds the sector_layout parameter to the SET/GET_TILING IOCTLs so that userspace can set this field appropriately. Patch 2 adds handling of the case where the buffer object passed to create a framebuffer is allocated with non-linear tiling but no modifier is reported. Diogo Ivo (2): drm/tegra: add sector layout to SET/GET_TILING IOCTLs drm/tegra: add scanout support for implicit tiling parameters drivers/gpu/drm/tegra/drm.c | 29 ++ drivers/gpu/drm/tegra/fb.c | 59 ++-- include/uapi/drm/tegra_drm.h | 16 ++ 3 files changed, 96 insertions(+), 8 deletions(-) -- 2.39.1
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Mon, Jan 16, 2023 at 07:45:05AM +1000, David Airlie wrote: > On Thu, Dec 29, 2022 at 12:58 AM Diogo Ivo > wrote: > As a quick check can you try changing > > drivers/gpu/drm/nouveau/nvkm/core/firmware.c:nvkm_firmware_mem_target > from NVKM_MEM_TARGET_HOST to NVKM_MEM_TARGET_NCOH ? Hello! Applying this change breaks probing in a different way, with a bad PC=0x0. From a quick look at nvkm_falcon_load_dmem it looks like this could happen due to the .load_dmem() callback not being properly initialized. This is the kernel log I got: [2.010601] Unable to handle kernel NULL pointer dereference at virtual address [2.019436] Mem abort info: [2.022273] ESR = 0x8605 [2.026066] EC = 0x21: IABT (current EL), IL = 32 bits [2.031429] SET = 0, FnV = 0 [2.034528] EA = 0, S1PTW = 0 [2.037694] FSC = 0x05: level 1 translation fault [2.042572] [] user address but active_mm is swapper [2.048961] Internal error: Oops: 8605 [#1] SMP [2.054529] Modules linked in: [2.057582] CPU: 0 PID: 36 Comm: kworker/u8:1 Not tainted 6.2.0-rc3+ #2 [2.064190] Hardware name: Google Pixel C (DT) [2.068628] Workqueue: events_unbound deferred_probe_work_func [2.074463] pstate: 4005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [2.081417] pc : 0x0 [2.083600] lr : nvkm_falcon_load_dmem+0x58/0x80 [2.088218] sp : ffc009ddb6f0 [2.091526] x29: ffc009ddb6f0 x28: ff808028a008 x27: ff8081e43c38 [2.098658] x26: 00ff x25: ff808028a0a0 x24: [2.105788] x23: ff8080c328f8 x22: 002c x21: 5fd4 [2.112917] x20: ffc009ddb76c x19: ff8080c328b8 x18: [2.120047] x17: 2e74696e695f646f x16: 6874656d5f77732f x15: [2.127176] x14: 02f546c2 x13: x12: 01ce [2.134306] x11: 0001 x10: 0a90 x9 : ffc009ddb600 [2.141436] x8 : ff80803d19f0 x7 : ff80bf971180 x6 : 01b9 [2.148565] x5 : x4 : x3 : 002c [2.155693] x2 : 5fd4 x1 : ffc009ddb76c x0 : ff8080c328b8 [2.162822] Call trace: [2.165264] 0x0 [2.167099] gm20b_pmu_init+0x78/0xb4 [2.170762] nvkm_pmu_init+0x20/0x34 [2.174334] nvkm_subdev_init_+0x60/0x12c [2.178339] nvkm_subdev_init+0x60/0xa0 [2.182171] nvkm_device_init+0x14c/0x2a0 [2.186178] nvkm_udevice_init+0x60/0x9c [2.190097] nvkm_object_init+0x48/0x1b0 [2.194013] nvkm_ioctl_new+0x168/0x254 [2.197843] nvkm_ioctl+0xd0/0x220 [2.201239] nvkm_client_ioctl+0x10/0x1c [2.205160] nvif_object_ctor+0xf4/0x22c [2.209079] nvif_device_ctor+0x28/0x70 [2.212910] nouveau_cli_init+0x150/0x590 [2.216916] nouveau_drm_device_init+0x60/0x2a0 [2.221442] nouveau_platform_device_create+0x90/0xd0 [2.226489] nouveau_platform_probe+0x3c/0x9c [2.230841] platform_probe+0x68/0xc0 [2.234500] really_probe+0xbc/0x2dc [2.238070] __driver_probe_device+0x78/0xe0 [2.242334] driver_probe_device+0xd8/0x160 [2.246511] __device_attach_driver+0xb8/0x134 [2.250948] bus_for_each_drv+0x78/0xd0 [2.254782] __device_attach+0x9c/0x1a0 [2.258612] device_initial_probe+0x14/0x20 [2.262789] bus_probe_device+0x98/0xa0 [2.266619] deferred_probe_work_func+0x88/0xc0 [2.271142] process_one_work+0x204/0x40c [2.275150] worker_thread+0x230/0x450 [2.278894] kthread+0xc8/0xcc [2.281946] ret_from_fork+0x10/0x20 [2.285525] Code: bad PC value [2.288576] ---[ end trace ]--- Diogo
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Sat, Jan 14, 2023 at 04:27:38AM +0100, Karol Herbst wrote: > I tried to look into it, but my jetson nano, just constantly behaves > in very strange ways. I tried to compile and install a 6.1 kernel onto > it, but any kernel just refuses to boot and I have no idea what's up > with that device. The kernel starts to boot and it just stops in the > middle. From what I can tell is that most of the tegra devices never > worked reliably in the first place and there are a couple of random > and strange bugs around. I've attached my dmesg, so if anybody has any > clues why the kernel just stops doing anything, it would really help > me. Hello, Thank you for looking into this! I have seen this type of hang in mainline on this SoC, and it was due to a reset not being deasserted. Would you mind getting a log with initcall_debug enabled to pinpoint where the hang occurs? I would be happy to help if I can. > But maybe it would be for the best to just pull tegra support out of > nouveau, because in the current situation we really can't spare much > time dealing with them and we are already busy enough just dealing > with the desktop GPUs. And the firmware we got from Nvidia is so > ancient and different from the desktop GPU ones, that without actually > having all those boards available and properly tested, we can't be > sure to not break them. > > And afaik there are almost no _actual_ users, just distribution folks > wanting to claim "support" for those devices, but then ending up using > Nvidia's out of tree Tegra driver in deployments anyway. > If there are actual users using them for their daily life, I'd like to > know, because I'm aware of none. For what it's worth, I consider myself a user of nouveau. Granted, I'm using it as a hobby project, but in its current state it is not far from a usable desktop experience on the Pixel C. Diogo
Re: [REGRESSION] GM20B probe fails after commit 2541626cfb79
On Fri, Jan 13, 2023 at 02:19:06PM +0100, Linux kernel regression tracking (Thorsten Leemhuis) wrote: > Diogo, for that it would be really helpful to known: is the issue still > happening with latest mainline? Is it possible to revert 2541626cfb79 > easily? And if so: do things work afterwards again? Hello, Thank you for your attention to this! I have checked the latest mainline and it still occurs. As for reverting, I think it is complicated to do, since this commit is a part of a larger rework, but I'm afraid I don't know enough about the code to give a proper answer. Diogo
Re: [PATCH v2 0/4] Add JDI LPM102A188A display panel support
On Tue, Oct 25, 2022 at 04:37:43PM +0100, Diogo Ivo wrote: > Hello, > > These patches add support for the JDI LPM102A188A display panel, > found in the Google Pixel C. > > Patch 1 adds the DT bindings for the panel. > > Patch 2 adds a register clear to the Tegra DSI driver, needed for the > panel initialization commands to be properly sent. > > Patch 3 adds the panel driver, which is based on the downstream > kernel driver published by Google and developed by Sean Paul. > > Patch 4 adds the DT node for the Google Pixel C. > > The first version of this patch series can be found at: > https://lore.kernel.org/all/20220929170502.1034040-1-diogo@tecnico.ulisboa.pt/ > > Changes in v2: > - Patch 1: remove touchscreen reset gpio property > - Patch 2: clear register based on its value rather than a DT property > - Patch 3: tune backlight delay values > - Patch 4: add generic node names, remove underscores > Hello, Gentle ping on this series. Thank you, Diogo
[REGRESSION] GM20B probe fails after commit 2541626cfb79
Hello, Commit 2541626cfb79 breaks GM20B probe with the following kernel log: [2.153892] [ cut here ] [2.153897] WARNING: CPU: 1 PID: 36 at drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c:273 gf100_vmm_valid+0x2c4/0x390 [2.153916] Modules linked in: [2.153922] CPU: 1 PID: 36 Comm: kworker/u8:1 Not tainted 6.1.0+ #1 [2.153929] Hardware name: Google Pixel C (DT) [2.153933] Workqueue: events_unbound deferred_probe_work_func [2.153943] pstate: 8005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [2.153950] pc : gf100_vmm_valid+0x2c4/0x390 [2.153959] lr : gf100_vmm_valid+0xb4/0x390 [2.153966] sp : ffc009e134b0 [2.153969] x29: ffc009e134b0 x28: x27: ffc008fd44c8 [2.153979] x26: ffea x25: ffc0087b98d0 x24: ff8080f89038 [2.153987] x23: ff8081fadc08 x22: x21: [2.153995] x20: ff8080f8a000 x19: ffc009e13678 x18: [2.154003] x17: f37a8b93418958e6 x16: ffc009f0d000 x15: [2.154011] x14: 0002 x13: 0003a020 x12: ffc00800 [2.154019] x11: 000102913000 x10: x9 : [2.154026] x8 : ffc009e136d8 x7 : ffc008fd44c8 x6 : ff80803d0f00 [2.154034] x5 : x4 : ff8080f88c00 x3 : 0010 [2.154041] x2 : 000c x1 : ffea x0 : ffea [2.154050] Call trace: [2.154053] gf100_vmm_valid+0x2c4/0x390 [2.154061] nvkm_vmm_map_valid+0xd4/0x204 [2.154069] nvkm_vmm_map_locked+0xa4/0x344 [2.154076] nvkm_vmm_map+0x50/0x84 [2.154083] nvkm_firmware_mem_map+0x84/0xc4 [2.154094] nvkm_falcon_fw_oneinit+0xc8/0x320 [2.154101] nvkm_acr_oneinit+0x428/0x5b0 [2.154109] nvkm_subdev_oneinit_+0x50/0x104 [2.154114] nvkm_subdev_init_+0x3c/0x12c [2.154119] nvkm_subdev_init+0x60/0xa0 [2.154125] nvkm_device_init+0x14c/0x2a0 [2.154133] nvkm_udevice_init+0x60/0x9c [2.154140] nvkm_object_init+0x48/0x1b0 [2.154144] nvkm_ioctl_new+0x168/0x254 [2.154149] nvkm_ioctl+0xd0/0x220 [2.154153] nvkm_client_ioctl+0x10/0x1c [2.154162] nvif_object_ctor+0xf4/0x22c [2.154168] nvif_device_ctor+0x28/0x70 [2.154174] nouveau_cli_init+0x150/0x590 [2.154180] nouveau_drm_device_init+0x60/0x2a0 [2.154187] nouveau_platform_device_create+0x90/0xd0 [2.154193] nouveau_platform_probe+0x3c/0x9c [2.154200] platform_probe+0x68/0xc0 [2.154207] really_probe+0xbc/0x2dc [2.154211] __driver_probe_device+0x78/0xe0 [2.154216] driver_probe_device+0xd8/0x160 [2.154221] __device_attach_driver+0xb8/0x134 [2.154226] bus_for_each_drv+0x78/0xd0 [2.154230] __device_attach+0x9c/0x1a0 [2.154234] device_initial_probe+0x14/0x20 [2.154239] bus_probe_device+0x98/0xa0 [2.154243] deferred_probe_work_func+0x88/0xc0 [2.154247] process_one_work+0x204/0x40c [2.154256] worker_thread+0x230/0x450 [2.154261] kthread+0xc8/0xcc [2.154266] ret_from_fork+0x10/0x20 [2.154273] ---[ end trace ]--- [2.154278] nouveau 5700.gpu: pmu: map -22 [2.154285] nouveau 5700.gpu: acr: one-time init failed, -22 [2.154559] nouveau 5700.gpu: init failed with -22 [2.154564] nouveau: DRM-master::0080: init failed with -22 [2.154574] nouveau 5700.gpu: DRM-master: Device allocation failed: -22 [2.162905] nouveau: probe of 5700.gpu failed with error -22 #regzbot introduced: 2541626cfb79 Thanks, Diogo Ivo
Re: [v2,3/4] drm/panel: Add driver for JDI LPM102A188A
Hello,
On Fri, Dec 23, 2022 at 03:33:40PM +, Rayyan Ansari wrote:
> On 25/10/2022 16:37, Diogo Ivo wrote:
> > +config DRM_PANEL_JDI_LPM102A188A
> > + tristate "JDI LPM102A188A DSI panel"
> > + depends on OF && GPIOLIB
> > + depends on DRM_MIPI_DSI
> > + depends on BACKLIGHT_CLASS_DEVICE
> > + help
> > + Say Y here if you want to enable support for JDI LPM102A188A DSI
> > + control mode panel as found in Google Pixel C devices.
> Shouldn't this be "command mode panel" instead of "control mode panel"?
Yes, it should.
> > +static struct mipi_dsi_driver jdi_panel_dsi_driver = {
> > + .driver = {
> > + .name = "panel-jdi-lpm102a188a-dsi",
> Is the "-dsi" suffix needed here? Other panel drivers don't have this.
I had not noticed this, and I will drop it.
Thank you for your review and attention to detail. I will address these
points in the next version.
Diogo Ivo
Re: [PATCH v2 RESEND 0/4] Add JDI LPM102A188A display panel support
On Mon, Nov 28, 2022 at 04:28:48PM +, Diogo Ivo wrote: > Hello, > > These patches add support for the JDI LPM102A188A display panel, > found in the Google Pixel C. Hello, Gentle ping on this series. Thank you, Diogo Ivo
[PATCH v2 RESEND 3/4] drm/panel: Add driver for JDI LPM102A188A
The JDI LPM102A188A is a 2560x1800 IPS panel found in the Google Pixel C.
This driver is based on the downstream GPLv2 driver released by Google
written by Sean Paul [1], which was then adapted to the newer kernel APIs.
[1]:
https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
Signed-off-by: Diogo Ivo
---
Changes in v2:
- tuned backlight delays
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 509 ++
3 files changed, 521 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a582ddd583c2..80eda8f6bee0 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -214,6 +214,17 @@ config DRM_PANEL_JDI_LT070ME05000
The panel has a 1200(RGB)×1920 (WUXGA) resolution and uses
24 bit per pixel.
+config DRM_PANEL_JDI_LPM102A188A
+ tristate "JDI LPM102A188A DSI panel"
+ depends on OF && GPIOLIB
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for JDI LPM102A188A DSI
+ control mode panel as found in Google Pixel C devices.
+ The panel has a 2560×1800 resolution. It provides a MIPI DSI interface
+ to the host.
+
config DRM_PANEL_JDI_R63452
tristate "JDI R63452 Full HD DSI panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..2870cba96d14 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) +=
panel-ilitek-ili9881c.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
+obj-$(CONFIG_DRM_PANEL_JDI_LPM102A188A) += panel-jdi-lpm102a188a.o
obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o
obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o
obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
diff --git a/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
new file mode 100644
index ..980af82ad6d6
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
@@ -0,0 +1,509 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * Copyright (C) 2022 Diogo Ivo
+ *
+ * Adapted from the downstream Pixel C driver written by Sean Paul
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+struct jdi_panel {
+ struct drm_panel base;
+ struct mipi_dsi_device *link1;
+ struct mipi_dsi_device *link2;
+
+ struct regulator *supply;
+ struct regulator *ddi_supply;
+ struct backlight_device *backlight;
+
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+
+ const struct drm_display_mode *mode;
+
+ bool prepared;
+ bool enabled;
+};
+
+static inline struct jdi_panel *to_panel_jdi(struct drm_panel *panel)
+{
+ return container_of(panel, struct jdi_panel, base);
+}
+
+static void jdi_wait_frames(struct jdi_panel *jdi, unsigned int frames)
+{
+ unsigned int refresh = drm_mode_vrefresh(jdi->mode);
+
+ if (WARN_ON(frames > refresh))
+ return;
+
+ msleep(1000 / (refresh / frames));
+}
+
+static int jdi_panel_disable(struct drm_panel *panel)
+{
+ struct jdi_panel *jdi = to_panel_jdi(panel);
+
+ if (!jdi->enabled)
+ return 0;
+
+ backlight_disable(jdi->backlight);
+
+ jdi_wait_frames(jdi, 2);
+
+ jdi->enabled = false;
+
+ return 0;
+}
+
+static int jdi_panel_unprepare(struct drm_panel *panel)
+{
+ struct jdi_panel *jdi = to_panel_jdi(panel);
+ int ret;
+
+ if (!jdi->prepared)
+ return 0;
+
+ ret = mipi_dsi_dcs_set_display_off(jdi->link1);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to set display off: %d\n", ret);
+ ret = mipi_dsi_dcs_set_display_off(jdi->link2);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to set display off: %d\n", ret);
+
+ /* Specified by JDI @ 50ms, subject to change */
+ msleep(50);
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link1);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
+ ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link2);
+ if (ret < 0)
+ dev_err(p
[PATCH v2 RESEND 0/4] Add JDI LPM102A188A display panel support
Hello, These patches add support for the JDI LPM102A188A display panel, found in the Google Pixel C. Patch 1 adds the DT bindings for the panel (omitted in RESEND). Patch 2 adds a register clear to the Tegra DSI driver, needed for the panel initialization commands to be properly sent. Patch 3 adds the panel driver, which is based on the downstream kernel driver published by Google and developed by Sean Paul. Patch 4 adds the DT node for the Google Pixel C. The first version of this patch series can be found at: https://lore.kernel.org/all/20220929170502.1034040-1-diogo@tecnico.ulisboa.pt/ The first submission of v2 can be found at: https://lore.kernel.org/all/20221025153746.101278-1-diogo@tecnico.ulisboa.pt/ Changes in v2: - Patch 1: remove touchscreen reset gpio property - Patch 2: clear register based on its value rather than a DT property - Patch 3: tune backlight delay values - Patch 4: add generic node names, remove underscores Thank you. Diogo Ivo (4): dt-bindings: display: Add bindings for JDI LPM102A188A drm/tegra: dsi: Clear enable register if powered by bootloader drm/panel: Add driver for JDI LPM102A188A arm64: dts: smaug: Add display panel node .../display/panel/jdi,lpm102a188a.yaml| 94 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 70 +++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 509 ++ drivers/gpu/drm/tegra/dsi.c | 9 + 6 files changed, 694 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c -- 2.38.1
[PATCH v2 RESEND 2/4] drm/tegra: dsi: Clear enable register if powered by bootloader
In cases where the DSI module is left on by the bootloader
some panels may fail to initialize if the enable register is not cleared
before the panel's initialization sequence is sent, so clear it if that
is the case.
Signed-off-by: Diogo Ivo
---
Changes in v2:
- detect if the DSI module is on based on the register value,
instead of a DT property.
- remove Display Controller clear, since it is redundant.
drivers/gpu/drm/tegra/dsi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index de1333dc0d86..5954676a7ab1 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -912,6 +912,15 @@ static void tegra_dsi_encoder_enable(struct drm_encoder
*encoder)
u32 value;
int err;
+ /* If the bootloader enabled DSI it needs to be disabled
+* in order for the panel initialization commands to be
+* properly sent.
+*/
+ value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
+
+ if (value & DSI_POWER_CONTROL_ENABLE)
+ tegra_dsi_disable(dsi);
+
err = tegra_dsi_prepare(dsi);
if (err < 0) {
dev_err(dsi->dev, "failed to prepare: %d\n", err);
--
2.38.1
[PATCH v2 RESEND 4/4] arm64: dts: smaug: Add display panel node
The Google Pixel C has a JDI LPM102A188A display panel. Add a
DT node for it. Tested on Pixel C.
Signed-off-by: Diogo Ivo
---
Changes in v2:
- renamed backlight node to a generic name
- removed underscores
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 70 +++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 84ec4d8b7f10..5db0b25c8d58 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -31,6 +31,37 @@ memory {
};
host1x@5000 {
+ dc@5420 {
+ status = "okay";
+ };
+
+ dsia: dsi@5430 {
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ status = "okay";
+
+ link2: panel@0 {
+ compatible = "jdi,lpm102a188a";
+ reg = <0>;
+ };
+ };
+
+ dsib: dsi@5440 {
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ nvidia,ganged-mode = <&dsia>;
+ status = "okay";
+
+ link1: panel@0 {
+ compatible = "jdi,lpm102a188a";
+ reg = <0>;
+ power-supply = <&pplcd_vdd>;
+ ddi-supply = <&pp1800_lcdio>;
+ enable-gpios = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(V, 2)
GPIO_ACTIVE_LOW>;
+ link2 = <&link2>;
+ backlight = <&backlight>;
+ };
+ };
+
dpaux: dpaux@545c {
status = "okay";
};
@@ -1627,6 +1658,37 @@ nau8825@1a {
status = "okay";
};
+ backlight: backlight@2c {
+ compatible = "ti,lp8557";
+ reg = <0x2c>;
+ power-supply = <&pplcd_vdd>;
+ enable-supply = <&pp1800_lcdio>;
+ bl-name = "lp8557-backlight";
+ dev-ctrl = /bits/ 8 <0x01>;
+ init-brt = /bits/ 8 <0x80>;
+
+ /* Full scale current, 20mA */
+ rom-11h {
+ rom-addr = /bits/ 8 <0x11>;
+ rom-val = /bits/ 8 <0x05>;
+ };
+ /* Frequency = 4.9kHz, magic undocumented val */
+ rom-12h {
+ rom-addr = /bits/ 8 <0x12>;
+ rom-val = /bits/ 8 <0x29>;
+ };
+ /* Boost freq = 1MHz, BComp option = 1 */
+ rom-13h {
+ rom-addr = /bits/ 8 <0x13>;
+ rom-val = /bits/ 8 <0x03>;
+ };
+ /* 4V OV, 6 output LED string enabled */
+ rom-14h {
+ rom-addr = /bits/ 8 <0x14>;
+ rom-val = /bits/ 8 <0xbf>;
+ };
+ };
+
audio-codec@2d {
compatible = "realtek,rt5677";
reg = <0x2d>;
@@ -1908,4 +1970,12 @@ usbc_vbus: regulator-usbc-vbus {
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+ vdd_dsi_csi: regulator-vdd-dsi-csi {
+ compatible = "regulator-fixed";
+ regulator-name = "AVDD_DSI_CSI_1V2";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ vin-supply = <&pp1200_avdd>;
+ };
};
--
2.38.1
[PATCH v2 4/4] arm64: dts: smaug: Add display panel node
The Google Pixel C has a JDI LPM102A188A display panel. Add a
DT node for it. Tested on Pixel C.
Signed-off-by: Diogo Ivo
---
Changes in v2:
- renamed backlight node to a generic name
- removed underscores
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 70 +++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 84ec4d8b7f10..5db0b25c8d58 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -31,6 +31,37 @@ memory {
};
host1x@5000 {
+ dc@5420 {
+ status = "okay";
+ };
+
+ dsia: dsi@5430 {
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ status = "okay";
+
+ link2: panel@0 {
+ compatible = "jdi,lpm102a188a";
+ reg = <0>;
+ };
+ };
+
+ dsib: dsi@5440 {
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ nvidia,ganged-mode = <&dsia>;
+ status = "okay";
+
+ link1: panel@0 {
+ compatible = "jdi,lpm102a188a";
+ reg = <0>;
+ power-supply = <&pplcd_vdd>;
+ ddi-supply = <&pp1800_lcdio>;
+ enable-gpios = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(V, 2)
GPIO_ACTIVE_LOW>;
+ link2 = <&link2>;
+ backlight = <&backlight>;
+ };
+ };
+
dpaux: dpaux@545c {
status = "okay";
};
@@ -1627,6 +1658,37 @@ nau8825@1a {
status = "okay";
};
+ backlight: backlight@2c {
+ compatible = "ti,lp8557";
+ reg = <0x2c>;
+ power-supply = <&pplcd_vdd>;
+ enable-supply = <&pp1800_lcdio>;
+ bl-name = "lp8557-backlight";
+ dev-ctrl = /bits/ 8 <0x01>;
+ init-brt = /bits/ 8 <0x80>;
+
+ /* Full scale current, 20mA */
+ rom-11h {
+ rom-addr = /bits/ 8 <0x11>;
+ rom-val = /bits/ 8 <0x05>;
+ };
+ /* Frequency = 4.9kHz, magic undocumented val */
+ rom-12h {
+ rom-addr = /bits/ 8 <0x12>;
+ rom-val = /bits/ 8 <0x29>;
+ };
+ /* Boost freq = 1MHz, BComp option = 1 */
+ rom-13h {
+ rom-addr = /bits/ 8 <0x13>;
+ rom-val = /bits/ 8 <0x03>;
+ };
+ /* 4V OV, 6 output LED string enabled */
+ rom-14h {
+ rom-addr = /bits/ 8 <0x14>;
+ rom-val = /bits/ 8 <0xbf>;
+ };
+ };
+
audio-codec@2d {
compatible = "realtek,rt5677";
reg = <0x2d>;
@@ -1908,4 +1970,12 @@ usbc_vbus: regulator-usbc-vbus {
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+ vdd_dsi_csi: regulator-vdd-dsi-csi {
+ compatible = "regulator-fixed";
+ regulator-name = "AVDD_DSI_CSI_1V2";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ vin-supply = <&pp1200_avdd>;
+ };
};
--
2.38.1
[PATCH v2 3/4] drm/panel: Add driver for JDI LPM102A188A
The JDI LPM102A188A is a 2560x1800 IPS panel found in the Google Pixel C.
This driver is based on the downstream GPLv2 driver released by Google
written by Sean Paul [1], which was then adapted to the newer kernel APIs.
[1]:
https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
Signed-off-by: Diogo Ivo
---
Changes in v2:
- tuned backlight delays
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 509 ++
3 files changed, 521 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index a582ddd583c2..80eda8f6bee0 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -214,6 +214,17 @@ config DRM_PANEL_JDI_LT070ME05000
The panel has a 1200(RGB)×1920 (WUXGA) resolution and uses
24 bit per pixel.
+config DRM_PANEL_JDI_LPM102A188A
+ tristate "JDI LPM102A188A DSI panel"
+ depends on OF && GPIOLIB
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for JDI LPM102A188A DSI
+ control mode panel as found in Google Pixel C devices.
+ The panel has a 2560×1800 resolution. It provides a MIPI DSI interface
+ to the host.
+
config DRM_PANEL_JDI_R63452
tristate "JDI R63452 Full HD DSI panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 34e717382dbb..2870cba96d14 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) +=
panel-ilitek-ili9881c.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
+obj-$(CONFIG_DRM_PANEL_JDI_LPM102A188A) += panel-jdi-lpm102a188a.o
obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o
obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o
obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
diff --git a/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
new file mode 100644
index ..980af82ad6d6
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
@@ -0,0 +1,509 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * Copyright (C) 2022 Diogo Ivo
+ *
+ * Adapted from the downstream Pixel C driver written by Sean Paul
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+struct jdi_panel {
+ struct drm_panel base;
+ struct mipi_dsi_device *link1;
+ struct mipi_dsi_device *link2;
+
+ struct regulator *supply;
+ struct regulator *ddi_supply;
+ struct backlight_device *backlight;
+
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+
+ const struct drm_display_mode *mode;
+
+ bool prepared;
+ bool enabled;
+};
+
+static inline struct jdi_panel *to_panel_jdi(struct drm_panel *panel)
+{
+ return container_of(panel, struct jdi_panel, base);
+}
+
+static void jdi_wait_frames(struct jdi_panel *jdi, unsigned int frames)
+{
+ unsigned int refresh = drm_mode_vrefresh(jdi->mode);
+
+ if (WARN_ON(frames > refresh))
+ return;
+
+ msleep(1000 / (refresh / frames));
+}
+
+static int jdi_panel_disable(struct drm_panel *panel)
+{
+ struct jdi_panel *jdi = to_panel_jdi(panel);
+
+ if (!jdi->enabled)
+ return 0;
+
+ backlight_disable(jdi->backlight);
+
+ jdi_wait_frames(jdi, 2);
+
+ jdi->enabled = false;
+
+ return 0;
+}
+
+static int jdi_panel_unprepare(struct drm_panel *panel)
+{
+ struct jdi_panel *jdi = to_panel_jdi(panel);
+ int ret;
+
+ if (!jdi->prepared)
+ return 0;
+
+ ret = mipi_dsi_dcs_set_display_off(jdi->link1);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to set display off: %d\n", ret);
+ ret = mipi_dsi_dcs_set_display_off(jdi->link2);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to set display off: %d\n", ret);
+
+ /* Specified by JDI @ 50ms, subject to change */
+ msleep(50);
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link1);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
+ ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link2);
+ if (ret < 0)
+ dev_err(p
[PATCH v2 2/4] drm/tegra: dsi: Clear enable register if powered by bootloader
In cases where the DSI module is left on by the bootloader
some panels may fail to initialize if the enable register is not cleared
before the panel's initialization sequence is sent, so clear it if that
is the case.
Signed-off-by: Diogo Ivo
---
Changes in v2:
- detect if the DSI module is on based on the register value,
instead of a DT property.
- remove Display Controller clear, since it is redundant.
drivers/gpu/drm/tegra/dsi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index de1333dc0d86..5954676a7ab1 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -912,6 +912,15 @@ static void tegra_dsi_encoder_enable(struct drm_encoder
*encoder)
u32 value;
int err;
+ /* If the bootloader enabled DSI it needs to be disabled
+* in order for the panel initialization commands to be
+* properly sent.
+*/
+ value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
+
+ if (value & DSI_POWER_CONTROL_ENABLE)
+ tegra_dsi_disable(dsi);
+
err = tegra_dsi_prepare(dsi);
if (err < 0) {
dev_err(dsi->dev, "failed to prepare: %d\n", err);
--
2.38.1
[PATCH v2 1/4] dt-bindings: display: Add bindings for JDI LPM102A188A
The LPM102A188A is a 10.2" 2560x1800 IPS panel found in
the Google Pixel C.
Signed-off-by: Diogo Ivo
---
Changes in v2:
- removed the touch screen property
.../display/panel/jdi,lpm102a188a.yaml| 94 +++
1 file changed, 94 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
b/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
new file mode 100644
index ..2f4d27a309a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/jdi,lpm102a188a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
+
+maintainers:
+ - Diogo Ivo
+
+description: |
+ This panel requires a dual-channel DSI host to operate. It supports two
modes:
+ - left-right: each channel drives the left or right half of the screen
+ - even-odd: each channel drives the even or odd lines of the screen
+
+ Each of the DSI channels controls a separate DSI peripheral. The peripheral
+ driven by the first link (DSI-LINK1) is considered the primary peripheral
+ and controls the device. The 'link2' property contains a phandle to the
+ peripheral driven by the second link (DSI-LINK2).
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: jdi,lpm102a188a
+
+ reg: true
+ enable-gpios: true
+ reset-gpios: true
+ power-supply: true
+ backlight: true
+
+ ddi-supply:
+description: The regulator that provides IOVCC (1.8V).
+
+ link2:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the DSI peripheral on the secondary link. Note that the
+ presence of this property marks the containing node as DSI-LINK1.
+
+required:
+ - compatible
+ - reg
+
+if:
+ required:
+- link2
+then:
+ required:
+- power-supply
+- ddi-supply
+- enable-gpios
+- reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+dsia: dsi@5430 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x0 0x5430 0x0 0x0004>;
+
+link2: panel@0 {
+compatible = "jdi,lpm102a188a";
+reg = <0>;
+};
+};
+
+dsib: dsi@5440{
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x0 0x5440 0x0 0x0004>;
+nvidia,ganged-mode = <&dsia>;
+
+link1: panel@0 {
+compatible = "jdi,lpm102a188a";
+reg = <0>;
+power-supply = <&pplcd_vdd>;
+ddi-supply = <&pp1800_lcdio>;
+enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+link2 = <&link2>;
+backlight = <&backlight>;
+};
+};
+
+...
--
2.38.1
[PATCH v2 0/4] Add JDI LPM102A188A display panel support
Hello, These patches add support for the JDI LPM102A188A display panel, found in the Google Pixel C. Patch 1 adds the DT bindings for the panel. Patch 2 adds a register clear to the Tegra DSI driver, needed for the panel initialization commands to be properly sent. Patch 3 adds the panel driver, which is based on the downstream kernel driver published by Google and developed by Sean Paul. Patch 4 adds the DT node for the Google Pixel C. The first version of this patch series can be found at: https://lore.kernel.org/all/20220929170502.1034040-1-diogo@tecnico.ulisboa.pt/ Changes in v2: - Patch 1: remove touchscreen reset gpio property - Patch 2: clear register based on its value rather than a DT property - Patch 3: tune backlight delay values - Patch 4: add generic node names, remove underscores Thank you. Diogo Ivo (4): dt-bindings: display: Add bindings for JDI LPM102A188A drm/tegra: dsi: Clear enable register if powered by bootloader drm/panel: Add driver for JDI LPM102A188A arm64: dts: smaug: Add display panel node .../display/panel/jdi,lpm102a188a.yaml| 94 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 70 +++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 509 ++ drivers/gpu/drm/tegra/dsi.c | 9 + 6 files changed, 694 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c -- 2.38.1
Re: [PATCH 1/4] dt-bindings: display: Add bindings for JDI LPM102A188A
On Tue, Oct 04, 2022 at 01:05:04PM +0200, Krzysztof Kozlowski wrote: > On 03/10/2022 19:06, Diogo Ivo wrote: > > On Fri, Sep 30, 2022 at 12:49:31PM +0200, Krzysztof Kozlowski wrote: > >> Isn't touchscreen a separate (input) device? > > > > Hello, thank you for the feedback. > > > > According to the downstream kernel's log, it seems like the panel and > > the touchscreen controller are considered to be embedded in the same unit > > (for example in [1]), > > Downstream kernel is not a proof of proper description of hardware. If > downstream says orange is an apple, does it mean orange is really an > apple? No... Downstream creates a lot of junk, hacks and workarounds. After some searching (which I should have done sooner, so apologies) I came across a teardown of the Pixel C ([1], for completeness), which incorporates this panel. Indeed a separate touch controller was found, so it seems the downstream kernel threw me off as per your warning. [1]: https://www.ifixit.com/Teardown/Google+Pixel+C+Teardown/62277 (Step 4) > > with the touch input being transmitted via HID-over-I2C, > > and since I did not find any reset gpio handling in that driver I opted to > > include this reset here, unless there is a better way of going about this. > > Instead it should be in touch screen device. Noted, I will remove it from the binding in the next version. > Where is the DTS of that device? The relevant part of the DTS can be found here: https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo/arch/arm64/boot/dts/tegra/tegra210-smaug.dtsi Best regards, Diogo
Re: [PATCH 2/4] drm/tegra: dsi: Clear enable register if powered by bootloader
On Fri, Sep 30, 2022 at 01:11:10PM +0200, Thierry Reding wrote:
> On Thu, Sep 29, 2022 at 06:05:00PM +0100, Diogo Ivo wrote:
> > +
> > err = tegra_dsi_prepare(dsi);
> > if (err < 0) {
> > dev_err(dsi->dev, "failed to prepare: %d\n", err);
> > @@ -1573,6 +1600,8 @@ static int tegra_dsi_probe(struct platform_device
> > *pdev)
> >
> > dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
> >
> > + /* Check if the DSI module was left on by bootloader. */
> > + dsi->enabled = of_property_read_bool(pdev->dev.of_node,
> > "nvidia,boot-on");
>
> The isn't a documented property. But before you go and add this, are
> there no alternative ways to detect that the DSI controller is active?
> Could we not read one of the registers to find out?
Hello, thank you for your feedback.
You are correct, it is possible to simply read a register to obtain
this information, and this property is not needed.
> DRM/KMS has built-in mechanisms to read back hardware state on boot, so
> I wonder if we can hook that up. It'd make the most sense if all sub-
> drivers did this, because then we could eventually inherit the
> bootloader configuration and transition to the kernel display driver
> seamlessly, but doing this in DSI first may help prepare for that more
> extended use-case.
I have only recently started digging in the DRM/KMS subsystem, could
you point out what those mechanisms are? That end goal seems like
something worth pursuing.
> A slightly simpler alternative would be to add the reset code to the
> encoder's or connector's ->reset() implementation. This is called at the
> right time (i.e. when the mode configuration is first reset), so you can
> run the workaround from tegra_dsi_encoder_enable() there. That's better
> than having this guarded by the dsi->enabled flag so that it is run only
> once.
>
> Thierry
Regarding the placement of the workaround, I placed it in encoder_enable()
since my attempts of placing it in other functions (such as the connector's
->reset() method) resulted in a kernel hang, and I have no solution for this.
I'm assuming this is due to some part of the DSI hardware not being fully
initialized, but I haven't been able to confirm this.
Best regards,
Diogo
Re: [PATCH 1/4] dt-bindings: display: Add bindings for JDI LPM102A188A
On Fri, Sep 30, 2022 at 12:49:31PM +0200, Krzysztof Kozlowski wrote: > > + ts-reset-gpios: > > +maxItems: 1 > > +description: | > > + Specifier for a GPIO connected to the touchscreen reset control > > signal. > > + The reset signal is active low. > > Isn't touchscreen a separate (input) device? Hello, thank you for the feedback. According to the downstream kernel's log, it seems like the panel and the touchscreen controller are considered to be embedded in the same unit (for example in [1]), with the touch input being transmitted via HID-over-I2C, and since I did not find any reset gpio handling in that driver I opted to include this reset here, unless there is a better way of going about this. Best regards, Diogo [1]: https://android.googlesource.com/kernel/tegra/+/bca61c34db9f72113af058f53eeb9fbd5e69a1d0
[PATCH 3/4] drm/panel: Add driver for JDI LPM102A188A
The JDI LPM102A188A is a 2560x1800 IPS panel found in the Google Pixel C.
This driver is based on the downstream GPLv2 driver released by Google
written by Sean Paul [1], which was then adapted to the newer kernel APIs.
[1]:
https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
Signed-off-by: Diogo Ivo
---
drivers/gpu/drm/panel/Kconfig | 11 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 513 ++
3 files changed, 525 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 38799effd00a..532a15a38b60 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -203,6 +203,17 @@ config DRM_PANEL_JDI_LT070ME05000
The panel has a 1200(RGB)×1920 (WUXGA) resolution and uses
24 bit per pixel.
+config DRM_PANEL_JDI_LPM102A188A
+ tristate "JDI LPM102A188A DSI panel"
+ depends on OF && GPIOLIB
+ depends on DRM_MIPI_DSI
+ depends on BACKLIGHT_CLASS_DEVICE
+ help
+ Say Y here if you want to enable support for JDI LPM102A188A DSI
+ control mode panel as found in Google Pixel C devices.
+ The panel has a 2560×1800 resolution. It provides a MIPI DSI interface
+ to the host.
+
config DRM_PANEL_JDI_R63452
tristate "JDI R63452 Full HD DSI panel"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 42a7ab54234b..774a5ce0ebb8 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) +=
panel-ilitek-ili9881c.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
+obj-$(CONFIG_DRM_PANEL_JDI_LPM102A188A) += panel-jdi-lpm102a188a.o
obj-$(CONFIG_DRM_PANEL_JDI_R63452) += panel-jdi-fhd-r63452.o
obj-$(CONFIG_DRM_PANEL_KHADAS_TS050) += panel-khadas-ts050.o
obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
diff --git a/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
new file mode 100644
index ..c7f13719d4ff
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c
@@ -0,0 +1,513 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * Copyright (C) 2022 Diogo Ivo
+ *
+ * Adapted from the downstream Pixel C driver written by Sean Paul
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+
+struct jdi_panel {
+ struct drm_panel base;
+ struct mipi_dsi_device *link1;
+ struct mipi_dsi_device *link2;
+
+ struct regulator *supply;
+ struct regulator *ddi_supply;
+ struct backlight_device *backlight;
+
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+
+ const struct drm_display_mode *mode;
+
+ bool prepared;
+ bool enabled;
+};
+
+static inline struct jdi_panel *to_panel_jdi(struct drm_panel *panel)
+{
+ return container_of(panel, struct jdi_panel, base);
+}
+
+static void jdi_wait_frames(struct jdi_panel *jdi, unsigned int frames)
+{
+ unsigned int refresh = drm_mode_vrefresh(jdi->mode);
+
+ if (WARN_ON(frames > refresh))
+ return;
+
+ msleep(1000 / (refresh / frames));
+}
+
+static int jdi_panel_disable(struct drm_panel *panel)
+{
+ struct jdi_panel *jdi = to_panel_jdi(panel);
+
+ if (!jdi->enabled)
+ return 0;
+
+ backlight_disable(jdi->backlight);
+
+ jdi_wait_frames(jdi, 2);
+
+ jdi->enabled = false;
+
+ return 0;
+}
+
+static int jdi_panel_unprepare(struct drm_panel *panel)
+{
+ struct jdi_panel *jdi = to_panel_jdi(panel);
+ int ret;
+
+ if (!jdi->prepared)
+ return 0;
+
+ ret = mipi_dsi_dcs_set_display_off(jdi->link1);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to set display off: %d\n", ret);
+ ret = mipi_dsi_dcs_set_display_off(jdi->link2);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to set display off: %d\n", ret);
+
+ /* Specified by JDI @ 50ms, subject to change */
+ msleep(50);
+
+ ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link1);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
+ ret = mipi_dsi_dcs_enter_sleep_mode(jdi->link2);
+ if (ret < 0)
+ dev_err(panel->dev, "failed to enter sleep mode: %d\n&q
[PATCH 4/4] arm64: dts: smaug: Add display panel node
The Google Pixel C has a JDI LPM102A188A display panel. Add a
DT node for it. Tested on Pixel C.
Signed-off-by: Diogo Ivo
---
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 72 +++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index 20d092812984..271ef70747f1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -31,6 +31,39 @@ memory {
};
host1x@5000 {
+ dc@5420 {
+ status = "okay";
+ };
+
+ dsia: dsi@5430 {
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ nvidia,boot-on;
+ status = "okay";
+
+ link2: panel@0 {
+ compatible = "jdi,lpm102a188a";
+ reg = <0>;
+ };
+ };
+
+ dsib: dsi@5440 {
+ avdd-dsi-csi-supply = <&vdd_dsi_csi>;
+ nvidia,ganged-mode = <&dsia>;
+ nvidia,boot-on;
+ status = "okay";
+
+ link1: panel@0 {
+ compatible = "jdi,lpm102a188a";
+ reg = <0>;
+ power-supply = <&pplcd_vdd>;
+ ddi-supply = <&pp1800_lcdio>;
+ enable-gpios = <&gpio TEGRA_GPIO(V, 1)
GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio TEGRA_GPIO(V, 2)
GPIO_ACTIVE_LOW>;
+ link2 = <&link2>;
+ backlight = <&backlight>;
+ };
+ };
+
dpaux: dpaux@545c {
status = "okay";
};
@@ -1627,6 +1660,37 @@ nau8825@1a {
status = "okay";
};
+ backlight: lp8557-backlight@2c {
+ compatible = "ti,lp8557";
+ reg = <0x2c>;
+ power-supply = <&pplcd_vdd>;
+ enable-supply = <&pp1800_lcdio>;
+ bl-name = "lp8557-backlight";
+ dev-ctrl = /bits/ 8 <0x01>;
+ init-brt = /bits/ 8 <0x80>;
+
+ /* Full scale current, 20mA */
+ rom_11h {
+ rom-addr = /bits/ 8 <0x11>;
+ rom-val = /bits/ 8 <0x05>;
+ };
+ /* Frequency = 4.9kHz, magic undocumented val */
+ rom_12h {
+ rom-addr = /bits/ 8 <0x12>;
+ rom-val = /bits/ 8 <0x29>;
+ };
+ /* Boost freq = 1MHz, BComp option = 1 */
+ rom_13h {
+ rom-addr = /bits/ 8 <0x13>;
+ rom-val = /bits/ 8 <0x03>;
+ };
+ /* 4V OV, 6 output LED string enabled */
+ rom_14h {
+ rom-addr = /bits/ 8 <0x14>;
+ rom-val = /bits/ 8 <0xbf>;
+ };
+ };
+
audio-codec@2d {
compatible = "realtek,rt5677";
reg = <0x2d>;
@@ -1908,4 +1972,12 @@ usbc_vbus: regulator-usbc-vbus {
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+ vdd_dsi_csi: regulator-vdd-dsi-csi {
+ compatible = "regulator-fixed";
+ regulator-name = "AVDD_DSI_CSI_1V2";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ vin-supply = <&pp1200_avdd>;
+ };
};
--
2.37.3
[PATCH 1/4] dt-bindings: display: Add bindings for JDI LPM102A188A
The LPM102A188A is a 10.2" 2560x1800 IPS panel found in
the Google Pixel C.
Signed-off-by: Diogo Ivo
---
.../display/panel/jdi,lpm102a188a.yaml| 100 ++
1 file changed, 100 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
b/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
new file mode 100644
index ..97f9db7152da
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/jdi,lpm102a188a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
+
+maintainers:
+ - Diogo Ivo
+
+description: |
+ This panel requires a dual-channel DSI host to operate. It supports two
modes:
+ - left-right: each channel drives the left or right half of the screen
+ - even-odd: each channel drives the even or odd lines of the screen
+
+ Each of the DSI channels controls a separate DSI peripheral. The peripheral
+ driven by the first link (DSI-LINK1) is considered the primary peripheral
+ and controls the device. The 'link2' property contains a phandle to the
+ peripheral driven by the second link (DSI-LINK2).
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+const: jdi,lpm102a188a
+
+ reg: true
+ enable-gpios: true
+ reset-gpios: true
+ power-supply: true
+ backlight: true
+
+ ts-reset-gpios:
+maxItems: 1
+description: |
+ Specifier for a GPIO connected to the touchscreen reset control signal.
+ The reset signal is active low.
+
+ ddi-supply:
+description: The regulator that provides IOVCC (1.8V).
+
+ link2:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the DSI peripheral on the secondary link. Note that the
+ presence of this property marks the containing node as DSI-LINK1.
+
+required:
+ - compatible
+ - reg
+
+if:
+ required:
+- link2
+then:
+ required:
+- power-supply
+- ddi-supply
+- enable-gpios
+- reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+dsia: dsi@5430 {
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x0 0x5430 0x0 0x0004>;
+
+link2: panel@0 {
+compatible = "jdi,lpm102a188a";
+reg = <0>;
+};
+};
+
+dsib: dsi@5440{
+#address-cells = <1>;
+#size-cells = <0>;
+reg = <0x0 0x5440 0x0 0x0004>;
+nvidia,ganged-mode = <&dsia>;
+
+link1: panel@0 {
+compatible = "jdi,lpm102a188a";
+reg = <0>;
+power-supply = <&pplcd_vdd>;
+ddi-supply = <&pp1800_lcdio>;
+enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+link2 = <&link2>;
+backlight = <&backlight>;
+};
+};
+
+...
--
2.37.3
[PATCH 0/4] Add JDI LPM102A188A display panel support
Hello! These patches add support for the JDI LPM102A188A display panel, found in the Google Pixel C. Patch 1 adds the DT bindings for the panel. Patch 2 adds an optional register clear to the Tegra DSI driver. Patch 3 adds the panel driver, which is based on the downstream kernel driver published by Google and developed by Sean Paul. Patch 4 adds the DT node for the Google Pixel C. There is one point in this series on which I would like to ask for some advice: Since the device's bootloader leaves the display on and in patch 3 I have assumed that the panel must be reset when probing, I was forced to add patch 2, discovered by poking at the DSI module's registers until the panel initialization sequence succeeded. However, if it is okay to keep the panel on from the bootloader then it would be possible to forego this second patch. Any comments on this would be highly appreciated. Thank you! Diogo Ivo (4): dt-bindings: display: Add bindings for JDI LPM102A188A drm/tegra: dsi: Clear enable register if powered by bootloader drm/panel: Add driver for JDI LPM102A188A arm64: dts: smaug: Add display panel node .../display/panel/jdi,lpm102a188a.yaml| 100 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 72 +++ drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c | 511 ++ drivers/gpu/drm/tegra/dsi.c | 29 + 6 files changed, 724 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/jdi,lpm102a188a.yaml create mode 100644 drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c -- 2.37.3
[PATCH 2/4] drm/tegra: dsi: Clear enable register if powered by bootloader
In cases where the DSI module is left on by the bootloader
some panels may fail to initialize if the enable register is not cleared
before the panel's initialization sequence. Clear it and add an optional
device tree property to inform the driver if this is the case.
Signed-off-by: Diogo Ivo
---
drivers/gpu/drm/tegra/dsi.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index de1333dc0d86..f66514379913 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -78,6 +78,8 @@ struct tegra_dsi {
unsigned int video_fifo_depth;
unsigned int host_fifo_depth;
+ bool enabled;
+
/* for ganged-mode support */
struct tegra_dsi *master;
struct tegra_dsi *slave;
@@ -460,6 +462,8 @@ static void tegra_dsi_enable(struct tegra_dsi *dsi)
value |= DSI_POWER_CONTROL_ENABLE;
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
+ dsi->enabled = true;
+
if (dsi->slave)
tegra_dsi_enable(dsi->slave);
}
@@ -737,6 +741,8 @@ static void tegra_dsi_disable(struct tegra_dsi *dsi)
value &= ~DSI_POWER_CONTROL_ENABLE;
tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
+ dsi->enabled = false;
+
if (dsi->slave)
tegra_dsi_disable(dsi->slave);
@@ -912,6 +918,27 @@ static void tegra_dsi_encoder_enable(struct drm_encoder
*encoder)
u32 value;
int err;
+ /* If the bootloader enabled DSI it needs to be disabled
+* in order for the panel initialization commands to be
+* properly sent.
+*/
+ if (dsi->enabled) {
+ if (dc) {
+ value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
+ value &= ~DSI_ENABLE;
+ tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
+
+ tegra_dc_commit(dc);
+ }
+
+ err = tegra_dsi_wait_idle(dsi, 100);
+ if (err < 0)
+ dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
+
+ /* disable DSI controller */
+ tegra_dsi_disable(dsi);
+ }
+
err = tegra_dsi_prepare(dsi);
if (err < 0) {
dev_err(dsi->dev, "failed to prepare: %d\n", err);
@@ -1573,6 +1600,8 @@ static int tegra_dsi_probe(struct platform_device *pdev)
dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
+ /* Check if the DSI module was left on by bootloader. */
+ dsi->enabled = of_property_read_bool(pdev->dev.of_node,
"nvidia,boot-on");
/*
* Assume these values by default. When a DSI peripheral driver
* attaches to the DSI host, the parameters will be taken from
--
2.37.3
