Re: [PATCHv2 00/56] drm/omap: Convert DSI code to use drm_mipi_dsi and drm_panel
Hi Sebastian, > Am 25.02.2020 um 00:20 schrieb Sebastian Reichel > : > > This updates the existing omapdrm DSI code, so that it uses > common drm_mipi_dsi API and drm_panel. > > The patchset has been tested with Droid 4 using Linux console, X.org and > Weston. The patchset is based on Laurent Pinchartl's patch series [0] > and removes the last custom panel driver, so quite a few cleanups on the > omapdrm codebase were possible. > > [0] [PATCH v7 00/54] drm/omap: Replace custom display drivers with drm_bridge > and drm_panel > > https://lore.kernel.org/dri-devel/20200222150106.22919-1-laurent.pinch...@ideasonboard.com/ >git://linuxtv.org/pinchartl/media.git omapdrm/bridge/devel > > I pushed this patchset into the following branch: > > git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-n900.git > omapdrm/bridge/devel-with-dsi > > The previous version of this patchset has been sent quite some time ago. > This version has been rebased and required cleaning up most of the > hacks. I do not have a detailed changelog, but quite a few things > changed. I decided against doing anything special for the DT change > (adding DSI channel number), since only 3 devices are affected. It is > quite likely, that all developers of those devices update DT together > with kernel for those devices. My suggestion is to merge the first two > patches ASAP and backport to stable, since it does not affect old > kernels and the change is rather small. > > RFCv1: > https://lore.kernel.org/dri-devel/20191117023946.VjCC3yE08DMx7JIKxNagPoT5et7WTnKGVV6MtOtB9Ro@z/ is there something new for this series? Is there a repo where it has been rebased to v5.8-rc1 (and tested)? Our Pyra MIPI/DSI omap5 panel setup is broken by upstream changes since v5.7-rc1 and I am not sure if it is better to search in the old omapdrm code what is missing now. Or to wait for your DSI code and just update/fix our panel driver (and have a chance to get that one upstream). BR and thanks, Nikolaus > > -- Sebastian > > Sebastian Reichel (56): > ARM: dts: omap: add channel to DSI panels > ARM: dts: omap4-droid4: add panel compatible > Revert "drm/omap: dss: Remove unused omap_dss_device operations" > omap/drm: drop unused dsi.configure_pins > drm/omap: dsi: use MIPI_DSI_FMT_* instead of OMAP_DSS_DSI_FMT_* > drm/omap: constify write buffers > drm/omap: dsi: add generic transfer function > drm/omap: panel-dsi-cm: convert to transfer API > drm/omap: dsi: unexport specific data transfer functions > drm/omap: dsi: drop virtual channel logic > drm/omap: dsi: simplify write function > drm/omap: dsi: simplify read functions > drm/omap: dsi: switch dsi_vc_send_long/short to mipi_dsi_msg > drm/omap: dsi: introduce mipi_dsi_host > drm/omap: panel-dsi-cm: use DSI helpers > drm/omap: dsi: request VC via mipi_dsi_attach > drm/omap: panel-dsi-cm: drop hardcoded VC > drm/omap: panel-dsi-cm: use common MIPI DCS 1.3 defines > drm/omap: dsi: drop unused memory_read() > drm/omap: dsi: drop unused get_te() > drm/omap: dsi: drop unused enable_te() > drm/omap: dsi: drop useless sync() > drm/omap: dsi: use pixel-format and mode from attach > drm/omap: panel-dsi-cm: use bulk regulator API > drm/omap: dsi: lp/hs switching support for transfer() > drm/omap: dsi: move TE GPIO handling into core > drm/omap: dsi: drop custom enable_te() API > drm/omap: dsi: do bus locking in host driver > drm/omap: dsi: untangle ulps ops from enable/disable > drm/dsi: add MIPI_DSI_MODE_ULPS_IDLE > drm/omap: dsi: do ULPS in host driver > drm/omap: dsi: move panel refresh function to host > drm/omap: dsi: Reverse direction of the DSS device enable/disable >operations > drm/omap: dsi: drop custom panel capability support > drm/omap: dsi: convert to drm_panel > drm/omap: drop omapdss-boot-init > drm/omap: dsi: implement check timings > drm/omap: panel-dsi-cm: use DEVICE_ATTR_RO > drm/omap: panel-dsi-cm: support unbinding > drm/omap: panel-dsi-cm: fix remove() > drm/omap: dsi: return proper error code from dsi_update_all() > drm/omap: remove global dss_device variable > drm/omap: bind components with drm_device argument > drm/panel: Move OMAP's DSI command mode panel driver > drm/omap: dsi: Register a drm_bridge > drm/omap: remove legacy DSS device operations > drm/omap: remove unused omap_connector > drm/omap: simplify omap_display_id > drm/omap: drop unused DSS next pointer > drm/omap: drop empty omap_encoder helper functions > drm/omap: drop DSS ops_flags > drm/omap: drop dssdev display field > drm/omap: simplify DSI manual update code > ARM: omap2plus_defconfig: Update for moved DSI command mode panel > drm/panel/panel-dsi-cm: support rotation property > ARM: dts: omap4-droid4: add panel orientation > > .../bindings/display/panel/panel-dsi-cm.txt |4 +- > .../boot/dts/motorola-mapphone-common.dtsi|6 +- > arch/arm/boot/dts/omap3-n950.dts |3 +- > arch/arm/boot/dts/omap3.dtsi |
Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Tony, > Am 03.05.2020 um 17:01 schrieb Tony Lindgren : > > * Paul Cercueil [200503 14:19]: >> You have a new SoC with a SGX, and you only need to enable one clock to get >> it to work. So you create a devicetree node which receives only one clock. >> >> Turns out, that the bootloader was enabling the other 3 clocks, and since >> the last release, it doesn't anymore. You're left with having to support a >> broken devicetree. >> >> That's the kind of problem that can be easily avoided by enforcing the >> number of clocks that have to be provided. > > The number of clocks depends on how it's wired for the SoC. > > On omaps, there's are no controls for additinoal SGX clocks. Sure some > of the clocks may be routed to multple places internally by the wrapper > module. But we have no control over that. > > If we wanted to specify just the "fck" clock on omaps, then we can > do it with something like this: > > allOf: > - if: >properites: > compatible: >enum: > - "ti,omap4-sgx544-112" > - "ti,omap5-sgx544-116" > - "ti,dra7-sgx544-116" >then: > properties: >clocks: > minItems: 1 > maxItems: 1 > >clock-names: > const: fck > >required: > - clocks > - clock-names will add to v8 of this series as a separate patch on top of the general one. This should make it easier to have a focussed discussion and revert/bisect if something goes wrong. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
> Am 05.05.2020 um 17:53 schrieb Rob Herring : > > On Fri, Apr 24, 2020 at 10:34:04PM +0200, H. Nikolaus Schaller wrote: >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers and interrupt). >> >> The interface also consists of clocks, reset, power but >> information from data sheets is vague and some SoC integrators >> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >> all clock, reset and power-management through registers >> outside of the sgx register block. >> >> Therefore all these properties are optional. >> >> Tested by make dt_binding_check >> >> Signed-off-by: H. Nikolaus Schaller >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++ >> 1 file changed, 150 insertions(+) >> +oneOf: >> + - description: SGX530-121 based SoC >> +items: >> + - enum: >> +- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz >> and similar > > Should be indented 2 more here and elsewhere where you have a list > under a list. added for patch v8 series. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Paul & Paul, > Am 03.05.2020 um 18:41 schrieb H. Nikolaus Schaller : > > Hi Paul and Paul, > >> Am 03.05.2020 um 16:18 schrieb Paul Cercueil : >> >> >> >> Le dim. 3 mai 2020 à 15:31, H. Nikolaus Schaller a >> écrit : >>> Hi Paul, >>>> Am 03.05.2020 um 14:52 schrieb Paul Cercueil : >>>>>> It's possible to forbid the presence of the 'clocks' property on some >>>>>> implementations, and require it on others. >>>>> To be precise we have to specify the exact number of clocks (between 0 >>>>> and 4) for every architecture. >>>>> This also contradicts my dream to get rid of the architecture specific >>>>> components in the long run. My dream (because I can't tell how it can be >>>>> done) is that we can one day develop something which just needs >>>>> compatible = img,530 or imp,540 or img,544. Then we can't make the number >>>>> clocks depend on the implementation any more. >>>> As we said before, the number of clocks is a property of the GPU and *not* >>>> its integration into the SoC. >>> Well, it is a not very well documented property of the GPU. We have no data >>> sheet of the standalone GPU. Only several SoC data sheets which give some >>> indications. >> >> Maybe we can nicely ask them? > > There is some (old) answer here: > > https://github.com/MIPS/CI20_linux/blob/ci20-v3.18/arch/mips/boot/dts/jz4780.dtsi#L63 > >> I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would >> be too much, but maybe they can help a bit with the DT bindings. > > Good idea! It is definitively worth to try. Therefore I have moved him from > CC: to To: Do we already have an idea if we can get into contact and get help from ImgTec for this topic or if we have to live with what we have? BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm: ingenic-drm: add MODULE_DEVICE_TABLE
so that the driver can load by matching the device tree
if compiled as module.
Cc: sta...@vger.kernel.org # v5.3+
Fixes: 90b86fcc47b4 ("DRM: Add KMS driver for the Ingenic JZ47xx SoCs")
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 9dfe7cb530e11..1754c05470690 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -843,6 +843,7 @@ static const struct of_device_id ingenic_drm_of_match[] = {
{ .compatible = "ingenic,jz4770-lcd", .data = _soc_info },
{ /* sentinel */ },
};
+MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
static struct platform_driver ingenic_drm_driver = {
.driver = {
--
2.26.2
___
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dri-devel@lists.freedesktop.org
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Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Paul, > Am 03.05.2020 um 14:52 schrieb Paul Cercueil : > >>> It's possible to forbid the presence of the 'clocks' property on some >>> implementations, and require it on others. >> To be precise we have to specify the exact number of clocks (between 0 and >> 4) for every architecture. >> This also contradicts my dream to get rid of the architecture specific >> components in the long run. My dream (because I can't tell how it can be >> done) is that we can one day develop something which just needs compatible = >> img,530 or imp,540 or img,544. Then we can't make the number clocks depend >> on the implementation any more. > > As we said before, the number of clocks is a property of the GPU and *not* > its integration into the SoC. Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications. It appears as if some sgx5xx versions have 3 clocks and some have 4. So you are right, the number of clocks depends on the sgx5xx version and that could be made dependent in the bindings (if necessary). > > So you would *not* have a number of clocks between 0 and 4. You get either 0, > or 4, depending on whether or not you have a wrapper. I think this is contradicting your previous sentence. If the number of clocks is a property of the GPU and not the integration it must also not depend on whether there is a wrapper. I.e. it must be a constant for any type of integration. The really correct variant would be to always make the SoC integration (wrapper) a separate subsystem (because it is never part of the SGX core but some interface bus) and clock provider and connect it explicitly to the clock inputs. To be clear: I am not at all against describing the clocks. I just doubt that the time we invest into discussing on this level of detail and adding conditional clock requirements is worth the result. IMHO the bindings and .dts do not become better by describing them in more detail than just "optional". It just takes our time from contributing to other subsystems. > > >>> See how it's done for instance on >>> Documentation/devicetree/bindings/serial/samsung_uart.yaml. >> Yes I know the design pattern, but I wonder if such a move makes the whole >> thing even less maintainable. >> Assume we have finished DTS for some SoC. Then these DTS have been tested on >> real hardware and are working. Clocks are there where needed and missing >> where not. We may now forbid or not forbid them for some implementations in >> the bindings.yaml but the result of dtbs_check won't change! Because they >> are tested and working and the bindings.yaml has been adapted to the result. >> So we have just duplicated something for no practical benefit. >> Next, assume there is coming support for more and more new SoC. Then, >> developers not only have to figure out which clocks they need in the DTS but >> they also have to add a patch to the implementation specific part of the >> bindings.yaml to clearly define exactly the same what they already have >> written into their .dts (the clocks are either there for the of_node or they >> are not). So again the rules are for no benefit, since a new SoC is >> introduced exactly once. And tested if it works. And if it is there, it will >> stay as it is. It is just work for maintainers to review that patch as well. > > If you add support for a new SoC, you'd still need to modify the binding to > add the compatible string. So the argument of "more work" is moot. Agreed, I forgot this aspect. Nevertheless, it is easier to review a new compatible string than a new clock number rule (question: how do you practically review this? By looking if it does match the DTS?). We have to add the compatible string as long as we need to have the SoC name in the compatible string (which as said is my dream to get rid of in far future). If we could get rid of it, there won't be a change any more. By just taking "img,sgx544" into a new SoC. The change would be moved into SoC specific wrappers. In such an ideal world, we would explicitly describe the wrappers as separate DT nodes. Even if they have no explicit driver (e.g. by some simple-pm-bus). PRCM,bus, Processor <<>> Wrapper <<->> SGX ti,... ti,sysc img,sgx530 img,...simple-busimg,sgx540 samsung,...... img,sgx544 other, other,gpu-wrapper img,... But this IMHO correct proposal was already rejected. So at the moment we are circling around several proposals because none can fulfill all requirements. Therefore my attempt to solve the gordian knot is to make clocks generally optional. This keeps the bindings simple but not generally wrong. And since the DTS are not only tested against bindings.yaml but on real hardware, the omission to enforce a specific number of clocks doesn't harm anyone. As said it is
Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Paul and Paul, > Am 03.05.2020 um 16:18 schrieb Paul Cercueil : > > > > Le dim. 3 mai 2020 à 15:31, H. Nikolaus Schaller a écrit > : >> Hi Paul, >>> Am 03.05.2020 um 14:52 schrieb Paul Cercueil : >>>>> It's possible to forbid the presence of the 'clocks' property on some >>>>> implementations, and require it on others. >>>> To be precise we have to specify the exact number of clocks (between 0 and >>>> 4) for every architecture. >>>> This also contradicts my dream to get rid of the architecture specific >>>> components in the long run. My dream (because I can't tell how it can be >>>> done) is that we can one day develop something which just needs compatible >>>> = img,530 or imp,540 or img,544. Then we can't make the number clocks >>>> depend on the implementation any more. >>> As we said before, the number of clocks is a property of the GPU and *not* >>> its integration into the SoC. >> Well, it is a not very well documented property of the GPU. We have no data >> sheet of the standalone GPU. Only several SoC data sheets which give some >> indications. > > Maybe we can nicely ask them? There is some (old) answer here: https://github.com/MIPS/CI20_linux/blob/ci20-v3.18/arch/mips/boot/dts/jz4780.dtsi#L63 > I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would > be too much, but maybe they can help a bit with the DT bindings. Good idea! It is definitively worth to try. Therefore I have moved him from CC: to To: > >> It appears as if some sgx5xx versions have 3 clocks and some have 4. So you >> are right, the number of clocks depends on the sgx5xx version and that could >> be made dependent in the bindings (if necessary). >>> So you would *not* have a number of clocks between 0 and 4. You get either >>> 0, or 4, depending on whether or not you have a wrapper. >> I think this is contradicting your previous sentence. If the number of >> clocks is a property of the GPU and not the integration it must also not >> depend on whether there is a wrapper. I.e. it must be a constant for any >> type of integration. > > Well, I expected all SGX versions to have 4 clocks. > > If some SGX versions have 3 clocks, and others have 4 clocks, it's still OK > as long as the number of clocks is enforced, so that all implementations of a > given SGX core will have to use the same number of clocks. > >> The really correct variant would be to always make the SoC integration >> (wrapper) a separate subsystem (because it is never part of the SGX core but >> some interface bus) and clock provider and connect it explicitly to the >> clock inputs. > > About the wrapper... I don't really know how it's done there. But you could > very well pass all clocks unconditionally to the SGX node, even if it's > inside a wrapper. > The wrapper itself probably needs only one clock, the one that allows it to > access its registers. > >> To be clear: I am not at all against describing the clocks. I just doubt >> that the time we invest into discussing on this level of detail and adding >> conditional clock requirements is worth the result. IMHO the bindings and >> .dts do not become better by describing them in more detail than just >> "optional". It just takes our time from contributing to other subsystems. > > You have a new SoC with a SGX, and you only need to enable one clock to get > it to work. So you create a devicetree node which receives only one clock. > > Turns out, that the bootloader was enabling the other 3 clocks, Does it? I haven't seen such boot loaders. Usually they bring up only the core and e.g. mmc to be able to boot. > and since the last release, it doesn't anymore. You're left with having to > support a broken devicetree. > > That's the kind of problem that can be easily avoided by enforcing the number > of clocks that have to be provided. >>>>> See how it's done for instance on >>>>> Documentation/devicetree/bindings/serial/samsung_uart.yaml. >>>> Yes I know the design pattern, but I wonder if such a move makes the whole >>>> thing even less maintainable. >>>> Assume we have finished DTS for some SoC. Then these DTS have been tested >>>> on real hardware and are working. Clocks are there where needed and >>>> missing where not. We may now forbid or not forbid them for some >>>> implementations in the bindings.yaml but the result of dtbs_check won't >>>> change! Because they are tested and working and the bindings.yaml has been >>>
Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Paul, > Am 26.04.2020 um 15:11 schrieb Paul Cercueil : > > Hi Nikolaus, > > Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller a > écrit : >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers and interrupt). >> The interface also consists of clocks, reset, power but >> information from data sheets is vague and some SoC integrators >> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >> all clock, reset and power-management through registers >> outside of the sgx register block. >> Therefore all these properties are optional. >> Tested by make dt_binding_check >> Signed-off-by: H. Nikolaus Schaller >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++ >> 1 file changed, 150 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> new file mode 100644 >> index ..33a9c4c6e784 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> @@ -0,0 +1,150 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Imagination PVR/SGX GPU >> + >> +maintainers: >> + - H. Nikolaus Schaller >> + >> +description: |+ >> + This binding describes the Imagination SGX5 series of 3D accelerators >> which >> + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, >> + Allwinner A83, and Intel Poulsbo and CedarView and more. >> + >> + For an extensive list see: >> https://en.wikipedia.org/wiki/PowerVR#Implementations >> + >> + The SGX node is usually a child node of some DT node belonging to the SoC >> + which handles clocks, reset and general address space mapping of the SGX >> + register area. If not, an optional clock can be specified here. >> + >> +properties: >> + $nodename: >> +pattern: '^gpu@[a-f0-9]+$' >> + compatible: >> +oneOf: >> + - description: SGX530-121 based SoC >> +items: >> + - enum: >> +- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz >> and similar >> + - const: img,sgx530-121 >> + - const: img,sgx530 >> + >> + - description: SGX530-125 based SoC >> +items: >> + - enum: >> +- ti,am3352-sgx530-125 # BeagleBone Black >> +- ti,am3517-sgx530-125 >> +- ti,am4-sgx530-125 >> +- ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz >> and similar >> +- ti,ti81xx-sgx530-125 >> + - const: ti,omap3-sgx530-125 >> + - const: img,sgx530-125 >> + - const: img,sgx530 >> + >> + - description: SGX535-116 based SoC >> +items: >> + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx >> + - const: img,sgx535-116 >> + - const: img,sgx535 >> + >> + - description: SGX540-116 based SoC >> +items: >> + - const: intel,medfield-gma-sgx540 # Atom Z24xx >> + - const: img,sgx540-116 >> + - const: img,sgx540 >> + >> + - description: SGX540-120 based SoC >> +items: >> + - enum: >> +- samsung,s5pv210-sgx540-120 >> +- ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar >> + - const: img,sgx540-120 >> + - const: img,sgx540 >> + >> + - description: SGX540-130 based SoC >> +items: >> + - enum: >> +- ingenic,jz4780-sgx540-130 # CI20 >> + - const: img,sgx540-130 >> + - const: img,sgx540 >> + >> + - description: SGX544-112 based SoC >> +items: >> + - const: ti,omap4470-sgx544-112 >> + - const: img,sgx544-112 >> + - const: img,sgx544 >> + >> + - description: SGX544-115 based SoC >> +items: >> + - enum: >> +- allwinner,sun8i-a31-sgx544-115 >> +- allwinner,sun8i-a31s-sgx
Re: [PATCH v7 06/12] ARM: DTS: omap4: add sgx gpu child node
Hi Paul,
> Am 26.04.2020 um 14:50 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
> Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller a
> écrit :
>> Add SGX GPU node with interrupt. Tested on PandaBoard ES.
>> Since omap4420/30/60 and omap4470 come with different SGX variants
>> we need to introduce a new omap4470.dtsi. If an omap4470 board
>> does not want to use SGX it is no problem to still include
>> omap4460.dtsi.
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> arch/arm/boot/dts/omap4.dtsi | 11 ++-
>> arch/arm/boot/dts/omap4470.dts | 15 +++
>> 2 files changed, 21 insertions(+), 5 deletions(-)
>> create mode 100644 arch/arm/boot/dts/omap4470.dts
>> diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
>> index 763bdea8c829..15ff3d7146af 100644
>> --- a/arch/arm/boot/dts/omap4.dtsi
>> +++ b/arch/arm/boot/dts/omap4.dtsi
>> @@ -389,7 +389,7 @@ abb_iva: regulator-abb-iva {
>> status = "disabled";
>> };
>> -target-module@5600 {
>> +sgx_module: target-module@5600 {
>> compatible = "ti,sysc-omap4", "ti,sysc";
>> reg = <0x5600fe00 0x4>,
>><0x5600fe10 0x4>;
>> @@ -408,10 +408,11 @@ target-module@5600 {
>> #size-cells = <1>;
>> ranges = <0 0x5600 0x200>;
>> -/*
>> - * Closed source PowerVR driver, no child device
>> - * binding or driver in mainline
>> - */
>> +gpu: gpu@0 {
>> +compatible = "ti,omap4-sgx540-120",
>> "img,sgx540-120", "img,sgx540";
>> +reg = <0x0 0x200>; /* 32MB */
>> +interrupts = ;
>> +};
>> };
>> /*
>> diff --git a/arch/arm/boot/dts/omap4470.dts b/arch/arm/boot/dts/omap4470.dts
>> new file mode 100644
>> index ..f29c581300bf
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/omap4470.dts
^^^ there is also a missing "i" in the file name
>> @@ -0,0 +1,15 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Device Tree Source for OMAP4470 SoC
>> + *
>> + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
>> + *
>> + * This file is licensed under the terms of the GNU General Public License
>> + * version 2. This program is licensed "as is" without any warranty of any
>> + * kind, whether express or implied.
>> + */
>> +#include "omap4460.dtsi"
>> +
>> + {
>
> Does this even compile?
Good question.
So far there is no well known eval board in mainline that #includes this .dtsi
(because it is new) and therefore it passes any compile tests.
DTC arch/arm/boot/dts/omap4470-test.dtb - due to target missing
Error: arch/arm/boot/dts/omap4470.dtsi:13.1-5 Label or path sgx not found
I have now added a dummy board (not to be mainlined) for my own compile test...
>
> The node's handle is named sgx_module, not sgx.
Indeed. A fix is queued for v8.
BR and thanks,
Nikolaus
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Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Philipp, > Am 26.04.2020 um 21:36 schrieb Philipp Rossak : > > Hi Nikolaus, > > On 24.04.20 22:34, H. Nikolaus Schaller wrote: >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers and interrupt). >> The interface also consists of clocks, reset, power but >> information from data sheets is vague and some SoC integrators >> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >> all clock, reset and power-management through registers >> outside of the sgx register block. >> Therefore all these properties are optional. >> Tested by make dt_binding_check >> Signed-off-by: H. Nikolaus Schaller >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++ >> 1 file changed, 150 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> new file mode 100644 >> index ..33a9c4c6e784 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> @@ -0,0 +1,150 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Imagination PVR/SGX GPU >> + ... >> + - description: SGX544-112 based SoC >> +items: >> + - const: ti,omap4470-sgx544-112 >> + - const: img,sgx544-112 >> + - const: img,sgx544 >> + >> + - description: SGX544-115 based SoC >> +items: >> + - enum: >> +- allwinner,sun8i-a31-sgx544-115 >> +- allwinner,sun8i-a31s-sgx544-115 > those two bindings are wrong. > It should be allwinner,sun6i-a31-sgx544-115 and > allwinner,sun6i-a31s-sgx544-115. I did a copy paste error in the patches that > I provided for this series. Ok, noted for v8. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v7 03/12] ARM: DTS: am3517: add sgx gpu child node
Add SGX GPU node with interrupt.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am3517.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index e0b5a00e2078..3fce56a646d1 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -138,10 +138,11 @@ sgx_module: target-module@5000 {
#size-cells = <1>;
ranges = <0 0x5000 0x4000>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,am3517-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x0 0x4000>;
+ interrupts = <21>;
+ };
};
};
};
--
2.25.1
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[PATCH v7 07/12] ARM: DTS: omap5: add sgx gpu child node
Add SGX GPU node with interrupt. Tested on Pyra-Handheld.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap5.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 2ac7f021c284..1cf41664fd00 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -270,7 +270,7 @@ sata: sata@4a141100 {
ports-implemented = <0x1>;
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -287,10 +287,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap5-sgx544-116",
"img,sgx544-116", "img,sgx544";
+ reg = <0x0 0x1>;
+ interrupts = ;
+ };
};
target-module@5800 {
--
2.25.1
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[PATCH v7 12/12] MIPS: DTS: jz4780: add sgx gpu node
and add interrupt and clocks.
Tested to build for CI20 board and load a driver.
Setup can not yet be fully tested since there is no working
HDMI driver for jz4780.
Suggested-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index bb89653d16a3..92b91aec7993 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -357,6 +357,17 @@ i2c4: i2c@10054000 {
status = "disabled";
};
+ gpu: gpu@1304 {
+ compatible = "ingenic,jz4780-sgx540-130", "img,sgx540-130",
"img,sgx540";
+ reg = <0x1304 0x4000>;
+
+ clocks = < JZ4780_CLK_GPU>;
+ clock-names = "core";
+
+ interrupt-parent = <>;
+ interrupts = <63>;
+ };
+
nemc: nemc@1341 {
compatible = "ingenic,jz4780-nemc";
reg = <0x1341 0x1>;
--
2.25.1
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[PATCH v7 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
* changed commit message for the dt-bindings to better describe latest situation * added properties for up to 4 clocks, reset, power-domains, sgx-supply - proposed by Maxime Ripard * fixed jz4780 and s5pv210 to use "core" clock name * simplified example * update for arm: dts: s5pv210 - by Jonathan Bakker * removed a stray " from binding which had creeped in through copy * fixed commit / tested-by messages and some not well formed commit messages - suggested by Krzysztof Kozlowski * added a $nodename: pattern: to enforce "gpu" nodenames - inspired by Neil Armstrong * fixed node name for s5pv210 - suggested by Sergei Shtylyov PATCH V6 2020-04-15 10:35:31: * rebased to v5.7-rc1 * added DTS for for a31, a31s, a83t - by Philipp Rossak * added DTS for "samsung,s5pv210-sgx540-120" - by Jonathan Bakker * bindings.yaml fixes: - added a31, a31 - fixes for omap4470 - jz4780 contains an sgx540-130 and not -120 - a83t contains an sgx544-115 and not -116 - removed "additionalProperties: false" because some SoC may need additional properties PATCH V5 2020-03-29 19:38:32: * reworked YAML bindings to pass dt_binding_check and be better grouped * rename all nodes to "gpu: gpu@" * removed "img,sgx5" from example - suggested by Rob Herring PATCH V4 2019-12-17 19:02:11: * MIPS: DTS: jz4780: removed "img,sgx5" from bindings * YAML bindings: updated according to suggestions by Rob Herring * MIPS: DTS: jz4780: insert-sorted gpu node by register address - suggested by Paul Cercueil PATCH V3 2019-11-24 12:40:33: * reworked YAML format with help by Rob Herring * removed .txt binding document * change compatible "ti,am335x-sgx" to "ti,am3352-sgx" - suggested by Tony Lindgren PATCH V2 2019-11-07 12:06:17: * tried to convert bindings to YAML format - suggested by Rob Herring * added JZ4780 DTS node (proven to load the driver) * removed timer and img,cores properties until we know we really need them - suggested by Rob Herring PATCH V1 2019-10-18 20:46:35: This patch series defines child nodes for the SGX5xx interface inside different SoC so that a driver can be found and probed by the compatible strings and can retrieve information about the SGX revision that is included in a specific SoC. It also defines the interrupt number to be used by the SGX driver, and optionally clocks, power, resets depending on how the SoC integration is done. There is currently no mainline driver for these GPUs, but a project [1] is ongoing with the goal to get the open-source part as provided by TI/IMG and others into drivers/gpu/drm/pvrsgx in the future. So this patch series is the basis. The kernel modules built from this project have successfully demonstrated to work with the DTS definitions from this patch set on AM335x BeagleBone Black, DM3730 and OMAP5 Pyra and Droid 4. They partially work on OMAP3530 and PandaBoard ES but that is likely a problem in the kernel driver or the (non-free) user-space libraries and binaries. The driver works on jz4780 but user-space could not yet be tested. [1]: https://github.com/openpvrsgx-devgroup H. Nikolaus Schaller (8): dt-bindings: add img,pvrsgx.yaml for Imagination GPUs ARM: DTS: am33xx: add sgx gpu child node ARM: DTS: am3517: add sgx gpu child node ARM: DTS: omap34xx: add sgx gpu child node ARM: DTS: omap36xx: add sgx gpu child node ARM: DTS: omap4: add sgx gpu child node ARM: DTS: omap5: add sgx gpu child node MIPS: DTS: jz4780: add sgx gpu node Jonathan Bakker (1): arm: dts: s5pv210: Add node for SGX 540 Philipp Rossak (3): ARM: dts: sun6i: a31: add sgx gpu child node ARM: dts: sun6i: a31s: add sgx gpu child node ARM: dts: sun8i: a83t: add sgx gpu child node .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++ arch/arm/boot/dts/am33xx.dtsi | 11 +- arch/arm/boot/dts/am3517.dtsi | 9 +- arch/arm/boot/dts/omap34xx.dtsi | 11 +- arch/arm/boot/dts/omap36xx.dtsi | 9 +- arch/arm/boot/dts/omap4.dtsi | 11 +- arch/arm/boot/dts/omap4470.dts| 15 ++ arch/arm/boot/dts/omap5.dtsi | 11 +- arch/arm/boot/dts/s5pv210.dtsi| 13 ++ arch/arm/boot/dts/sun6i-a31.dtsi | 11 ++ arch/arm/boot/dts/sun6i-a31s.dtsi | 10 ++ arch/arm/boot/dts/sun8i-a83t.dtsi | 11 ++ arch/mips/boot/dts/ingenic/jz4780.dtsi| 11 ++ 13 files changed, 255 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml create mode 100644 arch/arm/boot/dts/omap4470.dts -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v7 05/12] ARM: DTS: omap36xx: add sgx gpu child node
Add SGX GPU node with interrupt. Tested on GTA04, BeagleBoard XM.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap36xx.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 71f3c8f1f924..b308dbb3b1bb 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -211,10 +211,11 @@ sgx_module: target-module@5000 {
#size-cells = <1>;
ranges = <0 0x5000 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap3-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x0 0x1>;/* 64kB */
+ interrupts = <21>;
+ };
};
};
--
2.25.1
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[PATCH v7 09/12] ARM: dts: sun6i: a31: add sgx gpu child node
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo available.
The currently used binding that is used during development is more
complete and was already verifyed by loading the kernelmodule successful.
Signed-off-by: Philipp Rossak
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f3425a66fc0a..933a825bf460 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1417,5 +1417,16 @@ p2wi: i2c@1f03400 {
#address-cells = <1>;
#size-cells = <0>;
};
+
+ gpu: gpu@1c40 {
+ compatible = "allwinner,sun8i-a31-sgx544-115",
+"img,sgx544-115", "img,sgx544";
+ reg = <0x01c4 0x1>;
+ /*
+* This node is currently a placeholder for the gpu.
+* This will be completed when a full demonstration
+* of the openpvrsgx driver is available for this board.
+*/
+ };
};
};
--
2.25.1
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[PATCH v7 10/12] ARM: dts: sun6i: a31s: add sgx gpu child node
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo available.
The currently used binding that is used during development is more
complete and was already verifyed by loading the kernelmodule successful.
Signed-off-by: Philipp Rossak
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/sun6i-a31s.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi
b/arch/arm/boot/dts/sun6i-a31s.dtsi
index 97e2c51d0aea..669770d2934a 100644
--- a/arch/arm/boot/dts/sun6i-a31s.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -59,3 +59,13 @@ {
{
compatible = "allwinner,sun6i-a31s-tcon";
};
+
+ {
+ compatible = "allwinner,sun8i-a31s-sgx544-115",
+"img,sgx544-115", "img,sgx544";
+ /*
+* This node is currently a placeholder for the gpu.
+* This will be completed when a full demonstration
+* of the openpvrsgx driver is available for this board.
+*/
+};
--
2.25.1
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Re: [PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
> Am 24.04.2020 um 22:34 schrieb H. Nikolaus Schaller : > > The Imagination PVR/SGX GPU is part of several SoC from > multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, > Allwinner A83 and others. > > With this binding, we describe how the SGX processor is > interfaced to the SoC (registers and interrupt). > > The interface also consists of clocks, reset, power but > information from data sheets is vague and some SoC integrators > (TI) deciced to use a PRCM wrapper (ti,sysc) which does s/deciced/decided/ > all clock, reset and power-management through registers > outside of the sgx register block. > > Therefore all these properties are optional. > > Tested by make dt_binding_check > > Signed-off-by: H. Nikolaus Schaller > --- > .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > new file mode 100644 > index ..33a9c4c6e784 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Imagination PVR/SGX GPU > + > +maintainers: > + - H. Nikolaus Schaller > + > +description: |+ > + This binding describes the Imagination SGX5 series of 3D accelerators which > + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, > + Allwinner A83, and Intel Poulsbo and CedarView and more. > + > + For an extensive list see: > https://en.wikipedia.org/wiki/PowerVR#Implementations > + > + The SGX node is usually a child node of some DT node belonging to the SoC > + which handles clocks, reset and general address space mapping of the SGX > + register area. If not, an optional clock can be specified here. ^^^ this is no longer that way. now clocks, reset etc. are part of this node but can be omitted if done by the parent node. => either remove this sentence or rewrite. > + > +properties: > + $nodename: > +pattern: '^gpu@[a-f0-9]+$' > + compatible: > +oneOf: > + - description: SGX530-121 based SoC > +items: > + - enum: > +- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz > and similar > + - const: img,sgx530-121 > + - const: img,sgx530 > + > + - description: SGX530-125 based SoC > +items: > + - enum: > +- ti,am3352-sgx530-125 # BeagleBone Black > +- ti,am3517-sgx530-125 > +- ti,am4-sgx530-125 > +- ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz > and similar > +- ti,ti81xx-sgx530-125 > + - const: ti,omap3-sgx530-125 > + - const: img,sgx530-125 > + - const: img,sgx530 > + > + - description: SGX535-116 based SoC > +items: > + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx > + - const: img,sgx535-116 > + - const: img,sgx535 > + > + - description: SGX540-116 based SoC > +items: > + - const: intel,medfield-gma-sgx540 # Atom Z24xx > + - const: img,sgx540-116 > + - const: img,sgx540 > + > + - description: SGX540-120 based SoC > +items: > + - enum: > +- samsung,s5pv210-sgx540-120 > +- ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar > + - const: img,sgx540-120 > + - const: img,sgx540 > + > + - description: SGX540-130 based SoC > +items: > + - enum: > +- ingenic,jz4780-sgx540-130 # CI20 > + - const: img,sgx540-130 > + - const: img,sgx540 > + > + - description: SGX544-112 based SoC > +items: > + - const: ti,omap4470-sgx544-112 > + - const: img,sgx544-112 > + - const: img,sgx544 > + > + - description: SGX544-115 based SoC > +items: > + - enum: > +- allwinner,sun8i-a31-sgx544-115 > +- allwinner,sun8i-a31s-sgx544-115 > +- allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner > A83T) and similar > + - const: img,sgx544-115 > + - const: img,sgx544 > + > + - description: SGX544-116 based SoC > +items: > + - enum: > +- ti,d
[PATCH v7 11/12] ARM: dts: sun8i: a83t: add sgx gpu child node
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo available.
The currently used binding that is used during development is more
complete and was already verifyed by loading the kernelmodule successful.
Signed-off-by: Philipp Rossak
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 655404d6d3a3..bfb900622bf6 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1192,6 +1192,17 @@ ths: thermal-sensor@1f04000 {
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
+
+ gpu: gpu@1c40 {
+ compatible = "allwinner,sun8i-a83t-sgx544-115",
+"img,sgx544-115", "img,sgx544";
+ reg = <0x01c4 0x1>;
+ /*
+* This node is currently a placeholder for the gpu.
+* This will be completed when a full demonstration
+* of the openpvrsgx driver is available for this board.
+*/
+ };
};
thermal-zones {
--
2.25.1
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[PATCH v7 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
The Imagination PVR/SGX GPU is part of several SoC from
multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
Allwinner A83 and others.
With this binding, we describe how the SGX processor is
interfaced to the SoC (registers and interrupt).
The interface also consists of clocks, reset, power but
information from data sheets is vague and some SoC integrators
(TI) deciced to use a PRCM wrapper (ti,sysc) which does
all clock, reset and power-management through registers
outside of the sgx register block.
Therefore all these properties are optional.
Tested by make dt_binding_check
Signed-off-by: H. Nikolaus Schaller
---
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++
1 file changed, 150 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
new file mode 100644
index ..33a9c4c6e784
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |+
+ This binding describes the Imagination SGX5 series of 3D accelerators which
+ are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
+ Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+ For an extensive list see:
https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+ The SGX node is usually a child node of some DT node belonging to the SoC
+ which handles clocks, reset and general address space mapping of the SGX
+ register area. If not, an optional clock can be specified here.
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+ compatible:
+oneOf:
+ - description: SGX530-121 based SoC
+items:
+ - enum:
+- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and
similar
+ - const: img,sgx530-121
+ - const: img,sgx530
+
+ - description: SGX530-125 based SoC
+items:
+ - enum:
+- ti,am3352-sgx530-125 # BeagleBone Black
+- ti,am3517-sgx530-125
+- ti,am4-sgx530-125
+- ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz
and similar
+- ti,ti81xx-sgx530-125
+ - const: ti,omap3-sgx530-125
+ - const: img,sgx530-125
+ - const: img,sgx530
+
+ - description: SGX535-116 based SoC
+items:
+ - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+ - const: img,sgx535-116
+ - const: img,sgx535
+
+ - description: SGX540-116 based SoC
+items:
+ - const: intel,medfield-gma-sgx540 # Atom Z24xx
+ - const: img,sgx540-116
+ - const: img,sgx540
+
+ - description: SGX540-120 based SoC
+items:
+ - enum:
+- samsung,s5pv210-sgx540-120
+- ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+ - const: img,sgx540-120
+ - const: img,sgx540
+
+ - description: SGX540-130 based SoC
+items:
+ - enum:
+- ingenic,jz4780-sgx540-130 # CI20
+ - const: img,sgx540-130
+ - const: img,sgx540
+
+ - description: SGX544-112 based SoC
+items:
+ - const: ti,omap4470-sgx544-112
+ - const: img,sgx544-112
+ - const: img,sgx544
+
+ - description: SGX544-115 based SoC
+items:
+ - enum:
+- allwinner,sun8i-a31-sgx544-115
+- allwinner,sun8i-a31s-sgx544-115
+- allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T)
and similar
+ - const: img,sgx544-115
+ - const: img,sgx544
+
+ - description: SGX544-116 based SoC
+items:
+ - enum:
+- ti,dra7-sgx544-116 # DRA7
+- ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
+ - const: img,sgx544-116
+ - const: img,sgx544
+
+ - description: SGX545 based SoC
+items:
+ - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+ - const: img,sgx545-116
+ - const: img,sgx545
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ interrupt-names:
+maxItems: 1
+items:
+ - const: sgx
+
+ clocks:
+maxItems: 4
+
+ clock-names:
+maxItems: 4
+items:
+ - const: core
+ - const: sys
+ - const: mem
+ - const: hyd
+
+ sgx-supply: true
+
+ power-domains:
+maxItems: 1
+
+ resets:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |+
+#include
+
+gpu: gpu@fe00 {
+ compatible = "ti,
[PATCH v7 08/12] arm: dts: s5pv210: Add node for SGX 540
From: Jonathan Bakker
All s5pv210 devices have a PowerVR SGX 540 (revision 120) attached.
There is no external regulator for it so it can be enabled by default.
Signed-off-by: Jonathan Bakker
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/s5pv210.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index 2ad642f51fd9..abbdda205c1b 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -512,6 +512,19 @@ vic3: interrupt-controller@f230 {
#interrupt-cells = <1>;
};
+ gpu: gpu@f300 {
+ compatible = "samsung,s5pv210-sgx540-120";
+ reg = <0xf300 0x1>;
+ interrupt-parent = <>;
+ interrupts = <10>;
+ clock-names = "core";
+ clocks = < CLK_G3D>;
+
+ assigned-clocks = < MOUT_G3D>, <
DOUT_G3D>;
+ assigned-clock-rates = <0>, <6670>;
+ assigned-clock-parents = < MOUT_MPLL>;
+ };
+
fimd: fimd@f800 {
compatible = "samsung,s5pv210-fimd";
interrupt-parent = <>;
--
2.25.1
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[PATCH v7 06/12] ARM: DTS: omap4: add sgx gpu child node
Add SGX GPU node with interrupt. Tested on PandaBoard ES.
Since omap4420/30/60 and omap4470 come with different SGX variants
we need to introduce a new omap4470.dtsi. If an omap4470 board
does not want to use SGX it is no problem to still include
omap4460.dtsi.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap4.dtsi | 11 ++-
arch/arm/boot/dts/omap4470.dts | 15 +++
2 files changed, 21 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/omap4470.dts
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 763bdea8c829..15ff3d7146af 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -389,7 +389,7 @@ abb_iva: regulator-abb-iva {
status = "disabled";
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -408,10 +408,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap4-sgx540-120",
"img,sgx540-120", "img,sgx540";
+ reg = <0x0 0x200>; /* 32MB */
+ interrupts = ;
+ };
};
/*
diff --git a/arch/arm/boot/dts/omap4470.dts b/arch/arm/boot/dts/omap4470.dts
new file mode 100644
index ..f29c581300bf
--- /dev/null
+++ b/arch/arm/boot/dts/omap4470.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4470 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include "omap4460.dtsi"
+
+ {
+ compatible = "ti,omap4470-sgx544-112", "img,sgx544-112", "img,sgx544";
+};
--
2.25.1
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[PATCH v7 02/12] ARM: DTS: am33xx: add sgx gpu child node
Add SGX GPU node with interrupt. Tested on BeagleBone Black.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am33xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index a35f5052d76f..155424d87156 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -564,7 +564,7 @@ aes: aes@0 {
};
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -583,10 +583,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x100>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,am3352-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x00 0x100>; /* 16 MB */
+ interrupts = <37>;
+ };
};
};
};
--
2.25.1
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[PATCH v7 04/12] ARM: DTS: omap34xx: add sgx gpu child node
Add SGX GPU node with interrupt. Tested on OpenPandora 600 MHz.
According to omap3530 TRM the SGX register block is 64kB.
See: 13.4 SGX Register Mapping, Table 13-2
Reported-by: Andrew F. Davis # register size
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap34xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index c4dd9801840d..51c60ee2b68d 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -167,12 +167,13 @@ sgx_module: target-module@5000 {
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x5000 0x4000>;
+ ranges = <0 0x5000 0x1>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap3-sgx530-121",
"img,sgx530-121", "img,sgx530";
+ reg = <0x0 0x1>;/* 64kB */
+ interrupts = <21>;
+ };
};
};
--
2.25.1
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Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
Hi, > Am 23.04.2020 um 22:36 schrieb Maxime Ripard : >> My goal is to keep the bindings as minimalistic as possible. And reset >> lines and power domains are (at least for those we have in the works) >> not needed to make working systems. >> >> Therefore, for clocks I also would start with a minimalistic approach >> for a single optional GPU core clock and leave out reset and power >> completely. > > Like I said above, the DT is considered an ABI and you'll have to > maintain backward compatibility (ie, newer kernel running with older > DT). Generally I fully agree to this rule (although I have experienced that exceptions happen more often than I like). But here, we don't have any older DT which define something about SGX. We introduce SGX for the first time with bindings and DT in parallel. So they are in sync. Therefore, newer kernels with SGX support and older DT simply will skip SGX and not load any drivers. So we can't break older DT and older DT can't break SGX. What we introduce is a DT code that is well hung and tested (originating in vendor kernels). It is cast in a bindings.yaml where not everyone is happy with for reasons outside the originally proposed DT. For new SoC not yet supported, I don't see a need to touch the existing ones. This is because I only propose to *add* properties to the bindings for devices that have not been supported with SGX before and are not sufficiently covered by what exists. So backward compatibility is a non-problem. > Therefore, you won't be able to require a new clock, reset or > power-domain later on for example. > > I guess the question I'm really asking is: since you don't really know > how the hardware is integrated at the moment, Like I explained, we do not need to know and model all details about the hardware integration. The register set of an SoC does not always provide bits to control all signals we may see in a block diagram or think they must exist. We have a set of SoC where it is demonstrated to work without need for more detailed knowledge about specific hardware integration. So we know everything of importance for this initial set of SoC to make it work. > why should we have that > discussion *now*. It's really not suprising that you don't know yet, so > I'm not sure why we need to rush in the bindings. Because: * there are people who want to have upstream SGX support for an initial set of SoC *now* * the discussion already lasts ca. 6 months since I posted v1, that should be enough and is not a rush * it is not required to know more details to make a working system * we will not gain more information by waiting for another year or two * problems are not solved by postponing them * there are DTS for some initial SoC, tested to work * it is no longer possible to submit DT without bindings.yaml (or is it?) * we just need to define a bindings.yaml for them, not invent something completely new * we can start with a minimal bindings.yaml for the analysed SoC and *extend* it in the future if really needed * we can discuss changes & extensions for the bindings when they are really proposed * having this patch series upstream is a prerequisite for introducing the sgx kernel driver to staging In other words: your suggestion to postpone everything will keep finished work sitting in front of the door and rotting and blocking unfinished work... And to be honest, we have postponed SGX support already for too long time and could be much farther with more and broader community cooperation. So we should not block ourselves. So if you can contribute new information or proposals to specifically improve the proposed bindings.yaml, you are very welcome. But please do it *now*. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
Hi Neil, > Am 23.04.2020 um 17:00 schrieb Neil Armstrong : >> One thing we can learn is that "core" seems to be a de facto standard >> for the core clock-name. An alternative "gpu" is used by nvidia,gk20a.txt. > > Usually IPs needs a few clocks: > - pclk or apb or reg: the clock clocking the "slave" bus to serve the > registers > - axi or bus or ahb: the bus clocking the the "master" bus to get data from > system memory > - core: the actual clock feeding the GPU logic And the sgx544 seems to have two such clocks. > Sometimes you have a single clock for slave and master bus. > > But you can also have separate clocks for shader cores, .. this depends on > the IP and it's architecture. > The IP can also have memories with separate clocks, etc... Indeed. > But all these clocks can be source by an unique clock on a SoC, but different > on another > SoC, this is why it's important to list them all, even optional. > > You'll certainly have at least a reset signal, and a power domain, these > should exist and be optional. Well, they exist only as hints in block diagrams of some SoC data sheets (so we do not know if they represent the imagination definitions) and the current driver code doesn't make use of it. Still the gpu core works. So I do not see any urgent need to add a complete list to the bindings now. Unless some special SoC integration makes use of them. Then it is IMHO easier to extend the bindings by a follow-up patch than now thinking about all potential options and bloating the bindings with things we (the open source community) doesn't and can't know. My goal is to keep the bindings as minimalistic as possible. And reset lines and power domains are (at least for those we have in the works) not needed to make working systems. Therefore, for clocks I also would start with a minimalistic approach for a single optional GPU core clock and leave out reset and power completely. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
Hi Maxime, > Am 22.04.2020 um 17:13 schrieb Maxime Ripard : > > On Wed, Apr 22, 2020 at 09:10:57AM +0200, H. Nikolaus Schaller wrote: >>> Am 22.04.2020 um 08:58 schrieb Maxime Ripard : >>>> >>>> It also allows to handle different number of clocks (A31 seems to >>>> need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings >>>> or making big lists of conditionals. This variance would be handled >>>> outside the sgx core bindings and driver. >>> >>> I disagree. Every other GPU binding and driver is handling that just fine, >>> and >>> the SGX is not special in any case here. >> >> Can you please better explain this? With example or a description >> or a proposal? > > I can't, I don't have any knowledge about this GPU. Hm. Now I am fully puzzled. You have no knowledge about this GPU but disagree with our proposal? Is it just gut feeling? Anyways, we need to find a solution. Together. > >> I simply do not have your experience with "every other GPU" as you have. >> And I admit that I can't read from your statement what we should do >> to bring this topic forward. >> >> So please make a proposal how it should be in your view. > > If you need some inspiration, I guess you could look at the mali and vivante > bindings once you have an idea of what the GPU needs across the SoCs it's > integrated in. Well, I do not need inspiration, we need to come to an agreement about img,pvrsgx.yaml and we need some maintainer to finally pick it up. I wonder how we can come to this stage. If I look at vivante,gc.yaml or arm,mali-utgard.yaml I don't see big differences to what we propose and those I see seem to come from technical differences between sgx, vivante, mali etc. So there is no single scheme that fits all different gpu types. One thing we can learn is that "core" seems to be a de facto standard for the core clock-name. An alternative "gpu" is used by nvidia,gk20a.txt. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
Hi Maxime, > Am 22.04.2020 um 08:58 schrieb Maxime Ripard : > > On Tue, Apr 21, 2020 at 07:29:32PM +0200, H. Nikolaus Schaller wrote: >> >>> Am 21.04.2020 um 16:15 schrieb Tony Lindgren : >>> >>> * Maxime Ripard [200421 11:22]: >>>> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >>>>> I had a look on genpd and I'm not really sure if that fits. >>>>> >>>>> It is basically some bit that verify that the clocks should be enabled or >>>>> disabled. >>>> >>>> No, it can do much more than that. It's a framework to control the SoCs >>>> power >>>> domains, so clocks might be a part of it, but most of the time it's going >>>> to be >>>> about powering up a particular device. >>> >>> Note that on omaps there are actually SoC module specific registers. >> >> Ah, I see. This is of course a difference that the TI glue logic has >> its own registers in the same address range as the sgx and this can't >> be easily handled by a common sgx driver. >> >> This indeed seems to be unique with omap. >> >>> And there can be multiple devices within a single target module on >>> omaps. So the extra dts node and device is justified there. >>> >>> For other SoCs, the SGX clocks are probably best handled directly >>> in pvr-drv.c PM runtime functions unless a custom hardware wrapper >>> with SoC specific registers exists. >> >> That is why we need to evaluate what the better strategy is. >> >> So we have >> a) omap which has a custom wrapper around the sgx >> b) others without, i.e. an empty (or pass-through) wrapper >> >> Which one do we make the "standard" and which one the "exception"? >> What are good reasons for either one? >> >> >> I am currently in strong favour of a) being standard because it >> makes the pvr-drv.c simpler and really generic (independent of >> wrapping into any SoC). >> >> This will likely avoid problems if we find more SoC with yet another >> scheme how the SGX clocks are wrapped. >> >> It also allows to handle different number of clocks (A31 seems to >> need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings >> or making big lists of conditionals. This variance would be handled >> outside the sgx core bindings and driver. > > I disagree. Every other GPU binding and driver is handling that just fine, and > the SGX is not special in any case here. Can you please better explain this? With example or a description or a proposal? I simply do not have your experience with "every other GPU" as you have. And I admit that I can't read from your statement what we should do to bring this topic forward. So please make a proposal how it should be in your view. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
> Am 21.04.2020 um 16:15 schrieb Tony Lindgren : > > * Maxime Ripard [200421 11:22]: >> On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >>> I had a look on genpd and I'm not really sure if that fits. >>> >>> It is basically some bit that verify that the clocks should be enabled or >>> disabled. >> >> No, it can do much more than that. It's a framework to control the SoCs power >> domains, so clocks might be a part of it, but most of the time it's going to >> be >> about powering up a particular device. > > Note that on omaps there are actually SoC module specific registers. Ah, I see. This is of course a difference that the TI glue logic has its own registers in the same address range as the sgx and this can't be easily handled by a common sgx driver. This indeed seems to be unique with omap. > And there can be multiple devices within a single target module on > omaps. So the extra dts node and device is justified there. > > For other SoCs, the SGX clocks are probably best handled directly > in pvr-drv.c PM runtime functions unless a custom hardware wrapper > with SoC specific registers exists. That is why we need to evaluate what the better strategy is. So we have a) omap which has a custom wrapper around the sgx b) others without, i.e. an empty (or pass-through) wrapper Which one do we make the "standard" and which one the "exception"? What are good reasons for either one? I am currently in strong favour of a) being standard because it makes the pvr-drv.c simpler and really generic (independent of wrapping into any SoC). This will likely avoid problems if we find more SoC with yet another scheme how the SGX clocks are wrapped. It also allows to handle different number of clocks (A31 seems to need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings or making big lists of conditionals. This variance would be handled outside the sgx core bindings and driver. So instead of an img+omap.yaml and an img+a81.yaml and an img+a31.yaml etc. we have a single img,pvrsgx.yaml and individual wrappers (the omap one already exists as bindings/bus/ti-sysc.txt). The only drawback is that we need this "pass-through" wrapper in DTS and driver code to handle clocks, power etc. The second best solution in my view is to make b) the standard and allow the clock(s) to be optional to cover the omap case. And conditionals are added to properly describe the variance of how the sgx is wrapped/integrated. IMHO this is a decision which can not be easily revised later. It is an architectural decision. So we should base it on strategic goals. > > > Regards, > > Tony > BR and thanks for clarification, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [drm:simple_bridge_attach [simple_bridge]] *ERROR* Fix bridge driver to make connector optional!
Hi Laurent, > Am 17.04.2020 um 14:58 schrieb Laurent Pinchart > : > > Hello, > > On Fri, Apr 17, 2020 at 02:44:22PM +0200, Maxime Ripard wrote: >> On Fri, Apr 17, 2020 at 02:18:11PM +0200, H. Nikolaus Schaller wrote: >>> Hi Maxime, >>> I have started to test v5.7-rc1 and can't fully boot the GTA04 >>> device any more. >>> >>> What I see in the log is: >>> >>> [ 28.567840] [drm:simple_bridge_attach [simple_bridge]] *ERROR* Fix >>> bridge driver to make connector optional! >>> [ 28.567871] omapdrm omapdrm.0: unable to attach bridge >>> /ocp@6800/dss@4805/encoder@48050c00 >>> [ 28.786529] omapdrm omapdrm.0: omap_modeset_init failed: ret=-22 >>> [ 28.841552] omapdrm: probe of omapdrm.0 failed with error -22 >>> >>> This device uses the ti,opa362 chip which did have a dedicated >>> omapdss driver before (which is removed now) and which seems to >>> be supported by the simple_bridge now. >>> >>> The opa362 is sitting in the video out path from >>> >>> omapdrm -> venc -> opa362 -> video-out-connector. >>> >>> What does this error mean? How can it be fixed? >> >> -22 is usually EINVAL, which can be pretty much anything. A good thing to do >> would be to bisect to see which actual commit broke it, but if I was to bet >> on >> something I guess it would be >> >> https://lore.kernel.org/dri-devel/20200226112514.12455-1-laurent.pinch...@ideasonboard.com/ > > Would "[PATCH 0/2] drm: bridge: simple-bridge: Enable usage with DRM > bridge connector helper" solve it ? Yes, seems to magically solve the boot issue! I'll confirm later if the opa362 is still (or again) working. BR and thanks, Nikolaus Schaller ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[drm:simple_bridge_attach [simple_bridge]] *ERROR* Fix bridge driver to make connector optional!
Hi Maxime, I have started to test v5.7-rc1 and can't fully boot the GTA04 device any more. What I see in the log is: [ 28.567840] [drm:simple_bridge_attach [simple_bridge]] *ERROR* Fix bridge driver to make connector optional! [ 28.567871] omapdrm omapdrm.0: unable to attach bridge /ocp@6800/dss@4805/encoder@48050c00 [ 28.786529] omapdrm omapdrm.0: omap_modeset_init failed: ret=-22 [ 28.841552] omapdrm: probe of omapdrm.0 failed with error -22 This device uses the ti,opa362 chip which did have a dedicated omapdss driver before (which is removed now) and which seems to be supported by the simple_bridge now. The opa362 is sitting in the video out path from omapdrm -> venc -> opa362 -> video-out-connector. What does this error mean? How can it be fixed? BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Maxime,
> Am 17.04.2020 um 12:25 schrieb Maxime Ripard :
>
> Hi,
>
> On Wed, Apr 15, 2020 at 06:42:18PM +0200, H. Nikolaus Schaller wrote:
>>> Am 15.04.2020 um 18:21 schrieb Maxime Ripard :
>>>
>>> On Wed, Apr 15, 2020 at 05:09:45PM +0200, H. Nikolaus Schaller wrote:
>>>> Hi Maxime,
>>>>
>>>> Hm. Yes. We know that there likely are clocks and maybe reset
>>>> but for some SoC this seems to be undocumented and the reset
>>>> line the VHDL of the sgx gpu provides may be permanently tied
>>>> to "inactive".
>>>>
>>>> So if clocks are optional and not provided, a driver simply can assume
>>>> they are enabled somewhere else and does not have to care about. If
>>>> they are specified, the driver can enable/disable them.
>>>
>>> Except that at the hardware level, the clock is always going to be
>>> there. You can't control it, but it's there.
>>
>> Sure, we can deduce that from general hardware design knowledge.
>> But not every detail must be described in DT. Only the important
>> ones.
>>
>>>>> If OMAP is too much of a pain, you can also make
>>>>> a separate binding for it, and a generic one for the rest of us.
>>>>
>>>> No, omap isn't any pain at all.
>>>>
>>>> The pain is that some other SoC are most easily defined by clocks in
>>>> the gpu node which the omap doesn't need to explicitly specify.
>>>>
>>>> I would expect a much bigger nightmare if we split this into two
>>>> bindings variants.
>>>>
>>>>> I'd say that it's pretty unlikely that the clocks, interrupts (and
>>>>> even regulators) are optional. It might be fixed on some SoCs, but
>>>>> that's up to the DT to express that using fixed clocks / regulators,
>>>>> not the GPU binding itself.
>>>>
>>>> omap already has these defined them not to be part of the GPU binding.
>>>> The reason seems to be that this needs special clock gating control
>>>> especially for idle states which is beyond simple clock-enable.
>>>>
>>>> This sysc target-module@5600 node is already merged and therefore
>>>> we are only adding the gpu child node. Without defining clocks.
>>>>
>>>> For example:
>>>>
>>>>sgx_module: target-module@5600 {
>>>>compatible = "ti,sysc-omap4", "ti,sysc";
>>>>reg = <0x5600fe00 0x4>,
>>>> <0x5600fe10 0x4>;
>>>>reg-names = "rev", "sysc";
>>>>ti,sysc-midle = ,
>>>>,
>>>>;
>>>>ti,sysc-sidle = ,
>>>>,
>>>>;
>>>>clocks = <_clkctrl OMAP5_GPU_CLKCTRL 0>;
>>>>clock-names = "fck";
>>>>#address-cells = <1>;
>>>>#size-cells = <1>;
>>>>ranges = <0 0x5600 0x200>;
>>>>
>>>>gpu: gpu@0 {
>>>>compatible = "ti,omap5-sgx544-116",
>>>> "img,sgx544-116", "img,sgx544";
>>>>reg = <0x0 0x1>;
>>>>interrupts = ;
>>>>};
>>>>};
>>>>
>>>> The jz4780 example will like this:
>>>>
>>>>gpu: gpu@1304 {
>>>>compatible = "ingenic,jz4780-sgx540-130", "img,sgx540-130",
>>>> "img,sgx540";
>>>>reg = <0x1304 0x4000>;
>>>>
>>>>clocks = < JZ4780_CLK_GPU>;
>>>>clock-names = "gpu";
>>>>
>>>>interrupt-parent = <>;
>>>>interrupts = <63>;
>>>>};
>>>>
>>>> So the question is which one is "generic for the rest of us"?
>>>
>>> I'd say the latter.
>>
>> Why?
>>
>> TI SoC seem to be the broadest number of availabl
Re: [PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Rob, > Am 16.04.2020 um 22:41 schrieb Rob Herring : > > On Wed, 15 Apr 2020 10:35:08 +0200, "H. Nikolaus Schaller" wrote: >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers, interrupt etc.). >> >> In most cases, Clock, Reset and power management is handled >> by a parent node or elsewhere (e.g. code in the driver). >> >> Tested by make dt_binding_check dtbs_check >> >> Signed-off-by: H. Nikolaus Schaller >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 122 ++ >> 1 file changed, 122 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> > > My bot found errors running 'make dt_binding_check' on your patch: > > Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml: while parsing a block > mapping > in "", line 74, column 13 It turned out that there was a stray " in line 74 from the last editing phase. Will be fixed in v7. Would it be possible to make dt_binding_check not only report line/column but the contents of the line instead of ""? > did not find expected key > in "", line 117, column 21 > Documentation/devicetree/bindings/Makefile:12: recipe for target > 'Documentation/devicetree/bindings/gpu/img,pvrsgx.example.dts' failed > make[1]: *** [Documentation/devicetree/bindings/gpu/img,pvrsgx.example.dts] > Error 1 > make[1]: *** Waiting for unfinished jobs > Makefile:1264: recipe for target 'dt_binding_check' failed > make: *** [dt_binding_check] Error 2 > > See https://patchwork.ozlabs.org/patch/1270997 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master > --upgrade > > Please check and re-submit. BR and thanks, Nikolaus Schaller ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 08/12] arm: dts: s5pv210: Add G3D node
Hi Jonathan,
> Am 15.04.2020 um 20:17 schrieb Jonathan Bakker :
>
> Hi Nikolaus,
>
> On 2020-04-15 5:50 a.m., H. Nikolaus Schaller wrote:
>>
>>> Am 15.04.2020 um 13:49 schrieb Krzysztof Kozlowski :
>>>
>>> On Wed, 15 Apr 2020 at 10:36, H. Nikolaus Schaller
>>> wrote:
>>>>
>>>> From: Jonathan Bakker
>>>>
>>>> to add support for SGX540 GPU.
>>>
>>> Do not continue the subject in commit msg like it is one sentence.
>>> These are two separate sentences, so commit msg starts with capital
>>> letter and it is sentence by itself.
>>>
>
> Sorry, that's my fault, I should know better.
Mine as well...
>
> Nikolaus took this from my testing tree and I apparently didn't have it in
> as good as state as I should have.
>
>>>> Signed-off-by: Jonathan Bakker
>>>> Signed-off-by: H. Nikolaus Schaller
>>>> ---
>>>> arch/arm/boot/dts/s5pv210.dtsi | 15 +++
>>>> 1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/s5pv210.dtsi
>>>> b/arch/arm/boot/dts/s5pv210.dtsi
>>>> index 2ad642f51fd9..e7fc709c0cca 100644
>>>> --- a/arch/arm/boot/dts/s5pv210.dtsi
>>>> +++ b/arch/arm/boot/dts/s5pv210.dtsi
>>>> @@ -512,6 +512,21 @@ vic3: interrupt-controller@f230 {
>>>> #interrupt-cells = <1>;
>>>> };
>>>>
>>>> + g3d: g3d@f300 {
>>>> + compatible = "samsung,s5pv210-sgx540-120";
>>>> + reg = <0xf300 0x1>;
>>>> + interrupt-parent = <>;
>>>> + interrupts = <10>;
>>>> + clock-names = "sclk";
>>>> + clocks = < CLK_G3D>;
>>>
>>> Not part of bindings, please remove or add to the bindings.
>>
>> Well, the bindings should describe what is common for all SoC
>> and they are quite different in what they need in addition.
>>
>> Thererfore we have no "additionalProperties: false" in the
>> bindings [PATCH v6 01/12].
>>
>>>
>>>> +
>>>> + power-domains = < S5PV210_PD_G3D>;
>>>
>>> Ditto
>>
>> In this case it might be possible to add the clock/power-domains
>> etc. to a wrapper node compatible to "simple-pm-bus" or similar
>> and make the gpu a child of it.
>>
>> @Jontahan: can you please give it a try?
>>
>>
>
> The power-domains comes from a (so far) non-upstreamed power domain driver
> for s5pv210 that I've been playing around with. It's not necessary for proper
> operation as it's on by default.
>
> Looking at simple-pm-bus, I don't really understand its purpose. Is it a way
> of separating
> out a power domain from a main device's node? Or is it designed for when you
> have multiple
> devices under the same power domain?
>
> Nikolaus, I can regenerate a proper patch for you if you want that's not
> based on my testing tree.
Yes, please.
>
>>>
>>>> +
>>>> + assigned-clocks = < MOUT_G3D>, <
>>>> DOUT_G3D>;
>>>> + assigned-clock-rates = <0>, <6670>;
>>>> + assigned-clock-parents = < MOUT_MPLL>;
>>>
>>> Probably this should have status disabled because you do not set
>>> regulator supply.
>
> I don't believe there is a regulator on s5pv210, if there is, then it is a
> fixed regulator with no control on both s5pv210 devices that I have.
>
> The vendor driver did use the regulator framework for its power domain
> implementation, but that definitely shouldn't be upstreamed.
Ok, this means there is no need for regulators in the bindings.
BR,
Nikolaus
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Re: [PATCH v6 08/12] arm: dts: s5pv210: Add G3D node
> Am 15.04.2020 um 13:49 schrieb Krzysztof Kozlowski :
>
> On Wed, 15 Apr 2020 at 10:36, H. Nikolaus Schaller wrote:
>>
>> From: Jonathan Bakker
>>
>> to add support for SGX540 GPU.
>
> Do not continue the subject in commit msg like it is one sentence.
> These are two separate sentences, so commit msg starts with capital
> letter and it is sentence by itself.
>
>> Signed-off-by: Jonathan Bakker
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> arch/arm/boot/dts/s5pv210.dtsi | 15 +++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
>> index 2ad642f51fd9..e7fc709c0cca 100644
>> --- a/arch/arm/boot/dts/s5pv210.dtsi
>> +++ b/arch/arm/boot/dts/s5pv210.dtsi
>> @@ -512,6 +512,21 @@ vic3: interrupt-controller@f230 {
>>#interrupt-cells = <1>;
>>};
>>
>> + g3d: g3d@f300 {
>> + compatible = "samsung,s5pv210-sgx540-120";
>> + reg = <0xf300 0x1>;
>> + interrupt-parent = <>;
>> + interrupts = <10>;
>> + clock-names = "sclk";
>> + clocks = < CLK_G3D>;
>
> Not part of bindings, please remove or add to the bindings.
Well, the bindings should describe what is common for all SoC
and they are quite different in what they need in addition.
Thererfore we have no "additionalProperties: false" in the
bindings [PATCH v6 01/12].
>
>> +
>> + power-domains = < S5PV210_PD_G3D>;
>
> Ditto
In this case it might be possible to add the clock/power-domains
etc. to a wrapper node compatible to "simple-pm-bus" or similar
and make the gpu a child of it.
@Jontahan: can you please give it a try?
>
>> +
>> + assigned-clocks = < MOUT_G3D>, <
>> DOUT_G3D>;
>> + assigned-clock-rates = <0>, <6670>;
>> + assigned-clock-parents = < MOUT_MPLL>;
>
> Probably this should have status disabled because you do not set
> regulator supply.
>
> Best regards,
> Krzysztof
BR and thanks,
Nikolaus
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[PATCH v6 06/12] ARM: DTS: omap4: add sgx gpu child node
and add interrupt.
Since omap4420/30/60 and omap4470 come with different SGX variants
we need to introduce a new omap4470.dtsi. If an omap4470 board
does not want to use SGX it is no problem to still include
omap4460.dtsi.
Tested-by: H. Nikolaus Schaller # PandaBoard ES
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap4.dtsi | 11 ++-
arch/arm/boot/dts/omap4470.dts | 15 +++
2 files changed, 21 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/omap4470.dts
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 763bdea8c829..15ff3d7146af 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -389,7 +389,7 @@ abb_iva: regulator-abb-iva {
status = "disabled";
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -408,10 +408,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap4-sgx540-120",
"img,sgx540-120", "img,sgx540";
+ reg = <0x0 0x200>; /* 32MB */
+ interrupts = ;
+ };
};
/*
diff --git a/arch/arm/boot/dts/omap4470.dts b/arch/arm/boot/dts/omap4470.dts
new file mode 100644
index ..f29c581300bf
--- /dev/null
+++ b/arch/arm/boot/dts/omap4470.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4470 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include "omap4460.dtsi"
+
+ {
+ compatible = "ti,omap4470-sgx544-112", "img,sgx544-112", "img,sgx544";
+};
--
2.25.1
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[PATCH v6 10/12] ARM: dts: sun6i: a31s: add sgx gpu child node
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo available.
The currently used binding that is used during development is more
complete and was already verifyed by loading the kernelmodule successful.
Signed-off-by: Philipp Rossak
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/sun6i-a31s.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s.dtsi
b/arch/arm/boot/dts/sun6i-a31s.dtsi
index 97e2c51d0aea..669770d2934a 100644
--- a/arch/arm/boot/dts/sun6i-a31s.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s.dtsi
@@ -59,3 +59,13 @@ {
{
compatible = "allwinner,sun6i-a31s-tcon";
};
+
+ {
+ compatible = "allwinner,sun8i-a31s-sgx544-115",
+"img,sgx544-115", "img,sgx544";
+ /*
+* This node is currently a placeholder for the gpu.
+* This will be completed when a full demonstration
+* of the openpvrsgx driver is available for this board.
+*/
+};
--
2.25.1
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[PATCH v6 02/12] ARM: DTS: am33xx: add sgx gpu child node
and add interrupt.
Tested-by: H. Nikolaus Schaller # BeagleBone Black
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am33xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index a35f5052d76f..155424d87156 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -564,7 +564,7 @@ aes: aes@0 {
};
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -583,10 +583,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x100>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,am3352-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x00 0x100>; /* 16 MB */
+ interrupts = <37>;
+ };
};
};
};
--
2.25.1
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[PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
* rebased to v5.7-rc1 * added DTS for for a31, a31s, a83t - by Philipp Rossak * added DTS for "samsung,s5pv210-sgx540-120" - by Jonathan Bakker * bindings.yaml fixes: - added a31, a31 - fixes for omap4470 - jz4780 contains an sgx540-130 and not -120 - a83t contains an sgx544-115 and not -116 - removed "additionalProperties: false" because some SoC may need additional properties PATCH V5 2020-03-29 19:38:32: * reworked YAML bindings to pass dt_binding_check and be better grouped * rename all nodes to "gpu: gpu@" * removed "img,sgx5" from example - suggested by Rob Herring PATCH V4 2019-12-17 19:02:11: * MIPS: DTS: jz4780: removed "img,sgx5" from bindings * YAML bindings: updated according to suggestions by Rob Herring * MIPS: DTS: jz4780: insert-sorted gpu node by register address - suggested by Paul Cercueil PATCH V3 2019-11-24 12:40:33: * reworked YAML format with help by Rob Herring * removed .txt binding document * change compatible "ti,am335x-sgx" to "ti,am3352-sgx" - suggested by Tony Lindgren PATCH V2 2019-11-07 12:06:17: * tried to convert bindings to YAML format - suggested by Rob Herring * added JZ4780 DTS node (proven to load the driver) * removed timer and img,cores properties until we know we really need them - suggested by Rob Herring PATCH V1 2019-10-18 20:46:35: This patch series defines child nodes for the SGX5xx interface inside different SoC so that a driver can be found and probed by the compatible strings and can retrieve information about the SGX revision that is included in a specific SoC. It also defines the interrupt number to be used by the SGX driver. There is currently no mainline driver for these GPUs, but a project [1] is ongoing with the goal to get the open-source part as provided by TI/IMG and others into drivers/gpu/drm/pvrsgx. The kernel modules built from this project have successfully demonstrated to work with the DTS definitions from this patch set on AM335x BeagleBone Black, DM3730 and OMAP5 Pyra and Droid 4. They partially work on OMAP3530 and PandaBoard ES but that is likely a problem in the kernel driver or the (non-free) user-space libraries and binaries. Wotk for JZ4780 (CI20 board) is in progress and there is potential to extend this work to e.g. BananaPi-M3 (A83) and some Intel Poulsbo and CedarView devices. [1]: https://github.com/openpvrsgx-devgroup H. Nikolaus Schaller (8): dt-bindings: add img,pvrsgx.yaml for Imagination GPUs ARM: DTS: am33xx: add sgx gpu child node ARM: DTS: am3517: add sgx gpu child node ARM: DTS: omap34xx: add sgx gpu child node ARM: DTS: omap36xx: add sgx gpu child node ARM: DTS: omap4: add sgx gpu child node ARM: DTS: omap5: add sgx gpu child node MIPS: DTS: jz4780: add sgx gpu node Jonathan Bakker (1): arm: dts: s5pv210: Add G3D node Philipp Rossak (3): ARM: dts: sun6i: a31: add sgx gpu child node ARM: dts: sun6i: a31s: add sgx gpu child node ARM: dts: sun8i: a83t: add sgx gpu child node .../devicetree/bindings/gpu/img,pvrsgx.yaml | 122 ++ arch/arm/boot/dts/am33xx.dtsi | 11 +- arch/arm/boot/dts/am3517.dtsi | 9 +- arch/arm/boot/dts/omap34xx.dtsi | 11 +- arch/arm/boot/dts/omap36xx.dtsi | 9 +- arch/arm/boot/dts/omap4.dtsi | 11 +- arch/arm/boot/dts/omap4470.dts| 15 +++ arch/arm/boot/dts/omap5.dtsi | 11 +- arch/arm/boot/dts/s5pv210.dtsi| 15 +++ arch/arm/boot/dts/sun6i-a31.dtsi | 11 ++ arch/arm/boot/dts/sun6i-a31s.dtsi | 10 ++ arch/arm/boot/dts/sun8i-a83t.dtsi | 11 ++ arch/mips/boot/dts/ingenic/jz4780.dtsi| 11 ++ 13 files changed, 229 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml create mode 100644 arch/arm/boot/dts/omap4470.dts -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
> Am 15.04.2020 um 15:02 schrieb Maxime Ripard : > > On Wed, Apr 15, 2020 at 02:41:52PM +0200, H. Nikolaus Schaller wrote: >>>> The kernel modules built from this project have successfully >>>> demonstrated to work with the DTS definitions from this patch set on >>>> AM335x BeagleBone Black, DM3730 and OMAP5 Pyra and Droid 4. They >>>> partially work on OMAP3530 and PandaBoard ES but that is likely a >>>> problem in the kernel driver or the (non-free) user-space libraries >>>> and binaries. >>>> >>>> Wotk for JZ4780 (CI20 board) is in progress and there is potential >>>> to extend this work to e.g. BananaPi-M3 (A83) and some Intel Poulsbo >>>> and CedarView devices. >>> >>> If it's not been tested on any Allwinner board yet, I'll leave it >>> aside until it's been properly shown to work. >> >> Phillip has tested something on a83. > > I'm a bit skeptical on that one since it doesn't even list the > interrupts connected to the GPU that the binding mandates. I think he left it out for a future update. But best he comments himself. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Maxime,
> Am 15.04.2020 um 16:21 schrieb Maxime Ripard :
>
>>
>> Well we could add clocks and resets as optional but that would
>> allow to wrongly define omap.
>>
>> Or delegate them to a parent "simple-pm-bus" node.
>>
>> I have to study that material more to understand what you seem
>> to expect.
>
> The thing is, once that binding is in, it has to be backward
> compatible. So every thing that you leave out is something that you'll
> need to support in the driver eventually.
>
> If you don't want it to be a complete nightmare, you'll want to figure
> out as much as possible on how the GPU is integrated and make a
> binding out of that.
Hm. Yes. We know that there likely are clocks and maybe reset
but for some SoC this seems to be undocumented and the reset
line the VHDL of the sgx gpu provides may be permanently tied
to "inactive".
So if clocks are optional and not provided, a driver simply can assume
they are enabled somewhere else and does not have to care about. If
they are specified, the driver can enable/disable them.
> If OMAP is too much of a pain, you can also make
> a separate binding for it, and a generic one for the rest of us.
No, omap isn't any pain at all.
The pain is that some other SoC are most easily defined by clocks in
the gpu node which the omap doesn't need to explicitly specify.
I would expect a much bigger nightmare if we split this into two
bindings variants.
> I'd say that it's pretty unlikely that the clocks, interrupts (and
> even regulators) are optional. It might be fixed on some SoCs, but
> that's up to the DT to express that using fixed clocks / regulators,
> not the GPU binding itself.
omap already has these defined them not to be part of the GPU binding.
The reason seems to be that this needs special clock gating control
especially for idle states which is beyond simple clock-enable.
This sysc target-module@5600 node is already merged and therefore
we are only adding the gpu child node. Without defining clocks.
For example:
sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = ,
,
;
ti,sysc-sidle = ,
,
;
clocks = <_clkctrl OMAP5_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
gpu: gpu@0 {
compatible = "ti,omap5-sgx544-116",
"img,sgx544-116", "img,sgx544";
reg = <0x0 0x1>;
interrupts = ;
};
};
The jz4780 example will like this:
gpu: gpu@1304 {
compatible = "ingenic,jz4780-sgx540-130", "img,sgx540-130",
"img,sgx540";
reg = <0x1304 0x4000>;
clocks = < JZ4780_CLK_GPU>;
clock-names = "gpu";
interrupt-parent = <>;
interrupts = <63>;
};
So the question is which one is "generic for the rest of us"?
And how can we make a single binding for the sgx. Not one for each
special SoC variant that may exist.
IMHO the best answer is to make clocks an optional property.
Or if we do not want to define them explicitly, we use
additionalProperties: true.
An alternative could be to use a simple-pm-bus like:
sgx_module: sgx_module@1304 {
compatible = "simple-pm-bus";
clocks = < JZ4780_CLK_GPU>;
clock-names = "gpu";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1304 0x1>;
gpu: gpu@0 {
compatible = "ingenic,jz4780-sgx540-130",
"img,sgx540-130", "img,sgx540";
reg = <0x0 0x4000>;
interrupt-parent = <>;
interrupts = <63>;
};
};
This gets rid of any clock, reset and pm definitions for the sgx bindings.
But how this is done is outside this sgx bindings.
With such a scheme, the binding I propose here would be complete and fully
generic. We can even add additionalProperties: false.
BR,
Nikolaus
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[PATCH v6 12/12] MIPS: DTS: jz4780: add sgx gpu node
and add interrupt and clocks.
Tested to build for CI20 board and load a driver.
Setup can not yet be fully tested since there is no working
HDMI driver for jz4780.
Suggested-by: Paul Boddie
Tested-by: H. Nikolaus Schaller # CI20.
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index bb89653d16a3..883fe2c4c9e1 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -357,6 +357,17 @@ i2c4: i2c@10054000 {
status = "disabled";
};
+ gpu: gpu@1304 {
+ compatible = "ingenic,jz4780-sgx540-130", "img,sgx540-130",
"img,sgx540";
+ reg = <0x1304 0x4000>;
+
+ clocks = < JZ4780_CLK_GPU>;
+ clock-names = "gpu";
+
+ interrupt-parent = <>;
+ interrupts = <63>;
+ };
+
nemc: nemc@1341 {
compatible = "ingenic,jz4780-nemc";
reg = <0x1341 0x1>;
--
2.25.1
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Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
Hi Maxime, > Am 15.04.2020 um 12:10 schrieb Maxime Ripard : > > Hi, > > On Wed, Apr 15, 2020 at 10:35:07AM +0200, H. Nikolaus Schaller wrote: >> * rebased to v5.7-rc1 >> * added DTS for for a31, a31s, a83t - by Philipp Rossak >> * added DTS for "samsung,s5pv210-sgx540-120" - by Jonathan Bakker >> >> * bindings.yaml fixes: >> - added a31, a31 >> - fixes for omap4470 >> - jz4780 contains an sgx540-130 and not -120 >> - a83t contains an sgx544-115 and not -116 >> - removed "additionalProperties: false" because some SoC may need >> additional properties >> >> PATCH V5 2020-03-29 19:38:32: >> * reworked YAML bindings to pass dt_binding_check and be better grouped >> * rename all nodes to "gpu: gpu@" >> * removed "img,sgx5" from example - suggested by Rob Herring >> >> >> PATCH V4 2019-12-17 19:02:11: >> * MIPS: DTS: jz4780: removed "img,sgx5" from bindings >> * YAML bindings: updated according to suggestions by Rob Herring >> * MIPS: DTS: jz4780: insert-sorted gpu node by register address - suggested >> by Paul Cercueil >> >> PATCH V3 2019-11-24 12:40:33: >> * reworked YAML format with help by Rob Herring >> * removed .txt binding document >> * change compatible "ti,am335x-sgx" to "ti,am3352-sgx" - suggested by Tony >> Lindgren >> >> PATCH V2 2019-11-07 12:06:17: >> * tried to convert bindings to YAML format - suggested by Rob Herring >> * added JZ4780 DTS node (proven to load the driver) >> * removed timer and img,cores properties until we know we really need them - >> suggested by Rob Herring >> >> PATCH V1 2019-10-18 20:46:35: >> >> This patch series defines child nodes for the SGX5xx interface inside >> different SoC so that a driver can be found and probed by the >> compatible strings and can retrieve information about the SGX revision >> that is included in a specific SoC. It also defines the interrupt number >> to be used by the SGX driver. >> >> There is currently no mainline driver for these GPUs, but a project >> [1] is ongoing with the goal to get the open-source part as provided >> by TI/IMG and others into drivers/gpu/drm/pvrsgx. > > Just a heads up, DRM requires an open-source user-space, so if your > plan is to move the open-source kernel driver while using the > closed-source library (as that page seem to suggest), that might > change a few things. The far future goal is to arrive at a completely open implementation, but nobody knows how to get there. Therefore we bake smaller bread :) step 1: get SoC integration right and stable (this is what this series is for) step 2: make the open source kernel driver work with closed-source libs step 3: write open-source replacements for user-space > >> The kernel modules built from this project have successfully >> demonstrated to work with the DTS definitions from this patch set on >> AM335x BeagleBone Black, DM3730 and OMAP5 Pyra and Droid 4. They >> partially work on OMAP3530 and PandaBoard ES but that is likely a >> problem in the kernel driver or the (non-free) user-space libraries >> and binaries. >> >> Wotk for JZ4780 (CI20 board) is in progress and there is potential >> to extend this work to e.g. BananaPi-M3 (A83) and some Intel Poulsbo >> and CedarView devices. > > If it's not been tested on any Allwinner board yet, I'll leave it > aside until it's been properly shown to work. Phillip has testes something on a83. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6 07/12] ARM: DTS: omap5: add sgx gpu child node
> Am 15.04.2020 um 15:47 schrieb Krzysztof Kozlowski :
>
> On Wed, Apr 15, 2020 at 01:46:06PM +0200, H. Nikolaus Schaller wrote:
>> Hi Krzysztof,
>>
>>> Am 15.04.2020 um 13:38 schrieb Krzysztof Kozlowski :
>>>
>>> On Wed, 15 Apr 2020 at 10:36, H. Nikolaus Schaller
>>> wrote:
>>>>
>>>> and add interrupt.
>>>>
>>>> Tested-by: H. Nikolaus Schaller # Pyra-Handheld.
>>>
>>> Don't add your own Tested-by tags. These are implied by authorship,
>>> otherwise all patches people make should have such tag.
>>
>> Ok I see. AFAIR it originates in several phases of editing to report on
>> which device it was tested.
>>
>> Is there a canonical way of writing "tested-on: ${HARDWARE}"?
>>
>> E.g. would this be ok?
>>
>> Signed-off: H. Nikolaus Schaller # tested on
>> Pyra-Handheld
>
> If you think tested platform is worth mentioning in the commit msg
> (it will stay there forever, ever, ever) then just add a line like:
>
> "Add SGX GPU node. Tested on Pyra-Handheld."
>
> From time to time we add such information to note that only one platform
> was actually tested.
Yes that is what it should express.
> I am not sure what benefit it brings to most
> cases... but your commit msg is so short that adding one more sentence
> seems reasonable. :)
Ok, will queue for v7.
>
> Best regards,
> Krzysztof
BR and thanks,
Nikolaus
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[PATCH v6 08/12] arm: dts: s5pv210: Add G3D node
From: Jonathan Bakker
to add support for SGX540 GPU.
Signed-off-by: Jonathan Bakker
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/s5pv210.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index 2ad642f51fd9..e7fc709c0cca 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -512,6 +512,21 @@ vic3: interrupt-controller@f230 {
#interrupt-cells = <1>;
};
+ g3d: g3d@f300 {
+ compatible = "samsung,s5pv210-sgx540-120";
+ reg = <0xf300 0x1>;
+ interrupt-parent = <>;
+ interrupts = <10>;
+ clock-names = "sclk";
+ clocks = < CLK_G3D>;
+
+ power-domains = < S5PV210_PD_G3D>;
+
+ assigned-clocks = < MOUT_G3D>, <
DOUT_G3D>;
+ assigned-clock-rates = <0>, <6670>;
+ assigned-clock-parents = < MOUT_MPLL>;
+ };
+
fimd: fimd@f800 {
compatible = "samsung,s5pv210-fimd";
interrupt-parent = <>;
--
2.25.1
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Re: [PATCH v6 08/12] arm: dts: s5pv210: Add G3D node
Hi Sergei and Jonathan,
> Am 15.04.2020 um 11:15 schrieb Sergei Shtylyov
> :
>
> Hello!
>
> On 15.04.2020 11:35, H. Nikolaus Schaller wrote:
>
>> From: Jonathan Bakker
>> to add support for SGX540 GPU.
>> Signed-off-by: Jonathan Bakker
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> arch/arm/boot/dts/s5pv210.dtsi | 15 +++
>> 1 file changed, 15 insertions(+)
>> diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
>> index 2ad642f51fd9..e7fc709c0cca 100644
>> --- a/arch/arm/boot/dts/s5pv210.dtsi
>> +++ b/arch/arm/boot/dts/s5pv210.dtsi
>> @@ -512,6 +512,21 @@ vic3: interrupt-controller@f230 {
>> #interrupt-cells = <1>;
>> };
>> + g3d: g3d@f300 {
>
> Should be named generically, "gpu@f300", according to the DT spec 0.2,
> section 2.2.2. It's either "gpu" or "display" TTBOMK...
Yes, you are right and we have named it such for all other
devices in this series. I just missed that.
Jonathan, if you are ok, I'll fix that.
>
> [...]
>
> MBR, Sergei
BR and thanks,
Nikolaus
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Re: [PATCH v6 07/12] ARM: DTS: omap5: add sgx gpu child node
Hi Krzysztof,
> Am 15.04.2020 um 13:38 schrieb Krzysztof Kozlowski :
>
> On Wed, 15 Apr 2020 at 10:36, H. Nikolaus Schaller wrote:
>>
>> and add interrupt.
>>
>> Tested-by: H. Nikolaus Schaller # Pyra-Handheld.
>
> Don't add your own Tested-by tags. These are implied by authorship,
> otherwise all patches people make should have such tag.
Ok I see. AFAIR it originates in several phases of editing to report on which
device it was tested.
Is there a canonical way of writing "tested-on: ${HARDWARE}"?
E.g. would this be ok?
Signed-off: H. Nikolaus Schaller # tested on Pyra-Handheld
BR and thanks,
Nikolaus Schaller
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[PATCH v6 05/12] ARM: DTS: omap36xx: add sgx gpu child node
and add interrupt.
Tested-by: H. Nikolaus Schaller # GTA04, BeagleBoard XM
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap36xx.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 71f3c8f1f924..b308dbb3b1bb 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -211,10 +211,11 @@ sgx_module: target-module@5000 {
#size-cells = <1>;
ranges = <0 0x5000 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap3-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x0 0x1>;/* 64kB */
+ interrupts = <21>;
+ };
};
};
--
2.25.1
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[PATCH v6 09/12] ARM: dts: sun6i: a31: add sgx gpu child node
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo available.
The currently used binding that is used during development is more
complete and was already verifyed by loading the kernelmodule successful.
Signed-off-by: Philipp Rossak
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index f3425a66fc0a..933a825bf460 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1417,5 +1417,16 @@ p2wi: i2c@1f03400 {
#address-cells = <1>;
#size-cells = <0>;
};
+
+ gpu: gpu@1c40 {
+ compatible = "allwinner,sun8i-a31-sgx544-115",
+"img,sgx544-115", "img,sgx544";
+ reg = <0x01c4 0x1>;
+ /*
+* This node is currently a placeholder for the gpu.
+* This will be completed when a full demonstration
+* of the openpvrsgx driver is available for this board.
+*/
+ };
};
};
--
2.25.1
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Re: [PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
> Am 15.04.2020 um 12:12 schrieb Maxime Ripard : > > Hi, > > On Wed, Apr 15, 2020 at 10:35:08AM +0200, H. Nikolaus Schaller wrote: >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers, interrupt etc.). >> >> In most cases, Clock, Reset and power management is handled >> by a parent node or elsewhere (e.g. code in the driver). > > Wouldn't the "code in the driver" still require the clock / reset / > power domain to be set in the DT? Well, some SoC seem to use existing clocks and have no reset. Or, although not recommended, they may have the io-address range hard-coded. BR, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
The Imagination PVR/SGX GPU is part of several SoC from
multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
Allwinner A83 and others.
With this binding, we describe how the SGX processor is
interfaced to the SoC (registers, interrupt etc.).
In most cases, Clock, Reset and power management is handled
by a parent node or elsewhere (e.g. code in the driver).
Tested by make dt_binding_check dtbs_check
Signed-off-by: H. Nikolaus Schaller
---
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 122 ++
1 file changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
new file mode 100644
index ..e3a4208dfab1
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |+
+ This binding describes the Imagination SGX5 series of 3D accelerators which
+ are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
+ Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+ For an extensive list see:
https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+ The SGX node is usually a child node of some DT node belonging to the SoC
+ which handles clocks, reset and general address space mapping of the SGX
+ register area.
+
+properties:
+ compatible:
+oneOf:
+ - description: SGX530-121 based SoC
+items:
+ - enum:
+- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and
similar
+ - const: img,sgx530-121
+ - const: img,sgx530
+
+ - description: SGX530-125 based SoC
+items:
+ - enum:
+- ti,am3352-sgx530-125 # BeagleBone Black
+- ti,am3517-sgx530-125
+- ti,am4-sgx530-125
+- ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz
and similar
+- ti,ti81xx-sgx530-125
+ - const: ti,omap3-sgx530-125
+ - const: img,sgx530-125
+ - const: img,sgx530
+
+ - description: SGX535-116 based SoC
+items:
+ - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+ - const: img,sgx535-116
+ - const: img,sgx535
+
+ - description: SGX540-116 based SoC
+items:
+ - const: intel,medfield-gma-sgx540 # Atom Z24xx
+ - const: img,sgx540-116
+ - const: img,sgx540
+
+ - description: SGX540-120 based SoC
+items:
+ - enum:
+- samsung,s5pv210-sgx540-120
+- ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+ - const: img,sgx540-120
+ - const: img,sgx540
+
+ - description: SGX540-130 based SoC
+items:
+ - enum:
+- ingenic,jz4780-sgx540-130 # CI20
+ - const: img,sgx540-130
+ - const: img,sgx540
+
+ - description: SGX544-112 based SoC
+items:
+ - const: "ti,omap4470-sgx544-112
+ - const: img,sgx544-112
+ - const: img,sgx544
+
+ - description: SGX544-115 based SoC
+items:
+ - enum:
+- allwinner,sun8i-a31-sgx544-115
+- allwinner,sun8i-a31s-sgx544-115
+- allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T)
and similar
+ - const: img,sgx544-115
+ - const: img,sgx544
+
+ - description: SGX544-116 based SoC
+items:
+ - enum:
+- ti,dra7-sgx544-116 # DRA7
+- ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
+ - const: img,sgx544-116
+ - const: img,sgx544
+
+ - description: SGX545 based SoC
+items:
+ - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+ - const: img,sgx545-116
+ - const: img,sgx545
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |+
+#include
+
+gpu: gpu@fe00 {
+ compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
+ reg = <0xfe00 0x200>;
+ interrupts = ;
+};
+
+...
--
2.25.1
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[PATCH v6 11/12] ARM: dts: sun8i: a83t: add sgx gpu child node
From: Philipp Rossak
We are adding the devicetree binding for the PVR-SGX-544-115 gpu.
This driver is currently under development in the openpvrsgx-devgroup.
Right now the full binding is not figured out, so we provide here a
placeholder. It will be completed as soon as there is a demo available.
The currently used binding that is used during development is more
complete and was already verifyed by loading the kernelmodule successful.
Signed-off-by: Philipp Rossak
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 655404d6d3a3..bfb900622bf6 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1192,6 +1192,17 @@ ths: thermal-sensor@1f04000 {
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
+
+ gpu: gpu@1c40 {
+ compatible = "allwinner,sun8i-a83t-sgx544-115",
+"img,sgx544-115", "img,sgx544";
+ reg = <0x01c4 0x1>;
+ /*
+* This node is currently a placeholder for the gpu.
+* This will be completed when a full demonstration
+* of the openpvrsgx driver is available for this board.
+*/
+ };
};
thermal-zones {
--
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[PATCH v6 07/12] ARM: DTS: omap5: add sgx gpu child node
and add interrupt.
Tested-by: H. Nikolaus Schaller # Pyra-Handheld.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap5.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 2ac7f021c284..1cf41664fd00 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -270,7 +270,7 @@ sata: sata@4a141100 {
ports-implemented = <0x1>;
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -287,10 +287,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap5-sgx544-116",
"img,sgx544-116", "img,sgx544";
+ reg = <0x0 0x1>;
+ interrupts = ;
+ };
};
target-module@5800 {
--
2.25.1
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Re: [PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Neil, > Am 15.04.2020 um 14:54 schrieb Neil Armstrong : > > Hi, > > On 15/04/2020 14:43, H. Nikolaus Schaller wrote: >> >>> Am 15.04.2020 um 12:12 schrieb Maxime Ripard : >>> >>> Hi, >>> >>> On Wed, Apr 15, 2020 at 10:35:08AM +0200, H. Nikolaus Schaller wrote: >>>> The Imagination PVR/SGX GPU is part of several SoC from >>>> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >>>> Allwinner A83 and others. >>>> >>>> With this binding, we describe how the SGX processor is >>>> interfaced to the SoC (registers, interrupt etc.). >>>> >>>> In most cases, Clock, Reset and power management is handled >>>> by a parent node or elsewhere (e.g. code in the driver). >>> >>> Wouldn't the "code in the driver" still require the clock / reset / >>> power domain to be set in the DT? >> >> Well, some SoC seem to use existing clocks and have no reset. >> Or, although not recommended, they may have the io-address range >> hard-coded. > > The possible clocks and resets should be added, even if optional. > > Please look at the arm utgard, midgard and bifrost bindings. Interesting to compare to. Maybe we should also add the $nodename: pattern: '^gpu@[a-f0-9]+$' But the sgx binding is difficult to grasp here. Some SoC like the omap series have their own ti,sysc based target modules and the gpu nodes is a child of it lacking any clock and reset references for purpose. The jz4780 and some other need a clocks definition, but no reset. Having a reset seems to be an option for the SoC designer and not mandated by img. So is it part of the pvrsgx bindings or the SoC? Well we could add clocks and resets as optional but that would allow to wrongly define omap. Or delegate them to a parent "simple-pm-bus" node. I have to study that material more to understand what you seem to expect. BR and thanks, Nikolaus Schaller ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 03/12] ARM: DTS: am3517: add sgx gpu child node
and add interrupt.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am3517.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index e0b5a00e2078..3fce56a646d1 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -138,10 +138,11 @@ sgx_module: target-module@5000 {
#size-cells = <1>;
ranges = <0 0x5000 0x4000>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,am3517-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x0 0x4000>;
+ interrupts = <21>;
+ };
};
};
};
--
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[PATCH v6 04/12] ARM: DTS: omap34xx: add sgx gpu child node
and add interrupt.
According to omap3530 TRM the SGX register block is 64kB.
See: 13.4 SGX Register Mapping, Table 13-2
Reported-by: Andrew F. Davis # register size
Tested-by: H. Nikolaus Schaller # OpenPandora 600 MHz.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap34xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index c4dd9801840d..51c60ee2b68d 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -167,12 +167,13 @@ sgx_module: target-module@5000 {
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x5000 0x4000>;
+ ranges = <0 0x5000 0x1>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap3-sgx530-121",
"img,sgx530-121", "img,sgx530";
+ reg = <0x0 0x1>;/* 64kB */
+ interrupts = <21>;
+ };
};
};
--
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Re: [PATCH v6 01/12] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
Hi Maxime,
> Am 15.04.2020 um 18:21 schrieb Maxime Ripard :
>
> On Wed, Apr 15, 2020 at 05:09:45PM +0200, H. Nikolaus Schaller wrote:
>> Hi Maxime,
>>
>> Hm. Yes. We know that there likely are clocks and maybe reset
>> but for some SoC this seems to be undocumented and the reset
>> line the VHDL of the sgx gpu provides may be permanently tied
>> to "inactive".
>>
>> So if clocks are optional and not provided, a driver simply can assume
>> they are enabled somewhere else and does not have to care about. If
>> they are specified, the driver can enable/disable them.
>
> Except that at the hardware level, the clock is always going to be
> there. You can't control it, but it's there.
Sure, we can deduce that from general hardware design knowledge.
But not every detail must be described in DT. Only the important
ones.
>
>>> If OMAP is too much of a pain, you can also make
>>> a separate binding for it, and a generic one for the rest of us.
>>
>> No, omap isn't any pain at all.
>>
>> The pain is that some other SoC are most easily defined by clocks in
>> the gpu node which the omap doesn't need to explicitly specify.
>>
>> I would expect a much bigger nightmare if we split this into two
>> bindings variants.
>>
>>> I'd say that it's pretty unlikely that the clocks, interrupts (and
>>> even regulators) are optional. It might be fixed on some SoCs, but
>>> that's up to the DT to express that using fixed clocks / regulators,
>>> not the GPU binding itself.
>>
>> omap already has these defined them not to be part of the GPU binding.
>> The reason seems to be that this needs special clock gating control
>> especially for idle states which is beyond simple clock-enable.
>>
>> This sysc target-module@5600 node is already merged and therefore
>> we are only adding the gpu child node. Without defining clocks.
>>
>> For example:
>>
>> sgx_module: target-module@5600 {
>> compatible = "ti,sysc-omap4", "ti,sysc";
>> reg = <0x5600fe00 0x4>,
>><0x5600fe10 0x4>;
>> reg-names = "rev", "sysc";
>> ti,sysc-midle = ,
>> ,
>> ;
>> ti,sysc-sidle = ,
>> ,
>> ;
>> clocks = <_clkctrl OMAP5_GPU_CLKCTRL 0>;
>> clock-names = "fck";
>> #address-cells = <1>;
>> #size-cells = <1>;
>> ranges = <0 0x5600 0x200>;
>>
>> gpu: gpu@0 {
>> compatible = "ti,omap5-sgx544-116",
>> "img,sgx544-116", "img,sgx544";
>> reg = <0x0 0x1>;
>> interrupts = ;
>> };
>> };
>>
>> The jz4780 example will like this:
>>
>> gpu: gpu@1304 {
>> compatible = "ingenic,jz4780-sgx540-130", "img,sgx540-130",
>> "img,sgx540";
>> reg = <0x1304 0x4000>;
>>
>> clocks = < JZ4780_CLK_GPU>;
>> clock-names = "gpu";
>>
>> interrupt-parent = <>;
>> interrupts = <63>;
>> };
>>
>> So the question is which one is "generic for the rest of us"?
>
> I'd say the latter.
Why?
TI SoC seem to be the broadest number of available users
of sgx5xx in the past and nowadays. Others are more the exception.
> If your clock is optional, then you define it but don't mandate
> it. Not documenting it will only result in a mess where everyone will
> put some clock into it, possibly with different semantics each and
> every time.
So you mean that we should require a dummy clock for the omap gpu node
or did I misunderstand that?
Well, yes there is of course a clock connection between the
omap target-module and the sgx but it is IMHO pointless to
describe it because it can't and does not need to be controlled
separately.
As said the target-module is already accepted and upstream and my
proposal is to get the gpu node described there. There is simply
no need for a clocks node for the omap.
What I also assume is that developers of DTS know
Re: DRM interaction problems on Ingenic CI20 / jz4780 with dw-hdmi and ingenic-drm
> Am 13.04.2020 um 13:25 schrieb Paul Cercueil : > > Hi Nikolaus, > > > Le sam. 11 avril 2020 à 16:14, H. Nikolaus Schaller a > écrit : >> Hi, >> we (Paul Boddie and me) are working to get HDMI functional on the >> Ingenic CI20 board with jz4780 SoC which uses a specialization of >> the dw-hdmi driver. >> So far we have identified two issues. >> The first is that HPD interrupts are not properly processed. >> drm_helper_hpd_irq_event() is called by HPD events but >> dev->mode_config.poll_enabled is false. >> Therefore the interrupt is ignored and nothing happens. >> Now I wonder about the logic behind checking for poll_enabled. >> I understand that a driver can do either polling or irq or both. >> Therefore handling the irq_event shouldn't be disabled by poll_enabled >> being false. Otherwise we can only do: nothing, polling, polling+irq >> but not irq alone. >> The jz4780 hdmi subsystem (drm/bridge/dw-hdmi.c) uses >> connector->polled = DRM_CONNECTOR_POLL_HPD; >> but shouldn't this enable polling? Note that there seems to be >> no (direct) call to drm_kms_helper_poll_init(). >> If we set dev->mode_config.poll_enabled = true in >> drm_helper_hpd_irq_event() things start to work. >> Please can you clarify what would be best practise here to >> get HPD event handling working. >> The other issue is in dw-hdmi.c: >> We found out that ingenic_drm_encoder_atomic_check() fails because >> info->num_bus_formats == 0 >> and not 1. This blocks further initialization. >> The reason seems to be that dw_hdmi_bridge_attach() does not call >> drm_display_info_set_bus_formats() with a proper format like >> other drivers (e.g. drm/bridge/ti-tfp410.c) are doing. >> We have patched to set a single bus format MEDIA_BUS_FMT_RGB888_1X24 >> and then DRM setup seems to work (although we still have no valid >> HDMI signal but that is likely something else). >> Please can you explain how setting the bus format should be fixed >> in dw-hdmi.c. >> If these questions should be forwarded to other specialists, please >> do so. > > It should be sent to the DRI mailing list, you missed the most important one. Ah, ok. > > -Paul > >> BR and thanks, >> Nikolaus Schaller ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 1/8] dt-bindings: add img, pvrsgx.yaml for Imagination GPUs
> Am 29.03.2020 um 19:38 schrieb H. Nikolaus Schaller :
>
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
> Allwinner A83 and others.
>
> With this binding, we describe how the SGX processor is
> interfaced to the SoC (registers, interrupt etc.).
>
> In most cases, Clock, Reset and power management is handled
> by a parent node or elsewhere (e.g. code in the driver).
>
> Tested by make dt_binding_check dtbs_check
>
> Signed-off-by: H. Nikolaus Schaller
> ---
> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 109 ++
> 1 file changed, 109 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> new file mode 100644
> index ..aadfb2d9b012
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Imagination PVR/SGX GPU
> +
> +maintainers:
> + - H. Nikolaus Schaller
> +
> +description: |+
> + This binding describes the Imagination SGX5 series of 3D accelerators which
> + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
> + Allwinner A83, and Intel Poulsbo and CedarView and more.
> +
> + For an extensive list see:
> https://en.wikipedia.org/wiki/PowerVR#Implementations
> +
> + The SGX node is usually a child node of some DT node belonging to the SoC
> + which handles clocks, reset and general address space mapping of the SGX
> + register area.
> +
> +properties:
> + compatible:
> +oneOf:
> + - description: SGX530-121 based SoC
> +items:
> + - enum:
> +- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz
> and similar
> + - const: img,sgx530-121
> + - const: img,sgx530
> +
> + - description: SGX530-125 based SoC
> +items:
> + - enum:
> +- ti,am3352-sgx530-125 # BeagleBone Black
> +- ti,am3517-sgx530-125
> +- ti,am4-sgx530-125
> +- ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz
> and similar
> +- ti,ti81xx-sgx530-125
> + - const: ti,omap3-sgx530-125
> + - const: img,sgx530-125
> + - const: img,sgx530
> +
> + - description: SGX535-116 based SoC
> +items:
> + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
> + - const: img,sgx535-116
> + - const: img,sgx535
> +
> + - description: SGX540-116 based SoC
> +items:
> + - const: intel,medfield-gma-sgx540 # Atom Z24xx
> + - const: img,sgx540-116
> + - const: img,sgx540
> +
> + - description: SGX540-120 based SoC
> +items:
> + - enum:
> +- ingenic,jz4780-sgx540-120 # CI20
> +- ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
> + - const: img,sgx540-120
> + - const: img,sgx540
> +
> + - description: SGX544-112 based SoC
> +items:
> + - const: ti,omap4-sgx544-112
> + - const: img,sgx544-112
> + - const: img,sgx544
> +
> + - description: SGX544-116 based SoC
> +items:
> + - enum:
> +- allwinner,sun8i-a83t-sgx544-116 # Banana-Pi-M3 (Allwinner
> A83T) and similar
Philipp Rossak reported on a different list [1] that the a83t tells to have a
sgx544-115 inside.
So it needs a separate entry.
[1]:
http://lists.goldelico.com/pipermail/openpvrsgx-devgroup/2020-April/000263.html
> +- ti,dra7-sgx544-116 # DRA7
> +- ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
> + - const: img,sgx544-116
> + - const: img,sgx544
> +
> + - description: SGX545-116 based SoC
> +items:
> + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
> + - const: img,sgx545-116
> + - const: img,sgx545
> +
> + reg:
> +maxItems: 1
> +
> + interrupts:
> +maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |+
> +#include
> +
> +gpu: gpu@fe00 {
> + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
> + reg = <0xfe00 0x200>;
> + interrupts = ;
> +};
> +
> +...
> --
> 2.25.1
>
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Re: [RFC v3 1/8] dt-bindings: display: convert ingenic, lcd.txt to ingenic, lcd.yaml
Hi Paul, > Am 30.03.2020 um 17:42 schrieb Rob Herring : > > On Sun, 29 Mar 2020 19:35:47 +0200, "H. Nikolaus Schaller" wrote: >> and add compatible: jz4780-lcd, including an example how to >> configure both lcd controllers. >> >> Also fix the clock names and examples. >> >> Based on work by Paul Cercueil and >> Sam Ravnborg >> >> Signed-off-by: H. Nikolaus Schaller >> Cc: Rob Herring >> Cc: devicet...@vger.kernel.org >> --- >> .../bindings/display/ingenic,lcd.txt | 45 -- >> .../bindings/display/ingenic,lcd.yaml | 128 ++ >> 2 files changed, 128 insertions(+), 45 deletions(-) >> delete mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.txt >> create mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.yaml >> > > My bot found errors running 'make dt_binding_check' on your patch: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/ingenic,lcd.example.dt.yaml: > lcd-controller@1305: clocks: [[4294967295, 9]] is too short > > See https://patchwork.ozlabs.org/patch/1263508 If I read the message correctly, I think there should be 2 clocks specified in the jz4725b-lcd example and not just clocks = < JZ4725B_CLK_LCD>; Unfortunately the jz4725b.dtsi does not seem to be upstream or in linux-next so I don't know if it works without lcd_pclk or not. If there is really just one clock, we need to modify the clocks and clock-names schema and add minItems: 1 and maxItems: 2 to allow for this flexibility. Otherwise we have to fix the example. Do you have some git with an up-to-date jz4725b.dtsi to look at? > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master > --upgrade +++ :) > > Please check and re-submit. Sure, since it is a RFC. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC v3 5/8] drm: ingenic: add jz4780 Synopsys HDMI driver
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/Kconfig | 8 ++
drivers/gpu/drm/ingenic/Makefile | 1 +
drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c | 120 +++
3 files changed, 129 insertions(+)
create mode 100644 drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig
index d82c3d37ec9c..44bfd0d35af1 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu/drm/ingenic/Kconfig
@@ -14,3 +14,11 @@ config DRM_INGENIC
Choose this option for DRM support for the Ingenic SoCs.
If M is selected the module will be called ingenic-drm.
+
+config DRM_DW_HDMI_JZ4780
+ tristate "HDMI Support for Ingenic JZ4780"
+ depends on DRM_INGENIC
+ depends on OF
+ select DRM_DW_HDMI
+ help
+ Choose this option for HDMI output from the Ingenic JZ4780.
diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile
index 11cac42ce0bb..238383de63c7 100644
--- a/drivers/gpu/drm/ingenic/Makefile
+++ b/drivers/gpu/drm/ingenic/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
+obj-$(CONFIG_DRM_DW_HDMI_JZ4780) += dw_hdmi-jz4780.o
diff --git a/drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
b/drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
new file mode 100644
index ..fa379e337263
--- /dev/null
+++ b/drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019 Paul Boddie
+ *
+ * Derived from dw_hdmi-imx.c with i.MX portions removed.
+ * Probe and remove operations derived from rcar_dw_hdmi.c.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+static const struct dw_hdmi_mpll_config jz4780_mpll_cfg[] = {
+ { 4525, { { 0x01e0, 0x },
+ { 0x21e1, 0x },
+ { 0x41e2, 0x } } },
+ { 9250, { { 0x0140, 0x0005 },
+ { 0x2141, 0x0005 },
+ { 0x4142, 0x0005 } } },
+ { 14850, { { 0x00a0, 0x000a },
+ { 0x20a1, 0x000a },
+ { 0x40a2, 0x000a } } },
+ { 21600, { { 0x00a0, 0x000a },
+ { 0x2001, 0x000f },
+ { 0x4002, 0x000f } } },
+ { ~0UL, { { 0x, 0x },
+ { 0x, 0x },
+ { 0x, 0x } } }
+};
+
+static const struct dw_hdmi_curr_ctrl jz4780_cur_ctr[] = {
+ /*pixelclk bpp8bpp10 bpp12 */
+ { 5400, { 0x091c, 0x091c, 0x06dc } },
+ { 5840, { 0x091c, 0x06dc, 0x06dc } },
+ { 7200, { 0x06dc, 0x06dc, 0x091c } },
+ { 7425, { 0x06dc, 0x0b5c, 0x091c } },
+ { 11880, { 0x091c, 0x091c, 0x06dc } },
+ { 21600, { 0x06dc, 0x0b5c, 0x091c } },
+ { ~0UL, { 0x, 0x, 0x } },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config jz4780_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 21600, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x, 0x, 0x}
+};
+
+static enum drm_mode_status
+jz4780_hdmi_mode_valid(struct drm_connector *con,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct dw_hdmi_plat_data jz4780_dw_hdmi_plat_data = {
+ .mpll_cfg = jz4780_mpll_cfg,
+ .cur_ctr= jz4780_cur_ctr,
+ .phy_config = jz4780_phy_config,
+ .mode_valid = jz4780_hdmi_mode_valid,
+};
+
+static const struct of_device_id jz4780_dw_hdmi_dt_ids[] = {
+ { .compatible = "ingenic,jz4780-dw-hdmi" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_dw_hdmi_dt_ids);
+
+static int jz4780_dw_hdmi_probe(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi;
+
+ hdmi = dw_hdmi_probe(pdev, _dw_hdmi_plat_data);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
+
+ platform_set_drvdata(pdev, hdmi);
+
+ return 0;
+}
+
+static int jz4780_dw_hdmi_remove(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
+
+ dw_hdmi_remove(hdmi);
+
+ return 0;
+}
+
+static struct platform_driver jz4780_dw_hdmi_platform_driver = {
+ .probe = jz4780_dw_hdmi_probe,
+ .remove = jz4780_dw_hdmi_remove,
+ .driver = {
[PATCH v5 8/8] MIPS: DTS: jz4780: add sgx gpu node
and add interrupt and clocks.
Tested to build for CI20 board and load a driver.
Setup can not yet be tested since there is no working
HDMI driver for jz4780.
Suggested-by: Paul Boddie
Tested-by: H. Nikolaus Schaller # CI20.
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index bb89653d16a3..618e48c78a87 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -357,6 +357,17 @@ i2c4: i2c@10054000 {
status = "disabled";
};
+ gpu: gpu@1304 {
+ compatible = "ingenic,jz4780-sgx540-120", "img,sgx540-120",
"img,sgx540";
+ reg = <0x1304 0x4000>;
+
+ clocks = < JZ4780_CLK_GPU>;
+ clock-names = "gpu";
+
+ interrupt-parent = <>;
+ interrupts = <63>;
+ };
+
nemc: nemc@1341 {
compatible = "ingenic,jz4780-nemc";
reg = <0x1341 0x1>;
--
2.25.1
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[PATCH v5 4/8] ARM: DTS: omap34xx: add sgx gpu child node
and add interrupt.
According to omap3530 TRM the SGX register block is 64kB.
See: 13.4 SGX Register Mapping, Table 13-2
Reported-by: Andrew F. Davis # register size
Tested-by: H. Nikolaus Schaller # OpenPandora 600 MHz.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap34xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index c4dd9801840d..51c60ee2b68d 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -167,12 +167,13 @@ sgx_module: target-module@5000 {
clock-names = "fck", "ick";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x5000 0x4000>;
+ ranges = <0 0x5000 0x1>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap3-sgx530-121",
"img,sgx530-121", "img,sgx530";
+ reg = <0x0 0x1>;/* 64kB */
+ interrupts = <21>;
+ };
};
};
--
2.25.1
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[PATCH v5 7/8] ARM: DTS: omap5: add sgx gpu child node
and add interrupt.
Tested-by: H. Nikolaus Schaller # Pyra-Handheld.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap5.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index d0ecf54d5a23..4c7c4ca0bd87 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -269,7 +269,7 @@ sata: sata@4a141100 {
ports-implemented = <0x1>;
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -286,10 +286,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap5-sgx544-116",
"img,sgx544-116", "img,sgx544";
+ reg = <0x0 0x1>;
+ interrupts = ;
+ };
};
dss: dss@5800 {
--
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[RFC v3 6/8] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 46 ++
1 file changed, 46 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index bb89653d16a3..73776514bbe5 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -434,4 +434,50 @@ bch: bch@134d {
status = "disabled";
};
+
+ hdmi: hdmi@1018 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x1018 0x8000>;
+ reg-io-width = <4>;
+
+ clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
+ clock-names = "isfr" , "iahb";
+
+ assigned-clocks = < JZ4780_CLK_HDMI>;
+ assigned-clock-rates = <2700>;
+
+ interrupt-parent = <>;
+ interrupts = <3>;
+
+ /* ddc-i2c-bus = <>; */
+
+ status = "disabled";
+ };
+
+ lcdc0: lcdc0@1305 {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x1305 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
+ lcdc1: lcdc1@130a {
+ compatible = "ingenic,jz4780-lcd";
+ reg = <0x130a 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD1PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
+
};
--
2.25.1
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[RFC v3 0/8] MIPS: CI20: add HDMI out support
+++ help is needed: driver is not completely working and shows no output signal on the HDMI data and clock lanes +++ HPD is working and /dev/fb0 does appear +++ but there is no trigger to initialize the lcdc * add definition for second jz4780-lcdc * diverse fixes for yaml schema * make ingenic-drm driver compatible to ingenic,jz4780-lcd * converted existing ingenic,lcd.txt to ingenic,lcd.yaml - suggested by Paul Cercueil * removed blank line before MODULE_DEVICE_TABLE() macro - Paul Cercueil * added some missing Signed-off: * removed Zubair Lutfullah Kakakhel from the recipients list and Cc: since the address is no longer available. * removed "pinctrl: ingenic: add hdmi-ddc pin control group" from this patch series since it is already applied elsewhere (by Linus Walleij ) RFC V2 2020-02-28 19:19:40: * Converted .txt bindings to .yaml (by Sam Ravnborg - big THANKS) RFC V1 2020-02-26 20:13:06: This patch series adds HDMI output to the jz4780/CI20 board. It is based on taking the old 3.18 vendor kernel as well as an earlier submission from 2015: https://lore.kernel.org/patchwork/patch/547872/ and trying to achieve the same with modern DTS setup and new/modified drivers. Unfortunately, in this first RFC, only EDID and creation of /dev/fb0 are working. Also, HDMI hot plugging is detected. But there is no HDMI output signal. So some tiny piece seems to be missing to enable/configure the Synposys HDMI controller. We need help from the community to fix this. Original authors of most patches are * Paul Boddie * Zubair Lutfullah Kakakhel H. Nikolaus Schaller (4): dt-bindings: display: convert ingenic,lcd.txt to ingenic,lcd.yaml drm: ingenic-drm: add MODULE_DEVICE_TABLE drm: ingenic-drm: add support for ingenic,jz4780-lcd MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780 Paul Boddie (3): drm: ingenic: add jz4780 Synopsys HDMI driver MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller MIPS: DTS: CI20: add HDMI setup Sam Ravnborg (1): dt-bindings: display: add ingenic-jz4780-hdmi DT Schema .../bindings/display/ingenic,lcd.txt | 45 -- .../bindings/display/ingenic,lcd.yaml | 128 ++ .../bindings/display/ingenic-jz4780-hdmi.yaml | 82 +++ arch/mips/boot/dts/ingenic/ci20.dts | 64 + arch/mips/boot/dts/ingenic/jz4780.dtsi| 46 +++ arch/mips/configs/ci20_defconfig | 3 + drivers/gpu/drm/ingenic/Kconfig | 8 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c | 120 drivers/gpu/drm/ingenic/ingenic-drm.c | 8 ++ 10 files changed, 460 insertions(+), 45 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.txt create mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.yaml create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml create mode 100644 drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC v3 8/8] MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780
We configure them as loadable modules by default. Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index be41df2a81fb..3f733a555cb2 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -103,6 +103,9 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_JZ4740=y CONFIG_DMADEVICES=y CONFIG_DMA_JZ4780=y +CONFIG_DRM=m +CONFIG_DRM_DW_HDMI_JZ4780=m +CONFIG_DRM_DW_HDMI=m # CONFIG_IOMMU_SUPPORT is not set CONFIG_MEMORY=y CONFIG_EXT4_FS=y -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 1/8] dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
The Imagination PVR/SGX GPU is part of several SoC from
multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
Allwinner A83 and others.
With this binding, we describe how the SGX processor is
interfaced to the SoC (registers, interrupt etc.).
In most cases, Clock, Reset and power management is handled
by a parent node or elsewhere (e.g. code in the driver).
Tested by make dt_binding_check dtbs_check
Signed-off-by: H. Nikolaus Schaller
---
.../devicetree/bindings/gpu/img,pvrsgx.yaml | 109 ++
1 file changed, 109 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
new file mode 100644
index ..aadfb2d9b012
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Imagination PVR/SGX GPU
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |+
+ This binding describes the Imagination SGX5 series of 3D accelerators which
+ are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
+ Allwinner A83, and Intel Poulsbo and CedarView and more.
+
+ For an extensive list see:
https://en.wikipedia.org/wiki/PowerVR#Implementations
+
+ The SGX node is usually a child node of some DT node belonging to the SoC
+ which handles clocks, reset and general address space mapping of the SGX
+ register area.
+
+properties:
+ compatible:
+oneOf:
+ - description: SGX530-121 based SoC
+items:
+ - enum:
+- ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and
similar
+ - const: img,sgx530-121
+ - const: img,sgx530
+
+ - description: SGX530-125 based SoC
+items:
+ - enum:
+- ti,am3352-sgx530-125 # BeagleBone Black
+- ti,am3517-sgx530-125
+- ti,am4-sgx530-125
+- ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz
and similar
+- ti,ti81xx-sgx530-125
+ - const: ti,omap3-sgx530-125
+ - const: img,sgx530-125
+ - const: img,sgx530
+
+ - description: SGX535-116 based SoC
+items:
+ - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
+ - const: img,sgx535-116
+ - const: img,sgx535
+
+ - description: SGX540-116 based SoC
+items:
+ - const: intel,medfield-gma-sgx540 # Atom Z24xx
+ - const: img,sgx540-116
+ - const: img,sgx540
+
+ - description: SGX540-120 based SoC
+items:
+ - enum:
+- ingenic,jz4780-sgx540-120 # CI20
+- ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
+ - const: img,sgx540-120
+ - const: img,sgx540
+
+ - description: SGX544-112 based SoC
+items:
+ - const: ti,omap4-sgx544-112
+ - const: img,sgx544-112
+ - const: img,sgx544
+
+ - description: SGX544-116 based SoC
+items:
+ - enum:
+- allwinner,sun8i-a83t-sgx544-116 # Banana-Pi-M3 (Allwinner A83T)
and similar
+- ti,dra7-sgx544-116 # DRA7
+- ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
+ - const: img,sgx544-116
+ - const: img,sgx544
+
+ - description: SGX545-116 based SoC
+items:
+ - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
+ - const: img,sgx545-116
+ - const: img,sgx545
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |+
+#include
+
+gpu: gpu@fe00 {
+ compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
+ reg = <0xfe00 0x200>;
+ interrupts = ;
+};
+
+...
--
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[RFC v3 2/8] drm: ingenic-drm: add MODULE_DEVICE_TABLE
so that the driver can load by matching the device tree
if compiled as module.
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 6d47ef7b148c..bcba2f024842 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -843,6 +843,7 @@ static const struct of_device_id ingenic_drm_of_match[] = {
{ .compatible = "ingenic,jz4770-lcd", .data = _soc_info },
{ /* sentinel */ },
};
+MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
static struct platform_driver ingenic_drm_driver = {
.driver = {
--
2.25.1
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[RFC v3 7/8] MIPS: DTS: CI20: add HDMI setup
From: Paul Boddie
We need to hook up
* HDMI power regulator
* HDMI connector
* DDC pinmux
* HDMI and LCD endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index c340f947baa0..97e09382ebd7 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -62,6 +62,28 @@ eth0_power: fixedregulator@0 {
enable-active-high;
};
+ hdmi_power: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_hdmi_out>;
+ };
+ };
+ };
+
wlan0_power: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "wlan0_power";
@@ -435,6 +457,12 @@ pins_i2c4: i2c4 {
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we",
"nemc-frd-fwe";
@@ -471,3 +499,39 @@ {
assigned-clocks = < TCU_CLK_TIMER0>, < TCU_CLK_TIMER1>;
assigned-clock-rates = <300>, <300>;
};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_hdmi_ddc>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <_hdmi_in>;
+ };
+ };
+};
--
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[PATCH v5 3/8] ARM: DTS: am3517: add sgx gpu child node
and add interrupt.
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am3517.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index e0b5a00e2078..3fce56a646d1 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -138,10 +138,11 @@ sgx_module: target-module@5000 {
#size-cells = <1>;
ranges = <0 0x5000 0x4000>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,am3517-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x0 0x4000>;
+ interrupts = <21>;
+ };
};
};
};
--
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[PATCH v5 2/8] ARM: DTS: am33xx: add sgx gpu child node
and add interrupt.
Tested-by: H. Nikolaus Schaller # BeagleBone Black
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/am33xx.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 41dcfb37155a..cbdd85a1e4b0 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -497,7 +497,7 @@ aes: aes@0 {
};
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -516,10 +516,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x100>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,am3352-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x00 0x100>; /* 16 MB */
+ interrupts = <37>;
+ };
};
};
};
--
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[RFC v3 3/8] drm: ingenic-drm: add support for ingenic,jz4780-lcd
This adds jz_soc_info and a compatible string for the jz4780
lcd controller.
Note that the jz4780 lcdc is a superset of the jz4740 lcdc
and the additional functions are not used if they stay
uninitialized.
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm/ingenic/ingenic-drm.c
index bcba2f024842..82c28ef1ac02 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -837,10 +837,17 @@ static const struct jz_soc_info jz4770_soc_info = {
.max_height = 720,
};
+static const struct jz_soc_info jz4780_soc_info = {
+ .needs_dev_clk = true,
+ .max_width = 4096,
+ .max_height = 2048,
+};
+
static const struct of_device_id ingenic_drm_of_match[] = {
{ .compatible = "ingenic,jz4740-lcd", .data = _soc_info },
{ .compatible = "ingenic,jz4725b-lcd", .data = _soc_info },
{ .compatible = "ingenic,jz4770-lcd", .data = _soc_info },
+ { .compatible = "ingenic,jz4780-lcd", .data = _soc_info },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
--
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[RFC v3 1/8] dt-bindings: display: convert ingenic, lcd.txt to ingenic, lcd.yaml
and add compatible: jz4780-lcd, including an example how to
configure both lcd controllers.
Also fix the clock names and examples.
Based on work by Paul Cercueil and
Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../bindings/display/ingenic,lcd.txt | 45 --
.../bindings/display/ingenic,lcd.yaml | 128 ++
2 files changed, 128 insertions(+), 45 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.txt
create mode 100644 Documentation/devicetree/bindings/display/ingenic,lcd.yaml
diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.txt
b/Documentation/devicetree/bindings/display/ingenic,lcd.txt
deleted file mode 100644
index 01e3261defb6..
--- a/Documentation/devicetree/bindings/display/ingenic,lcd.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Ingenic JZ47xx LCD driver
-
-Required properties:
-- compatible: one of:
- * ingenic,jz4740-lcd
- * ingenic,jz4725b-lcd
- * ingenic,jz4770-lcd
-- reg: LCD registers location and length
-- clocks: LCD pixclock and device clock specifiers.
- The device clock is only required on the JZ4740.
-- clock-names: "lcd_pclk" and "lcd"
-- interrupts: Specifies the interrupt line the LCD controller is connected to.
-
-Example:
-
-panel {
- compatible = "sharp,ls020b1dd01d";
-
- backlight = <>;
- power-supply = <>;
-
- port {
- panel_input: endpoint {
- remote-endpoint = <_output>;
- };
- };
-};
-
-
-lcd: lcd-controller@1305 {
- compatible = "ingenic,jz4725b-lcd";
- reg = <0x1305 0x1000>;
-
- interrupt-parent = <>;
- interrupts = <31>;
-
- clocks = < JZ4725B_CLK_LCD>;
- clock-names = "lcd";
-
- port {
- panel_output: endpoint {
- remote-endpoint = <_input>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/ingenic,lcd.yaml
b/Documentation/devicetree/bindings/display/ingenic,lcd.yaml
new file mode 100644
index ..8b6467cfc191
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ingenic,lcd.yaml
@@ -0,0 +1,128 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic,lcd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 LCD Controller
+
+maintainers:
+ - Paul Cercueil
+
+description: |
+ LCD Controller is the Display Controller for the Ingenic JZ47xx SoC
+
+properties:
+ compatible:
+oneOf:
+ - const: ingenic,jz4725b-lcd
+ - const: ingenic,jz4740-lcd
+ - const: ingenic,jz4770-lcd
+ - const: ingenic,jz4780-lcd
+
+ reg:
+maxItems: 1
+description: LCD registers location and length
+
+ interrupts:
+maxItems: 1
+description: Specifies the interrupt provided by parent
+
+ clocks:
+maxItems: 2
+description: Clock specifiers for LCD pixclock and device clock.
+ The device clock is only required on the JZ4740 and JZ4780
+
+ clock-names:
+items:
+ - const: lcd
+ - const: lcd_pclk
+
+ port:
+type: object
+description: |
+ A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+required:
+- compatible
+- reg
+- interrupts
+- clocks
+- clock-names
+- port
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+panel {
+ compatible = "sharp,ls020b1dd01d";
+
+ backlight = <>;
+ power-supply = <>;
+
+ port {
+panel_input: endpoint {
+ remote-endpoint = <_output>;
+ };
+};
+ };
+
+lcd: lcd-controller@1305 {
+ compatible = "ingenic,jz4725b-lcd";
+ reg = <0x1305 0x1000>;
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ clocks = < JZ4725B_CLK_LCD>;
+ clock-names = "lcd", "lcd_pclk";
+
+ port {
+panel_output: endpoint {
+ remote-endpoint = <_input>;
+ };
+};
+ };
+
+ - |
+#include
+
+lcdc0: lcdc0@1305 {
+compatible = "ingenic,jz4780-lcd";
+reg = <0x1305 0x1800>;
+
+clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+clock-names = "lcd", "lcd_pclk";
+
+interrupt-parent = <>;
+interrupts = <31>;
+
+jz4780_lcd_out: port {
+#address-cells = <1>;
+#size-cells = <0>;
+
+jz4780_out_hdmi: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_in_lcd>;
+
[PATCH v5 0/8] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more)
* reworked YAML bindings to pass dt_binding_check and be better grouped * rename all nodes to "gpu: gpu@" * removed "img,sgx5" from example - suggested by Rob Herring PATCH V4 2019-12-17 19:02:11: * MIPS: DTS: jz4780: removed "img,sgx5" from bindings * YAML bindings: updated according to suggestions by Rob Herring * MIPS: DTS: jz4780: insert-sorted gpu node by register address - suggested by Paul Cercueil PATCH V3 2019-11-24 12:40:33: * reworked YAML format with help by Rob Herring * removed .txt binding document * change compatible "ti,am335x-sgx" to "ti,am3352-sgx" - suggested by Tony Lindgren PATCH V2 2019-11-07 12:06:17: * tried to convert bindings to YAML format - suggested by Rob Herring * added JZ4780 DTS node (proven to load the driver) * removed timer and img,cores properties until we know we really need them - suggested by Rob Herring PATCH V1 2019-10-18 20:46:35: This patch series defines child nodes for the SGX5xx interface inside different SoC so that a driver can be found and probed by the compatible strings and can retrieve information about the SGX revision that is included in a specific SoC. It also defines the interrupt number to be used by the SGX driver. There is currently no mainline driver for these GPUs, but a project [1] is ongoing with the goal to get the open-source part as provided by TI/IMG and others into drivers/gpu/drm/pvrsgx. The kernel modules built from this project have successfully demonstrated to work with the DTS definitions from this patch set on AM335x BeagleBone Black, DM3730 and OMAP5 Pyra and Droid 4. They partially work on OMAP3530 and PandaBoard ES but that is likely a problem in the kernel driver or the (non-free) user-space libraries and binaries. Wotk for JZ4780 (CI20 board) is in progress and there is potential to extend this work to e.g. BananaPi-M3 (A83) and some Intel Poulsbo and CedarView devices. [1]: https://github.com/openpvrsgx-devgroup H. Nikolaus Schaller (8): dt-bindings: add img,pvrsgx.yaml for Imagination GPUs ARM: DTS: am33xx: add sgx gpu child node ARM: DTS: am3517: add sgx gpu child node ARM: DTS: omap34xx: add sgx gpu child node ARM: DTS: omap36xx: add sgx gpu child node ARM: DTS: omap4: add sgx gpu child node ARM: DTS: omap5: add sgx gpu child node MIPS: DTS: jz4780: add sgx gpu node .../devicetree/bindings/gpu/img,pvrsgx.yaml | 109 ++ arch/arm/boot/dts/am33xx.dtsi | 11 +- arch/arm/boot/dts/am3517.dtsi | 9 +- arch/arm/boot/dts/omap34xx.dtsi | 11 +- arch/arm/boot/dts/omap36xx.dtsi | 9 +- arch/arm/boot/dts/omap4.dtsi | 11 +- arch/arm/boot/dts/omap4470.dts| 15 +++ arch/arm/boot/dts/omap5.dtsi | 11 +- arch/mips/boot/dts/ingenic/jz4780.dtsi| 11 ++ 9 files changed, 169 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml create mode 100644 arch/arm/boot/dts/omap4470.dts -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC v3 4/8] dt-bindings: display: add ingenic-jz4780-hdmi DT Schema
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
Signed-off-by: Sam Ravnborg
Signed-off-by: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../bindings/display/ingenic-jz4780-hdmi.yaml | 82 +++
1 file changed, 82 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
new file mode 100644
index ..a545ff8704eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic-jz4780-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 HDMI Transmitter
+
+maintainers:
+ - H. Nikolaus Schaller
+
+description: |
+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
+ TX controller IP with accompanying PHY IP.
+
+allOf:
+ - $ref: panel/panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: ingenic,jz4780-hdmi
+
+ reg:
+maxItems: 1
+description: the address & size of the LCD controller registers
+
+ reg-io-width:
+const: 4
+
+ interrupts:
+maxItems: 1
+description: Specifies the interrupt provided by parent
+
+ clocks:
+maxItems: 2
+description: Clock specifiers for isrf and iahb clocks
+
+ clock-names:
+items:
+ - const: isfr
+ - const: iahb
+
+ ddc-i2c-bus: true
+ ports: true
+
+required:
+- compatible
+- clocks
+- clock-names
+- ports
+- reg-io-width
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+hdmi: hdmi@1018 {
+compatible = "ingenic,jz4780-hdmi";
+reg = <0x1018 0x8000>;
+reg-io-width = <4>;
+ddc-i2c-bus = <>;
+interrupt-parent = <>;
+interrupts = <3>;
+clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
+clock-names = "isfr", "iahb";
+
+ports {
+hdmi_in: port {
+#address-cells = <1>;
+#size-cells = <0>;
+hdmi_in_lcd: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_out_hdmi>;
+};
+};
+};
+};
+
+...
--
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[PATCH v5 6/8] ARM: DTS: omap4: add sgx gpu child node
and add interrupt.
Since omap4420/30/60 and omap4470 come with different SGX variants
we need to introduce a new omap4470.dtsi. If an omap4470 board
does not want to use SGX it is no problem to still include
omap4460.dtsi.
Tested-by: H. Nikolaus Schaller # PandaBoard ES
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap4.dtsi | 11 ++-
arch/arm/boot/dts/omap4470.dts | 15 +++
2 files changed, 21 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/omap4470.dts
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 9a87440d0b9d..939061f96523 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -390,7 +390,7 @@ abb_iva: regulator-abb-iva {
status = "disabled";
};
- target-module@5600 {
+ sgx_module: target-module@5600 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
@@ -409,10 +409,11 @@ target-module@5600 {
#size-cells = <1>;
ranges = <0 0x5600 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap4-sgx540-120",
"img,sgx540-120", "img,sgx540";
+ reg = <0x0 0x200>; /* 32MB */
+ interrupts = ;
+ };
};
dss: dss@5800 {
diff --git a/arch/arm/boot/dts/omap4470.dts b/arch/arm/boot/dts/omap4470.dts
new file mode 100644
index ..19b554612401
--- /dev/null
+++ b/arch/arm/boot/dts/omap4470.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for OMAP4470 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#include "omap4460.dtsi"
+
+ {
+ compatible = "img,sgx544-112", "img,sgx544", "ti,omap-omap4-sgx544-112";
+};
--
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[PATCH v5 5/8] ARM: DTS: omap36xx: add sgx gpu child node
and add interrupt.
Tested-by: H. Nikolaus Schaller # GTA04, BeagleBoard XM
Signed-off-by: H. Nikolaus Schaller
---
arch/arm/boot/dts/omap36xx.dtsi | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 71f3c8f1f924..b308dbb3b1bb 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -211,10 +211,11 @@ sgx_module: target-module@5000 {
#size-cells = <1>;
ranges = <0 0x5000 0x200>;
- /*
-* Closed source PowerVR driver, no child device
-* binding or driver in mainline
-*/
+ gpu: gpu@0 {
+ compatible = "ti,omap3-sgx530-125",
"img,sgx530-125", "img,sgx530";
+ reg = <0x0 0x1>;/* 64kB */
+ interrupts = <21>;
+ };
};
};
--
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Re: [RFC v2 6/8] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller
Hi Paul, > Am 11.03.2020 um 14:20 schrieb Paul Cercueil : > > Hi Nikolaus, > > > Le mer., mars 11, 2020 at 13:43, H. Nikolaus Schaller a > écrit : >> Hi Paul, >>> The JZ4780's LCD controller is much newer than the JZ4740 one, so even if >>> it works with the "ingenic,jz4740-lcd" compatible string, you want it as a >>> fallback. >>> So this should be: compatible = "ingenic,jz4780-lcd", "ingenic,jz4740-lcd". >>> That means the YAML should be updated too. >> I have started to look into jz4780 HDMI setup again. >> Well, there is no driver compatible to "ingenic,jz4780-lcd" so far >> and it is questionalbe if we need a different one. >> I think we should rather make the driver also compatible >> than adding a fallback to ingenic,jz4740-lcdto the DTS. >> The reason why this is better even if both LCDC are almost >> compatible is that the jz4780 allows for much bigger displays >> and therefore should have its own jz_soc_info with 4k x 2k >> as maximum. > > Sure, feel free to extend the driver. > >> Next I tried to find out if the LCDC are really compatible. >> Well the jz4780 has two lcdc instances but they are separated >> by the reg addr. Next, there are unique features (like picture in >> picture with alpha blending) but those are probably disabled >> if not programmed from reset state. This may become a reason >> to separate or augment the driver for the jz4780 but at the >> moment we can ignore that. > > Two LCDC instances -> two lcd-controller@... nodes. It's that simple. Indeed :) > > The other features you listed are outside the LCDC, so outside the scope of > this driver. Well, in the description they are mixed but I think we do not have to care about now. > >> There are also subtly different bit definitions and register >> widths (e.g. 24 bit in addition to 16/18 bit modes or more bits >> for the sync position) but it looks as if the ingenic_drm >> driver already handles this. >> Then I tried to read back the registers. Strangely they >> are all 0x. So there is no programming of the >> lcd-controller in our DT setup with HDMI at all! > > How did you read them? I used devmem2 (may be an omap tool I have recompiled for MIPS - it uses /dev/mem). > Do it from the regmap: should be "cat > /sys/kernel/debug/regmap/1305.lcd-controller/registers" (not sure about > the path) Well seems to give the same result: root@letux:~# cat /sys/kernel/debug/regmap/1305.lcd-controller/registers 00: 04: 08: 0c: 10: 14: 18: 1c: 20: 24: 28: 2c: 30: 34: 38: 3c: 40: 44: 48: 4c: 50: 54: 58: 5c: root@letux:~# > >> I also checked that ingenic_drm_probe() is called and >> returns successfully 0. It also reports that a /dev/fb >> has been created: >> [7.908830] ingenic-drm 1305.lcd-controller: fb0: ingenic-drmdrmf >> frame buffer device >> But for example ingenic_drm_encoder_atomic_mode_set() is >> never called which should write some registers of the LCDC. >> I only did see some calls to ingenic_drm_encoder_atomic_check(). >> This of course explains why we have no HDMI signals despite >> proper HPD and a /dev/fb0. Because the LCDC is not being >> programmed. > > It won't be called until the HDMI driver says that the cable is plugged, and > there's a client application (e.g. fbdev emulation) running. So the problem > is most likely within the HDMI driver. Ok! The HDMI subsystem says (with some printk inserted) on cable unplug/replug: root@letux:~# [ 3894.370706] dw_hdmi_update_power [ 3894.373984] dw_hdmi_update_power: hdmi->force=0 [ 3894.378759] dw_hdmi_update_power: hdmi->disabled=0 [ 3894.383756] dw_hdmi_update_power: hdmi->bridge_is_on=1 [ 3894.388947] dw_hdmi_update_power: hdmi->rxsense=1 [ 3894.393831] dw_hdmi_update_power: force=2 [ 3894.397895] dw_hdmi_update_power: hdmi->bridge_is_on=1 [ 3894.403200] dw_hdmi_phy_update_hpd [ 3894.406784] dw_hdmi_update_power [ 3894.410054] dw_hdmi_update_power: hdmi->force=0 [ 3894.414766] dw_hdmi_update_power: hdmi->disabled=0 [ 3894.419611] dw_hdmi_update_power: hdmi->bridge_is_on=1 [ 3894.424928] dw_hdmi_update_power: hdmi->rxsense=1 [ 3894.429699] dw_hdmi_update_power: force=2 [ 3894.433876] dw_hdmi_update_power: hdmi->bridge_is_on=1 [ 3894.439068] dw_hdmi_phy_update_hpd [ 3894.452316] dw_hdmi_update_power [ 3894.455596] dw_hdmi_update_power: hdmi->force=0 [ 3894.460150] dw_hdmi_update_power: hdmi
Re: [RFC v2 6/8] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller
Hi Paul,
> Am 02.03.2020 um 20:27 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
>
> Le ven., févr. 28, 2020 at 19:19, H. Nikolaus Schaller a
> écrit :
>> From: Paul Boddie
>> A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
>> HDMI support. This requires a new driver, plus device tree and configuration
>> modifications.
>> Signed-off-by: Paul Boddie
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 32 ++
>> 1 file changed, 32 insertions(+)
>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> index f928329b034b..391d4e1efd35 100644
>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> @@ -433,4 +433,36 @@
>> status = "disabled";
>> };
>> +
>> +hdmi: hdmi@1018 {
>> +compatible = "ingenic,jz4780-dw-hdmi";
>> +reg = <0x1018 0x8000>;
>> +reg-io-width = <4>;
>> +
>> +clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
>> +clock-names = "isfr" , "iahb";
>> +
>> +assigned-clocks = < JZ4780_CLK_HDMI>;
>> +assigned-clock-rates = <2700>;
>
> I *think* this should go to the board file.
>
>> +
>> +interrupt-parent = <>;
>> +interrupts = <3>;
>> +
>> +/* ddc-i2c-bus = <>; */
>> +
>> +status = "disabled";
>> +};
>> +
>> +lcd: lcd@1305 {
>
> The node name should be 'lcd-controller'.
>
>> +compatible = "ingenic,jz4740-lcd";
>
> The JZ4780's LCD controller is much newer than the JZ4740 one, so even if it
> works with the "ingenic,jz4740-lcd" compatible string, you want it as a
> fallback.
> So this should be: compatible = "ingenic,jz4780-lcd", "ingenic,jz4740-lcd".
>
> That means the YAML should be updated too.
I have started to look into jz4780 HDMI setup again.
Well, there is no driver compatible to "ingenic,jz4780-lcd" so far
and it is questionalbe if we need a different one.
I think we should rather make the driver also compatible
than adding a fallback to ingenic,jz4740-lcdto the DTS.
The reason why this is better even if both LCDC are almost
compatible is that the jz4780 allows for much bigger displays
and therefore should have its own jz_soc_info with 4k x 2k
as maximum.
Next I tried to find out if the LCDC are really compatible.
Well the jz4780 has two lcdc instances but they are separated
by the reg addr. Next, there are unique features (like picture in
picture with alpha blending) but those are probably disabled
if not programmed from reset state. This may become a reason
to separate or augment the driver for the jz4780 but at the
moment we can ignore that.
There are also subtly different bit definitions and register
widths (e.g. 24 bit in addition to 16/18 bit modes or more bits
for the sync position) but it looks as if the ingenic_drm
driver already handles this.
Then I tried to read back the registers. Strangely they
are all 0x. So there is no programming of the
lcd-controller in our DT setup with HDMI at all!
I also checked that ingenic_drm_probe() is called and
returns successfully 0. It also reports that a /dev/fb
has been created:
[7.908830] ingenic-drm 1305.lcd-controller: fb0: ingenic-drmdrmf frame
buffer device
But for example ingenic_drm_encoder_atomic_mode_set() is
never called which should write some registers of the LCDC.
I only did see some calls to ingenic_drm_encoder_atomic_check().
This of course explains why we have no HDMI signals despite
proper HPD and a /dev/fb0. Because the LCDC is not being
programmed.
Any ideas / hints how to check or improve?
BR and thanks,
Nikolaus
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Re: [PATCH 24/33] drm/panel-simple: Fix dotclock for Ortustech COM37H3M
> Am 09.03.2020 um 14:00 schrieb Ville Syrjälä :
>
> On Thu, Mar 05, 2020 at 08:41:43PM +0100, H. Nikolaus Schaller wrote:
>>
>>> Am 03.03.2020 um 16:49 schrieb H. Nikolaus Schaller :
>>>
>>> Hi,
>>>
>>>> Am 03.03.2020 um 16:03 schrieb Ville Syrjälä
>>>> :
>>>>
>>>>> I haven't looked into the driver code, but would it be
>>>>> possible to specify .clock = 0 (or leave it out) to
>>>>> calculate it bottom up? This would avoid such inconsistencies.
>>>>
>>>> I'm going to remove .vrefresh entirely from the struct.
>>>> It'll just be calculated from the other timings as needed.
>>>
>>> Ok!
>>>
>>> Anyways we should fix the panel timings so that it is compatible to
>>> .vrefresh = 60.
>>>
>>> I'll give it a try and let you know.
>>
>> Ok, here is a new parameter set within data sheet limits for both
>> panel variants:
>>
>> static const struct drm_display_mode ortustech_com37h3m_mode = {
>> .clock = 22153,
>> .hdisplay = 480,
>> .hsync_start = 480 + 40,
>> .hsync_end = 480 + 40 + 10,
>> .htotal = 480 + 40 + 10 + 40,
>> .vdisplay = 640,
>> .vsync_start = 640 + 4,
>> .vsync_end = 640 + 4 + 2,
>> .vtotal = 640 + 4 + 2 + 4,
>> .vrefresh = 60,
>> .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
>> };
>>
>> I have tested on our omap3 based board and didn't find an issue
>> so you can insert into your patch.
>
> Migth be better if you send that so we get proper attribution and
> you can explain the change properly in the commit message.
Ok, will do asap.
BR and thanks,
Nikolaus
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[PATCH] drm/panel-simple: Fix dotclock for Ortustech COM37H3M
The currently listed dotclock disagrees with the currently
listed vrefresh rate. Change the dotclock to match the vrefresh.
There are two variants of the COM37H3M panel.
The older one's COM37H3M05DTC data sheet specifies:
MIN TYP MAX
CLK frequencyfCLK -- 22.426.3 MHz (in VGA mode)
VSYNC Frequency fVSYNC 54 60 66 Hz
VSYNC cycle time tv -- 650 -- H
HSYNC frequency fHSYNC -- 39.3-- kHz
HSYNC cycle time th -- 570 -- CLK
The newer one's COM37H3M99DTC data sheet says:
MIN TYP MAX
CLK frequencyfCLK 18 19.827 MHz
VSYNC Frequency fVSYNC 54 60 66 Hz
VSYNC cycle time tv 646 650 700 H
HSYNC frequency fHSYNC --39.050.0 kHz
HSYNC cycle time th 504 508 630 CLK
So we choose a parameter set that lies within the specs
of both variants. We start at .vrefresh = 60,
choose .htotal = 570 and .vtotal = 650 and end up
in a clock of 22.230 MHz.
Reported-by: Ville Syrjala
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/panel/panel-simple.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index e14c14ac62b5..b4cb23d4898d 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2390,15 +2390,15 @@ static const struct panel_desc ontat_yx700wv03 = {
};
static const struct drm_display_mode ortustech_com37h3m_mode = {
- .clock = 22153,
+ .clock = 22230,
.hdisplay = 480,
- .hsync_start = 480 + 8,
- .hsync_end = 480 + 8 + 10,
- .htotal = 480 + 8 + 10 + 10,
+ .hsync_start = 480 + 40,
+ .hsync_end = 480 + 40 + 10,
+ .htotal = 480 + 40 + 10 + 40,
.vdisplay = 640,
.vsync_start = 640 + 4,
- .vsync_end = 640 + 4 + 3,
- .vtotal = 640 + 4 + 3 + 4,
+ .vsync_end = 640 + 4 + 2,
+ .vtotal = 640 + 4 + 2 + 4,
.vrefresh = 60,
.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
};
--
2.23.0
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Re: [PATCH 24/33] drm/panel-simple: Fix dotclock for Ortustech COM37H3M
> Am 03.03.2020 um 16:49 schrieb H. Nikolaus Schaller :
>
> Hi,
>
>> Am 03.03.2020 um 16:03 schrieb Ville Syrjälä :
>>
>>> I haven't looked into the driver code, but would it be
>>> possible to specify .clock = 0 (or leave it out) to
>>> calculate it bottom up? This would avoid such inconsistencies.
>>
>> I'm going to remove .vrefresh entirely from the struct.
>> It'll just be calculated from the other timings as needed.
>
> Ok!
>
> Anyways we should fix the panel timings so that it is compatible to .vrefresh
> = 60.
>
> I'll give it a try and let you know.
Ok, here is a new parameter set within data sheet limits for both
panel variants:
static const struct drm_display_mode ortustech_com37h3m_mode = {
.clock = 22153,
.hdisplay = 480,
.hsync_start = 480 + 40,
.hsync_end = 480 + 40 + 10,
.htotal = 480 + 40 + 10 + 40,
.vdisplay = 640,
.vsync_start = 640 + 4,
.vsync_end = 640 + 4 + 2,
.vtotal = 640 + 4 + 2 + 4,
.vrefresh = 60,
.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
};
I have tested on our omap3 based board and didn't find an issue
so you can insert into your patch.
BR and thanks,
Nikolaus
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Re: [RFC 0/8] MIPS: CI20: add HDMI out support
Hi Rob, > Am 03.03.2020 um 15:58 schrieb Rob Herring : > > On Thu, Feb 27, 2020 at 01:56:56PM +0100, H. Nikolaus Schaller wrote: >> Hi Sam, >> >> >> Or that there will appear good tools soon. E.g. some GUI >> based editor tool would be very helpful so that you don't have >> to fight with the yaml indentation rules. Like there are XML >> and DTD editors. And even HTML is rarely written manually any more. >> >> IMHO such tools should have been developed and in place *before* >> the rule to provide DT schemata is enforced. > > You mean tools like what is discussed here: > > https://www.redhat.com/sysadmin/yaml-tips > > There's also yaml-format in the dtschema repo which will reformat a file > to the desired formatting. It is just a wrapper around ruamel yaml > library. What I dream of is a higher level higher abstraction than a YAML editor because the problems I face are not only YAML syntax but that I don't know what should be where in a scheme file and why. So I'd like to have a Schema editor. I.e. some editor where I can edit a list of properties and can e.g. checkmark "required". And simply type a description into some text field. And the editor knows where to place the keywords -item -enum -oneOf -description etc. when doing a Save operation. Basically what I dream of is more like MarkDown where you write text, titles paragraphs etc. and that gets magically translated into valid HTML. Or even better analogy: OpenOffice where you just write and format your text and one does not have to edit PostScript printer commands. But it is likely to stay a dream. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 24/33] drm/panel-simple: Fix dotclock for Ortustech COM37H3M
Hi, > Am 03.03.2020 um 16:03 schrieb Ville Syrjälä : > >> I haven't looked into the driver code, but would it be >> possible to specify .clock = 0 (or leave it out) to >> calculate it bottom up? This would avoid such inconsistencies. > > I'm going to remove .vrefresh entirely from the struct. > It'll just be calculated from the other timings as needed. Ok! Anyways we should fix the panel timings so that it is compatible to .vrefresh = 60. I'll give it a try and let you know. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC v2 1/8] dt-bindings: display: add ingenic-jz4780-lcd DT Schema
Hi Paul,
> Am 02.03.2020 um 20:10 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
>
> Le ven., févr. 28, 2020 at 19:19, H. Nikolaus Schaller a
> écrit :
>> From: Sam Ravnborg
>> Add DT bindings for the LCD controller on the jz4780 SoC
>> Based on .txt binding from Zubair Lutfullah Kakakhel
>
> If you mean Documentation/devicetree/bindings/display/ingenic,lcd.txt then it
> was written by me.
Ah, ok. We didn't recognise this before. 6 eyes see more than 4...
I just did cherry-pick this old 4.0 patch from 2015 by Zubair
and it created a ingenic-jz4780-lcd.txt:
https://lore.kernel.org/patchwork/patch/547872/
and Sam was so kind to convert it to yaml.
>
>> Signed-off-by: Sam Ravnborg
>> Cc: Zubair Lutfullah Kakakhel
>> Cc: H. Nikolaus Schaller
>> Cc: Rob Herring
>> Cc: devicet...@vger.kernel.org
>> ---
>> .../bindings/display/ingenic-jz4780-lcd.yaml | 78 +++
>> 1 file changed, 78 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> diff --git
>> a/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> b/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> new file mode 100644
>> index ..c71415a3a342
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> @@ -0,0 +1,78 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/ingenic-jz4780-lcd.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Bindings for Ingenic JZ4780 LCD Controller
>> +
>> +maintainers:
>> + - Zubair Lutfullah Kakakhel
>> + - H. Nikolaus Schaller
>
> I'm the author of the driver, please put me here; and remove Zubair, which 1.
> didn't touch the DRM driver at all, and 2. isn't working at ImgTec anymore.
Yes that is true.
> Also, no need to put yourself here, unless you maintain the Ingenic DRM/KMS
> driver.
Agreed. That was suggested by Sam.
>
>> +
>> +description: |
>> + LCD Controller is the Display Controller for the Ingenic JZ4780 SoC
>> +
>> +properties:
>
> You should add a '$nodename' property.
>
>> + compatible:
>> +items:
>> + - const: ingenic,jz4780-lcd
>
> The .txt lists more compatible strings. Please add them all.
>
>> +
>> + reg:
>> +maxItems: 1
>> +description: the address & size of the LCD controller registers
>
> Drop the description here,
>
>> +
>> + interrupts:
>> +maxItems: 1
>> +description: Specifies the interrupt provided by parent
>
> and here.
>
>> +
>> + clocks:
>> +maxItems: 2
>> +description: Clock specifiers for the JZ4780_CLK_TVE
>> JZ4780_CLK_LCD0PIXCLK
>
> Add one 'description:' per item.
>
>> +
>> + clock-names:
>> +items:
>> + - const: lcd_clk
>> + - const: lcd_pixclk
>> +
>> + port:
>> +type: object
>> +description: |
>> + A port node with endpoint definitions as defined in
>> + Documentation/devicetree/bindings/media/video-interfaces.txt
>> +
>> +required:
>> +- compatible
>> +- reg
>> +- interrupts
>> +- clocks
>> +- clock-names
>> +- port
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> +#include
>> +lcd: jz4780-lcdk@0x1305 {
>
> The node name does not comply with the DT spec, it should be 'lcd-controller'.
Ok, I think I'll review all so that it does match/replace
Documentation/devicetree/bindings/display/ingenic,lcd.txt
and no information is lost.
>
> Cheers,
> -Paul
BR and thanks,
Nikolaus
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Re: [RFC v2 6/8] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller
Hi Paul,
> Am 02.03.2020 um 20:27 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
>
> Le ven., févr. 28, 2020 at 19:19, H. Nikolaus Schaller a
> écrit :
>> From: Paul Boddie
>> A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
>> HDMI support. This requires a new driver, plus device tree and configuration
>> modifications.
>> Signed-off-by: Paul Boddie
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 32 ++
>> 1 file changed, 32 insertions(+)
>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> index f928329b034b..391d4e1efd35 100644
>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> @@ -433,4 +433,36 @@
>> status = "disabled";
>> };
>> +
>> +hdmi: hdmi@1018 {
>> +compatible = "ingenic,jz4780-dw-hdmi";
>> +reg = <0x1018 0x8000>;
>> +reg-io-width = <4>;
>> +
>> +clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
>> +clock-names = "isfr" , "iahb";
>> +
>> +assigned-clocks = < JZ4780_CLK_HDMI>;
>> +assigned-clock-rates = <2700>;
>
> I *think* this should go to the board file.
Hm. I am not sure.
Can there be differences in HDMI between different boards so
that it needs to be defined there?
IMHO the HDMI subsystem is completely sitting on the jz4780 SoC
and clocked by the master clock. So boards should only differ in the
ESD protection and mechanical connector...
And status = "ok".
>
>> +
>> +interrupt-parent = <>;
>> +interrupts = <3>;
>> +
>> +/* ddc-i2c-bus = <>; */
>> +
>> +status = "disabled";
>> +};
>> +
>> +lcd: lcd@1305 {
>
> The node name should be 'lcd-controller'.
>
>> +compatible = "ingenic,jz4740-lcd";
>
> The JZ4780's LCD controller is much newer than the JZ4740 one, so even if it
> works with the "ingenic,jz4740-lcd" compatible string, you want it as a
> fallback.
> So this should be: compatible = "ingenic,jz4780-lcd", "ingenic,jz4740-lcd".
Ah, that is an interesting detail.
It could be the reason why the HDMI does not show an output signal yet.
If the jz4740-lcd and jz4780-lcd are not really 100% compatible.
I'll give it try asap.
If it does not help to get output signals, we need community members who
can test (i.e. own an CI20 board) and can help to identify the bug(s).
>
> That means the YAML should be updated too.
Ok.
BR,
Nikolaus
>
> -Paul
>
>> +reg = <0x1305 0x1800>;
>> +
>> +clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
>> +clock-names = "lcd", "lcd_pclk";
>> +
>> +interrupt-parent = <>;
>> +interrupts = <31>;
>> +
>> +status = "disabled";
>> +};
>> };
>> --
>> 2.23.0
>
>
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Re: [RFC v2 3/8] drm: ingenic-drm: add MODULE_DEVICE_TABLE
> Am 02.03.2020 um 20:21 schrieb Paul Cercueil :
>
> Hi Nikolaus,
>
>
> Le ven., févr. 28, 2020 at 19:19, H. Nikolaus Schaller a
> écrit :
>> so that the driver can load by matching the device tree
>> if compiled as module.
>> Signed-off-by: H. Nikolaus Schaller
>> ---
>> drivers/gpu/drm/ingenic/ingenic-drm.c | 2 ++
>> 1 file changed, 2 insertions(+)
>> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
>> b/drivers/gpu/drm/ingenic/ingenic-drm.c
>> index 6d47ef7b148c..d8617096dd8e 100644
>> --- a/drivers/gpu/drm/ingenic/ingenic-drm.c
>> +++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
>> @@ -844,6 +844,8 @@ static const struct of_device_id ingenic_drm_of_match[]
>> = {
>> { /* sentinel */ },
>> };
>> +MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
>
> Please remove the blank line above the MODULE_DEVICE_TABLE() macro.
Ok.
>
> -Paul
>
>> +
>> static struct platform_driver ingenic_drm_driver = {
>> .driver = {
>> .name = "ingenic-drm",
>> --
>> 2.23.0
>
>
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Re: [RFC v2 2/8] dt-bindings: display: add ingenic-jz4780-hdmi DT Schema
> Am 02.03.2020 um 20:19 schrieb Paul Cercueil : > > Hi Nikolaus, > > > Le ven., févr. 28, 2020 at 19:19, H. Nikolaus Schaller a > écrit : >> From: Sam Ravnborg >> Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC. >> Based on .txt binding from Zubair Lutfullah Kakakhel >> Signed-off-by: Sam Ravnborg >> Cc: Zubair Lutfullah Kakakhel >> Cc: H. Nikolaus Schaller >> Cc: Rob Herring >> Cc: devicet...@vger.kernel.org >> --- >> .../bindings/display/ingenic-jz4780-hdmi.yaml | 83 +++ >> 1 file changed, 83 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml >> diff --git >> a/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml >> b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml >> new file mode 100644 >> index ..9b71c427bd69 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml >> @@ -0,0 +1,83 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/ingenic-jz4780-hdmi.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Bindings for Ingenic JZ4780 HDMI Transmitter >> + >> +maintainers: >> + - Zubair Lutfullah Kakakhel >> + - H. Nikolaus Schaller > > Did Zubair write this glue driver? He's been MIA for a while, doesn't work at > ImgTec anymore, and this email doesn't work. He did write the original .txt version of [RFC v1 2/8] and Sam simply added him. > >> + >> +description: | >> + The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI >> 1.4 >> + TX controller IP with accompanying PHY IP. >> + >> +allOf: >> + - $ref: panel/panel-common.yaml# >> + >> +properties: >> + compatible: >> +items: >> + - const: ingenic,jz4780-hdmi >> + >> + reg: >> +maxItems: 1 >> +description: the address & size of the LCD controller registers > > Remove the description here, > >> + >> + reg-io-width: >> +const: 4 >> + >> + interrupts: >> +maxItems: 1 >> +description: Specifies the interrupt provided by parent > > and here. > > The rule is that if there is only one "reg", "interrupts" or "clocks" entry > then a description is not needed as it's pretty obvious what it's for. > >> + >> + clocks: >> +maxItems: 2 >> +description: Clock specifiers for isrf and iahb clocks > > You need two 'description:' like this: > > clocks: > items: > - description: ISRF clock > - description: IAHB clock Ok. BR and thanks, Nikolaus ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 24/33] drm/panel-simple: Fix dotclock for Ortustech COM37H3M
Hi Ville,
> Am 02.03.2020 um 21:34 schrieb Ville Syrjala :
>
> From: Ville Syrjälä
>
> The currently listed dotclock disagrees with the currently
> listed vrefresh rate. Change the dotclock to match the vrefresh.
>
> Someone tell me which (if either) of the dotclock or vreresh is
> correct?
Data sheet of COM37H3M99DTC says:
MIN TYP MAX
CLK frequency fCLK18 19.827 MHz
VSYNC Frequency fVSYNC 54 60 66 Hz
VSYNC cycle time tv 646 650 700 H
HSYNC frequency fHSYNC -- 39.050.0Khz
HSYNC cycle time th 504 508 630 CLK
But data sheet of COM37H3M05DTC says
MIN TYP MAX
CLK frequency fCLK-- 22.426.3MHz (in VGA mode - there is
also an QVGA mode)
VSYNC Frequency fVSYNC 54 60 66 Hz
VSYNC cycle time tv -- 650 -- H
HSYNC frequency fHSYNC -- 39.3-- Khz
HSYNC cycle time th -- 570 -- CLK
So there are two different subvariants of the same panel.
If I remember correctly, the 05 is older (April 2010)
and the 99DTC newer (Dec 2011).
So 22 MHz isn't outside of either spec but may be higher
than needed for the 99DTC. I.e. the panel is probably
running at higher frame rate than 60 fps.
Hm. I think we should define some compromise. I.e.
.clock = 22230
.vrefresh = 60
.vtotal = 650
.htotal = 570
Probably we originally tried to do this with the parameter
set but got something wrong.
If you agree with this approach, I can try to figure out
the other parameters so that they should fit both panel
variants. I can only test with COM37H3M99DTC since I
do no longer have a device with COM37H3M05DTC.
In general it seems that the structure drm_display_mode
is overdetermined.
Either .clock could be calculated from .vrefresh (and
the other .vtotal and .htotal) or vice versa like I
did for the proposal above.
I haven't looked into the driver code, but would it be
possible to specify .clock = 0 (or leave it out) to
calculate it bottom up? This would avoid such inconsistencies.
On the other hand it is not easily visible any more
from the code if the clock is in range of the data
sheet limits.
BR and thanks,
Nikolaus
>
> Cc: H. Nikolaus Schaller
> Cc: Sam Ravnborg
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/panel/panel-simple.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c
> b/drivers/gpu/drm/panel/panel-simple.c
> index ca72b73408e9..f9b4f84bffb3 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -2617,7 +2617,7 @@ static const struct panel_desc ontat_yx700wv03 = {
> };
>
> static const struct drm_display_mode ortustech_com37h3m_mode = {
> - .clock = 22153,
> + .clock = 19842,
> .hdisplay = 480,
> .hsync_start = 480 + 8,
> .hsync_end = 480 + 8 + 10,
> --
> 2.24.1
>
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[RFC v2 4/8] drm: ingenic: add jz4780 Synopsys HDMI driver.
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/Kconfig | 8 ++
drivers/gpu/drm/ingenic/Makefile | 1 +
drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c | 120 +++
3 files changed, 129 insertions(+)
create mode 100644 drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
diff --git a/drivers/gpu/drm/ingenic/Kconfig b/drivers/gpu/drm/ingenic/Kconfig
index d82c3d37ec9c..44bfd0d35af1 100644
--- a/drivers/gpu/drm/ingenic/Kconfig
+++ b/drivers/gpu/drm/ingenic/Kconfig
@@ -14,3 +14,11 @@ config DRM_INGENIC
Choose this option for DRM support for the Ingenic SoCs.
If M is selected the module will be called ingenic-drm.
+
+config DRM_DW_HDMI_JZ4780
+ tristate "HDMI Support for Ingenic JZ4780"
+ depends on DRM_INGENIC
+ depends on OF
+ select DRM_DW_HDMI
+ help
+ Choose this option for HDMI output from the Ingenic JZ4780.
diff --git a/drivers/gpu/drm/ingenic/Makefile b/drivers/gpu/drm/ingenic/Makefile
index 11cac42ce0bb..238383de63c7 100644
--- a/drivers/gpu/drm/ingenic/Makefile
+++ b/drivers/gpu/drm/ingenic/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_DRM_INGENIC) += ingenic-drm.o
+obj-$(CONFIG_DRM_DW_HDMI_JZ4780) += dw_hdmi-jz4780.o
diff --git a/drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
b/drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
new file mode 100644
index ..fa379e337263
--- /dev/null
+++ b/drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2019 Paul Boddie
+ *
+ * Derived from dw_hdmi-imx.c with i.MX portions removed.
+ * Probe and remove operations derived from rcar_dw_hdmi.c.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+
+static const struct dw_hdmi_mpll_config jz4780_mpll_cfg[] = {
+ { 4525, { { 0x01e0, 0x },
+ { 0x21e1, 0x },
+ { 0x41e2, 0x } } },
+ { 9250, { { 0x0140, 0x0005 },
+ { 0x2141, 0x0005 },
+ { 0x4142, 0x0005 } } },
+ { 14850, { { 0x00a0, 0x000a },
+ { 0x20a1, 0x000a },
+ { 0x40a2, 0x000a } } },
+ { 21600, { { 0x00a0, 0x000a },
+ { 0x2001, 0x000f },
+ { 0x4002, 0x000f } } },
+ { ~0UL, { { 0x, 0x },
+ { 0x, 0x },
+ { 0x, 0x } } }
+};
+
+static const struct dw_hdmi_curr_ctrl jz4780_cur_ctr[] = {
+ /*pixelclk bpp8bpp10 bpp12 */
+ { 5400, { 0x091c, 0x091c, 0x06dc } },
+ { 5840, { 0x091c, 0x06dc, 0x06dc } },
+ { 7200, { 0x06dc, 0x06dc, 0x091c } },
+ { 7425, { 0x06dc, 0x0b5c, 0x091c } },
+ { 11880, { 0x091c, 0x091c, 0x06dc } },
+ { 21600, { 0x06dc, 0x0b5c, 0x091c } },
+ { ~0UL, { 0x, 0x, 0x } },
+};
+
+/*
+ * Resistance term 133Ohm Cfg
+ * PREEMP config 0.00
+ * TX/CK level 10
+ */
+static const struct dw_hdmi_phy_config jz4780_phy_config[] = {
+ /*pixelclk symbol term vlev */
+ { 21600, 0x800d, 0x0005, 0x01ad},
+ { ~0UL, 0x, 0x, 0x}
+};
+
+static enum drm_mode_status
+jz4780_hdmi_mode_valid(struct drm_connector *con,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock < 13500)
+ return MODE_CLOCK_LOW;
+ /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
+ if (mode->clock > 216000)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static struct dw_hdmi_plat_data jz4780_dw_hdmi_plat_data = {
+ .mpll_cfg = jz4780_mpll_cfg,
+ .cur_ctr= jz4780_cur_ctr,
+ .phy_config = jz4780_phy_config,
+ .mode_valid = jz4780_hdmi_mode_valid,
+};
+
+static const struct of_device_id jz4780_dw_hdmi_dt_ids[] = {
+ { .compatible = "ingenic,jz4780-dw-hdmi" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_dw_hdmi_dt_ids);
+
+static int jz4780_dw_hdmi_probe(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi;
+
+ hdmi = dw_hdmi_probe(pdev, _dw_hdmi_plat_data);
+ if (IS_ERR(hdmi))
+ return PTR_ERR(hdmi);
+
+ platform_set_drvdata(pdev, hdmi);
+
+ return 0;
+}
+
+static int jz4780_dw_hdmi_remove(struct platform_device *pdev)
+{
+ struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
+
+ dw_hdmi_remove(hdmi);
+
+ return 0;
+}
+
+static struct platform_driver jz4780_dw_hdmi_platform_driver = {
+ .probe = jz4780_dw_hdmi_probe,
+ .remove = jz4780_dw_hdmi_remove,
+ .driver = {
[RFC v2 5/8] pinctrl: ingenic: add hdmi-ddc pin control group
From: Paul Boddie
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
drivers/pinctrl/pinctrl-ingenic.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-ingenic.c
b/drivers/pinctrl/pinctrl-ingenic.c
index 96f04d121ebd..1599a003c31f 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -4,6 +4,7 @@
*
* Copyright (c) 2017 Paul Cercueil
* Copyright (c) 2019 周琰杰 (Zhou Yanjie)
+ * Copyright (c) 2017, 2019 Paul Boddie
*/
#include
@@ -900,6 +901,7 @@ static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06,
0x07, 0x18, };
static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
+static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
static int jz4780_uart2_data_funcs[] = { 1, 1, };
static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
@@ -908,6 +910,7 @@ static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
static int jz4780_i2c3_funcs[] = { 1, 1, };
static int jz4780_i2c4_e_funcs[] = { 1, 1, };
static int jz4780_i2c4_f_funcs[] = { 1, 1, };
+static int jz4780_hdmi_ddc_funcs[] = { 0, 0, };
static const struct group_desc jz4780_groups[] = {
INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
@@ -950,6 +953,7 @@ static const struct group_desc jz4780_groups[] = {
INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
+ INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
{ "lcd-no-pins", },
@@ -982,6 +986,7 @@ static const char *jz4780_nemc_groups[] = {
static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
static const char *jz4780_cim_groups[] = { "cim-data", };
+static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
static const struct function_desc jz4780_functions[] = {
{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -1014,6 +1019,8 @@ static const struct function_desc jz4780_functions[] = {
{ "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
+ { "hdmi-ddc", jz4780_hdmi_ddc_groups,
+ ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
};
static const struct ingenic_chip_info jz4780_chip_info = {
--
2.23.0
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[RFC v2 2/8] dt-bindings: display: add ingenic-jz4780-hdmi DT Schema
From: Sam Ravnborg
Add DT bindings for the hdmi driver for the Ingenic JZ4780 SoC.
Based on .txt binding from Zubair Lutfullah Kakakhel
Signed-off-by: Sam Ravnborg
Cc: Zubair Lutfullah Kakakhel
Cc: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../bindings/display/ingenic-jz4780-hdmi.yaml | 83 +++
1 file changed, 83 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
new file mode 100644
index ..9b71c427bd69
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic-jz4780-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 HDMI Transmitter
+
+maintainers:
+ - Zubair Lutfullah Kakakhel
+ - H. Nikolaus Schaller
+
+description: |
+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
+ TX controller IP with accompanying PHY IP.
+
+allOf:
+ - $ref: panel/panel-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: ingenic,jz4780-hdmi
+
+ reg:
+maxItems: 1
+description: the address & size of the LCD controller registers
+
+ reg-io-width:
+const: 4
+
+ interrupts:
+maxItems: 1
+description: Specifies the interrupt provided by parent
+
+ clocks:
+maxItems: 2
+description: Clock specifiers for isrf and iahb clocks
+
+ clock-names:
+items:
+ - const: isfr
+ - const: iahb
+
+ ddc-i2c-bus: true
+ ports: true
+
+required:
+- compatible
+- clocks
+- clock-names
+- ports
+- reg-io-width
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+
+hdmi: hdmi@1018 {
+compatible = "ingenic,jz4780-hdmi";
+reg = <0x1018 0x8000>;
+reg-io-width = <4>;
+ddc-i2c-bus = <>;
+interrupt-parent = <>;
+interrupts = <3>;
+clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
+clock-names = "isfr", "iahb";
+
+ports {
+hdmi_in: port {
+#address-cells = <1>;
+#size-cells = <0>;
+hdmi_in_lcd: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_out_hdmi>;
+};
+};
+};
+};
+
+...
--
2.23.0
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[RFC v2 6/8] MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller
From: Paul Boddie
A specialisation of the generic Synopsys HDMI driver is employed for JZ4780
HDMI support. This requires a new driver, plus device tree and configuration
modifications.
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 32 ++
1 file changed, 32 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index f928329b034b..391d4e1efd35 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -433,4 +433,36 @@
status = "disabled";
};
+
+ hdmi: hdmi@1018 {
+ compatible = "ingenic,jz4780-dw-hdmi";
+ reg = <0x1018 0x8000>;
+ reg-io-width = <4>;
+
+ clocks = < JZ4780_CLK_HDMI>, < JZ4780_CLK_AHB0>;
+ clock-names = "isfr" , "iahb";
+
+ assigned-clocks = < JZ4780_CLK_HDMI>;
+ assigned-clock-rates = <2700>;
+
+ interrupt-parent = <>;
+ interrupts = <3>;
+
+ /* ddc-i2c-bus = <>; */
+
+ status = "disabled";
+ };
+
+ lcd: lcd@1305 {
+ compatible = "ingenic,jz4740-lcd";
+ reg = <0x1305 0x1800>;
+
+ clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+ clock-names = "lcd", "lcd_pclk";
+
+ interrupt-parent = <>;
+ interrupts = <31>;
+
+ status = "disabled";
+ };
};
--
2.23.0
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[RFC v2 0/8] MIPS: CI20: add HDMI out support
* Converted .txt bindings to .yaml (by Sam Ravnborg - big THANKS) RFC V1 2020-02-26 20:13:06: This patch series adds HDMI output to the jz4780/CI20 board. It is based on taking the old 3.18 vendor kernel and trying to achieve the same with modern DTS setup and new/modified drivers. Unfortunately, in this first RFC, only EDID and creation of /dev/fb0 are working. Also, HDMI hot plugging is detected. But there is no HDMI output signal. So some tiny piece seems to be missing to enable/configure the Synposys HDMI controller. We need help from the community to fix this. Original authors of most patches are * Paul Boddie * Zubair Lutfullah Kakakhel H. Nikolaus Schaller (2): drm: ingenic-drm: add MODULE_DEVICE_TABLE MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780 Paul Boddie (4): drm: ingenic: add jz4780 Synopsys HDMI driver. pinctrl: ingenic: add hdmi-ddc pin control group MIPS: DTS: jz4780: account for Synopsys HDMI driver and LCD controller MIPS: DTS: CI20: add HDMI setup Sam Ravnborg (2): dt-bindings: display: add ingenic-jz4780-lcd DT Schema dt-bindings: display: add ingenic-jz4780-hdmi DT Schema .../bindings/display/ingenic-jz4780-hdmi.yaml | 83 .../bindings/display/ingenic-jz4780-lcd.yaml | 78 arch/mips/boot/dts/ingenic/ci20.dts | 64 ++ arch/mips/boot/dts/ingenic/jz4780.dtsi| 32 + arch/mips/configs/ci20_defconfig | 3 + drivers/gpu/drm/ingenic/Kconfig | 8 ++ drivers/gpu/drm/ingenic/Makefile | 1 + drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c | 120 ++ drivers/gpu/drm/ingenic/ingenic-drm.c | 2 + drivers/pinctrl/pinctrl-ingenic.c | 7 + 10 files changed, 398 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml create mode 100644 drivers/gpu/drm/ingenic/dw_hdmi-jz4780.c -- 2.23.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [RFC v2 1/8] dt-bindings: display: add ingenic-jz4780-lcd DT Schema
Hi Sam,
> Am 28.02.2020 um 19:42 schrieb Sam Ravnborg :
>
> Hi Nikolaus.
>
> On Fri, Feb 28, 2020 at 07:19:26PM +0100, H. Nikolaus Schaller wrote:
>> From: Sam Ravnborg
>>
>> Add DT bindings for the LCD controller on the jz4780 SoC
>> Based on .txt binding from Zubair Lutfullah Kakakhel
>>
>> Signed-off-by: Sam Ravnborg
>> Cc: Zubair Lutfullah Kakakhel
>> Cc: H. Nikolaus Schaller
>> Cc: Rob Herring
>> Cc: devicet...@vger.kernel.org
>
> As this patch was sent to you and you forward it you need to
> testify that this is OK.
> To do so follow the rules of the Developemnt Certificate of Origin
> as can be found in SubmittingPatches.rst.
>
> In other words - you need to add your Signed-off-by: xxx
> to the patch.
> In the end we want to be able to see the patch the patch has taken
> reading the Signed-off-by: lines from top to bottom.
Ok, never someone explained this as precise as you did. Thanks!
> Please check other patches in this series for the same issue.
Ok.
BR and thanks,
Nikolaus
>
> Sam
>
>> ---
>> .../bindings/display/ingenic-jz4780-lcd.yaml | 78 +++
>> 1 file changed, 78 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> b/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> new file mode 100644
>> index ..c71415a3a342
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
>> @@ -0,0 +1,78 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/ingenic-jz4780-lcd.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Bindings for Ingenic JZ4780 LCD Controller
>> +
>> +maintainers:
>> + - Zubair Lutfullah Kakakhel
>> + - H. Nikolaus Schaller
>> +
>> +description: |
>> + LCD Controller is the Display Controller for the Ingenic JZ4780 SoC
>> +
>> +properties:
>> + compatible:
>> +items:
>> + - const: ingenic,jz4780-lcd
>> +
>> + reg:
>> +maxItems: 1
>> +description: the address & size of the LCD controller registers
>> +
>> + interrupts:
>> +maxItems: 1
>> +description: Specifies the interrupt provided by parent
>> +
>> + clocks:
>> +maxItems: 2
>> +description: Clock specifiers for the JZ4780_CLK_TVE
>> JZ4780_CLK_LCD0PIXCLK
>> +
>> + clock-names:
>> +items:
>> + - const: lcd_clk
>> + - const: lcd_pixclk
>> +
>> + port:
>> +type: object
>> +description: |
>> + A port node with endpoint definitions as defined in
>> + Documentation/devicetree/bindings/media/video-interfaces.txt
>> +
>> +required:
>> +- compatible
>> +- reg
>> +- interrupts
>> +- clocks
>> +- clock-names
>> +- port
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> +#include
>> +lcd: jz4780-lcdk@0x1305 {
>> +compatible = "ingenic,jz4780-lcd";
>> +reg = <0x1305 0x1800>;
>> +
>> +clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
>> +clock-names = "lcd_clk", "lcd_pixclk";
>> +
>> +interrupt-parent = <>;
>> +interrupts = <31>;
>> +
>> +jz4780_lcd_out: port {
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +
>> +jz4780_out_hdmi: endpoint@0 {
>> +reg = <0>;
>> +remote-endpoint = <_in_lcd>;
>> +};
>> +};
>> +};
>> +
>> +...
>> --
>> 2.23.0
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[RFC v2 1/8] dt-bindings: display: add ingenic-jz4780-lcd DT Schema
From: Sam Ravnborg
Add DT bindings for the LCD controller on the jz4780 SoC
Based on .txt binding from Zubair Lutfullah Kakakhel
Signed-off-by: Sam Ravnborg
Cc: Zubair Lutfullah Kakakhel
Cc: H. Nikolaus Schaller
Cc: Rob Herring
Cc: devicet...@vger.kernel.org
---
.../bindings/display/ingenic-jz4780-lcd.yaml | 78 +++
1 file changed, 78 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
diff --git a/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
b/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
new file mode 100644
index ..c71415a3a342
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/ingenic-jz4780-lcd.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic-jz4780-lcd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Ingenic JZ4780 LCD Controller
+
+maintainers:
+ - Zubair Lutfullah Kakakhel
+ - H. Nikolaus Schaller
+
+description: |
+ LCD Controller is the Display Controller for the Ingenic JZ4780 SoC
+
+properties:
+ compatible:
+items:
+ - const: ingenic,jz4780-lcd
+
+ reg:
+maxItems: 1
+description: the address & size of the LCD controller registers
+
+ interrupts:
+maxItems: 1
+description: Specifies the interrupt provided by parent
+
+ clocks:
+maxItems: 2
+description: Clock specifiers for the JZ4780_CLK_TVE JZ4780_CLK_LCD0PIXCLK
+
+ clock-names:
+items:
+ - const: lcd_clk
+ - const: lcd_pixclk
+
+ port:
+type: object
+description: |
+ A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+required:
+- compatible
+- reg
+- interrupts
+- clocks
+- clock-names
+- port
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+lcd: jz4780-lcdk@0x1305 {
+compatible = "ingenic,jz4780-lcd";
+reg = <0x1305 0x1800>;
+
+clocks = < JZ4780_CLK_TVE>, < JZ4780_CLK_LCD0PIXCLK>;
+clock-names = "lcd_clk", "lcd_pixclk";
+
+interrupt-parent = <>;
+interrupts = <31>;
+
+jz4780_lcd_out: port {
+#address-cells = <1>;
+#size-cells = <0>;
+
+jz4780_out_hdmi: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_in_lcd>;
+};
+};
+};
+
+...
--
2.23.0
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[RFC v2 7/8] MIPS: DTS: CI20: add HDMI setup
From: Paul Boddie
We need to hook up
* HDMI power regulator
* HDMI connector
* DDC pinmux
* HDMI and LCD endpoint connections
Signed-off-by: Paul Boddie
Signed-off-by: H. Nikolaus Schaller
---
arch/mips/boot/dts/ingenic/ci20.dts | 64 +
1 file changed, 64 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts
b/arch/mips/boot/dts/ingenic/ci20.dts
index 37b93166bf22..efa8270afbba 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -60,6 +60,28 @@
enable-active-high;
};
+ hdmi_power: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "hdmi_power";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ gpio = < 25 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ hdmi_out: connector {
+ compatible = "hdmi-connector";
+ label = "HDMI OUT";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_hdmi_out>;
+ };
+ };
+ };
+
wlan0_power: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "wlan0_power";
@@ -423,6 +445,12 @@
bias-disable;
};
+ pins_hdmi_ddc: hdmi_ddc {
+ function = "hdmi-ddc";
+ groups = "hdmi-ddc";
+ bias-disable;
+ };
+
pins_nemc: nemc {
function = "nemc";
groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we",
"nemc-frd-fwe";
@@ -459,3 +487,39 @@
assigned-clocks = < TCU_CLK_TIMER0>, < TCU_CLK_TIMER1>;
assigned-clock-rates = <300>, <300>;
};
+
+ {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_hdmi_ddc>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dw_hdmi_in: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dw_hdmi_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ port {
+ lcd_out: endpoint {
+ remote-endpoint = <_hdmi_in>;
+ };
+ };
+};
--
2.23.0
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[RFC v2 3/8] drm: ingenic-drm: add MODULE_DEVICE_TABLE
so that the driver can load by matching the device tree
if compiled as module.
Signed-off-by: H. Nikolaus Schaller
---
drivers/gpu/drm/ingenic/ingenic-drm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c
b/drivers/gpu/drm/ingenic/ingenic-drm.c
index 6d47ef7b148c..d8617096dd8e 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.c
@@ -844,6 +844,8 @@ static const struct of_device_id ingenic_drm_of_match[] = {
{ /* sentinel */ },
};
+MODULE_DEVICE_TABLE(of, ingenic_drm_of_match);
+
static struct platform_driver ingenic_drm_driver = {
.driver = {
.name = "ingenic-drm",
--
2.23.0
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[RFC v2 8/8] MIPS: CI20: defconfig: configure for DRM_DW_HDMI_JZ4780
We configure them as loadable modules by default. Signed-off-by: H. Nikolaus Schaller --- arch/mips/configs/ci20_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig index be41df2a81fb..3f733a555cb2 100644 --- a/arch/mips/configs/ci20_defconfig +++ b/arch/mips/configs/ci20_defconfig @@ -103,6 +103,9 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_JZ4740=y CONFIG_DMADEVICES=y CONFIG_DMA_JZ4780=y +CONFIG_DRM=m +CONFIG_DRM_DW_HDMI_JZ4780=m +CONFIG_DRM_DW_HDMI=m # CONFIG_IOMMU_SUPPORT is not set CONFIG_MEMORY=y CONFIG_EXT4_FS=y -- 2.23.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
