Re: [PATCH] drm: xlnx: Use dma_request_chan for DMA channel request
On Tue, Oct 27, 2020 at 06:36:02PM -0700, Hyun Kwon wrote:
> Hi Peter,
>
> Thanks for the patch.
>
> On Fri, Oct 23, 2020 at 02:46:02AM -0700, Peter Ujfalusi wrote:
> > There is no need to use the of_dma_request_slave_channel() directly as
> > dma_request_chan() is going to try to get the channel via OF as well.
> >
> > Signed-off-by: Peter Ujfalusi
>
> So now dma_request_chan() has sysfs / debugfs registrations, and this looks
> good to me. I'll commit this within next couple days and keep it posted here.
>
Applied to drm-misc-next.
Thanks!
-hyun
> Thanks,
> -hyun
>
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_disp.c | 4 +---
> > 1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > index 98bd48f13fd1..a4405d081aca 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > @@ -28,7 +28,6 @@
> > #include
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include
> > @@ -1316,8 +1315,7 @@ static int zynqmp_disp_layer_request_dma(struct
> > zynqmp_disp *disp,
> >
> > snprintf(dma_channel_name, sizeof(dma_channel_name),
> > "%s%u", dma_names[layer->id], i);
> > - dma->chan = of_dma_request_slave_channel(disp->dev->of_node,
> > -dma_channel_name);
> > + dma->chan = dma_request_chan(disp->dev, dma_channel_name);
> > if (IS_ERR(dma->chan)) {
> > dev_err(disp->dev, "failed to request dma channel\n");
> > ret = PTR_ERR(dma->chan);
> > --
> > Peter
> >
> > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> > Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> >
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Re: [PATCH] drm: xlnx: Use dma_request_chan for DMA channel request
Hi Peter,
Thanks for the patch.
On Fri, Oct 23, 2020 at 02:46:02AM -0700, Peter Ujfalusi wrote:
> There is no need to use the of_dma_request_slave_channel() directly as
> dma_request_chan() is going to try to get the channel via OF as well.
>
> Signed-off-by: Peter Ujfalusi
So now dma_request_chan() has sysfs / debugfs registrations, and this looks
good to me. I'll commit this within next couple days and keep it posted here.
Thanks,
-hyun
> ---
> drivers/gpu/drm/xlnx/zynqmp_disp.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> index 98bd48f13fd1..a4405d081aca 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> @@ -28,7 +28,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -1316,8 +1315,7 @@ static int zynqmp_disp_layer_request_dma(struct
> zynqmp_disp *disp,
>
> snprintf(dma_channel_name, sizeof(dma_channel_name),
>"%s%u", dma_names[layer->id], i);
> - dma->chan = of_dma_request_slave_channel(disp->dev->of_node,
> - dma_channel_name);
> + dma->chan = dma_request_chan(disp->dev, dma_channel_name);
> if (IS_ERR(dma->chan)) {
> dev_err(disp->dev, "failed to request dma channel\n");
> ret = PTR_ERR(dma->chan);
> --
> Peter
>
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
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Re: [PATCH v2 20/21] drm/xlnx: Initialize DRM driver instance with CMA helper macro
Hi Tomas,
Thanks for the patch.
On Tue, Sep 15, 2020 at 08:53:46AM -0700, Laurent Pinchart wrote:
> Hi Thomas,
>
> Thank you for the patch.
>
> On Tue, Sep 15, 2020 at 04:59:57PM +0200, Thomas Zimmermann wrote:
> > The xlnx driver uses CMA helpers with default callback functions.
> > Initialize the driver structure with the rsp CMA helper macro. The
> > driver is being converted to use GEM object functions as part of
> > this change.
> >
> > Two callbacks, .dumb_destroy and .gem_prime_import, were initialized
> > to their default implementations, so they are just kept empty now.
> >
> > v2:
> > * initialize with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE (Laurent)
> >
> > Signed-off-by: Thomas Zimmermann
>
> Reviewed-by: Laurent Pinchart
>
Reviewed-by: Hyun Kwon
Thanks,
-hyun
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 14 +-
> > 1 file changed, 1 insertion(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> > b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> > index 8e69303aad3f..f3ffc3703a0e 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> > @@ -80,19 +80,7 @@ static struct drm_driver zynqmp_dpsub_drm_driver = {
> > .driver_features= DRIVER_MODESET | DRIVER_GEM |
> > DRIVER_ATOMIC,
> >
> > - .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> > - .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> > - .gem_prime_export = drm_gem_prime_export,
> > - .gem_prime_import = drm_gem_prime_import,
> > - .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> > - .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> > - .gem_prime_vmap = drm_gem_cma_prime_vmap,
> > - .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> > - .gem_prime_mmap = drm_gem_cma_prime_mmap,
> > - .gem_free_object_unlocked = drm_gem_cma_free_object,
> > - .gem_vm_ops = _gem_cma_vm_ops,
> > - .dumb_create= zynqmp_dpsub_dumb_create,
> > - .dumb_destroy = drm_gem_dumb_destroy,
> > + DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(zynqmp_dpsub_dumb_create),
> >
> > .fops = _dpsub_drm_fops,
> >
>
> --
> Regards,
>
> Laurent Pinchart
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Re: [PATCH] drm: xlnx: remove defined but not used 'scaling_factors_666'
On Fri, Sep 11, 2020 at 09:27:08AM -0700, Hyun Kwon wrote:
> Hi Daniel,
>
> On Fri, Sep 11, 2020 at 01:15:19AM -0700, Daniel Vetter wrote:
> > On Thu, Sep 10, 2020 at 11:14:18AM -0700, Hyun Kwon wrote:
> > > Hi Jason,
> > >
> > > On Thu, Sep 10, 2020 at 07:06:30AM -0700, Jason Yan wrote:
> > > > This addresses the following gcc warning with "make W=1":
> > > >
> > > > drivers/gpu/drm/xlnx/zynqmp_disp.c:245:18: warning:
> > > > ‘scaling_factors_666’ defined but not used [-Wunused-const-variable=]
> > > > 245 | static const u32 scaling_factors_666[] = {
> > > > | ^~~
> > > >
> > > > Reported-by: Hulk Robot
> > > > Signed-off-by: Jason Yan
> > >
> > > Reviewed-by: Hyun Kwon
> >
> > I think you're the maintainer, so please also push patches to
> > drm-misc-next. Otherwise they'll just get lost, or at least it's very
> > confusing when a maintainer reviews a patch but there's no indication what
> > will happen with the patch.
>
> Right. I wanted to give it some time before pushing. I'll clearly state going
> forward.
>
Pushed to drm-misc/drm-misc-next.
Thanks,
-hyun
> Thanks,
> -hyun
>
> > -Daniel
> >
> > >
> > > Thanks!
> > >
> > > -hyun
> > >
> > > > ---
> > > > drivers/gpu/drm/xlnx/zynqmp_disp.c | 6 --
> > > > 1 file changed, 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > > b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > > index a455cfc1bee5..98bd48f13fd1 100644
> > > > --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > > @@ -242,12 +242,6 @@ static const u32 scaling_factors_565[] = {
> > > > ZYNQMP_DISP_AV_BUF_5BIT_SF,
> > > > };
> > > >
> > > > -static const u32 scaling_factors_666[] = {
> > > > - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> > > > - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> > > > - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> > > > -};
> > > > -
> > > > static const u32 scaling_factors_888[] = {
> > > > ZYNQMP_DISP_AV_BUF_8BIT_SF,
> > > > ZYNQMP_DISP_AV_BUF_8BIT_SF,
> > > > --
> > > > 2.25.4
> > > >
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
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Re: [PATCH] drm: xlnx: remove defined but not used 'scaling_factors_666'
Hi Daniel,
On Fri, Sep 11, 2020 at 01:15:19AM -0700, Daniel Vetter wrote:
> On Thu, Sep 10, 2020 at 11:14:18AM -0700, Hyun Kwon wrote:
> > Hi Jason,
> >
> > On Thu, Sep 10, 2020 at 07:06:30AM -0700, Jason Yan wrote:
> > > This addresses the following gcc warning with "make W=1":
> > >
> > > drivers/gpu/drm/xlnx/zynqmp_disp.c:245:18: warning:
> > > ‘scaling_factors_666’ defined but not used [-Wunused-const-variable=]
> > > 245 | static const u32 scaling_factors_666[] = {
> > > | ^~~
> > >
> > > Reported-by: Hulk Robot
> > > Signed-off-by: Jason Yan
> >
> > Reviewed-by: Hyun Kwon
>
> I think you're the maintainer, so please also push patches to
> drm-misc-next. Otherwise they'll just get lost, or at least it's very
> confusing when a maintainer reviews a patch but there's no indication what
> will happen with the patch.
Right. I wanted to give it some time before pushing. I'll clearly state going
forward.
Thanks,
-hyun
> -Daniel
>
> >
> > Thanks!
> >
> > -hyun
> >
> > > ---
> > > drivers/gpu/drm/xlnx/zynqmp_disp.c | 6 --
> > > 1 file changed, 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > index a455cfc1bee5..98bd48f13fd1 100644
> > > --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> > > @@ -242,12 +242,6 @@ static const u32 scaling_factors_565[] = {
> > > ZYNQMP_DISP_AV_BUF_5BIT_SF,
> > > };
> > >
> > > -static const u32 scaling_factors_666[] = {
> > > - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> > > - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> > > - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> > > -};
> > > -
> > > static const u32 scaling_factors_888[] = {
> > > ZYNQMP_DISP_AV_BUF_8BIT_SF,
> > > ZYNQMP_DISP_AV_BUF_8BIT_SF,
> > > --
> > > 2.25.4
> > >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [PATCH] drm: xlnx: remove defined but not used 'scaling_factors_666'
Hi Jason,
On Thu, Sep 10, 2020 at 07:06:30AM -0700, Jason Yan wrote:
> This addresses the following gcc warning with "make W=1":
>
> drivers/gpu/drm/xlnx/zynqmp_disp.c:245:18: warning:
> ‘scaling_factors_666’ defined but not used [-Wunused-const-variable=]
> 245 | static const u32 scaling_factors_666[] = {
> | ^~~
>
> Reported-by: Hulk Robot
> Signed-off-by: Jason Yan
Reviewed-by: Hyun Kwon
Thanks!
-hyun
> ---
> drivers/gpu/drm/xlnx/zynqmp_disp.c | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> index a455cfc1bee5..98bd48f13fd1 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> @@ -242,12 +242,6 @@ static const u32 scaling_factors_565[] = {
> ZYNQMP_DISP_AV_BUF_5BIT_SF,
> };
>
> -static const u32 scaling_factors_666[] = {
> - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> - ZYNQMP_DISP_AV_BUF_6BIT_SF,
> -};
> -
> static const u32 scaling_factors_888[] = {
> ZYNQMP_DISP_AV_BUF_8BIT_SF,
> ZYNQMP_DISP_AV_BUF_8BIT_SF,
> --
> 2.25.4
>
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Re: [PATCH] drm/xlnx: Use devm_drm_dev_alloc
Hi Daniel,
On Mon, Sep 07, 2020 at 01:22:25AM -0700, Daniel Vetter wrote:
> Gets rid of drmm_add_final_kfree, which I want to unexport so that it
> stops confusion people about this transitional state of rolling drm
> managed memory out.
>
> This also fixes the missing drm_dev_put in the error path of the probe
> code.
>
> v2: Drop the misplaced drm_dev_put from zynqmp_dpsub_drm_init (all
> other paths leaked on error, this should have been in
> zynqmp_dpsub_probe), now that subsumed by the auto-cleanup of
> devm_drm_dev_alloc.
>
> Signed-off-by: Daniel Vetter
> Cc: Hyun Kwon
> Cc: Laurent Pinchart
> Cc: Michal Simek
> Cc: linux-arm-ker...@lists.infradead.org
Looks correct to me.
Reviewed-by: Hyun Kwon
Thanks!
-hyun
> ---
> drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 27 ++-
> 1 file changed, 6 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> index 26328c76305b..8e69303aad3f 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
> @@ -111,7 +111,7 @@ static int zynqmp_dpsub_drm_init(struct zynqmp_dpsub
> *dpsub)
> /* Initialize mode config, vblank and the KMS poll helper. */
> ret = drmm_mode_config_init(drm);
> if (ret < 0)
> - goto err_dev_put;
> + return ret;
>
> drm->mode_config.funcs = _dpsub_mode_config_funcs;
> drm->mode_config.min_width = 0;
> @@ -121,7 +121,7 @@ static int zynqmp_dpsub_drm_init(struct zynqmp_dpsub
> *dpsub)
>
> ret = drm_vblank_init(drm, 1);
> if (ret)
> - goto err_dev_put;
> + return ret;
>
> drm->irq_enabled = 1;
>
> @@ -154,8 +154,6 @@ static int zynqmp_dpsub_drm_init(struct zynqmp_dpsub
> *dpsub)
>
> err_poll_fini:
> drm_kms_helper_poll_fini(drm);
> -err_dev_put:
> - drm_dev_put(drm);
> return ret;
> }
>
> @@ -208,27 +206,16 @@ static int zynqmp_dpsub_probe(struct platform_device
> *pdev)
> int ret;
>
> /* Allocate private data. */
> - dpsub = kzalloc(sizeof(*dpsub), GFP_KERNEL);
> - if (!dpsub)
> - return -ENOMEM;
> + dpsub = devm_drm_dev_alloc(>dev, _dpsub_drm_driver,
> +struct zynqmp_dpsub, drm);
> + if (IS_ERR(dpsub))
> + return PTR_ERR(dpsub);
>
> dpsub->dev = >dev;
> platform_set_drvdata(pdev, dpsub);
>
> dma_set_mask(dpsub->dev, DMA_BIT_MASK(ZYNQMP_DISP_MAX_DMA_BIT));
>
> - /*
> - * Initialize the DRM device early, as the DRM core mandates usage of
> - * the managed memory helpers tied to the DRM device.
> - */
> - ret = drm_dev_init(>drm, _dpsub_drm_driver, >dev);
> - if (ret < 0) {
> - kfree(dpsub);
> - return ret;
> - }
> -
> - drmm_add_final_kfree(>drm, dpsub);
> -
> /* Try the reserved memory. Proceed if there's none. */
> of_reserved_mem_device_init(>dev);
>
> @@ -286,8 +273,6 @@ static int zynqmp_dpsub_remove(struct platform_device
> *pdev)
> clk_disable_unprepare(dpsub->apb_clk);
> of_reserved_mem_device_release(>dev);
>
> - drm_dev_put(drm);
> -
> return 0;
> }
>
> --
> 2.28.0
>
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RE: dt-bindings: display: xlnx: mixer: Inconsistent pixel format terminology in dt docs
Hi Kenneth, > -Original Message- > From: Kenneth Sloat > Sent: Thursday, August 20, 2020 2:18 PM > To: Hyun Kwon ; linux-arm-ker...@lists.infradead.org > Cc: Michal Simek ; dri-devel@lists.freedesktop.org; linux- > ker...@vger.kernel.org; laurent.pinch...@ideasonboard.com; > devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; > mark.rutl...@arm.com > Subject: dt-bindings: display: xlnx: mixer: Inconsistent pixel format > terminology > in dt docs > > Hello, > > The Xilinx Video mixer IP uses the DRM fourcc string as a device tree binding > in > order to describe the format for a specific DRM layer/plane. Currently, in the > device tree doc in > "Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt" there is a > list > called "VIDEO FORMATS" with a table containing "Mixer IP Format" and > associated "Driver supported Format String" (fourcc). In general, this table > is not > helpful, because "Mixer IP Format" does not match the Xilinx IP datasheet > terminology for formats but rather some other commonly used nomenclature. > This is also inconsistent from other Xilinx dts binding docs which specify the > actual correct IP name and at times list other format nomenclature where > helpful (i.e. xilinx_frmbuf.txt) > > My suggestion is to remove the current "Mixer IP Format" strings in the doc > and > replace them with the actual IP names in the datasheet (which also match those > used in Xilinx's Vivado FPGA tool). Otherwise, the programmer must cross > reference other dts documentation or the code in order to figure these out. I > am > happy to provide a patch for this but wanted to throw out the suggestion > first. I agree. The bindings should be in sync with datasheet and not rely on software definitions. Since the driver is only in Xilinx vendor tree, please send directly to g...@xilinx.com. Thanks! -hyun > > Thanks > > Sincerely, > Ken Sloat ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [PATCH v2 1/1] drm: xlnx: zynqmp: Use switch - case for link rate downshift
> -Original Message-
> From: dri-devel On Behalf Of Hyun
> Kwon
> Sent: Thursday, July 30, 2020 7:33 PM
> To: Laurent Pinchart
> Cc: Dan Carpenter ; dri-
> de...@lists.freedesktop.org; Daniel Vetter
> Subject: Re: [PATCH v2 1/1] drm: xlnx: zynqmp: Use switch - case for link rate
> downshift
>
> Hi Laurent,
>
> Thanks for the comment.
>
> On Thu, Jul 30, 2020 at 04:12:46PM -0700, Laurent Pinchart wrote:
> > Hi Hyun,
> >
> > Thank you for the patch.
> >
> > On Wed, Jul 29, 2020 at 04:30:45PM -0700, Hyun Kwon wrote:
> > > Use switch - case to downshift from the current link rate. It's a small
> > > loop now, so fine to be replaced with switch - case. With a loop, it is
> > > confusing and hard to follow as reported below.
> > >
> > > The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> > > DisplayPort Subsystem" from Jul 7, 2018, leads to the following
> > > static checker warning:
> > >
> > > drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
> > > error: iterator underflow 'bws' (-1)-2
> > >
> > > Reported-by: Dan Carpenter
> > > Signed-off-by: Hyun Kwon
> > > ---
> > > v2
> > > - Convert the for loop into switch - case
> > > ---
> > > ---
> > > drivers/gpu/drm/xlnx/zynqmp_dp.c | 29 -
> > > 1 file changed, 16 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > index b735072..5d6adeaa 100644
> > > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > @@ -567,34 +567,37 @@ static int zynqmp_dp_mode_configure(struct
> zynqmp_dp *dp, int pclock,
> > > u8 current_bw)
> > > {
> > > int max_rate = dp->link_config.max_rate;
> > > - u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7,
> DP_LINK_BW_5_4 };
> > > + u8 bw_code;
> > > u8 max_lanes = dp->link_config.max_lanes;
> > > u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
> > > u8 bpp = dp->config.bpp;
> > > u8 lane_cnt;
> > > - s8 i;
> > >
> > > - if (current_bw == DP_LINK_BW_1_62) {
> > > + /* Downshift from current one */
> >
> > Maybe "Downshift from the current bandwidth" ?
> >
> > Reviewed-by: Laurent Pinchart
> >
>
> I agree. I'll fix and add the tag.
>
Applied to drm-misc-next-fixes.
Thanks,
-hyun
> Thanks!
>
> -hyun
>
> > > + switch (current_bw) {
> > > + case DP_LINK_BW_5_4:
> > > + bw_code = DP_LINK_BW_2_7;
> > > + break;
> > > + case DP_LINK_BW_2_7:
> > > + bw_code = DP_LINK_BW_1_62;
> > > + break;
> > > + case DP_LINK_BW_1_62:
> > > dev_err(dp->dev, "can't downshift. already lowest link rate\n");
> > > return -EINVAL;
> > > - }
> > > -
> > > - for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
> > > - if (current_bw && bws[i] >= current_bw)
> > > - continue;
> > > -
> > > - if (bws[i] <= max_link_rate_code)
> > > - break;
> > > + default:
> > > + /* If not given, start with max supported */
> > > + bw_code = max_link_rate_code;
> > > + break;
> > > }
> > >
> > > for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
> > > int bw;
> > > u32 rate;
> > >
> > > - bw = drm_dp_bw_code_to_link_rate(bws[i]);
> > > + bw = drm_dp_bw_code_to_link_rate(bw_code);
> > > rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
> > > if (pclock <= rate) {
> > > - dp->mode.bw_code = bws[i];
> > > + dp->mode.bw_code = bw_code;
> > > dp->mode.lane_cnt = lane_cnt;
> > > dp->mode.pclock = pclock;
> > > return dp->mode.bw_code;
> >
> > --
> > Regards,
> >
> > Laurent Pinchart
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Re: [PATCH v2 1/1] drm: xlnx: zynqmp: Use switch - case for link rate downshift
Hi Laurent,
Thanks for the comment.
On Thu, Jul 30, 2020 at 04:12:46PM -0700, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wed, Jul 29, 2020 at 04:30:45PM -0700, Hyun Kwon wrote:
> > Use switch - case to downshift from the current link rate. It's a small
> > loop now, so fine to be replaced with switch - case. With a loop, it is
> > confusing and hard to follow as reported below.
> >
> > The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> > DisplayPort Subsystem" from Jul 7, 2018, leads to the following
> > static checker warning:
> >
> > drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
> > error: iterator underflow 'bws' (-1)-2
> >
> > Reported-by: Dan Carpenter
> > Signed-off-by: Hyun Kwon
> > ---
> > v2
> > - Convert the for loop into switch - case
> > ---
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_dp.c | 29 -
> > 1 file changed, 16 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > index b735072..5d6adeaa 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > @@ -567,34 +567,37 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp
> > *dp, int pclock,
> > u8 current_bw)
> > {
> > int max_rate = dp->link_config.max_rate;
> > - u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
> > + u8 bw_code;
> > u8 max_lanes = dp->link_config.max_lanes;
> > u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
> > u8 bpp = dp->config.bpp;
> > u8 lane_cnt;
> > - s8 i;
> >
> > - if (current_bw == DP_LINK_BW_1_62) {
> > + /* Downshift from current one */
>
> Maybe "Downshift from the current bandwidth" ?
>
> Reviewed-by: Laurent Pinchart
>
I agree. I'll fix and add the tag.
Thanks!
-hyun
> > + switch (current_bw) {
> > + case DP_LINK_BW_5_4:
> > + bw_code = DP_LINK_BW_2_7;
> > + break;
> > + case DP_LINK_BW_2_7:
> > + bw_code = DP_LINK_BW_1_62;
> > + break;
> > + case DP_LINK_BW_1_62:
> > dev_err(dp->dev, "can't downshift. already lowest link rate\n");
> > return -EINVAL;
> > - }
> > -
> > - for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
> > - if (current_bw && bws[i] >= current_bw)
> > - continue;
> > -
> > - if (bws[i] <= max_link_rate_code)
> > - break;
> > + default:
> > + /* If not given, start with max supported */
> > + bw_code = max_link_rate_code;
> > + break;
> > }
> >
> > for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
> > int bw;
> > u32 rate;
> >
> > - bw = drm_dp_bw_code_to_link_rate(bws[i]);
> > + bw = drm_dp_bw_code_to_link_rate(bw_code);
> > rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
> > if (pclock <= rate) {
> > - dp->mode.bw_code = bws[i];
> > + dp->mode.bw_code = bw_code;
> > dp->mode.lane_cnt = lane_cnt;
> > dp->mode.pclock = pclock;
> > return dp->mode.bw_code;
>
> --
> Regards,
>
> Laurent Pinchart
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[PATCH v2 1/1] drm: xlnx: zynqmp: Use switch - case for link rate downshift
Use switch - case to downshift from the current link rate. It's a small
loop now, so fine to be replaced with switch - case. With a loop, it is
confusing and hard to follow as reported below.
The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
DisplayPort Subsystem" from Jul 7, 2018, leads to the following
static checker warning:
drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
error: iterator underflow 'bws' (-1)-2
Reported-by: Dan Carpenter
Signed-off-by: Hyun Kwon
---
v2
- Convert the for loop into switch - case
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
index b735072..5d6adeaa 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
@@ -567,34 +567,37 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp,
int pclock,
u8 current_bw)
{
int max_rate = dp->link_config.max_rate;
- u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
+ u8 bw_code;
u8 max_lanes = dp->link_config.max_lanes;
u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
u8 bpp = dp->config.bpp;
u8 lane_cnt;
- s8 i;
- if (current_bw == DP_LINK_BW_1_62) {
+ /* Downshift from current one */
+ switch (current_bw) {
+ case DP_LINK_BW_5_4:
+ bw_code = DP_LINK_BW_2_7;
+ break;
+ case DP_LINK_BW_2_7:
+ bw_code = DP_LINK_BW_1_62;
+ break;
+ case DP_LINK_BW_1_62:
dev_err(dp->dev, "can't downshift. already lowest link rate\n");
return -EINVAL;
- }
-
- for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
- if (current_bw && bws[i] >= current_bw)
- continue;
-
- if (bws[i] <= max_link_rate_code)
- break;
+ default:
+ /* If not given, start with max supported */
+ bw_code = max_link_rate_code;
+ break;
}
for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
int bw;
u32 rate;
- bw = drm_dp_bw_code_to_link_rate(bws[i]);
+ bw = drm_dp_bw_code_to_link_rate(bw_code);
rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
if (pclock <= rate) {
- dp->mode.bw_code = bws[i];
+ dp->mode.bw_code = bw_code;
dp->mode.lane_cnt = lane_cnt;
dp->mode.pclock = pclock;
return dp->mode.bw_code;
--
2.7.4
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Re: [PATCH 1/1] drm: xlnx: zynqmp: Stop the loop at lowest link rate without check
Hi Daniel,
Thanks for the review.
On Wed, Jul 29, 2020 at 02:34:16PM -0700, Daniel Vetter wrote:
> On Wed, Jul 29, 2020 at 8:21 PM Hyun Kwon wrote:
> >
> > The loop should exit at the lowest link rate, so break the loop
> > at the lowest link rate without check. The check is always true
> > because lowest link rate is smaller than current one and maximum
> > of current display. Otherwise, it may be seen as the loop can
> > potentially result in negative array offset.
> >
> > The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> > DisplayPort Subsystem" from Jul 7, 2018, leads to the following
> > static checker warning:
> >
> > drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
> > error: iterator underflow 'bws' (-1)-2
> >
> > Reported-by: Dan Carpenter
> > Signed-off-by: Hyun Kwon
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > index b735072..1be2b19 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > @@ -579,7 +579,7 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp
> > *dp, int pclock,
> > return -EINVAL;
> > }
> >
> > - for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
> > + for (i = ARRAY_SIZE(bws) - 1; i > 0; i--) {
>
> But now we don't go through the lowest element anymore, which also
> looks wrong. Or I'm blind.
>
Currently, the lowest element always breaks without decrement by the check of
the loop.
> I think the problem is later on that we should bail out of the loop on
> the last iteration (when i == 0) before we decrement, since otherwise
> we then look at bws[-1] in the next loop, which is clearly wrong. I
> guess your code results in the same, but it's very confusing logic for
> me ...
Indeed. I can convert the for loop into switch - case in v2. Hope it makes less
confusing. :)
Thanks,
-hyun
> -Daniel
>
> > if (current_bw && bws[i] >= current_bw)
> > continue;
> >
> > --
> > 2.7.4
> >
> > ___
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> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [PATCH -next] drm: xlnx: Fix typo in parameter description
Hi Wei,
Thanks for the patch.
On Tue, Jul 28, 2020 at 03:33:49PM -0700, Laurent Pinchart wrote:
> Hi Wei,
>
> Thank you for the patch.
>
> On Sat, Jul 25, 2020 at 06:34:29AM +, Wei Yongjun wrote:
> > Fix typo in parameter description.
> >
> > Fixes: d76271d22694 ("drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> > DisplayPort Subsystem")
> > Reported-by: Hulk Robot
> > Signed-off-by: Wei Yongjun
>
> Reviewed-by: Laurent Pinchart
>
Reviewed-by: Hyun Kwon
I'll commit this to drm-misc-next-fixes soon.
Thanks,
-hyun
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > index 821f7a71e182..3d53638ab15e 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > @@ -44,7 +44,7 @@ MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in
> > msec (default: 50)");
> > */
> > static uint zynqmp_dp_power_on_delay_ms = 4;
> > module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint,
> > 0444);
> > -MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)");
> > +MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default:
> > 4)");
> >
> > /* Link configuration registers */
> > #define ZYNQMP_DP_LINK_BW_SET 0x0
>
> --
> Regards,
>
> Laurent Pinchart
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Re: [PATCH][next] drm: xln: fix spelling mistake "failes" -> "failed"
Hi Colin,
Thanks for the patch.
On Tue, Jul 28, 2020 at 03:37:39PM -0700, Laurent Pinchart wrote:
> Hi Colin,
>
> Thank you for the patch.
>
> On Fri, Jul 24, 2020 at 12:12:58PM +0100, Colin King wrote:
> > From: Colin Ian King
> >
> > There is a spelling mistake in a dev_dbg messages. Fix it.
>
> There is a spelling mistake in the commit message, s/xln/xlnx/ ;-)
>
> > Signed-off-by: Colin Ian King
>
> Reviewed-by: Laurent Pinchart
>
Reviewed-by: Hyun Kwon
I'll fix the commit message and commit this change to drm-misc-next-fixes soon.
Thanks,
-hyun
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > index 821f7a71e182..0e1c818746eb 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > @@ -1308,7 +1308,7 @@ zynqmp_dp_connector_detect(struct drm_connector
> > *connector, bool force)
> > ret = drm_dp_dpcd_read(>aux, 0x0, dp->dpcd,
> >sizeof(dp->dpcd));
> > if (ret < 0) {
> > - dev_dbg(dp->dev, "DPCD read failes");
> > + dev_dbg(dp->dev, "DPCD read failed");
> > goto disconnected;
> > }
> >
>
> --
> Regards,
>
> Laurent Pinchart
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Re: [bug report] drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem
Hi Dan,
Thanks for sharing.
On Mon, Jul 27, 2020 at 04:18:25AM -0700, dan.carpen...@oracle.com wrote:
> Hello Hyun Kwon,
>
> The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> DisplayPort Subsystem" from Jul 7, 2018, leads to the following
> static checker warning:
>
> drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
> error: iterator underflow 'bws' (-1)-2
>
> drivers/gpu/drm/xlnx/zynqmp_dp.c
>566 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
>567 u8 current_bw)
>568 {
>569 int max_rate = dp->link_config.max_rate;
>570 u8 bws[3] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4
> };
>571 u8 max_lanes = dp->link_config.max_lanes;
>572 u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
>573 u8 bpp = dp->config.bpp;
>574 u8 lane_cnt;
>575 s8 i;
>576
>577 if (current_bw == DP_LINK_BW_1_62) {
>578 dev_err(dp->dev, "can't downshift. already lowest
> link rate\n");
>579 return -EINVAL;
>580 }
There are checks like this that ensure the 'i' to be not negative, but I agree
it should be made clearer. I've sumitted a fix for it [1].
[1] https://lists.freedesktop.org/archives/dri-devel/2020-July/274190.html
Thanks,
-hyun
>581
>582 for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
> ^^
> This exits with i == -1.
>
>583 if (current_bw && bws[i] >= current_bw)
>584 continue;
>585
>586 if (bws[i] <= max_link_rate_code)
>587 break;
>588 }
>589
>590 for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
>591 int bw;
>592 u32 rate;
>593
>594 bw = drm_dp_bw_code_to_link_rate(bws[i]);
> ^^
> Potential negative array offset.
>
>595 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
>596 if (pclock <= rate) {
>597 dp->mode.bw_code = bws[i];
>598 dp->mode.lane_cnt = lane_cnt;
>599 dp->mode.pclock = pclock;
>600 return dp->mode.bw_code;
>601 }
>602 }
>603
>604 dev_err(dp->dev, "failed to configure link values\n");
>605
>606 return -EINVAL;
>607 }
>
> regards,
> dan carpenter
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[PATCH 1/1] drm: xlnx: zynqmp: Stop the loop at lowest link rate without check
The loop should exit at the lowest link rate, so break the loop
at the lowest link rate without check. The check is always true
because lowest link rate is smaller than current one and maximum
of current display. Otherwise, it may be seen as the loop can
potentially result in negative array offset.
The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
DisplayPort Subsystem" from Jul 7, 2018, leads to the following
static checker warning:
drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure()
error: iterator underflow 'bws' (-1)-2
Reported-by: Dan Carpenter
Signed-off-by: Hyun Kwon
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
index b735072..1be2b19 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
@@ -579,7 +579,7 @@ static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp,
int pclock,
return -EINVAL;
}
- for (i = ARRAY_SIZE(bws) - 1; i >= 0; i--) {
+ for (i = ARRAY_SIZE(bws) - 1; i > 0; i--) {
if (current_bw && bws[i] >= current_bw)
continue;
--
2.7.4
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Re: [PATCH -next] drm: xlnx: Fix typo in parameter description
Hello,
On Tue, Jul 28, 2020 at 03:35:43PM -0700, Laurent Pinchart wrote:
> On Wed, Jul 29, 2020 at 12:02:05AM +0200, dan...@ffwll.ch wrote:
> > Hi Hyun Kwon,
> >
> > Are you all sorted with drm-misc commit rights so you can push the 3
> > (maybe there's more) xlnx fixup patches to drm-misc-next-fixes?
>
> Thanks Daniel for bringing this up.
>
> Hyun, would that work for you ?
>
Should I commit small fixups directly to,
https://cgit.freedesktop.org/drm/drm-misc/log/?h=drm-misc-next-fixes?
I received the account for drm-misc a couple years ago, and was able to access
back then. But now someting has changed, and I can't access at the moment. I'll
need some time to fix my setup. Maybe some help would be appreciated to speed
up. I may ping you offline if you don't mind.
Thanks,
-hyun
> > On Sat, Jul 25, 2020 at 06:34:29AM +, Wei Yongjun wrote:
> > > Fix typo in parameter description.
> > >
> > > Fixes: d76271d22694 ("drm: xlnx: DRM/KMS driver for Xilinx ZynqMP
> > > DisplayPort Subsystem")
> > > Reported-by: Hulk Robot
> > > Signed-off-by: Wei Yongjun
> > > ---
> > > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > index 821f7a71e182..3d53638ab15e 100644
> > > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > > @@ -44,7 +44,7 @@ MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value
> > > in msec (default: 50)");
> > > */
> > > static uint zynqmp_dp_power_on_delay_ms = 4;
> > > module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint,
> > > 0444);
> > > -MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default:
> > > 4)");
> > > +MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default:
> > > 4)");
> > >
> > > /* Link configuration registers */
> > > #define ZYNQMP_DP_LINK_BW_SET0x0
>
> --
> Regards,
>
> Laurent Pinchart
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Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Hi Laurent, On Wed, 2020-05-27 at 15:45:24 -0700, Laurent Pinchart wrote: > Hi Hyun, > > On Wed, May 27, 2020 at 10:54:35AM -0700, Hyun Kwon wrote: > > On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote: > > > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: > > >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote: > > >>> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video > > >>> data from AXI-4 stream interface. > > >>> > > >>> It supports upto 4 lanes, optional register interface for the DPHY, > > >> > > >> I don't see the register interface for dphy support. > > > > > > I think the D-PHY should be supported through a PHY driver, as it seems > > > to be shared between different subsystems. > > > > Right, if the logic is shared across subsystems. I can't tell if that's > > the case as the IP comes as a single block. Maybe GVRao can confirm. > > I believe the CSI2-RX subsystem uses the same D-PHY IP core, but a > confirmation would be nice. > > > >>> multiple RGB color formats, command mode and video mode. > > >>> This is a MIPI-DSI host driver and provides DSI bus for panels. > > >>> This driver also helps to communicate with its panel using panel > > >>> framework. > > >>> > > >>> Signed-off-by: Venkateshwar Rao Gannavarapu > > >>> > > >>> --- > > >>> drivers/gpu/drm/xlnx/Kconfig| 11 + > > >>> drivers/gpu/drm/xlnx/Makefile | 2 + > > >>> drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 > > >>> > > > > > > Daniel Vetter has recently expressed his opiion that bridge drivers > > > should go to drivers/gpu/drm/bridge/. It would then be > > > drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself. > > > > > >>> 3 files changed, 768 insertions(+) > > >>> create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> > > >>> diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig > > >>> index aa6cd88..73873cf 100644 > > >>> --- a/drivers/gpu/drm/xlnx/Kconfig > > >>> +++ b/drivers/gpu/drm/xlnx/Kconfig > > >>> @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB > > >>> This is a DRM/KMS driver for ZynqMP DisplayPort controller. > > >>> Choose > > >>> this option if you have a Xilinx ZynqMP SoC with DisplayPort > > >>> subsystem. > > >>> + > > >>> +config DRM_XLNX_DSI > > >>> +tristate "Xilinx DRM DSI Subsystem Driver" > > >>> +select DRM_MIPI_DSI > > >>> +select DRM_PANEL > > >>> +select DRM_PANEL_SIMPLE > > >>> +help > > >>> + This enables support for Xilinx MIPI-DSI. > > >> > > >> This sentence is not needed with below. Could you please rephrase the > > >> whole? > > >> > > >>> + This is a DRM/KMS driver for Xilinx programmable DSI > > >>> controller. > > >>> + Choose this option if you have a Xilinx MIPI DSI-TX controller > > >>> + subsytem. > > >> > > >> These seem incorrectly indented. > > >> > > >>> diff --git a/drivers/gpu/drm/xlnx/Makefile > > >>> b/drivers/gpu/drm/xlnx/Makefile > > >>> index 2b844c6..b7ee6ef 100644 > > >>> --- a/drivers/gpu/drm/xlnx/Makefile > > >>> +++ b/drivers/gpu/drm/xlnx/Makefile > > >>> @@ -1,2 +1,4 @@ > > >>> zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o > > >>> obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o > > >>> + > > >>> +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o > > >>> diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> new file mode 100644 > > >>> index 000..b8cae59 > > >>> --- /dev/null > > >>> +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > >>> @@ -0,0 +1,755 @@ > > >>> +// SPDX-License-Identifier: GPL-2.0 > > >>> +/* > > >>> + * Xilinx FPGA MIPI DSI Tx Controller driver > > >>> + * > > >>> + * Copy
Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Hi Laurent, On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote: > Hi GVRao, > > Thank you for the patch. > > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote: > > On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote: > > > The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video > > > data from AXI-4 stream interface. > > > > > > It supports upto 4 lanes, optional register interface for the DPHY, > > > > I don't see the register interface for dphy support. > > I think the D-PHY should be supported through a PHY driver, as it seems > to be shared between different subsystems. > Right, if the logic is shared across subsystems. I can't tell if that's the case as the IP comes as a single block. Maybe GVRao can confirm. > > > multiple RGB color formats, command mode and video mode. > > > This is a MIPI-DSI host driver and provides DSI bus for panels. > > > This driver also helps to communicate with its panel using panel > > > framework. > > > > > > Signed-off-by: Venkateshwar Rao Gannavarapu > > > > > > --- > > > drivers/gpu/drm/xlnx/Kconfig| 11 + > > > drivers/gpu/drm/xlnx/Makefile | 2 + > > > drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 > > > > > Daniel Vetter has recently expressed his opiion that bridge drivers > should go to drivers/gpu/drm/bridge/. It would then be > drivers/gpu/drm/bridge/xlnx/. I don't have a strong opinion myself. > > > > 3 files changed, 768 insertions(+) > > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c > > > > > > diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig > > > index aa6cd88..73873cf 100644 > > > --- a/drivers/gpu/drm/xlnx/Kconfig > > > +++ b/drivers/gpu/drm/xlnx/Kconfig > > > @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB > > > This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose > > > this option if you have a Xilinx ZynqMP SoC with DisplayPort > > > subsystem. > > > + > > > +config DRM_XLNX_DSI > > > +tristate "Xilinx DRM DSI Subsystem Driver" > > > +select DRM_MIPI_DSI > > > +select DRM_PANEL > > > +select DRM_PANEL_SIMPLE > > > +help > > > + This enables support for Xilinx MIPI-DSI. > > > > This sentence is not needed with below. Could you please rephrase the whole? > > > > > + This is a DRM/KMS driver for Xilinx programmable DSI controller. > > > + Choose this option if you have a Xilinx MIPI DSI-TX controller > > > + subsytem. > > > > These seem incorrectly indented. > > > > > diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile > > > index 2b844c6..b7ee6ef 100644 > > > --- a/drivers/gpu/drm/xlnx/Makefile > > > +++ b/drivers/gpu/drm/xlnx/Makefile > > > @@ -1,2 +1,4 @@ > > > zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o > > > obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o > > > + > > > +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o > > > diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c > > > b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > > new file mode 100644 > > > index 000..b8cae59 > > > --- /dev/null > > > +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c > > > @@ -0,0 +1,755 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Xilinx FPGA MIPI DSI Tx Controller driver > > > + * > > > + * Copyright (C) 2017 - 2019 Xilinx, Inc. > > > + * > > > + * Authors: > > > + * - Saurabh Sengar > > > + * - Venkateshwar Rao Gannavarapu > > > > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > + > > > +/* DSI Tx IP registers */ > > > +#define XDSI_CCR 0x00 > > > +#define XDSI_CCR_COREENB BIT(0) > > > +#define XDSI_CCR_SOFTRST BIT(1) > > > +#
Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
Hi GVRao, Thanks for the patch. Sorry for late reply. On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote: > The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video > data from AXI-4 stream interface. > > It supports upto 4 lanes, optional register interface for the DPHY, I don't see the register interface for dphy support. > multiple RGB color formats, command mode and video mode. > This is a MIPI-DSI host driver and provides DSI bus for panels. > This driver also helps to communicate with its panel using panel > framework. > > Signed-off-by: Venkateshwar Rao Gannavarapu > > --- > drivers/gpu/drm/xlnx/Kconfig| 11 + > drivers/gpu/drm/xlnx/Makefile | 2 + > drivers/gpu/drm/xlnx/xlnx_dsi.c | 755 > > 3 files changed, 768 insertions(+) > create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c > > diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig > index aa6cd88..73873cf 100644 > --- a/drivers/gpu/drm/xlnx/Kconfig > +++ b/drivers/gpu/drm/xlnx/Kconfig > @@ -11,3 +11,14 @@ config DRM_ZYNQMP_DPSUB > This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose > this option if you have a Xilinx ZynqMP SoC with DisplayPort > subsystem. > + > +config DRM_XLNX_DSI > +tristate "Xilinx DRM DSI Subsystem Driver" > +select DRM_MIPI_DSI > +select DRM_PANEL > +select DRM_PANEL_SIMPLE > +help > + This enables support for Xilinx MIPI-DSI. This sentence is not needed with below. Could you please rephrase the whole? > + This is a DRM/KMS driver for Xilinx programmable DSI controller. > + Choose this option if you have a Xilinx MIPI DSI-TX controller > + subsytem. These seem incorrectly indented. > diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile > index 2b844c6..b7ee6ef 100644 > --- a/drivers/gpu/drm/xlnx/Makefile > +++ b/drivers/gpu/drm/xlnx/Makefile > @@ -1,2 +1,4 @@ > zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o > obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o > + > +obj-$(CONFIG_DRM_XLNX_DSI) += xlnx_dsi.o > diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_dsi.c > new file mode 100644 > index 000..b8cae59 > --- /dev/null > +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c > @@ -0,0 +1,755 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx FPGA MIPI DSI Tx Controller driver > + * > + * Copyright (C) 2017 - 2019 Xilinx, Inc. > + * > + * Authors: > + * - Saurabh Sengar > + * - Venkateshwar Rao Gannavarapu > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +/* DSI Tx IP registers */ > +#define XDSI_CCR 0x00 > +#define XDSI_CCR_COREENB BIT(0) > +#define XDSI_CCR_SOFTRST BIT(1) > +#define XDSI_CCR_CRREADY BIT(2) > +#define XDSI_CCR_CMDMODE BIT(3) > +#define XDSI_CCR_DFIFORSTBIT(4) > +#define XDSI_CCR_CMDFIFORST BIT(5) > +#define XDSI_PCR 0x04 > +#define XDSI_PCR_VIDEOMODE(x)(((x) & 0x3) << 3) > +#define XDSI_PCR_VIDEOMODE_MASK (0x3 << 3) > +#define XDSI_PCR_VIDEOMODE_SHIFT 3 > +#define XDSI_PCR_BLLPTYPE(x) ((x) << 5) > +#define XDSI_PCR_BLLPMODE(x) ((x) << 6) > +#define XDSI_PCR_EOTPENABLE(x) ((x) << 13) > +#define XDSI_GIER0x20 > +#define XDSI_ISR 0x24 > +#define XDSI_IER 0x28 > +#define XDSI_STR 0x2C > +#define XDSI_STR_RDY_SHPKT BIT(6) > +#define XDSI_STR_RDY_LNGPKT BIT(7) > +#define XDSI_STR_DFIFO_FULL BIT(8) > +#define XDSI_STR_DFIFO_EMPTY BIT(9) > +#define XDSI_STR_WAITFR_DATA BIT(10) > +#define XDSI_STR_CMD_EXE_PGS BIT(11) > +#define XDSI_STR_CCMD_PROC BIT(12) > +#define XDSI_STR_LPKT_MASK (0x5 << 7) > +#define XDSI_CMD 0x30 > +#define XDSI_CMD_QUEUE_PACKET(x) ((x) & GENMASK(23, 0)) > +#define XDSI_DFR 0x34 > +#define XDSI_TIME1 0x50 > +#define XDSI_TIME1_BLLP_BURST(x) ((x) & GENMASK(15, 0)) > +#define XDSI_TIME1_HSA(x)(((x) & GENMASK(15, 0)) << 16) > +#define XDSI_TIME2 0x54 > +#define XDSI_TIME2_VACT(x) ((x) & GENMASK(15, 0)) > +#define XDSI_TIME2_HACT(x) (((x) & GENMASK(15, 0)) << 16) > +#define XDSI_HACT_MULTIPLIER GENMASK(1, 0) > +#define XDSI_TIME3 0x58 > +#define XDSI_TIME3_HFP(x)((x) & GENMASK(15, 0)) > +#define XDSI_TIME3_HBP(x)(((x) & GENMASK(15, 0)) << 16) > +#define XDSI_TIME4 0x5c > +#define
Re: [PATCH v11 1/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
Hi Sam, On Wed, 2020-03-18 at 12:26:51 -0700, Sam Ravnborg wrote: > On Wed, Mar 18, 2020 at 05:37:24PM +0200, Laurent Pinchart wrote: > > From: Hyun Kwon > > > > The bindings describe the ZynqMP DP subsystem. They don't support the > > interface with the programmable logic (FPGA) or audio yet. > > > > Signed-off-by: Hyun Kwon > > Signed-off-by: Laurent Pinchart > > Reviewed-by: Rob Herring > > Bikeshedding - examples with indent on 4 spaces to make them easier to > read. > > Would it be possible to make this binding: (GPL-2.0-only OR BSD-2-Clause) > This is preferred for new bindings. > In this case asking Hyun Kwon should be enough? It should be possible. But to be safer and if needed, I need to check with corperate policy before I can confirm. Michal, have you already checked about adding 'OR BSD-2-Clause'? or should I take it up to Xilinx legal? Thanks, -hyun > > With or without the suggestions above: > Acked-by: Sam Ravnborg > > Sam > > > --- > > Changes since v10: > > > > - Update example to new PHY DT bindings without subnodes > > - Add resets property > > > > Changes since v9: > > > > - Fix constraints on clock-names > > - Document dp_apb_clk as the APB clock, not the AXI clock > > > > Changes since v8: > > > > - Convert to yaml > > - Rename aclk to dp_apb_clk > > --- > > .../display/xlnx/xlnx,zynqmp-dpsub.yaml | 174 ++ > > 1 file changed, 174 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml > > b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml > > new file mode 100644 > > index ..05e6a14de75c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml > > @@ -0,0 +1,174 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Xilinx ZynqMP DisplayPort Subsystem > > + > > +description: | > > + The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC) > > + implements the display and audio pipelines based on the DisplayPort v1.2 > > + standard. The subsystem includes multiple functional blocks as below: > > + > > + > > ++ > > + ++ | ++ +---+ > > | > > + | DPDMA | --->|| --> | Video | Video > > +-+ | > > + | 4x vid | | || | Rendering | -+--> | > > | | +--+ > > + | 2x aud | | | Audio/Video | --> | Pipeline | || DisplayPort > > |---> | PHY0 | > > + ++ | | Buffer Manager | +---+ || Source > > | | +--+ > > + | |and STC | +---+ || Controller > > | | +--+ > > + Live Video --->|| --> | Audio | Audio | > > |---> | PHY1 | > > + | || | Mixer | --+-> | > > | | +--+ > > + Live Audio --->|| --> | | || > > +-+ | > > + | ++ +---+ || > > | > > + > > +---||---+ > > + vv > > + Blended Video and > > + Mixed Audio to PL > > + > > + The Buffer Manager interacts with external interface such as DMA engines > > or > > + live audio/video streams from the programmable logic. The Video Rendering > > + Pipeline blends the video and graphics layers and performs colorspace > > + conversion. The Audio Mixer mixes the incoming audio streams. The > > DisplayPort > > + Source Controller handles the DisplayPort protocol and connects to > > external > > + PHYs. > > + > > + The subsystem supports 2 video and 2 audio streams, and various pixel > > formats > > + and depths up to 4K@30 resolution. > > + > > + Please refer to "Z
Re: [PATCH v9 2/4] drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem
Hi Laurent, On Fri, 2019-11-08 at 09:13:25 -0800, Laurent Pinchart wrote: > Hi Hyun, > > (CC'ing Daniel, with a question for him below) > > On Fri, Sep 27, 2019 at 05:04:57PM -0700, Hyun Kwon wrote: > > On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wrote: > > > From: Hyun Kwon > > > > > > The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort > > > Subsystem. It includes a buffer manager, a video pipeline renderer > > > (blender), an audio mixer and a DisplayPort source controller > > > (transmitter). The DMA engine the provide data to the buffer manager, as > > > well as the DisplayPort PHYs that drive the lanes, are external to the > > > subsystem and interfaced using the DMA engine and PHY APIs respectively. > > > > > > This driver supports the DisplayPort Subsystem and implements > > > > > > - Two planes, for graphics and video > > > - One CRTC that supports alpha blending > > > - One encoder for the DisplayPort transmitter > > > - One connector for an external monitor > > > > > > It currently doesn't support > > > > > > - Color keying > > > - Test pattern generation > > > - Audio > > > - Live input from the Programmable Logic (FPGA) > > > - Output to the Programmable Logic (FPGA) > > > > > > Signed-off-by: Hyun Kwon > > > Signed-off-by: Laurent Pinchart > > > --- > > > Notable changes since v8: > > > > > > - Rebase on top of v5.3 and update to API changes > > > - Cleanup #include statements > > > - Use the mode config suspend/resume helpers > > > - Remove unused code (macros, fields, functions, ...) > > > - Sort headers and forward declarations alphabetically > > > - Use more standard DRM/KMS helpers (suspend/resume, fbdev, > > > DEFINE_DRM_GEM_CMA_FOPS) > > > - Drop support for half-implemented or unsupported features (sound DT > > > bindings parsing, interface with PL) > > > - Remove the xlnx drm helpers > > > > This will have impact on other downstream drivers, as this is shared layer > > in xlnx tree. > > Right. We may not want to drop them completely, but I don't think > introducing them for this driver is the right thing to do. It's usually > better to start with two drivers and create helpers out of them instead > of creating helpers up-front and making the drivers fit them. > > I can certainly help with the helpers and the other drivers that use > them, but based on what I've seen, there's no code that exposes multiple > CRTCs at the moment, so helpers for this are likely not needed. Or did I > miss something ? You are correct. Initially there was requirement to support that, but i don't see anything coming up that needs multiple CRTCs. So we can put it aside for now. Meanwhile we can confirm if it has to be really supported even in the future. > > > > - Remove some module parameters > > > > The default format module parameter is required to change the fbdev > > format. The fbdev seems widely used in many applications, especially > > along with graphics stack. > > Doesn't fbdev always perform a mode set, and thus override this ? > As far as I remember, the emulated fbdev format is picked at initiliazation time based on bpp / depth, and never changes after all. Maybe it's just me not knowing how to do. The command line mode may work. > > > - Reorganize code in sections, with better separation of operations > > > - Better separation of the encoder from the CRTC > > > - Drop the component framework > > > - Various kerneldoc reworks, with renames of structures, fields and > > > functions > > > - Fix vblank and page flip event handling > > > - Remove hack to disable clocks at startup > > > > Hoepfully, it's fixed in firmware. Previously it wasn't guaranteed > > that the clock is disabled at bootup, because it was one of design > > parameters. Then if the clock rate changed when enabled, it resulted > > in incorrect rate. > > Even if the firmware handles this incorrectly, I think the workaround > should be in the clock driver, not in the dpsub driver. I can try to > handle this on top of the dpsub series. It will require moving to > programmable clocks first though, the upstream ZynqMP DT sources use > fixed clocks. > Ah makes sense. I don't know why I didn't think it that way. There may be some complications to fix in clock driver, such as some clocks shouldn't be disabled, and it's not easy to which ones? We'll figure it out! > > > - Update copyright head
Re: [PATCH v9 2/4] drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem
Hi Laurent, Thanks for the patch. On Wed, 2019-09-25 at 16:55:42 -0700, Laurent Pinchart wrote: > From: Hyun Kwon > > The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort > Subsystem. It includes a buffer manager, a video pipeline renderer > (blender), an audio mixer and a DisplayPort source controller > (transmitter). The DMA engine the provide data to the buffer manager, as > well as the DisplayPort PHYs that drive the lanes, are external to the > subsystem and interfaced using the DMA engine and PHY APIs respectively. > > This driver supports the DisplayPort Subsystem and implements > > - Two planes, for graphics and video > - One CRTC that supports alpha blending > - One encoder for the DisplayPort transmitter > - One connector for an external monitor > > It currently doesn't support > > - Color keying > - Test pattern generation > - Audio > - Live input from the Programmable Logic (FPGA) > - Output to the Programmable Logic (FPGA) > > Signed-off-by: Hyun Kwon > Signed-off-by: Laurent Pinchart > --- > Notable changes since v8: > > - Rebase on top of v5.3 and update to API changes > - Cleanup #include statements > - Use the mode config suspend/resume helpers > - Remove unused code (macros, fields, functions, ...) > - Sort headers and forward declarations alphabetically > - Use more standard DRM/KMS helpers (suspend/resume, fbdev, > DEFINE_DRM_GEM_CMA_FOPS) > - Drop support for half-implemented or unsupported features (sound DT > bindings parsing, interface with PL) > - Remove the xlnx drm helpers This will have impact on other downstream drivers, as this is shared layer in xlnx tree. > - Remove some module parameters The default format module parameter is required to change the fbdev format. The fbdev seems widely used in many applications, especially along with graphics stack. > - Reorganize code in sections, with better separation of operations > - Better separation of the encoder from the CRTC > - Drop the component framework > - Various kerneldoc reworks, with renames of structures, fields and > functions > - Fix vblank and page flip event handling > - Remove hack to disable clocks at startup Hoepfully, it's fixed in firmware. Previously it wasn't guaranteed that the clock is disabled at bootup, because it was one of design parameters. Then if the clock rate changed when enabled, it resulted in incorrect rate. > - Update copyright headers > - Move checks from atomic commit time to atomic check time > - Remove partial support for the TPG > - Remove partial support for live inputs > - Remove async update support All above 3 are actually requested features / fixes. > - Clean up DP TX initialisation and cleanup > --- > MAINTAINERS |9 + > drivers/gpu/drm/Kconfig |2 + > drivers/gpu/drm/Makefile|1 + > drivers/gpu/drm/xlnx/Kconfig| 13 + > drivers/gpu/drm/xlnx/Makefile |2 + > drivers/gpu/drm/xlnx/zynqmp_disp.c | 1678 +++ > drivers/gpu/drm/xlnx/zynqmp_disp.h | 43 + > drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 201 +++ > drivers/gpu/drm/xlnx/zynqmp_dp.c| 1677 ++ > drivers/gpu/drm/xlnx/zynqmp_dp.h| 29 + > drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 331 + > drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 48 + > 12 files changed, 4034 insertions(+) > create mode 100644 drivers/gpu/drm/xlnx/Kconfig > create mode 100644 drivers/gpu/drm/xlnx/Makefile > create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c > create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h > create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp_regs.h > create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c [snip] > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > index 9f0d2ee35794..eb91cfdac13a 100644 > --- a/drivers/gpu/drm/Makefile > +++ b/drivers/gpu/drm/Makefile > @@ -120,3 +120,4 @@ obj-$(CONFIG_DRM_LIMA) += lima/ > obj-$(CONFIG_DRM_PANFROST) += panfrost/ > obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ > obj-$(CONFIG_DRM_MCDE) += mcde/ > +obj-y+= xlnx/ > diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig > new file mode 100644 > index ..aa6cd889bd11 > --- /dev/null > +++ b/drivers/gpu/drm/xlnx/Kconfig > @@ -0,0 +1,13 @@ > +config DRM_ZYNQMP_DPSUB > + tristate "ZynqMP DisplayPort Controller Driver" > + depends on ARCH_ZYNQMP || COMPILE_TEST > + depends on COMMON_CLK && DRM && OF > + select DMA_ENGINE > + select DRM_GEM_CMA_HELPER > + select DRM_KMS_CMA_HELPER > + select DRM_KMS_HELPER > + select G
Re: [PATCH RFC 1/1] uio: Add dma-buf import ioctls
Hi Daniel, On Thu, 2019-02-28 at 02:01:46 -0800, Daniel Vetter wrote: > On Wed, Feb 27, 2019 at 04:36:06PM -0800, Hyun Kwon wrote: > > Hi Daniel, > > > > On Wed, 2019-02-27 at 06:13:45 -0800, Daniel Vetter wrote: > > > On Tue, Feb 26, 2019 at 11:20 PM Hyun Kwon wrote: > > > > > > > > Hi Daniel, > > > > > > > > Thanks for the comment. > > > > > > > > On Tue, 2019-02-26 at 04:06:13 -0800, Daniel Vetter wrote: > > > > > On Tue, Feb 26, 2019 at 12:53 PM Greg Kroah-Hartman > > > > > wrote: > > > > > > > > > > > > On Sat, Feb 23, 2019 at 12:28:17PM -0800, Hyun Kwon wrote: > > > > > > > Add the dmabuf map / unmap interfaces. This allows the user driver > > > > > > > to be able to import the external dmabuf and use it from user > > > > > > > space. > > > > > > > > > > > > > > Signed-off-by: Hyun Kwon > > > > > > > --- > > > > > > > drivers/uio/Makefile | 2 +- > > > > > > > drivers/uio/uio.c| 43 + > > > > > > > drivers/uio/uio_dmabuf.c | 210 > > > > > > > +++ > > > > > > > drivers/uio/uio_dmabuf.h | 26 ++ > > > > > > > include/uapi/linux/uio/uio.h | 33 +++ > > > > > > > 5 files changed, 313 insertions(+), 1 deletion(-) > > > > > > > create mode 100644 drivers/uio/uio_dmabuf.c > > > > > > > create mode 100644 drivers/uio/uio_dmabuf.h > > > > > > > create mode 100644 include/uapi/linux/uio/uio.h > > > > > > > > > > > > > > diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile > > > > > > > index c285dd2..5da16c7 100644 > > > > > > > --- a/drivers/uio/Makefile > > > > > > > +++ b/drivers/uio/Makefile > > > > > > > @@ -1,5 +1,5 @@ [snip] > > > > > Frankly looks like a ploy to sidestep review by graphics folks. We'd > > > > > ask for the userspace first :-) > > > > > > > > Please refer to pull request [1]. > > > > > > > > For any interest in more details, the libmetal is the abstraction layer > > > > which provides platform independent APIs. The backend implementation > > > > can be selected per different platforms: ex, rtos, linux, > > > > standalone (xilinx),,,. For Linux, it supports UIO / vfio as of now. > > > > The actual user space drivers sit on top of libmetal. Such drivers can > > > > be > > > > found in [2]. This is why I try to avoid any device specific code in > > > > Linux kernel. > > > > > > > > > > > > > > Also, exporting dma_addr to userspace is considered a very bad idea. > > > > > > > > I agree, hence the RFC to pick some brains. :-) Would it make sense > > > > if this call doesn't export the physicall address, but instead takes > > > > only the dmabuf fd and register offsets to be programmed? > > > > > > > > > If you want to do this properly, you need a minimal in-kernel memory > > > > > manager, and those tend to be based on top of drm_gem.c and merged > > > > > through the gpu tree. The last place where we accidentally leaked a > > > > > dma addr for gpu buffers was in the fbdev code, and we plugged that > > > > > one with > > > > > > > > Could you please help me understand how having a in-kernel memory > > > > manager > > > > helps? Isn't it just moving same dmabuf import / paddr export > > > > functionality > > > > in different modules: kernel memory manager vs uio. In fact, Xilinx > > > > does have > > > > such memory manager based on drm gem in downstream. But for this time > > > > we took > > > > the approach of implementing this through generic dmabuf allocator, > > > > ION, and > > > > enabling the import capability in the UIO infrastructure instead. > > > > > > There's a group of people working on upstreaming a xilinx drm driver > > > already. Which driver are we talking about? Can you pls provide a link > > > to that xilinx drm driver? > > > > > > > The one I was pushing [1] is implemented purely for display, and not > >
Re: [PATCH RFC 1/1] uio: Add dma-buf import ioctls
Hi Daniel,
On Wed, 2019-02-27 at 06:13:45 -0800, Daniel Vetter wrote:
> On Tue, Feb 26, 2019 at 11:20 PM Hyun Kwon wrote:
> >
> > Hi Daniel,
> >
> > Thanks for the comment.
> >
> > On Tue, 2019-02-26 at 04:06:13 -0800, Daniel Vetter wrote:
> > > On Tue, Feb 26, 2019 at 12:53 PM Greg Kroah-Hartman
> > > wrote:
> > > >
> > > > On Sat, Feb 23, 2019 at 12:28:17PM -0800, Hyun Kwon wrote:
> > > > > Add the dmabuf map / unmap interfaces. This allows the user driver
> > > > > to be able to import the external dmabuf and use it from user space.
> > > > >
> > > > > Signed-off-by: Hyun Kwon
> > > > > ---
> > > > > drivers/uio/Makefile | 2 +-
> > > > > drivers/uio/uio.c| 43 +
> > > > > drivers/uio/uio_dmabuf.c | 210
> > > > > +++
> > > > > drivers/uio/uio_dmabuf.h | 26 ++
> > > > > include/uapi/linux/uio/uio.h | 33 +++
> > > > > 5 files changed, 313 insertions(+), 1 deletion(-)
> > > > > create mode 100644 drivers/uio/uio_dmabuf.c
> > > > > create mode 100644 drivers/uio/uio_dmabuf.h
> > > > > create mode 100644 include/uapi/linux/uio/uio.h
> > > > >
> > > > > diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
> > > > > index c285dd2..5da16c7 100644
> > > > > --- a/drivers/uio/Makefile
> > > > > +++ b/drivers/uio/Makefile
> > > > > @@ -1,5 +1,5 @@
> > > > > # SPDX-License-Identifier: GPL-2.0
> > > > > -obj-$(CONFIG_UIO)+= uio.o
> > > > > +obj-$(CONFIG_UIO)+= uio.o uio_dmabuf.o
> > > > > obj-$(CONFIG_UIO_CIF)+= uio_cif.o
> > > > > obj-$(CONFIG_UIO_PDRV_GENIRQ)+= uio_pdrv_genirq.o
> > > > > obj-$(CONFIG_UIO_DMEM_GENIRQ)+= uio_dmem_genirq.o
> > > > > diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
> > > > > index 1313422..6841f98 100644
> > > > > --- a/drivers/uio/uio.c
> > > > > +++ b/drivers/uio/uio.c
> > > > > @@ -24,6 +24,12 @@
> > > > > #include
> > > > > #include
> > > > > #include
> > > > > +#include
> > > > > +#include
> > > > > +
> > > > > +#include
> > > > > +
> > > > > +#include "uio_dmabuf.h"
> > > > >
> > > > > #define UIO_MAX_DEVICES (1U << MINORBITS)
> > > > >
> > > > > @@ -454,6 +460,8 @@ static irqreturn_t uio_interrupt(int irq, void
> > > > > *dev_id)
> > > > > struct uio_listener {
> > > > > struct uio_device *dev;
> > > > > s32 event_count;
> > > > > + struct list_head dbufs;
> > > > > + struct mutex dbufs_lock; /* protect @dbufs */
> > > > > };
> > > > >
> > > > > static int uio_open(struct inode *inode, struct file *filep)
> > > > > @@ -500,6 +508,9 @@ static int uio_open(struct inode *inode, struct
> > > > > file *filep)
> > > > > if (ret)
> > > > > goto err_infoopen;
> > > > >
> > > > > + INIT_LIST_HEAD(>dbufs);
> > > > > + mutex_init(>dbufs_lock);
> > > > > +
> > > > > return 0;
> > > > >
> > > > > err_infoopen:
> > > > > @@ -529,6 +540,10 @@ static int uio_release(struct inode *inode,
> > > > > struct file *filep)
> > > > > struct uio_listener *listener = filep->private_data;
> > > > > struct uio_device *idev = listener->dev;
> > > > >
> > > > > + ret = uio_dmabuf_cleanup(idev, >dbufs,
> > > > > >dbufs_lock);
> > > > > + if (ret)
> > > > > + dev_err(>dev, "failed to clean up the dma
> > > > > bufs\n");
> > > > > +
> > > > > mutex_lock(>info_lock);
> > > > > if (idev->info && idev->info->release)
> > > > > ret = idev->info->release(idev->info, inode);
> > > > > @@ -652,6 +667,33 @@ static ssize_t uio_write(struct file *filep,
> > > > > const char __user *
Re: [PATCH RFC 1/1] uio: Add dma-buf import ioctls
Hi Daniel,
Thanks for the comment.
On Tue, 2019-02-26 at 04:06:13 -0800, Daniel Vetter wrote:
> On Tue, Feb 26, 2019 at 12:53 PM Greg Kroah-Hartman
> wrote:
> >
> > On Sat, Feb 23, 2019 at 12:28:17PM -0800, Hyun Kwon wrote:
> > > Add the dmabuf map / unmap interfaces. This allows the user driver
> > > to be able to import the external dmabuf and use it from user space.
> > >
> > > Signed-off-by: Hyun Kwon
> > > ---
> > > drivers/uio/Makefile | 2 +-
> > > drivers/uio/uio.c| 43 +
> > > drivers/uio/uio_dmabuf.c | 210
> > > +++
> > > drivers/uio/uio_dmabuf.h | 26 ++
> > > include/uapi/linux/uio/uio.h | 33 +++
> > > 5 files changed, 313 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/uio/uio_dmabuf.c
> > > create mode 100644 drivers/uio/uio_dmabuf.h
> > > create mode 100644 include/uapi/linux/uio/uio.h
> > >
> > > diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
> > > index c285dd2..5da16c7 100644
> > > --- a/drivers/uio/Makefile
> > > +++ b/drivers/uio/Makefile
> > > @@ -1,5 +1,5 @@
> > > # SPDX-License-Identifier: GPL-2.0
> > > -obj-$(CONFIG_UIO)+= uio.o
> > > +obj-$(CONFIG_UIO)+= uio.o uio_dmabuf.o
> > > obj-$(CONFIG_UIO_CIF)+= uio_cif.o
> > > obj-$(CONFIG_UIO_PDRV_GENIRQ)+= uio_pdrv_genirq.o
> > > obj-$(CONFIG_UIO_DMEM_GENIRQ)+= uio_dmem_genirq.o
> > > diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
> > > index 1313422..6841f98 100644
> > > --- a/drivers/uio/uio.c
> > > +++ b/drivers/uio/uio.c
> > > @@ -24,6 +24,12 @@
> > > #include
> > > #include
> > > #include
> > > +#include
> > > +#include
> > > +
> > > +#include
> > > +
> > > +#include "uio_dmabuf.h"
> > >
> > > #define UIO_MAX_DEVICES (1U << MINORBITS)
> > >
> > > @@ -454,6 +460,8 @@ static irqreturn_t uio_interrupt(int irq, void
> > > *dev_id)
> > > struct uio_listener {
> > > struct uio_device *dev;
> > > s32 event_count;
> > > + struct list_head dbufs;
> > > + struct mutex dbufs_lock; /* protect @dbufs */
> > > };
> > >
> > > static int uio_open(struct inode *inode, struct file *filep)
> > > @@ -500,6 +508,9 @@ static int uio_open(struct inode *inode, struct file
> > > *filep)
> > > if (ret)
> > > goto err_infoopen;
> > >
> > > + INIT_LIST_HEAD(>dbufs);
> > > + mutex_init(>dbufs_lock);
> > > +
> > > return 0;
> > >
> > > err_infoopen:
> > > @@ -529,6 +540,10 @@ static int uio_release(struct inode *inode, struct
> > > file *filep)
> > > struct uio_listener *listener = filep->private_data;
> > > struct uio_device *idev = listener->dev;
> > >
> > > + ret = uio_dmabuf_cleanup(idev, >dbufs,
> > > >dbufs_lock);
> > > + if (ret)
> > > + dev_err(>dev, "failed to clean up the dma bufs\n");
> > > +
> > > mutex_lock(>info_lock);
> > > if (idev->info && idev->info->release)
> > > ret = idev->info->release(idev->info, inode);
> > > @@ -652,6 +667,33 @@ static ssize_t uio_write(struct file *filep, const
> > > char __user *buf,
> > > return retval ? retval : sizeof(s32);
> > > }
> > >
> > > +static long uio_ioctl(struct file *filep, unsigned int cmd, unsigned
> > > long arg)
> >
> > We have resisted adding a uio ioctl for a long time, can't you do this
> > through sysfs somehow?
> >
> > A meta-comment about your ioctl structure:
> >
> > > +#define UIO_DMABUF_DIR_BIDIR 1
> > > +#define UIO_DMABUF_DIR_TO_DEV2
> > > +#define UIO_DMABUF_DIR_FROM_DEV 3
> > > +#define UIO_DMABUF_DIR_NONE 4
> >
> > enumerated type?
> >
> > > +
> > > +struct uio_dmabuf_args {
> > > + __s32 dbuf_fd;
> > > + __u64 dma_addr;
> > > + __u64 size;
> > > + __u32 dir;
> >
> > Why the odd alignment? Are you sure this is the best packing for such a
> > structure?
> >
> > Why is dbuf_fd __s32? dir can be __u8, right?
> >
> >
Re: [PATCH RFC 1/1] uio: Add dma-buf import ioctls
Hi Greg,
Thanks for the comments.
On Tue, 2019-02-26 at 03:53:11 -0800, Greg Kroah-Hartman wrote:
> On Sat, Feb 23, 2019 at 12:28:17PM -0800, Hyun Kwon wrote:
> > Add the dmabuf map / unmap interfaces. This allows the user driver
> > to be able to import the external dmabuf and use it from user space.
> >
> > Signed-off-by: Hyun Kwon
> > ---
> > drivers/uio/Makefile | 2 +-
> > drivers/uio/uio.c| 43 +
> > drivers/uio/uio_dmabuf.c | 210
> > +++
> > drivers/uio/uio_dmabuf.h | 26 ++
> > include/uapi/linux/uio/uio.h | 33 +++
> > 5 files changed, 313 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/uio/uio_dmabuf.c
> > create mode 100644 drivers/uio/uio_dmabuf.h
> > create mode 100644 include/uapi/linux/uio/uio.h
> >
> > diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
> > index c285dd2..5da16c7 100644
> > --- a/drivers/uio/Makefile
> > +++ b/drivers/uio/Makefile
> > @@ -1,5 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0
> > -obj-$(CONFIG_UIO) += uio.o
> > +obj-$(CONFIG_UIO) += uio.o uio_dmabuf.o
> > obj-$(CONFIG_UIO_CIF) += uio_cif.o
> > obj-$(CONFIG_UIO_PDRV_GENIRQ) += uio_pdrv_genirq.o
> > obj-$(CONFIG_UIO_DMEM_GENIRQ) += uio_dmem_genirq.o
> > diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
> > index 1313422..6841f98 100644
> > --- a/drivers/uio/uio.c
> > +++ b/drivers/uio/uio.c
> > @@ -24,6 +24,12 @@
> > #include
> > #include
> > #include
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +#include "uio_dmabuf.h"
> >
> > #define UIO_MAX_DEVICES(1U << MINORBITS)
> >
> > @@ -454,6 +460,8 @@ static irqreturn_t uio_interrupt(int irq, void *dev_id)
> > struct uio_listener {
> > struct uio_device *dev;
> > s32 event_count;
> > + struct list_head dbufs;
> > + struct mutex dbufs_lock; /* protect @dbufs */
> > };
> >
> > static int uio_open(struct inode *inode, struct file *filep)
> > @@ -500,6 +508,9 @@ static int uio_open(struct inode *inode, struct file
> > *filep)
> > if (ret)
> > goto err_infoopen;
> >
> > + INIT_LIST_HEAD(>dbufs);
> > + mutex_init(>dbufs_lock);
> > +
> > return 0;
> >
> > err_infoopen:
> > @@ -529,6 +540,10 @@ static int uio_release(struct inode *inode, struct
> > file *filep)
> > struct uio_listener *listener = filep->private_data;
> > struct uio_device *idev = listener->dev;
> >
> > + ret = uio_dmabuf_cleanup(idev, >dbufs, >dbufs_lock);
> > + if (ret)
> > + dev_err(>dev, "failed to clean up the dma bufs\n");
> > +
> > mutex_lock(>info_lock);
> > if (idev->info && idev->info->release)
> > ret = idev->info->release(idev->info, inode);
> > @@ -652,6 +667,33 @@ static ssize_t uio_write(struct file *filep, const
> > char __user *buf,
> > return retval ? retval : sizeof(s32);
> > }
> >
> > +static long uio_ioctl(struct file *filep, unsigned int cmd, unsigned long
> > arg)
>
> We have resisted adding a uio ioctl for a long time, can't you do this
> through sysfs somehow?
>
The dmabuf is managed as per process resource, so it's hard to do it through
sysfs.
> A meta-comment about your ioctl structure:
>
> > +#define UIO_DMABUF_DIR_BIDIR 1
> > +#define UIO_DMABUF_DIR_TO_DEV 2
> > +#define UIO_DMABUF_DIR_FROM_DEV3
> > +#define UIO_DMABUF_DIR_NONE4
>
> enumerated type?
>
> > +
> > +struct uio_dmabuf_args {
> > + __s32 dbuf_fd;
> > + __u64 dma_addr;
> > + __u64 size;
> > + __u32 dir;
>
> Why the odd alignment? Are you sure this is the best packing for such a
> structure?
>
> Why is dbuf_fd __s32? dir can be __u8, right?
The dmabuf fd is defined as int, so __s32 seems correct. Please let me know
otherwise. The dir can be __u8. Will fix if there is v2 at all.
>
> I don't know that dma layer very well, it would be good to get some
> review from others to see if this really is even a viable thing to do.
> The fd handling seems a bit "odd" here, but maybe I just do not
> understand it.
Agreed. So I'm looking forward to feedback or if there's more sensible
alternative.
Thanks,
-hyun
>
> thanks,
>
> greg k-h
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[PATCH RFC 1/1] uio: Add dma-buf import ioctls
Add the dmabuf map / unmap interfaces. This allows the user driver
to be able to import the external dmabuf and use it from user space.
Signed-off-by: Hyun Kwon
---
drivers/uio/Makefile | 2 +-
drivers/uio/uio.c| 43 +
drivers/uio/uio_dmabuf.c | 210 +++
drivers/uio/uio_dmabuf.h | 26 ++
include/uapi/linux/uio/uio.h | 33 +++
5 files changed, 313 insertions(+), 1 deletion(-)
create mode 100644 drivers/uio/uio_dmabuf.c
create mode 100644 drivers/uio/uio_dmabuf.h
create mode 100644 include/uapi/linux/uio/uio.h
diff --git a/drivers/uio/Makefile b/drivers/uio/Makefile
index c285dd2..5da16c7 100644
--- a/drivers/uio/Makefile
+++ b/drivers/uio/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_UIO) += uio.o
+obj-$(CONFIG_UIO) += uio.o uio_dmabuf.o
obj-$(CONFIG_UIO_CIF) += uio_cif.o
obj-$(CONFIG_UIO_PDRV_GENIRQ) += uio_pdrv_genirq.o
obj-$(CONFIG_UIO_DMEM_GENIRQ) += uio_dmem_genirq.o
diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
index 1313422..6841f98 100644
--- a/drivers/uio/uio.c
+++ b/drivers/uio/uio.c
@@ -24,6 +24,12 @@
#include
#include
#include
+#include
+#include
+
+#include
+
+#include "uio_dmabuf.h"
#define UIO_MAX_DEVICES(1U << MINORBITS)
@@ -454,6 +460,8 @@ static irqreturn_t uio_interrupt(int irq, void *dev_id)
struct uio_listener {
struct uio_device *dev;
s32 event_count;
+ struct list_head dbufs;
+ struct mutex dbufs_lock; /* protect @dbufs */
};
static int uio_open(struct inode *inode, struct file *filep)
@@ -500,6 +508,9 @@ static int uio_open(struct inode *inode, struct file *filep)
if (ret)
goto err_infoopen;
+ INIT_LIST_HEAD(>dbufs);
+ mutex_init(>dbufs_lock);
+
return 0;
err_infoopen:
@@ -529,6 +540,10 @@ static int uio_release(struct inode *inode, struct file
*filep)
struct uio_listener *listener = filep->private_data;
struct uio_device *idev = listener->dev;
+ ret = uio_dmabuf_cleanup(idev, >dbufs, >dbufs_lock);
+ if (ret)
+ dev_err(>dev, "failed to clean up the dma bufs\n");
+
mutex_lock(>info_lock);
if (idev->info && idev->info->release)
ret = idev->info->release(idev->info, inode);
@@ -652,6 +667,33 @@ static ssize_t uio_write(struct file *filep, const char
__user *buf,
return retval ? retval : sizeof(s32);
}
+static long uio_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
+{
+ struct uio_listener *listener = filep->private_data;
+ struct uio_device *idev = listener->dev;
+ long ret;
+
+ if (!idev->info)
+ return -EIO;
+
+ switch (cmd) {
+ case UIO_IOC_MAP_DMABUF:
+ ret = uio_dmabuf_map(idev, >dbufs,
+>dbufs_lock, (void __user *)arg);
+ break;
+ case UIO_IOC_UNMAP_DMABUF:
+ ret = uio_dmabuf_unmap(idev, >dbufs,
+ >dbufs_lock,
+ (void __user *)arg);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
static int uio_find_mem_index(struct vm_area_struct *vma)
{
struct uio_device *idev = vma->vm_private_data;
@@ -821,6 +863,7 @@ static const struct file_operations uio_fops = {
.write = uio_write,
.mmap = uio_mmap,
.poll = uio_poll,
+ .unlocked_ioctl = uio_ioctl,
.fasync = uio_fasync,
.llseek = noop_llseek,
};
diff --git a/drivers/uio/uio_dmabuf.c b/drivers/uio/uio_dmabuf.c
new file mode 100644
index 000..b18f146
--- /dev/null
+++ b/drivers/uio/uio_dmabuf.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon
+ *
+ * DMA buf support for UIO device
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "uio_dmabuf.h"
+
+struct uio_dmabuf_mem {
+ int dbuf_fd;
+ struct dma_buf *dbuf;
+ struct dma_buf_attachment *dbuf_attach;
+ struct sg_table *sgt;
+ enum dma_data_direction dir;
+ struct list_head list;
+};
+
+long uio_dmabuf_map(struct uio_device *dev, struct list_head *dbufs,
+ struct mutex *dbufs_lock, void __user *user_args)
+{
+ struct uio_dmabuf_args args;
+ struct uio_dmabuf_mem *dbuf_mem;
+ struct dma_buf *dbuf;
+ struct dma_buf_attachment *dbuf_attach;
+ enum dma_data_direction dir;
+ struct sg_table *sgt;
+ long ret;
+
+ if (copy_from_user(, user_args, sizeof(args))) {
+ ret = -EFAULT;
+ dev_err(de
[PATCH RFC 0/1] uio: Add dmabuf import ioctl
Hi, I'm looking to enable platform independent device driver stacks on Linux. Currently, I have some driver built on top of Linux UIO [1], and possibly there can be more of such drivers: ex, soft IP drivers programmed on FPGA. Some device includes data movers such as DMA, and that requires some mechanism to import external buffers and program the data movers from user space. Thus this patch set adds a couple of ioctls to import the dmabuf and return required information back to user. This allows the user drivers to use dmabuf compatible external buffers: ex, it's tested with ION allocator. I'd like to understand if this is right approach which can be used to develop the user space software stacks further, especially because - adding new ioctls to generic uio - security concerns from exposing low level information: dma addr For example, vfio isn't option as iommu may not be available for all such devices on all platforms. So any feedback to move forward would be appreciated. Thanks, -hyun [1] https://patchwork.kernel.org/patch/10774761/ Hyun Kwon (1): uio: Add dma-buf import ioctls drivers/uio/Makefile | 2 +- drivers/uio/uio.c| 43 + drivers/uio/uio_dmabuf.c | 210 +++ drivers/uio/uio_dmabuf.h | 26 ++ include/uapi/linux/uio/uio.h | 33 +++ 5 files changed, 313 insertions(+), 1 deletion(-) create mode 100644 drivers/uio/uio_dmabuf.c create mode 100644 drivers/uio/uio_dmabuf.h create mode 100644 include/uapi/linux/uio/uio.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 0/1] staging: android: ion: add the GPL exception note to header
Hi, I wonder if the exception, "WITH Linux-syscall-note", can be added to the ion header license, to allow user source code with different license to include it without being derivative of GPL. More specifically, we want to use this ion header in a BSD license module [1], without enforcing the GPL license on its users or on the module itself when it has a copy of the header in its source code. Any guide on what can be done would be appreciated. Thanks, -hyun [1] https://github.com/OpenAMP/libmetal/blob/master/LICENSE.md Hyun Kwon (1): staging: android: ion: Add the GPL exception for syscalls drivers/staging/android/uapi/ion.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/1] staging: android: ion: Add the GPL exception for syscalls
Add "WITH Linux-syscall-note" to the license to not put GPL restrictions on user space programs using this header. Signed-off-by: Hyun Kwon --- drivers/staging/android/uapi/ion.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/android/uapi/ion.h b/drivers/staging/android/uapi/ion.h index 5d70098..46c93fc 100644 --- a/drivers/staging/android/uapi/ion.h +++ b/drivers/staging/android/uapi/ion.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * drivers/staging/android/uapi/ion.h * -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH libdrm 1/3] tests: util: pattern: Use 64bit RGB samples
Use of 32bit RGB samples, where each component is 8bit, cannot
support formats with components greater than 8bit (ex, XRGB2101010).
Introduce MAKE_RGBA_64() which creates pixels from a 64bit sample.
Each component in a 64bit sample is 16bit long, thus a pixel with 10bit
components can be generated correctly.
MAKE_RGBA() can use MAKE_RGBA_64() by scaling each 8bit component
to 16bit, for compatilbity.
Signed-off-by: Hyun Kwon
---
tests/util/pattern.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index 9fa0a41..aa067c9 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -60,11 +60,17 @@ struct color_yuv {
.u = MAKE_YUV_601_U(r, g, b), \
.v = MAKE_YUV_601_V(r, g, b) }
+#define COLOR_MASK(value, color) \
+ ((value & ((1 << (color).length) - 1)) << (color).offset)
+
+#define MAKE_RGBA_64(rgb, r, g, b, a) \
+ (COLOR_MASK(((r) >> (16 - (rgb)->red.length)), (rgb)->red) | \
+COLOR_MASK(((g) >> (16 - (rgb)->green.length)), (rgb)->green) | \
+COLOR_MASK(((b) >> (16 - (rgb)->blue.length)), (rgb)->blue) | \
+COLOR_MASK(((a) >> (16 - (rgb)->alpha.length)), (rgb)->alpha))
+
#define MAKE_RGBA(rgb, r, g, b, a) \
- r) >> (8 - (rgb)->red.length)) << (rgb)->red.offset) | \
-(((g) >> (8 - (rgb)->green.length)) << (rgb)->green.offset) | \
-(((b) >> (8 - (rgb)->blue.length)) << (rgb)->blue.offset) | \
-(((a) >> (8 - (rgb)->alpha.length)) << (rgb)->alpha.offset))
+ MAKE_RGBA_64(rgb, (r) * 0x101, (g) * 0x101, (b) * 0x101, (a) * 0x101)
#define MAKE_RGB24(rgb, r, g, b) \
{ .value = MAKE_RGBA(rgb, r, g, b, 0) }
--
2.7.4
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[PATCH libdrm 0/3] Enable more formats in modetest
Hi, This is a reminder of previously submitted patch [1]. The set is just rebased on the lastet master branch, but nothing still changed. This set adds more formats for modetest, including fixes for 10bit RGB formats and adding 422/444 YUV formats. Thanks, -hyun [1] https://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg219340.html Hyun Kwon (3): tests: util: pattern: Use 64bit RGB samples modetest: Add support for YUV422 and YUV444 tests: util: Add support for YUV422 and YUV444 tests/modetest/buffers.c | 29 ++--- tests/util/format.c | 4 tests/util/pattern.c | 22 ++ 3 files changed, 48 insertions(+), 7 deletions(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH libdrm 2/3] modetest: Add support for YUV422 and YUV444
This allows dumb buffer allocation for YUV422 and YUV444 with correct
subsampling values.
Signed-off-by: Hyun Kwon
---
tests/modetest/buffers.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
index 9b635c0..769399e 100644
--- a/tests/modetest/buffers.c
+++ b/tests/modetest/buffers.c
@@ -127,7 +127,7 @@ bo_create(int fd, unsigned int format,
unsigned int handles[4], unsigned int pitches[4],
unsigned int offsets[4], enum util_fill_pattern pattern)
{
- unsigned int virtual_height;
+ unsigned int virtual_height, hsub, vsub;
struct bo *bo;
unsigned int bpp;
void *planes[3] = { 0, };
@@ -141,6 +141,10 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_NV61:
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
bpp = 8;
break;
@@ -204,15 +208,30 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
virtual_height = height * 3 / 2;
+ hsub = 2;
+ vsub = 2;
break;
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
virtual_height = height * 2;
+ hsub = 2;
+ vsub = 1;
+ break;
+
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
+ virtual_height = height * 3;
+ hsub = 1;
+ vsub = 1;
break;
default:
virtual_height = height;
+ hsub = 1;
+ vsub = 1;
break;
}
@@ -260,14 +279,18 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
offsets[0] = 0;
handles[0] = bo->handle;
pitches[0] = bo->pitch;
- pitches[1] = pitches[0] / 2;
+ pitches[1] = pitches[0] / hsub;
offsets[1] = pitches[0] * height;
handles[1] = bo->handle;
pitches[2] = pitches[1];
- offsets[2] = offsets[1] + pitches[1] * height / 2;
+ offsets[2] = offsets[1] + pitches[1] * height / vsub;
handles[2] = bo->handle;
planes[0] = virtual;
--
2.7.4
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[PATCH libdrm 3/3] tests: util: Add support for YUV422 and YUV444
Enable YUV422 and YUV444 formats by adding to the format table
and pattern generation calls.
Signed-off-by: Hyun Kwon
---
tests/util/format.c | 4
tests/util/pattern.c | 8
2 files changed, 12 insertions(+)
diff --git a/tests/util/format.c b/tests/util/format.c
index 15ac5e1..b48594c 100644
--- a/tests/util/format.c
+++ b/tests/util/format.c
@@ -52,6 +52,10 @@ static const struct util_format_info format_info[] = {
/* YUV planar */
{ DRM_FORMAT_YUV420, "YU12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 1) },
{ DRM_FORMAT_YVU420, "YV12", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 1) },
+ { DRM_FORMAT_YUV422, "YU16", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 1) },
+ { DRM_FORMAT_YVU422, "YV16", MAKE_YUV_INFO(YUV_YCrCb, 2, 1, 1) },
+ { DRM_FORMAT_YUV444, "YU24", MAKE_YUV_INFO(YUV_YCbCr, 1, 1, 1) },
+ { DRM_FORMAT_YVU444, "YV24", MAKE_YUV_INFO(YUV_YCrCb, 1, 1, 1) },
/* RGB16 */
{ DRM_FORMAT_ARGB, "AR12", MAKE_RGB_INFO(4, 8, 4, 4, 4, 0, 4, 12) },
{ DRM_FORMAT_XRGB, "XR12", MAKE_RGB_INFO(4, 8, 4, 4, 4, 0, 0, 0) },
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index aa067c9..2805724 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -487,10 +487,14 @@ static void fill_smpte(const struct util_format_info
*info, void *planes[3],
width, height, stride);
case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YUV444:
return fill_smpte_yuv_planar(>yuv, planes[0], planes[1],
planes[2], width, height, stride);
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YVU444:
return fill_smpte_yuv_planar(>yuv, planes[0], planes[2],
planes[1], width, height, stride);
@@ -772,10 +776,14 @@ static void fill_tiles(const struct util_format_info
*info, void *planes[3],
width, height, stride);
case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YUV444:
return fill_tiles_yuv_planar(info, planes[0], planes[1],
planes[2], width, height, stride);
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YVU444:
return fill_tiles_yuv_planar(info, planes[0], planes[2],
planes[1], width, height, stride);
--
2.7.4
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[PATCH v8 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
Xilinx ZynqMP has a hardened display pipeline. The pipeline can
be logically partitioned into 2 parts: display controller and
DisplayPort encoder / transmitter. This driver handles the display
controller part of the pipeline that handles buffer management and
blending.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v8
- Added a module param to specify the initial format for fbdev
- Don't update the plane for the same fb
v7
- Disable a plane when the fb format changes
- Update planes asynchronously in the legacy set plane entry
v6
- Use the new crtc op struct
- Clean up the duplicated license paragraphs
- Declare function pointer structures as static const
- Do complete forward declaration in headers
v4
- Use drm_crtc_funcs for vblank
- Remove child nodes for layer
v3
- Fix a small typo
v2
- Use drm_fb_cma_get_gem_addr()
- Use drm_crtc_arm_vblank_event()
- Split drm properties into a separate patch
- Remove dummy funcs
- Don't add offset as it's already done by a new helper
- Change the SPDX identifier format
- Minor change of a commit message
---
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 2777
drivers/gpu/drm/xlnx/zynqmp_disp.h | 29 +
2 files changed, 2806 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
new file mode 100644
index 000..de5c4a2
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -0,0 +1,2777 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP Display Controller Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "xlnx_crtc.h"
+#include "xlnx_fb.h"
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+/*
+ * Overview
+ *
+ *
+ * The display part of ZynqMP DP subsystem. Internally, the device
+ * is partitioned into 3 blocks: AV buffer manager, Blender, Audio.
+ * The driver creates the DRM crtc and plane objectes and maps the DRM
+ * interface into those 3 blocks. In high level, the driver is layered
+ * in the following way:
+ *
+ * zynqmp_disp_crtc & zynqmp_disp_plane
+ * |->zynqmp_disp
+ * |->zynqmp_disp_aud
+ * |->zynqmp_disp_blend
+ * |->zynqmp_disp_av_buf
+ *
+ * The driver APIs are used externally by
+ * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver
+ * - zynqmp_dp: ZynqMP DP driver
+ * - xlnx_crtc: Xilinx DRM specific crtc functions
+ */
+
+/* The default value is ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB565 */
+static uint zynqmp_disp_gfx_init_fmt;
+module_param_named(gfx_init_fmt, zynqmp_disp_gfx_init_fmt, uint, 0444);
+MODULE_PARM_DESC(gfx_init_fmt, "The initial format of the graphics layer\n"
+ "\t\t0 = rgb565 (default)\n"
+ "\t\t1 = rgb888\n"
+ "\t\t2 = argb\n");
+/* These value should be mapped to index of av_buf_gfx_fmts[] */
+#define ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB565 10
+#define ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB888 5
+#define ZYNQMP_DISP_AV_BUF_GFX_FMT_ARGB1
+static const u32 zynqmp_disp_gfx_init_fmts[] = {
+ ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB565,
+ ZYNQMP_DISP_AV_BUF_GFX_FMT_RGB888,
+ ZYNQMP_DISP_AV_BUF_GFX_FMT_ARGB,
+};
+
+/* Blender registers */
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4
+#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8
+#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe
+#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4
+#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1)
+#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8)
+#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9
+#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20
+#define ZYNQMP
[PATCH v8 0/5] Xilinx ZynqMP DisplayPort KMS driver
Hi Laurent, This series is primary waiting for your ack as I didn't hear back on v7 [1]. Please take a look and let me know if there's any concern. I've addressed most of your comments in v6. Thanks, -hyun [1] https://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg218915.html Hyun Kwon (5): drm: xlnx: Xilinx DRM KMS module dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort drm: xlnx: ZynqMP DP subsystem DRM KMS driver .../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 77 + MAINTAINERS|9 + drivers/gpu/drm/Kconfig|2 + drivers/gpu/drm/Makefile |1 + drivers/gpu/drm/xlnx/Kconfig | 23 + drivers/gpu/drm/xlnx/Makefile |5 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 142 + drivers/gpu/drm/xlnx/xlnx_crtc.h | 83 + drivers/gpu/drm/xlnx/xlnx_drv.c| 433 +++ drivers/gpu/drm/xlnx/xlnx_drv.h| 23 + drivers/gpu/drm/xlnx/xlnx_fb.c | 249 ++ drivers/gpu/drm/xlnx/xlnx_fb.h | 27 + drivers/gpu/drm/xlnx/xlnx_gem.c| 36 + drivers/gpu/drm/xlnx/xlnx_gem.h| 21 + drivers/gpu/drm/xlnx/zynqmp_disp.c | 2777 drivers/gpu/drm/xlnx/zynqmp_disp.h | 29 + drivers/gpu/drm/xlnx/zynqmp_dp.c | 1756 + drivers/gpu/drm/xlnx/zynqmp_dp.h | 30 + drivers/gpu/drm/xlnx/zynqmp_dpsub.c| 158 ++ drivers/gpu/drm/xlnx/zynqmp_dpsub.h| 23 + 20 files changed, 5904 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v8 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
This driver creates DRM encoder and connector for ZynqMP DisplayPort. Signed-off-by: Hyun Kwon Acked-by: Daniel Vetter --- v8 - Allow to initialize without any phy lane v7 - Use correct number of lanes v6 - Constify all function pointers - Clean up the duplicated license paragraphs - Do complete forward declaration in the header v2 - Change the SPDX identifier format - Split drm properties into a separate patch --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1756 ++ drivers/gpu/drm/xlnx/zynqmp_dp.h | 30 + 2 files changed, 1786 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c new file mode 100644 index 000..e60f07b --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -0,0 +1,1756 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP DisplayPort Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "zynqmp_disp.h" +#include "zynqmp_dpsub.h" + +static uint zynqmp_dp_aux_timeout_ms = 50; +module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); + +/* + * Some sink requires a delay after power on request + */ +static uint zynqmp_dp_power_on_delay_ms = 4; +module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); + +/* Link configuration registers */ +#define ZYNQMP_DP_TX_LINK_BW_SET 0x0 +#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4 +#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8 +#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc +#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE0x14 +#define ZYNQMP_DP_TX_DOWNSPREAD_CTL0x18 +#define ZYNQMP_DP_TX_SW_RESET 0x1c +#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0) +#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1) +#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2) +#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3) +#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7) +#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM2 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM3 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM4 | \ + ZYNQMP_DP_TX_SW_RESET_AUX) + +/* Core enable registers */ +#define ZYNQMP_DP_TX_ENABLE0x80 +#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM0x84 +#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0 +#define ZYNQMP_DP_TX_VERSION 0xf8 +#define ZYNQMP_DP_TX_VERSION_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_VERSION_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12) +#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT12 +#define ZYNQMP_DP_TX_VERSION_PATCH_MASKGENMASK(11, 8) +#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8 +#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0) +#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT0 + +/* Core ID registers */ +#define ZYNQMP_DP_TX_CORE_ID 0xfc +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8) +#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT8 +#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1) + +/* AUX channel interface registers */ +#define ZYNQMP_DP_TX_AUX_COMMAND 0x100 +#define ZYNQMP_DP_TX_AUX_COMMAND_CMD_SHIFT 8 +#define ZYNQMP_DP_TX_AUX_COMMAND_ADDRESS_ONLY BIT(12) +#define ZYNQMP_DP_TX_AUX_COMMAND_BYTES_SHIFT 0 +#define ZYNQMP_DP_TX_AUX_WRITE_FIFO0x104 +#define ZYNQMP_DP_TX_AUX_ADDRESS 0x108 +#define ZYNQMP_DP_TX_CLK_DIVI
[PATCH v8 1/5] drm: xlnx: Xilinx DRM KMS module
Xilinx has various platforms for display, where users can create using multiple IPs in the programmable FPGA fabric, or where some hardened pipeline is available on the chip. Furthermore, hardened pipeline can also interact with soft logics in FPGA. The Xilinx DRM KMS module is to integrate multiple subdevices and to represent the entire pipeline as a single DRM device. The module includes helper (ex, framebuffer and gem helpers) and glue logic (ex, crtc interface) functions. Signed-off-by: Hyun Kwon Acked-by: Daniel Vetter --- v7 - Unbind as component in shutdown - Register release callback for master device v6 - Fix the function desc for pipeline calls - Rebase on drm-misc-next - Fix typos in documentation - Match types for return and internal variables - Remove use of 'tmp' variables - Protect any crtc list iteration with mutex - Remove a check for drm device in crtc unregistration - Split the crtc ops as a separate struct to constify - Embed xlnx_crtc_helper into xlnx_drm - Move to_xlnx_crtc macro close to xlnx_crtc - Remove unneeded include - Replace custom vres module param with CONFIG_DRM_FBDEV_OVERALLOC - Rename crtc to crtc_helper to make it clearer - Use 'DRM device' instead of 'DRM core' - Remove unused function, xlnx_get_format() - Use device instead of platform device for the logical master - Inline xlnx_of_component_probe() - Use of_get_parent() - Remove the port binding handling in the driver - Do complete forward-declarations in headers - Constify all function pointers - Use the default ioctl from fb helper - Return the minimum pitch always - Clean up the duplicate license paragraphs - Get common bits for dma mask instead of minimum value - Remove dummy function declaration from header - Fix a typo in the commit message with some re-organization v5 - Redefine xlnx_pipeline_init() v4 - Fix a bug in of graph binding handling - Remove vblank callbacks from xlnx_crtc - Remove the dt binding. This module becomes more like a library. - Rephrase the commit message v3 - Add Laurent as a maintainer - Fix multiple-reference on gem objects v2 - Change the SPDX identifier format - Merge patches(crtc, gem, fb) into single one v2 of xlnx_drv - Rename kms to display in xlnx_drv - Replace some xlnx specific fb helper with common helpers in xlnx_drv - Don't set the commit tail callback in xlnx_drv - Support 'ports' graph binding in xlnx_drv v2 of xlnx_fb - Remove wrappers in xlnx_fb - Replace some functions with drm core helpers in xlnx_fb --- --- MAINTAINERS | 9 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/xlnx/Kconfig | 12 ++ drivers/gpu/drm/xlnx/Makefile| 2 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 142 + drivers/gpu/drm/xlnx/xlnx_crtc.h | 83 drivers/gpu/drm/xlnx/xlnx_drv.c | 433 +++ drivers/gpu/drm/xlnx/xlnx_drv.h | 23 +++ drivers/gpu/drm/xlnx/xlnx_fb.c | 249 ++ drivers/gpu/drm/xlnx/xlnx_fb.h | 27 +++ drivers/gpu/drm/xlnx/xlnx_gem.c | 36 drivers/gpu/drm/xlnx/xlnx_gem.h | 21 ++ 13 files changed, 1040 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h diff --git a/MAINTAINERS b/MAINTAINERS index 07d1576..137efd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4846,6 +4846,15 @@ F: drivers/gpu/drm/etnaviv/ F: include/uapi/drm/etnaviv_drm.h F: Documentation/devicetree/bindings/display/etnaviv/ +DRM DRIVERS FOR XILINX +M: Hyun Kwon +M: Laurent Pinchart +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/xlnx/ +F: Documentation/devicetree/bindings/display/xlnx/ +T: git git://anongit.freedesktop.org/drm/drm-misc + DRM DRIVERS FOR ZTE ZX M: Shawn Guo L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 10f9f01..ad6891f 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -304,6 +304,8 @@ source "drivers/gpu/drm/tve200/Kconfig" source "drivers/gpu/drm/xen/Kconfig" +source "drivers/gpu/drm/xlnx/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 6ae535c..f6672a5 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -106,3 +106,4 @@ obj-$(CONFIG_DRM_TINYDRM) += tinydrm/ obj-$(CONFIG_DRM_PL111) += pl111/ obj-$(CONFIG_DRM_TVE200) += tve200/ obj-$(CONFIG_DRM_XEN) += xen/ +
[PATCH v8 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon
Reviewed-by: Rob Herring
---
v6
- Add more descriptions and references
- Remove the description for child node
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under 'ports'
- Replace linux specific terms with generic hardware descriptions
---
---
.../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 77 ++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
diff --git
a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
new file mode 100644
index 000..ec8a58a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
@@ -0,0 +1,77 @@
+Xilinx ZynqMP DisplayPort subsystem
+---
+
+The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC) implements
+the display and audio pipelines based on the DisplayPort v1.2 standard.
+The subsystem includes multiple functional blocks as below:
+
+ buffer manager <-> blender & mixer <-> DP Tx
+
+The buffer manager interacts with external interface such as DMA engines or
+live streams. The blender and mixer blends the incoming video / audio streams
+into single stream. The DP Tx converts and transmits the stream into
DisplayPort
+protocol through external phy. The subsystem supports 2 video and 2 audio
+streams, and various pixel formats / depths up to 4K@30 resolution.
+
+Please refer to "Zynq UltraScale+ Device Technical Reference Manual" [UG1085]
+for more details.
+
+Required properties:
+
+- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
+
+- reg: Physical base address and length of the registers set for the device.
+- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register
+ partitions.
+
+- interrupts: Interrupt number.
+- interrupts-parent: phandle for interrupt controller.
+
+- clocks: phandles for axi, audio, non-live video, and live video clocks.
+ axi clock is required. Audio clock is optional. If not present, audio will
+ be disabled. One of non-live or live video clock should be present.
+- clock-names: The identification strings are required. "aclk" for axi clock.
+ "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock.
+ "dp_live_video_in_clk" for live video clock (clock from programmable logic).
+
+- phys: phandles for phy specifier. The number of lanes is configurable
+ between 1 and 2. The number of phandles should be 1 or 2.
+- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
+ For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0"
+ and "dp-phy1" are required where "dp-phy0" is the primary lane.
+
+- power-domains: phandle for the corresponding power domain
+
+- dmas: phandles for DMA channels as defined in
+ Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names: The identifier strings are required. "gfx0" for graphics layer
+ dma channel. "vid" followed by index (0 - 2) for video layer dma channels.
+
+Example:
+ zynqmp-display-subsystem@fd4a {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ reg = <0x0 0xfd4a 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_live_video_in_clk";
+ clocks = <_aclk>, < 17>, <_1>;
+
+ phys = <>, <>;
+ phy-names = "dp-phy0", "dp-phy1";
+
+ power-domains = <_dp>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <_dpdma 0>,
+ <_dpdma 1>,
+ <_dpdma 2>,
+ <_dpdma 3>;
+ };
+};
+
+[UG1085]
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
--
2.7.4
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v8 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon
Acked-by: Daniel Vetter
---
v8
- Support reserved memory through memory-region dt binding
v6
- Accomodate the migration of logical master from platform device to device
- Remove the duplicate license paragraphs
- Do complete forward declaration in the header
v5
- Add an error handling of pipeline initialization
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 158
drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 23 ++
4 files changed, 195 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h
diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
index 19fd7cd..7c5529c 100644
--- a/drivers/gpu/drm/xlnx/Kconfig
+++ b/drivers/gpu/drm/xlnx/Kconfig
@@ -10,3 +10,14 @@ config DRM_XLNX
display pipeline using Xilinx IPs in FPGA. This module
provides the kernel mode setting functionalities
for Xilinx display drivers.
+
+config DRM_ZYNQMP_DPSUB
+ tristate "ZynqMP DP Subsystem Driver"
+ depends on ARCH_ZYNQMP && OF && DRM_XLNX && COMMON_CLK
+ select DMA_ENGINE
+ select GENERIC_PHY
+ help
+ DRM KMS driver for ZynqMP DP Subsystem controller. Choose
+ this option if you have a Xilinx ZynqMP SoC with DisplayPort
+ subsystem. The driver provides the kernel mode setting
+ functionlaities for ZynqMP DP subsystem.
diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile
index c60a281..064a05a 100644
--- a/drivers/gpu/drm/xlnx/Makefile
+++ b/drivers/gpu/drm/xlnx/Makefile
@@ -1,2 +1,5 @@
xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o
obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o
+
+zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
+obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
new file mode 100644
index 000..34e81d0
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DP Subsystem Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "xlnx_drv.h"
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+static int
+zynqmp_dpsub_bind(struct device *dev, struct device *master, void *data)
+{
+ int ret;
+
+ ret = zynqmp_disp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ /* zynqmp_disp should bind first, so zynqmp_dp encoder can find crtc */
+ ret = zynqmp_dp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+zynqmp_dpsub_unbind(struct device *dev, struct device *master, void *data)
+{
+ zynqmp_dp_unbind(dev, master, data);
+ zynqmp_disp_unbind(dev, master, data);
+}
+
+static const struct component_ops zynqmp_dpsub_component_ops = {
+ .bind = zynqmp_dpsub_bind,
+ .unbind = zynqmp_dpsub_unbind,
+};
+
+static int zynqmp_dpsub_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ int ret;
+
+ dpsub = devm_kzalloc(>dev, sizeof(*dpsub), GFP_KERNEL);
+ if (!dpsub)
+ return -ENOMEM;
+
+ /* Sub-driver will access dpsub from drvdata */
+ platform_set_drvdata(pdev, dpsub);
+ pm_runtime_enable(>dev);
+
+ /*
+* DP should be probed first so that the zynqmp_disp can set the output
+* format accordingly.
+*/
+ ret = zynqmp_dp_probe(pdev);
+ if (ret)
+ goto err_pm;
+
+ ret = zynqmp_disp_probe(pdev);
+ if (ret)
+ goto err_dp;
+
+ ret = component_add(>dev, _dpsub_component_ops);
+ if (ret)
+ goto err_disp;
+
+ /* Try the reserved memory. Proceed if there's none */
+ of_reserved_mem_device_init(>dev);
+
+ /* Populate the sound child nodes */
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
+ if (ret) {
+ dev_err(>dev, "failed to populate child nodes\n");
+ goto err_rmem;
+ }
+
+ dpsub->master = xlnx_drm_pipeline_init(>dev);
+ if (IS_ERR(dpsub->master)) {
+ dev_err(>dev, "failed to initialize the drm pipeline\n");
+ goto err_populate;
+ }
+
+ dev_info(>dev, "ZynqMP DisplayPort Subsystem driver probed");
+
+ return 0
[PATCH LIBDRM 2/3] modetest: Add support for YUV422 and YUV444
This allows dumb buffer allocation for YUV422 and YUV444 with correct
subsampling values.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
tests/modetest/buffers.c | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
index 9b635c0..769399e 100644
--- a/tests/modetest/buffers.c
+++ b/tests/modetest/buffers.c
@@ -127,7 +127,7 @@ bo_create(int fd, unsigned int format,
unsigned int handles[4], unsigned int pitches[4],
unsigned int offsets[4], enum util_fill_pattern pattern)
{
- unsigned int virtual_height;
+ unsigned int virtual_height, hsub, vsub;
struct bo *bo;
unsigned int bpp;
void *planes[3] = { 0, };
@@ -141,6 +141,10 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_NV61:
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
bpp = 8;
break;
@@ -204,15 +208,30 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
virtual_height = height * 3 / 2;
+ hsub = 2;
+ vsub = 2;
break;
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
virtual_height = height * 2;
+ hsub = 2;
+ vsub = 1;
+ break;
+
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
+ virtual_height = height * 3;
+ hsub = 1;
+ vsub = 1;
break;
default:
virtual_height = height;
+ hsub = 1;
+ vsub = 1;
break;
}
@@ -260,14 +279,18 @@ bo_create(int fd, unsigned int format,
case DRM_FORMAT_YUV420:
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YUV444:
+ case DRM_FORMAT_YVU444:
offsets[0] = 0;
handles[0] = bo->handle;
pitches[0] = bo->pitch;
- pitches[1] = pitches[0] / 2;
+ pitches[1] = pitches[0] / hsub;
offsets[1] = pitches[0] * height;
handles[1] = bo->handle;
pitches[2] = pitches[1];
- offsets[2] = offsets[1] + pitches[1] * height / 2;
+ offsets[2] = offsets[1] + pitches[1] * height / vsub;
handles[2] = bo->handle;
planes[0] = virtual;
--
2.7.4
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[PATCH LIBDRM 0/3] Enable more formats in modetest
Hi, This set adds more format support for modetest, including fixes for 10bit RGB formats and addition of 422/444 YUV formats. Thanks, -hyun Hyun Kwon (3): tests: util: pattern: Use 64bit RGB samples modetest: Add support for YUV422 and YUV444 tests: util: Add support for YUV422 and YUV444 tests/modetest/buffers.c | 29 ++--- tests/util/format.c | 4 tests/util/pattern.c | 22 ++ 3 files changed, 48 insertions(+), 7 deletions(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH LIBDRM 1/3] tests: util: pattern: Use 64bit RGB samples
Use of 32bit RGB samples, where each component is 8bit, cannot
support formats with components greater than 8bit (ex, XRGB2101010).
Introduce MAKE_RGBA_64() which creates pixels from a 64bit sample.
Each component in a 64bit sample is 16bit long, thus a pixel with 10bit
components can be generated correctly.
MAKE_RGBA() can use MAKE_RGBA_64() by scaling each 8bit component
to 16bit, for compatilbity.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
tests/util/pattern.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index 9fa0a41..aa067c9 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -60,11 +60,17 @@ struct color_yuv {
.u = MAKE_YUV_601_U(r, g, b), \
.v = MAKE_YUV_601_V(r, g, b) }
+#define COLOR_MASK(value, color) \
+ ((value & ((1 << (color).length) - 1)) << (color).offset)
+
+#define MAKE_RGBA_64(rgb, r, g, b, a) \
+ (COLOR_MASK(((r) >> (16 - (rgb)->red.length)), (rgb)->red) | \
+COLOR_MASK(((g) >> (16 - (rgb)->green.length)), (rgb)->green) | \
+COLOR_MASK(((b) >> (16 - (rgb)->blue.length)), (rgb)->blue) | \
+COLOR_MASK(((a) >> (16 - (rgb)->alpha.length)), (rgb)->alpha))
+
#define MAKE_RGBA(rgb, r, g, b, a) \
- r) >> (8 - (rgb)->red.length)) << (rgb)->red.offset) | \
-(((g) >> (8 - (rgb)->green.length)) << (rgb)->green.offset) | \
-(((b) >> (8 - (rgb)->blue.length)) << (rgb)->blue.offset) | \
-(((a) >> (8 - (rgb)->alpha.length)) << (rgb)->alpha.offset))
+ MAKE_RGBA_64(rgb, (r) * 0x101, (g) * 0x101, (b) * 0x101, (a) * 0x101)
#define MAKE_RGB24(rgb, r, g, b) \
{ .value = MAKE_RGBA(rgb, r, g, b, 0) }
--
2.7.4
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[PATCH LIBDRM 3/3] tests: util: Add support for YUV422 and YUV444
Enable YUV422 and YUV444 formats by adding to the format table
and pattern generation calls.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
tests/util/format.c | 4
tests/util/pattern.c | 8
2 files changed, 12 insertions(+)
diff --git a/tests/util/format.c b/tests/util/format.c
index 15ac5e1..b48594c 100644
--- a/tests/util/format.c
+++ b/tests/util/format.c
@@ -52,6 +52,10 @@ static const struct util_format_info format_info[] = {
/* YUV planar */
{ DRM_FORMAT_YUV420, "YU12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 1) },
{ DRM_FORMAT_YVU420, "YV12", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 1) },
+ { DRM_FORMAT_YUV422, "YU16", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 1) },
+ { DRM_FORMAT_YVU422, "YV16", MAKE_YUV_INFO(YUV_YCrCb, 2, 1, 1) },
+ { DRM_FORMAT_YUV444, "YU24", MAKE_YUV_INFO(YUV_YCbCr, 1, 1, 1) },
+ { DRM_FORMAT_YVU444, "YV24", MAKE_YUV_INFO(YUV_YCrCb, 1, 1, 1) },
/* RGB16 */
{ DRM_FORMAT_ARGB, "AR12", MAKE_RGB_INFO(4, 8, 4, 4, 4, 0, 4, 12) },
{ DRM_FORMAT_XRGB, "XR12", MAKE_RGB_INFO(4, 8, 4, 4, 4, 0, 0, 0) },
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index aa067c9..2805724 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -487,10 +487,14 @@ static void fill_smpte(const struct util_format_info
*info, void *planes[3],
width, height, stride);
case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YUV444:
return fill_smpte_yuv_planar(>yuv, planes[0], planes[1],
planes[2], width, height, stride);
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YVU444:
return fill_smpte_yuv_planar(>yuv, planes[0], planes[2],
planes[1], width, height, stride);
@@ -772,10 +776,14 @@ static void fill_tiles(const struct util_format_info
*info, void *planes[3],
width, height, stride);
case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YUV422:
+ case DRM_FORMAT_YUV444:
return fill_tiles_yuv_planar(info, planes[0], planes[1],
planes[2], width, height, stride);
case DRM_FORMAT_YVU420:
+ case DRM_FORMAT_YVU422:
+ case DRM_FORMAT_YVU444:
return fill_tiles_yuv_planar(info, planes[0], planes[2],
planes[1], width, height, stride);
--
2.7.4
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[PATCH v7 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
v6
- Add more descriptions and references
- Remove the description for child node
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under 'ports'
- Replace linux specific terms with generic hardware descriptions
---
---
.../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 77 ++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
diff --git
a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
new file mode 100644
index 000..ec8a58a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
@@ -0,0 +1,77 @@
+Xilinx ZynqMP DisplayPort subsystem
+---
+
+The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC) implements
+the display and audio pipelines based on the DisplayPort v1.2 standard.
+The subsystem includes multiple functional blocks as below:
+
+ buffer manager <-> blender & mixer <-> DP Tx
+
+The buffer manager interacts with external interface such as DMA engines or
+live streams. The blender and mixer blends the incoming video / audio streams
+into single stream. The DP Tx converts and transmits the stream into
DisplayPort
+protocol through external phy. The subsystem supports 2 video and 2 audio
+streams, and various pixel formats / depths up to 4K@30 resolution.
+
+Please refer to "Zynq UltraScale+ Device Technical Reference Manual" [UG1085]
+for more details.
+
+Required properties:
+
+- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
+
+- reg: Physical base address and length of the registers set for the device.
+- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register
+ partitions.
+
+- interrupts: Interrupt number.
+- interrupts-parent: phandle for interrupt controller.
+
+- clocks: phandles for axi, audio, non-live video, and live video clocks.
+ axi clock is required. Audio clock is optional. If not present, audio will
+ be disabled. One of non-live or live video clock should be present.
+- clock-names: The identification strings are required. "aclk" for axi clock.
+ "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock.
+ "dp_live_video_in_clk" for live video clock (clock from programmable logic).
+
+- phys: phandles for phy specifier. The number of lanes is configurable
+ between 1 and 2. The number of phandles should be 1 or 2.
+- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
+ For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0"
+ and "dp-phy1" are required where "dp-phy0" is the primary lane.
+
+- power-domains: phandle for the corresponding power domain
+
+- dmas: phandles for DMA channels as defined in
+ Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names: The identifier strings are required. "gfx0" for graphics layer
+ dma channel. "vid" followed by index (0 - 2) for video layer dma channels.
+
+Example:
+ zynqmp-display-subsystem@fd4a {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ reg = <0x0 0xfd4a 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_live_video_in_clk";
+ clocks = <_aclk>, < 17>, <_1>;
+
+ phys = <>, <>;
+ phy-names = "dp-phy0", "dp-phy1";
+
+ power-domains = <_dp>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <_dpdma 0>,
+ <_dpdma 1>,
+ <_dpdma 2>,
+ <_dpdma 3>;
+ };
+};
+
+[UG1085]
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
--
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[PATCH v7 0/5] Xilinx ZynqMP DisplayPort KMS driver
Hi Laurent, On top of addressing your comments in v6, I've incorporated some relatively small fixes in v7. I'm mainly waiting for your feedback before committing this series, unless there's any additional review comments. Please take a look. Thanks, -hyun Hyun Kwon (5): drm: xlnx: Xilinx DRM KMS module dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort drm: xlnx: ZynqMP DP subsystem DRM KMS driver .../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 77 + MAINTAINERS|9 + drivers/gpu/drm/Kconfig|2 + drivers/gpu/drm/Makefile |1 + drivers/gpu/drm/xlnx/Kconfig | 23 + drivers/gpu/drm/xlnx/Makefile |5 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 142 + drivers/gpu/drm/xlnx/xlnx_crtc.h | 83 + drivers/gpu/drm/xlnx/xlnx_drv.c| 433 +++ drivers/gpu/drm/xlnx/xlnx_drv.h| 23 + drivers/gpu/drm/xlnx/xlnx_fb.c | 249 ++ drivers/gpu/drm/xlnx/xlnx_fb.h | 27 + drivers/gpu/drm/xlnx/xlnx_gem.c| 36 + drivers/gpu/drm/xlnx/xlnx_gem.h| 21 + drivers/gpu/drm/xlnx/zynqmp_disp.c | 2755 drivers/gpu/drm/xlnx/zynqmp_disp.h | 29 + drivers/gpu/drm/xlnx/zynqmp_dp.c | 1733 drivers/gpu/drm/xlnx/zynqmp_dp.h | 30 + drivers/gpu/drm/xlnx/zynqmp_dpsub.c| 152 ++ drivers/gpu/drm/xlnx/zynqmp_dpsub.h| 23 + 20 files changed, 5853 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v7 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
This driver creates DRM encoder and connector for ZynqMP DisplayPort. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v7 - Use correct number of lanes v6 - Constify all function pointers - Clean up the duplicated license paragraphs - Do complete forward declaration in the header v2 - Change the SPDX identifier format - Split drm properties into a separate patch --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1733 ++ drivers/gpu/drm/xlnx/zynqmp_dp.h | 30 + 2 files changed, 1763 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c new file mode 100644 index 000..8378fe2 --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -0,0 +1,1733 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP DisplayPort Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "zynqmp_disp.h" +#include "zynqmp_dpsub.h" + +static uint zynqmp_dp_aux_timeout_ms = 50; +module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); + +/* + * Some sink requires a delay after power on request + */ +static uint zynqmp_dp_power_on_delay_ms = 4; +module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); + +/* Link configuration registers */ +#define ZYNQMP_DP_TX_LINK_BW_SET 0x0 +#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4 +#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8 +#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc +#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE0x14 +#define ZYNQMP_DP_TX_DOWNSPREAD_CTL0x18 +#define ZYNQMP_DP_TX_SW_RESET 0x1c +#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0) +#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1) +#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2) +#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3) +#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7) +#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM2 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM3 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM4 | \ + ZYNQMP_DP_TX_SW_RESET_AUX) + +/* Core enable registers */ +#define ZYNQMP_DP_TX_ENABLE0x80 +#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM0x84 +#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0 +#define ZYNQMP_DP_TX_VERSION 0xf8 +#define ZYNQMP_DP_TX_VERSION_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_VERSION_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12) +#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT12 +#define ZYNQMP_DP_TX_VERSION_PATCH_MASKGENMASK(11, 8) +#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8 +#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0) +#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT0 + +/* Core ID registers */ +#define ZYNQMP_DP_TX_CORE_ID 0xfc +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8) +#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT8 +#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1) + +/* AUX channel interface registers */ +#define ZYNQMP_DP_TX_AUX_COMMAND 0x100 +#define ZYNQMP_DP_TX_AUX_COMMAND_CMD_SHIFT 8 +#define ZYNQMP_DP_TX_AUX_COMMAND_ADDRESS_ONLY BIT(12) +#define ZYNQMP_DP_TX_AUX_COMMAND_BYTES_SHIFT 0 +#define ZYNQMP_DP_TX_AUX_WRITE_FIFO0x104 +#define ZYNQMP_DP_TX_AUX_ADDRESS 0x108 +#define ZYN
[PATCH v7 1/5] drm: xlnx: Xilinx DRM KMS module
Xilinx has various platforms for display, where users can create using multiple IPs in the programmable FPGA fabric, or where some hardened pipeline is available on the chip. Furthermore, hardened pipeline can also interact with soft logics in FPGA. The Xilinx DRM KMS module is to integrate multiple subdevices and to represent the entire pipeline as a single DRM device. The module includes helper (ex, framebuffer and gem helpers) and glue logic (ex, crtc interface) functions. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v7 - Unbind as component in shutdown - Register release callback for master device v6 - Fix the function desc for pipeline calls - Rebase on drm-misc-next - Fix typos in documentation - Match types for return and internal variables - Remove use of 'tmp' variables - Protect any crtc list iteration with mutex - Remove a check for drm device in crtc unregistration - Split the crtc ops as a separate struct to constify - Embed xlnx_crtc_helper into xlnx_drm - Move to_xlnx_crtc macro close to xlnx_crtc - Remove unneeded include - Replace custom vres module param with CONFIG_DRM_FBDEV_OVERALLOC - Rename crtc to crtc_helper to make it clearer - Use 'DRM device' instead of 'DRM core' - Remove unused function, xlnx_get_format() - Use device instead of platform device for the logical master - Inline xlnx_of_component_probe() - Use of_get_parent() - Remove the port binding handling in the driver - Do complete forward-declarations in headers - Constify all function pointers - Use the default ioctl from fb helper - Return the minimum pitch always - Clean up the duplicate license paragraphs - Get common bits for dma mask instead of minimum value - Remove dummy function declaration from header - Fix a typo in the commit message with some re-organization v5 - Redefine xlnx_pipeline_init() v4 - Fix a bug in of graph binding handling - Remove vblank callbacks from xlnx_crtc - Remove the dt binding. This module becomes more like a library. - Rephrase the commit message v3 - Add Laurent as a maintainer - Fix multiple-reference on gem objects v2 - Change the SPDX identifier format - Merge patches(crtc, gem, fb) into single one v2 of xlnx_drv - Rename kms to display in xlnx_drv - Replace some xlnx specific fb helper with common helpers in xlnx_drv - Don't set the commit tail callback in xlnx_drv - Support 'ports' graph binding in xlnx_drv v2 of xlnx_fb - Remove wrappers in xlnx_fb - Replace some functions with drm core helpers in xlnx_fb --- --- MAINTAINERS | 9 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/xlnx/Kconfig | 12 ++ drivers/gpu/drm/xlnx/Makefile| 2 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 142 + drivers/gpu/drm/xlnx/xlnx_crtc.h | 83 drivers/gpu/drm/xlnx/xlnx_drv.c | 433 +++ drivers/gpu/drm/xlnx/xlnx_drv.h | 23 +++ drivers/gpu/drm/xlnx/xlnx_fb.c | 249 ++ drivers/gpu/drm/xlnx/xlnx_fb.h | 27 +++ drivers/gpu/drm/xlnx/xlnx_gem.c | 36 drivers/gpu/drm/xlnx/xlnx_gem.h | 21 ++ 13 files changed, 1040 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h diff --git a/MAINTAINERS b/MAINTAINERS index 4af7f61..3bd61bc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4815,6 +4815,15 @@ F: drivers/gpu/drm/etnaviv/ F: include/uapi/drm/etnaviv_drm.h F: Documentation/devicetree/bindings/display/etnaviv/ +DRM DRIVERS FOR XILINX +M: Hyun Kwon <hyun.k...@xilinx.com> +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/xlnx/ +F: Documentation/devicetree/bindings/display/xlnx/ +T: git git://anongit.freedesktop.org/drm/drm-misc + DRM DRIVERS FOR ZTE ZX M: Shawn Guo <shawn...@kernel.org> L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 757825a..badd34c 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -291,6 +291,8 @@ source "drivers/gpu/drm/tve200/Kconfig" source "drivers/gpu/drm/xen/Kconfig" +source "drivers/gpu/drm/xlnx/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 9d66657..c05922f 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@
[PATCH v7 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
Xilinx ZynqMP has a hardened display pipeline. The pipeline can be logically partitioned into 2 parts: display controller and DisplayPort encoder / transmitter. This driver handles the display controller part of the pipeline that handles buffer management and blending. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v7 - Disable a plane when the fb format changes - Update planes asynchronously in the legacy set plane entry v6 - Use the new crtc op struct - Clean up the duplicated license paragraphs - Declare function pointer structures as static const - Do complete forward declaration in headers v4 - Use drm_crtc_funcs for vblank - Remove child nodes for layer v3 - Fix a small typo v2 - Use drm_fb_cma_get_gem_addr() - Use drm_crtc_arm_vblank_event() - Split drm properties into a separate patch - Remove dummy funcs - Don't add offset as it's already done by a new helper - Change the SPDX identifier format - Minor change of a commit message --- --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 2755 drivers/gpu/drm/xlnx/zynqmp_disp.h | 29 + 2 files changed, 2784 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c new file mode 100644 index 000..9592df1 --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -0,0 +1,2755 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP Display Controller Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xlnx_crtc.h" +#include "xlnx_fb.h" +#include "zynqmp_disp.h" +#include "zynqmp_dp.h" +#include "zynqmp_dpsub.h" + +/* + * Overview + * + * + * The display part of ZynqMP DP subsystem. Internally, the device + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio. + * The driver creates the DRM crtc and plane objectes and maps the DRM + * interface into those 3 blocks. In high level, the driver is layered + * in the following way: + * + * zynqmp_disp_crtc & zynqmp_disp_plane + * |->zynqmp_disp + * |->zynqmp_disp_aud + * |->zynqmp_disp_blend + * |->zynqmp_disp_av_buf + * + * The driver APIs are used externally by + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver + * - zynqmp_dp: ZynqMP DP driver + * - xlnx_crtc: Xilinx DRM specific crtc functions + */ + +/* Blender registers */ +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 +#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18 +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3 0x50 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF4 0x54 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF5 0x58 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF6
[PATCH v7 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
v6
- Accomodate the migration of logical master from platform device to device
- Remove the duplicate license paragraphs
- Do complete forward declaration in the header
v5
- Add an error handling of pipeline initialization
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 152
drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 23 ++
4 files changed, 189 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h
diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
index 19fd7cd..7c5529c 100644
--- a/drivers/gpu/drm/xlnx/Kconfig
+++ b/drivers/gpu/drm/xlnx/Kconfig
@@ -10,3 +10,14 @@ config DRM_XLNX
display pipeline using Xilinx IPs in FPGA. This module
provides the kernel mode setting functionalities
for Xilinx display drivers.
+
+config DRM_ZYNQMP_DPSUB
+ tristate "ZynqMP DP Subsystem Driver"
+ depends on ARCH_ZYNQMP && OF && DRM_XLNX && COMMON_CLK
+ select DMA_ENGINE
+ select GENERIC_PHY
+ help
+ DRM KMS driver for ZynqMP DP Subsystem controller. Choose
+ this option if you have a Xilinx ZynqMP SoC with DisplayPort
+ subsystem. The driver provides the kernel mode setting
+ functionlaities for ZynqMP DP subsystem.
diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile
index c60a281..064a05a 100644
--- a/drivers/gpu/drm/xlnx/Makefile
+++ b/drivers/gpu/drm/xlnx/Makefile
@@ -1,2 +1,5 @@
xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o
obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o
+
+zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
+obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
new file mode 100644
index 000..7c6981b
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DP Subsystem Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.k...@xilinx.com>
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "xlnx_drv.h"
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+static int
+zynqmp_dpsub_bind(struct device *dev, struct device *master, void *data)
+{
+ int ret;
+
+ ret = zynqmp_disp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ /* zynqmp_disp should bind first, so zynqmp_dp encoder can find crtc */
+ ret = zynqmp_dp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+zynqmp_dpsub_unbind(struct device *dev, struct device *master, void *data)
+{
+ zynqmp_dp_unbind(dev, master, data);
+ zynqmp_disp_unbind(dev, master, data);
+}
+
+static const struct component_ops zynqmp_dpsub_component_ops = {
+ .bind = zynqmp_dpsub_bind,
+ .unbind = zynqmp_dpsub_unbind,
+};
+
+static int zynqmp_dpsub_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ int ret;
+
+ dpsub = devm_kzalloc(>dev, sizeof(*dpsub), GFP_KERNEL);
+ if (!dpsub)
+ return -ENOMEM;
+
+ /* Sub-driver will access dpsub from drvdata */
+ platform_set_drvdata(pdev, dpsub);
+ pm_runtime_enable(>dev);
+
+ /*
+* DP should be probed first so that the zynqmp_disp can set the output
+* format accordingly.
+*/
+ ret = zynqmp_dp_probe(pdev);
+ if (ret)
+ goto err_pm;
+
+ ret = zynqmp_disp_probe(pdev);
+ if (ret)
+ goto err_dp;
+
+ ret = component_add(>dev, _dpsub_component_ops);
+ if (ret)
+ goto err_disp;
+
+ /* Populate the sound child nodes */
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
+ if (ret) {
+ dev_err(>dev, "failed to populate child nodes\n");
+ goto err_component;
+ }
+
+ dpsub->master = xlnx_drm_pipeline_init(>dev);
+ if (IS_ERR(dpsub->master)) {
+ dev_err(>dev, "failed to initialize the drm pipeline\n");
+ goto err_populate;
+ }
+
+ dev_info(>dev, "ZynqMP DisplayPort Subsystem driver probed");
+
+ return 0;
+
+err_populate:
+ of_platform_depopulate(>dev);
+err_component:
+ component_d
[PATCH v6 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
Xilinx ZynqMP has a hardened display pipeline. The pipeline can be logically partitioned into 2 parts: display controller and DisplayPort encoder / transmitter. This driver handles the display controller part of the pipeline that handles buffer management and blending. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v6 - Use the new crtc op struct - Clean up the duplicated license paragraphs - Declare function pointer structures as static const - Do complete forward declaration in headers v4 - Use drm_crtc_funcs for vblank - Remove child nodes for layer v3 - Fix a small typo v2 - Use drm_fb_cma_get_gem_addr() - Use drm_crtc_arm_vblank_event() - Split drm properties into a separate patch - Remove dummy funcs - Don't add offset as it's already done by a new helper - Change the SPDX identifier format - Minor change of a commit message --- --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 2671 drivers/gpu/drm/xlnx/zynqmp_disp.h | 29 + 2 files changed, 2700 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c new file mode 100644 index 000..cc16cdc --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -0,0 +1,2671 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP Display Controller Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xlnx_crtc.h" +#include "xlnx_fb.h" +#include "zynqmp_disp.h" +#include "zynqmp_dp.h" +#include "zynqmp_dpsub.h" + +/* + * Overview + * + * + * The display part of ZynqMP DP subsystem. Internally, the device + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio. + * The driver creates the DRM crtc and plane objectes and maps the DRM + * interface into those 3 blocks. In high level, the driver is layered + * in the following way: + * + * zynqmp_disp_crtc & zynqmp_disp_plane + * |->zynqmp_disp + * |->zynqmp_disp_aud + * |->zynqmp_disp_blend + * |->zynqmp_disp_av_buf + * + * The driver APIs are used externally by + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver + * - zynqmp_dp: ZynqMP DP driver + * - xlnx_crtc: Xilinx DRM specific crtc functions + */ + +/* Blender registers */ +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 +#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18 +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3 0x50 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF4 0x54 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF5 0x58 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF6 0x5c +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF7 0x60 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF8
[PATCH v6 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
v6
- Accomodate the migration of logical master from platform device to device
- Remove the duplicate license paragraphs
- Do complete forward declaration in the header
v5
- Add an error handling of pipeline initialization
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 152
drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 23 ++
4 files changed, 189 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h
diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
index 19fd7cd..7c5529c 100644
--- a/drivers/gpu/drm/xlnx/Kconfig
+++ b/drivers/gpu/drm/xlnx/Kconfig
@@ -10,3 +10,14 @@ config DRM_XLNX
display pipeline using Xilinx IPs in FPGA. This module
provides the kernel mode setting functionalities
for Xilinx display drivers.
+
+config DRM_ZYNQMP_DPSUB
+ tristate "ZynqMP DP Subsystem Driver"
+ depends on ARCH_ZYNQMP && OF && DRM_XLNX && COMMON_CLK
+ select DMA_ENGINE
+ select GENERIC_PHY
+ help
+ DRM KMS driver for ZynqMP DP Subsystem controller. Choose
+ this option if you have a Xilinx ZynqMP SoC with DisplayPort
+ subsystem. The driver provides the kernel mode setting
+ functionlaities for ZynqMP DP subsystem.
diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile
index c60a281..064a05a 100644
--- a/drivers/gpu/drm/xlnx/Makefile
+++ b/drivers/gpu/drm/xlnx/Makefile
@@ -1,2 +1,5 @@
xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o
obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o
+
+zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
+obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
new file mode 100644
index 000..7c6981b
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DP Subsystem Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.k...@xilinx.com>
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "xlnx_drv.h"
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+static int
+zynqmp_dpsub_bind(struct device *dev, struct device *master, void *data)
+{
+ int ret;
+
+ ret = zynqmp_disp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ /* zynqmp_disp should bind first, so zynqmp_dp encoder can find crtc */
+ ret = zynqmp_dp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+zynqmp_dpsub_unbind(struct device *dev, struct device *master, void *data)
+{
+ zynqmp_dp_unbind(dev, master, data);
+ zynqmp_disp_unbind(dev, master, data);
+}
+
+static const struct component_ops zynqmp_dpsub_component_ops = {
+ .bind = zynqmp_dpsub_bind,
+ .unbind = zynqmp_dpsub_unbind,
+};
+
+static int zynqmp_dpsub_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ int ret;
+
+ dpsub = devm_kzalloc(>dev, sizeof(*dpsub), GFP_KERNEL);
+ if (!dpsub)
+ return -ENOMEM;
+
+ /* Sub-driver will access dpsub from drvdata */
+ platform_set_drvdata(pdev, dpsub);
+ pm_runtime_enable(>dev);
+
+ /*
+* DP should be probed first so that the zynqmp_disp can set the output
+* format accordingly.
+*/
+ ret = zynqmp_dp_probe(pdev);
+ if (ret)
+ goto err_pm;
+
+ ret = zynqmp_disp_probe(pdev);
+ if (ret)
+ goto err_dp;
+
+ ret = component_add(>dev, _dpsub_component_ops);
+ if (ret)
+ goto err_disp;
+
+ /* Populate the sound child nodes */
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
+ if (ret) {
+ dev_err(>dev, "failed to populate child nodes\n");
+ goto err_component;
+ }
+
+ dpsub->master = xlnx_drm_pipeline_init(>dev);
+ if (IS_ERR(dpsub->master)) {
+ dev_err(>dev, "failed to initialize the drm pipeline\n");
+ goto err_populate;
+ }
+
+ dev_info(>dev, "ZynqMP DisplayPort Subsystem driver probed");
+
+ return 0;
+
+err_populate:
+ of_platform_depopulate(>dev);
+err_component:
+ component_d
[PATCH v6 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
v6
- Add more descriptions and references
- Remove the description for child node
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under 'ports'
- Replace linux specific terms with generic hardware descriptions
---
---
.../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 77 ++
1 file changed, 77 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
diff --git
a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
new file mode 100644
index 000..ec8a58a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
@@ -0,0 +1,77 @@
+Xilinx ZynqMP DisplayPort subsystem
+---
+
+The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC) implements
+the display and audio pipelines based on the DisplayPort v1.2 standard.
+The subsystem includes multiple functional blocks as below:
+
+ buffer manager <-> blender & mixer <-> DP Tx
+
+The buffer manager interacts with external interface such as DMA engines or
+live streams. The blender and mixer blends the incoming video / audio streams
+into single stream. The DP Tx converts and transmits the stream into
DisplayPort
+protocol through external phy. The subsystem supports 2 video and 2 audio
+streams, and various pixel formats / depths up to 4K@30 resolution.
+
+Please refer to "Zynq UltraScale+ Device Technical Reference Manual" [UG1085]
+for more details.
+
+Required properties:
+
+- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
+
+- reg: Physical base address and length of the registers set for the device.
+- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register
+ partitions.
+
+- interrupts: Interrupt number.
+- interrupts-parent: phandle for interrupt controller.
+
+- clocks: phandles for axi, audio, non-live video, and live video clocks.
+ axi clock is required. Audio clock is optional. If not present, audio will
+ be disabled. One of non-live or live video clock should be present.
+- clock-names: The identification strings are required. "aclk" for axi clock.
+ "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock.
+ "dp_live_video_in_clk" for live video clock (clock from programmable logic).
+
+- phys: phandles for phy specifier. The number of lanes is configurable
+ between 1 and 2. The number of phandles should be 1 or 2.
+- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
+ For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0"
+ and "dp-phy1" are required where "dp-phy0" is the primary lane.
+
+- power-domains: phandle for the corresponding power domain
+
+- dmas: phandles for DMA channels as defined in
+ Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names: The identifier strings are required. "gfx0" for graphics layer
+ dma channel. "vid" followed by index (0 - 2) for video layer dma channels.
+
+Example:
+ zynqmp-display-subsystem@fd4a {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ reg = <0x0 0xfd4a 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_live_video_in_clk";
+ clocks = <_aclk>, < 17>, <_1>;
+
+ phys = <>, <>;
+ phy-names = "dp-phy0", "dp-phy1";
+
+ power-domains = <_dp>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <_dpdma 0>,
+ <_dpdma 1>,
+ <_dpdma 2>,
+ <_dpdma 3>;
+ };
+};
+
+[UG1085]
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
--
2.7.4
___
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[PATCH v6 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
This driver creates DRM encoder and connector for ZynqMP DisplayPort. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v6 - Constify all function pointers - Clean up the duplicated license paragraphs - Do complete forward declaration in the header v2 - Change the SPDX identifier format - Split drm properties into a separate patch --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1730 ++ drivers/gpu/drm/xlnx/zynqmp_dp.h | 30 + 2 files changed, 1760 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c new file mode 100644 index 000..9ed55dd --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -0,0 +1,1730 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP DisplayPort Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "zynqmp_disp.h" +#include "zynqmp_dpsub.h" + +static uint zynqmp_dp_aux_timeout_ms = 50; +module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); + +/* + * Some sink requires a delay after power on request + */ +static uint zynqmp_dp_power_on_delay_ms = 4; +module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); + +/* Link configuration registers */ +#define ZYNQMP_DP_TX_LINK_BW_SET 0x0 +#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4 +#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8 +#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc +#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE0x14 +#define ZYNQMP_DP_TX_DOWNSPREAD_CTL0x18 +#define ZYNQMP_DP_TX_SW_RESET 0x1c +#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0) +#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1) +#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2) +#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3) +#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7) +#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM2 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM3 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM4 | \ + ZYNQMP_DP_TX_SW_RESET_AUX) + +/* Core enable registers */ +#define ZYNQMP_DP_TX_ENABLE0x80 +#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM0x84 +#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0 +#define ZYNQMP_DP_TX_VERSION 0xf8 +#define ZYNQMP_DP_TX_VERSION_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_VERSION_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12) +#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT12 +#define ZYNQMP_DP_TX_VERSION_PATCH_MASKGENMASK(11, 8) +#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8 +#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0) +#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT0 + +/* Core ID registers */ +#define ZYNQMP_DP_TX_CORE_ID 0xfc +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8) +#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT8 +#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1) + +/* AUX channel interface registers */ +#define ZYNQMP_DP_TX_AUX_COMMAND 0x100 +#define ZYNQMP_DP_TX_AUX_COMMAND_CMD_SHIFT 8 +#define ZYNQMP_DP_TX_AUX_COMMAND_ADDRESS_ONLY BIT(12) +#define ZYNQMP_DP_TX_AUX_COMMAND_BYTES_SHIFT 0 +#define ZYNQMP_DP_TX_AUX_WRITE_FIFO0x104 +#define ZYNQMP_DP_TX_AUX_ADDRESS 0x108 +#define ZYNQMP_DP_TX_CLK_DIVIDER
[PATCH v6 1/5] drm: xlnx: Xilinx DRM KMS module
Xilinx has various platforms for display, where users can create using multiple IPs in the programmable FPGA fabric, or where some hardened pipeline is available on the chip. Furthermore, hardened pipeline can also interact with soft logics in FPGA. The Xilinx DRM KMS module is to integrate multiple subdevices and to represent the entire pipeline as a single DRM device. The module includes helper (ex, framebuffer and gem helpers) and glue logic (ex, crtc interface) functions. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v6 - Fix the function desc for pipeline calls - Rebase on drm-misc-next - Fix typos in documentation - Match types for return and internal variables - Remove use of 'tmp' variables - Protect any crtc list iteration with mutex - Remove a check for drm device in crtc unregistration - Split the crtc ops as a separate struct to constify - Embed xlnx_crtc_helper into xlnx_drm - Move to_xlnx_crtc macro close to xlnx_crtc - Remove unneeded include - Replace custom vres module param with CONFIG_DRM_FBDEV_OVERALLOC - Rename crtc to crtc_helper to make it clearer - Use 'DRM device' instead of 'DRM core' - Remove unused function, xlnx_get_format() - Use device instead of platform device for the logical master - Inline xlnx_of_component_probe() - Use of_get_parent() - Remove the port binding handling in the driver - Do complete forward-declarations in headers - Constify all function pointers - Use the default ioctl from fb helper - Return the minimum pitch always - Clean up the duplicate license paragraphs - Get common bits for dma mask instead of minimum value - Remove dummy function declaration from header - Fix a typo in the commit message with some re-organization v5 - Redefine xlnx_pipeline_init() v4 - Fix a bug in of graph binding handling - Remove vblank callbacks from xlnx_crtc - Remove the dt binding. This module becomes more like a library. - Rephrase the commit message v3 - Add Laurent as a maintainer - Fix multiple-reference on gem objects v2 - Change the SPDX identifier format - Merge patches(crtc, gem, fb) into single one v2 of xlnx_drv - Rename kms to display in xlnx_drv - Replace some xlnx specific fb helper with common helpers in xlnx_drv - Don't set the commit tail callback in xlnx_drv - Support 'ports' graph binding in xlnx_drv v2 of xlnx_fb - Remove wrappers in xlnx_fb - Replace some functions with drm core helpers in xlnx_fb --- --- MAINTAINERS | 9 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/xlnx/Kconfig | 12 ++ drivers/gpu/drm/xlnx/Makefile| 2 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 142 + drivers/gpu/drm/xlnx/xlnx_crtc.h | 83 drivers/gpu/drm/xlnx/xlnx_drv.c | 430 +++ drivers/gpu/drm/xlnx/xlnx_drv.h | 23 +++ drivers/gpu/drm/xlnx/xlnx_fb.c | 249 +++ drivers/gpu/drm/xlnx/xlnx_fb.h | 27 +++ drivers/gpu/drm/xlnx/xlnx_gem.c | 36 drivers/gpu/drm/xlnx/xlnx_gem.h | 21 ++ 13 files changed, 1037 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h diff --git a/MAINTAINERS b/MAINTAINERS index 2afba90..44cac79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4810,6 +4810,15 @@ F: drivers/gpu/drm/etnaviv/ F: include/uapi/drm/etnaviv_drm.h F: Documentation/devicetree/bindings/display/etnaviv/ +DRM DRIVERS FOR XILINX +M: Hyun Kwon <hyun.k...@xilinx.com> +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/xlnx/ +F: Documentation/devicetree/bindings/display/xlnx/ +T: git git://anongit.freedesktop.org/drm/drm-misc + DRM DRIVERS FOR ZTE ZX M: Shawn Guo <shawn...@kernel.org> L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index deeefa7..5a3ec66 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -289,6 +289,8 @@ source "drivers/gpu/drm/pl111/Kconfig" source "drivers/gpu/drm/tve200/Kconfig" +source "drivers/gpu/drm/xlnx/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 50093ff..f93557e 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -103,3 +103,4 @@ obj-$(CONFIG_DRM_MXSFB) += mxsfb/ obj-$(CONFIG_DRM_
Re: [PATCH v5 1/5] drm: xlnx: Xilinx DRM KMS module
Hi Laurent, On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote: > Hi Hyun, > > Thank you for the patch. > > On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote: > > Xilinx has various platforms for display, where users can create > > using multiple IPs in the programmable FPGA fabric, or where > > some hardened piepline is available on the chip. Furthermore, > > s/piepline/pipeline/ > Will fix. > > hardened pipeline can also interact with soft logics in FPGA. > > > > The Xilinx DRM KMS module is to integrate multiple subdevices and > > to represent the entire pipeline as a single DRM device. The module > > includes helper (ex, framebuffer and gem helpers) and > > glue logic (ex, crtc interface) functions. > > > > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> > > Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> > > --- > > v5 > > - Redefine xlnx_pipeline_init() > > v4 > > - Fix a bug in of graph binding handling > > - Remove vblank callbacks from xlnx_crtc > > - Remove the dt binding. This module becomes more like a library. > > - Rephrase the commit message > > v3 > > - Add Laurent as a maintainer > > - Fix multiple-reference on gem objects > > v2 > > - Change the SPDX identifier format > > - Merge patches(crtc, gem, fb) into single one > > v2 of xlnx_drv > > - Rename kms to display in xlnx_drv > > - Replace some xlnx specific fb helper with common helpers in xlnx_drv > > - Don't set the commit tail callback in xlnx_drv > > - Support 'ports' graph binding in xlnx_drv > > v2 of xlnx_fb > > - Remove wrappers in xlnx_fb > > - Replace some functions with drm core helpers in xlnx_fb > > --- > > --- > > MAINTAINERS | 9 + > > drivers/gpu/drm/Kconfig | 2 + > > drivers/gpu/drm/Makefile | 1 + > > drivers/gpu/drm/xlnx/Kconfig | 12 + > > drivers/gpu/drm/xlnx/Makefile| 2 + > > drivers/gpu/drm/xlnx/xlnx_crtc.c | 177 ++ > > drivers/gpu/drm/xlnx/xlnx_crtc.h | 70 ++ > > drivers/gpu/drm/xlnx/xlnx_drv.c | 501 > > drivers/gpu/drm/xlnx/xlnx_drv.h | 33 +++ > > drivers/gpu/drm/xlnx/xlnx_fb.c | 298 +++ > > drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++ > > drivers/gpu/drm/xlnx/xlnx_gem.c | 47 > > drivers/gpu/drm/xlnx/xlnx_gem.h | 26 ++ > > 13 files changed, 1211 insertions(+) > > create mode 100644 drivers/gpu/drm/xlnx/Kconfig > > create mode 100644 drivers/gpu/drm/xlnx/Makefile > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 5bc088f..07c0e73 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -4789,6 +4789,15 @@ F: drivers/gpu/drm/etnaviv/ > > F: include/uapi/drm/etnaviv_drm.h > > F: Documentation/devicetree/bindings/display/etnaviv/ > > > > +DRM DRIVERS FOR XILINX > > +M: Hyun Kwon <hyun.k...@xilinx.com> > > +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> > > +L: dri-devel@lists.freedesktop.org > > +S: Maintained > > +F: drivers/gpu/drm/xlnx/ > > +F: Documentation/devicetree/bindings/display/xlnx/ > > +T: git git://anongit.freedesktop.org/drm/drm-misc > > + > > DRM DRIVERS FOR ZTE ZX > > M: Shawn Guo <shawn...@kernel.org> > > L: dri-devel@lists.freedesktop.org > > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig > > index deeefa7..5a3ec66 100644 > > --- a/drivers/gpu/drm/Kconfig > > + * This software is licensed under the terms of the GNU General Public [snip] > > + * License version 2, as published by the Free Software Foundation, and > > + * may be copied, distributed, and modified under those terms. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > You can drop those two paragraphs as you now have an SPDX license header. >
Re: [PATCH RFC v3 4/6] drm: drm_fourcc: Add new formats for Xilinx IPs
Hi Danidel,
Thanks for the comment.
On Mon, 2018-02-19 at 06:22:56 -0800, Daniel Vetter wrote:
> On Fri, Feb 09, 2018 at 05:35:54PM -0800, Hyun Kwon wrote:
> > This patch adds new formats needed by Xilinx IP. Pixels are not
> > byte-aligned in these formats, and the drm_format_info for these
> > formats has macro-pixel information.
> >
> > Signed-off-by: Jeffrey Mouroux <jmour...@xilinx.com>
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > ---
> > v3
> > - Update entries for changes
> > - Squash fourcc patch into this
> > v2
> > - Add detailed descriptions
> > - Remove formats with no user
> > ---
> > ---
> > drivers/gpu/drm/drm_fourcc.c | 2 ++
> > include/uapi/drm/drm_fourcc.h | 8
> > 2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index ed95de2..36bff7a 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -168,6 +168,8 @@ const struct drm_format_info *__drm_format_info(u32
> > format)
> > { .format = DRM_FORMAT_NV61,.depth = 0,
> > .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1 },
> > { .format = DRM_FORMAT_NV24,.depth = 0,
> > .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
> > { .format = DRM_FORMAT_NV42,.depth = 0,
> > .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
> > + { .format = DRM_FORMAT_XV15,.depth = 0,
> > .num_planes = 2, .pixels_per_macropixel = { 3, 3, 0 },
> > .bytes_per_macropixel = { 4, 8, 0 }, .hsub = 2, .vsub = 2, },
> > + { .format = DRM_FORMAT_XV20,.depth = 0,
> > .num_planes = 2, .pixels_per_macropixel = { 3, 3, 0 },
> > .bytes_per_macropixel = { 4, 8, 0 }, .hsub = 2, .vsub = 1, },
>
> There's no need to set fields explicitly to 0. I think we could even do a
> separate patch to nuke all the .depth = 0, assignments.
>
> One thing that I've realized now that your new pixel formats stick out:
> How is macropixel supposed to interact with hsub/vsub? From you example it
> looks like macropixels are applied after subsampling (i.e. a macropixel
> block of 3 pixels, but hsub = 2 means the macroblock will actually span 6
> pixels). I think the kerneldoc in the earlier patch should explain this is
> allowed, and how it's supposed to work exactly.
>
> Also, do we have open-source userspace somewhere for this new pixel format?
>
We have modified modetest to test these formats. The change, especially
the pattern generation part, isn't clean enough to be shared at the moment. But
I can do some clean-up and share if that helps.
Then this change (may not be the latest set) was used to prototype the support
in the gstreamer kmssink plug-in, but it's implemented by Collabora. Not sure
if the change is accessible, but I can check.
I'll address rest of your comments.
Thanks,
-hyun
> Thanks, Daniel
>
>
> > { .format = DRM_FORMAT_YUYV,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> > { .format = DRM_FORMAT_YVYU,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> > { .format = DRM_FORMAT_UYVY,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> > index e04613d..6ac5282 100644
> > --- a/include/uapi/drm/drm_fourcc.h
> > +++ b/include/uapi/drm/drm_fourcc.h
> > @@ -142,6 +142,14 @@ extern "C" {
> > #define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /*
> > non-subsampled Cb:Cr plane */
> >
> > /*
> > + * 2 plane 10 bit per component YCbCr
> > + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
> > + * index 1 = Cb:Cr plane, [63:0] x:Cb2:Cr2:Cb1:x:Cr1:Cb0:Cr0
> > 2:10:10:10:2:10:10:10 little endian
> > + */
> > +#define DRM_FORMAT_XV15fourcc_code('X', 'V', '1', '5') /* 2x2
> > subsampled Cb:Cr plane 2:10:10:10 */
> > +#define DRM_FORMAT_XV20fourcc_code('X', 'V', '2', '0') /* 2x1
> > subsampled Cb:Cr plane 2:10:10:10 */
> > +
> > +/*
> > * 3 plane YCbCr
> > * index 0: Y plane, [7:0] Y
> > * index 1: Cb plane, [7:0] Cb
> > --
> > 2.7.4
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [PATCH v5 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
Hi Laurent,
On Thu, 2018-02-22 at 06:23:38 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> Thank you for the patch.
>
> On Wednesday, 7 February 2018 03:36:37 EET Hyun Kwon wrote:
> > This add a dt binding for ZynqMP DP subsystem.
> >
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > Reviewed-by: Rob Herring <r...@kernel.org>
> > ---
> > v4
> > - Specify phy related descriptions
> > - Specify dma related descriptions
> > - Remove ports
> > - Remove child nodes for layers
> > - Update the example accordingly
> > v2
> > - Group multiple ports under 'ports'
> > - Replace linux specific terms with generic hardware descriptions
> > ---
> > ---
> > .../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 67 +++
> > 1 file changed, 67 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
> > b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt new
> > file mode 100644
> > index 000..f4a2e6d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
> > @@ -0,0 +1,67 @@
> > +Xilinx ZynqMP DisplayPort subsystem
> > +---
>
> A short description of the hardware would be useful. You can also link to the
> documentation. I have found v1.0, v2.0 and v2.1 of the PG199 document, which
> seem to correspond to the "dp" register map (and confusingly documented as
> the
> "DisplayPort TX Subsystem"), but no document that describes the full
> DisplayPort subsystem as defined by these bindings.
Please refer to chapter 33 in
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
Not sure if it has enough details, but only public documentation that I know of.
>
> > +Required properties:
> > +
> > +- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
> > +
> > +- reg: Physical base address and length of the registers set for the
> > device.
> > +- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical
> > register
> > + partitions.
> > +
> > +- interrupts: Interrupt number.
> > +- interrupts-parent: phandle for interrupt controller.
> > +
> > +- clocks: phandles for axi, audio, non-live video, and live video clocks.
> > + axi clock is required. Audio clock is optional. If not present, audio
> > will
> > + be disabled. One of non-live or live video clock should be present.
> > +- clock-names: The identification strings are required. "aclk" for axi
> > clock.
> > + "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video
> > clock.
> > + "dp_live_video_in_clk" for live video clock (clock from programmable
> > logic).
> > +
> > +- phys: phandles for phy specifier. The number of lanes is configurable
> > + between 1 and 2. The number of phandles should be 1 or 2.
> > +- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
> > + For single lane, only "dp-phy0" is required. For dual lane, both
> > "dp-phy0"
> > + and "dp-phy1" are required where "dp-phy0" is the primary lane.
> > +
> > +- power-domains: phandle for the corresponding power domain
> > +
> > +- dmas: phandles for DMA channels as defined in
> > + Documentation/devicetree/bindings/dma/dma.txt.
> > +- dma-names: The identifier strings are required. "gfx0" for graphics layer
> > + dma channel. "vid" followed by index (0 - 2) for video layer dma
> > channels.
> > +
> > +Optional child node
> > +
> > +- The driver populates any child device node in this node. This can be
> > used,
> > + for example, to populate the sound device from the DisplayPort subsystem
> > + driver.
>
> DT bindings should describe the hardware, not the OS software. You should not
> mention drivers.
>
> Furthermore the above paragraph doesn't seem very clear to me, and the
> example
> doesn't include any child node, so I'm left wondering what you meant.
I left some room for future and downstream, but I agree. I can remove this from
this set.
>
> > +Example:
> > + zynqmp-display-subsystem@fd4a {
> > + compatible = "xlnx,zynqmp-dpsub-1.7";
> > + reg = <0x0 0xfd4a 0x0 0x1000>
Re: [PATCH v5 1/5] drm: xlnx: Xilinx DRM KMS module
Hi Laurent,
On Thu, 2018-02-22 at 05:40:50 -0800, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Thursday, 22 February 2018 04:50:42 EET Hyun Kwon wrote:
> > On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote:
> > > On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote:
> > >> Xilinx has various platforms for display, where users can create
> > >> using multiple IPs in the programmable FPGA fabric, or where
> > >> some hardened piepline is available on the chip. Furthermore,
> > >
> > > s/piepline/pipeline/
> > >
> > >> hardened pipeline can also interact with soft logics in FPGA.
> > >>
> > >> The Xilinx DRM KMS module is to integrate multiple subdevices and
> > >> to represent the entire pipeline as a single DRM device. The module
> > >> includes helper (ex, framebuffer and gem helpers) and
> > >> glue logic (ex, crtc interface) functions.
> > >>
> > >> Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > >> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> > >> ---
> > >> v5
> > >> - Redefine xlnx_pipeline_init()
> > >> v4
> > >> - Fix a bug in of graph binding handling
> > >> - Remove vblank callbacks from xlnx_crtc
> > >> - Remove the dt binding. This module becomes more like a library.
> > >> - Rephrase the commit message
> > >> v3
> > >> - Add Laurent as a maintainer
> > >> - Fix multiple-reference on gem objects
> > >> v2
> > >> - Change the SPDX identifier format
> > >> - Merge patches(crtc, gem, fb) into single one
> > >> v2 of xlnx_drv
> > >> - Rename kms to display in xlnx_drv
> > >> - Replace some xlnx specific fb helper with common helpers in xlnx_drv
> > >> - Don't set the commit tail callback in xlnx_drv
> > >> - Support 'ports' graph binding in xlnx_drv
> > >> v2 of xlnx_fb
> > >> - Remove wrappers in xlnx_fb
> > >> - Replace some functions with drm core helpers in xlnx_fb
> > >> ---
> > >> ---
> > >>
> > >> MAINTAINERS | 9 +
> > >> drivers/gpu/drm/Kconfig | 2 +
> > >> drivers/gpu/drm/Makefile | 1 +
> > >> drivers/gpu/drm/xlnx/Kconfig | 12 +
> > >> drivers/gpu/drm/xlnx/Makefile| 2 +
> > >> drivers/gpu/drm/xlnx/xlnx_crtc.c | 177 ++
> > >> drivers/gpu/drm/xlnx/xlnx_crtc.h | 70 ++
> > >> drivers/gpu/drm/xlnx/xlnx_drv.c | 501 +
> > >> drivers/gpu/drm/xlnx/xlnx_drv.h | 33 +++
> > >> drivers/gpu/drm/xlnx/xlnx_fb.c | 298 +++
> > >> drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++
> > >> drivers/gpu/drm/xlnx/xlnx_gem.c | 47
> > >> drivers/gpu/drm/xlnx/xlnx_gem.h | 26 ++
> > >> 13 files changed, 1211 insertions(+)
> > >> create mode 100644 drivers/gpu/drm/xlnx/Kconfig
> > >> create mode 100644 drivers/gpu/drm/xlnx/Makefile
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c
> > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h
>
> [snip]
>
> > >> diff --git a/drivers/gpu/drm/xlnx/xlnx_crtc.c
> > >> b/drivers/gpu/drm/xlnx/xlnx_crtc.c new file mode 100644
> > >> index 000..de83905
> > >> --- /dev/null
> > >> +++ b/drivers/gpu/drm/xlnx/xlnx_crtc.c
>
> [snip]
>
> > >> +uint32_t xlnx_crtc_helper_get_format(struct xlnx_crtc_helper *helper)
> > >
> > > You can use the u32 type within the kernel.
> > >
> > >> +{
> > >> +struct xlnx_crtc *crtc;
> > >> +u32 format = 0, tmp;
> > >> +
> > >> +list_for_each_entry(crtc, >xlnx_crtcs, list) {
> > >> +if (crtc->get_format) {
> > >> +tmp = crtc->get_format(crtc);
> > >> +if (format && format != tmp)
> > >> +
Re: [PATCH v5 1/5] drm: xlnx: Xilinx DRM KMS module
Hi Laurent, On Wed, 2018-02-21 at 15:22:31 -0800, Laurent Pinchart wrote: > Hi Hyun, > > On Tuesday, 20 February 2018 19:11:42 EET hyun.k...@xilinx.com wrote: > > On Monday, February 19, 2018 1:43 AM Daniel Vetter wrote: > > > On Tue, Feb 06, 2018 at 05:36:36PM -0800, Hyun Kwon wrote: > > >> Xilinx has various platforms for display, where users can create > > >> using multiple IPs in the programmable FPGA fabric, or where > > >> some hardened piepline is available on the chip. Furthermore, > > >> hardened pipeline can also interact with soft logics in FPGA. > > >> > > >> The Xilinx DRM KMS module is to integrate multiple subdevices and > > >> to represent the entire pipeline as a single DRM device. The module > > >> includes helper (ex, framebuffer and gem helpers) and > > >> glue logic (ex, crtc interface) functions. > > >> > > >> Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> > > >> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> > > > > > > Looks all ready for merging. Did you apply for commit rights to drm-misc > > > already so you could push this right away? > > > > Yes, I've created the request, and am waiting for the response there: > > https://bugs.freedesktop.org/show_bug.cgi?id=105017 > > I've just sent an in-depth review of patch 1/5 (sorry for being late). There > are lots of small comments that could be addressed as follow-up patches in > the > worst case, but there's one comment regarding the ports DT property that > worries me and that I'd like to see addressed (or, if I got it wrong, > explained) before we merge this. Another related issue that I'd like to > discuss is the need for the artificial xilinx-drm platform device. And of > course if a v6 is needed, you can address all the other small comments :-) > Thanks! I skimmed through your comments, and I prefer to clear and address all in v6 before committing this. I've replied directly to those comments so we can continue to discuss there. Thanks, -hyun > > >> --- > > >> v5 > > >> - Redefine xlnx_pipeline_init() > > >> v4 > > >> - Fix a bug in of graph binding handling > > >> - Remove vblank callbacks from xlnx_crtc > > >> - Remove the dt binding. This module becomes more like a library. > > >> - Rephrase the commit message > > >> v3 > > >> - Add Laurent as a maintainer > > >> - Fix multiple-reference on gem objects > > >> v2 > > >> - Change the SPDX identifier format > > >> - Merge patches(crtc, gem, fb) into single one > > >> v2 of xlnx_drv > > >> - Rename kms to display in xlnx_drv > > >> - Replace some xlnx specific fb helper with common helpers in xlnx_drv > > >> - Don't set the commit tail callback in xlnx_drv > > >> - Support 'ports' graph binding in xlnx_drv > > >> v2 of xlnx_fb > > >> - Remove wrappers in xlnx_fb > > >> - Replace some functions with drm core helpers in xlnx_fb > > >> --- > > >> --- > > >> > > >> MAINTAINERS | 9 + > > >> drivers/gpu/drm/Kconfig | 2 + > > >> drivers/gpu/drm/Makefile | 1 + > > >> drivers/gpu/drm/xlnx/Kconfig | 12 + > > >> drivers/gpu/drm/xlnx/Makefile| 2 + > > >> drivers/gpu/drm/xlnx/xlnx_crtc.c | 177 ++ > > >> drivers/gpu/drm/xlnx/xlnx_crtc.h | 70 ++ > > >> drivers/gpu/drm/xlnx/xlnx_drv.c | 501 + > > >> drivers/gpu/drm/xlnx/xlnx_drv.h | 33 +++ > > >> drivers/gpu/drm/xlnx/xlnx_fb.c | 298 +++ > > >> drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++ > > >> drivers/gpu/drm/xlnx/xlnx_gem.c | 47 > > >> drivers/gpu/drm/xlnx/xlnx_gem.h | 26 ++ > > >> 13 files changed, 1211 insertions(+) > > >> create mode 100644 drivers/gpu/drm/xlnx/Kconfig > > >> create mode 100644 drivers/gpu/drm/xlnx/Makefile > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c > > >> create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h > > [snip] > > -- > Regards, > > Laurent Pinchart > > ___ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
Hi Laurent, Thanks for the comment. On Wed, 2018-02-21 at 16:18:35 -0800, Laurent Pinchart wrote: > Hi Hyun, > > Thank you for the patch. > > On Wednesday, 7 February 2018 03:36:39 EET Hyun Kwon wrote: > > This driver creates DRM encoder and connector for ZynqMP DisplayPort. > > > > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> > > Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> > > Before I go and review the code, shouldn't this be implemented as a > drm_bridge > driver ? The hardware itself has complete encoder and connector functionalities, so I don't think it needs to be a drm_bridge. Thanks, -hyun > > > --- > > v2 > > - Change the SPDX identifier format > > - Split drm properties into a separate patch > > --- > > --- > > drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738 +++ > > drivers/gpu/drm/xlnx/zynqmp_dp.h | 37 + > > 2 files changed, 1775 insertions(+) > > create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c > > create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h > > [snip] > > -- > Regards, > > Laurent Pinchart > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 1/5] drm: xlnx: Xilinx DRM KMS module
Hi Laurent, Thanks for the review. On Wed, 2018-02-21 at 15:17:25 -0800, Laurent Pinchart wrote: > Hi Hyun, > > Thank you for the patch. > > On Wednesday, 7 February 2018 03:36:36 EET Hyun Kwon wrote: > > Xilinx has various platforms for display, where users can create > > using multiple IPs in the programmable FPGA fabric, or where > > some hardened piepline is available on the chip. Furthermore, > > s/piepline/pipeline/ > > > hardened pipeline can also interact with soft logics in FPGA. > > > > The Xilinx DRM KMS module is to integrate multiple subdevices and > > to represent the entire pipeline as a single DRM device. The module > > includes helper (ex, framebuffer and gem helpers) and > > glue logic (ex, crtc interface) functions. > > > > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> > > Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> > > --- > > v5 > > - Redefine xlnx_pipeline_init() > > v4 > > - Fix a bug in of graph binding handling > > - Remove vblank callbacks from xlnx_crtc > > - Remove the dt binding. This module becomes more like a library. > > - Rephrase the commit message > > v3 > > - Add Laurent as a maintainer > > - Fix multiple-reference on gem objects > > v2 > > - Change the SPDX identifier format > > - Merge patches(crtc, gem, fb) into single one > > v2 of xlnx_drv > > - Rename kms to display in xlnx_drv > > - Replace some xlnx specific fb helper with common helpers in xlnx_drv > > - Don't set the commit tail callback in xlnx_drv > > - Support 'ports' graph binding in xlnx_drv > > v2 of xlnx_fb > > - Remove wrappers in xlnx_fb > > - Replace some functions with drm core helpers in xlnx_fb > > --- > > --- > > MAINTAINERS | 9 + > > drivers/gpu/drm/Kconfig | 2 + > > drivers/gpu/drm/Makefile | 1 + > > drivers/gpu/drm/xlnx/Kconfig | 12 + > > drivers/gpu/drm/xlnx/Makefile| 2 + > > drivers/gpu/drm/xlnx/xlnx_crtc.c | 177 ++ > > drivers/gpu/drm/xlnx/xlnx_crtc.h | 70 ++ > > drivers/gpu/drm/xlnx/xlnx_drv.c | 501 > > drivers/gpu/drm/xlnx/xlnx_drv.h | 33 +++ > > drivers/gpu/drm/xlnx/xlnx_fb.c | 298 +++ > > drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++ > > drivers/gpu/drm/xlnx/xlnx_gem.c | 47 > > drivers/gpu/drm/xlnx/xlnx_gem.h | 26 ++ > > 13 files changed, 1211 insertions(+) > > create mode 100644 drivers/gpu/drm/xlnx/Kconfig > > create mode 100644 drivers/gpu/drm/xlnx/Makefile > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 5bc088f..07c0e73 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -4789,6 +4789,15 @@ F: drivers/gpu/drm/etnaviv/ > > F: include/uapi/drm/etnaviv_drm.h > > F: Documentation/devicetree/bindings/display/etnaviv/ > > > > +DRM DRIVERS FOR XILINX > > +M: Hyun Kwon <hyun.k...@xilinx.com> > > +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> > > +L: dri-devel@lists.freedesktop.org > > +S: Maintained > > +F: drivers/gpu/drm/xlnx/ > > +F: Documentation/devicetree/bindings/display/xlnx/ > > +T: git git://anongit.freedesktop.org/drm/drm-misc > > + > > DRM DRIVERS FOR ZTE ZX > > M: Shawn Guo <shawn...@kernel.org> > > L: dri-devel@lists.freedesktop.org > > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig > > index deeefa7..5a3ec66 100644 > > --- a/drivers/gpu/drm/Kconfig > > +++ b/drivers/gpu/drm/Kconfig > > @@ -289,6 +289,8 @@ source "drivers/gpu/drm/pl111/Kconfig" > > > > source "drivers/gpu/drm/tve200/Kconfig" > > > > +source "drivers/gpu/drm/xlnx/Kconfig" > > I would have spelled that out completely as I think it will be easier to > understand, but it's up to you. > > > # Keep legacy drivers last > > > > menuconfig DRM_LEGACY > > diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile > > index 50093ff..f93557e 100644 > > --- a/drivers/gpu/drm/Ma
[PATCH RFC v3 4/6] drm: drm_fourcc: Add new formats for Xilinx IPs
This patch adds new formats needed by Xilinx IP. Pixels are not
byte-aligned in these formats, and the drm_format_info for these
formats has macro-pixel information.
Signed-off-by: Jeffrey Mouroux <jmour...@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v3
- Update entries for changes
- Squash fourcc patch into this
v2
- Add detailed descriptions
- Remove formats with no user
---
---
drivers/gpu/drm/drm_fourcc.c | 2 ++
include/uapi/drm/drm_fourcc.h | 8
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index ed95de2..36bff7a 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -168,6 +168,8 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_NV61,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_NV24,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_NV42,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XV15,.depth = 0,
.num_planes = 2, .pixels_per_macropixel = { 3, 3, 0 }, .bytes_per_macropixel =
{ 4, 8, 0 }, .hsub = 2, .vsub = 2, },
+ { .format = DRM_FORMAT_XV20,.depth = 0,
.num_planes = 2, .pixels_per_macropixel = { 3, 3, 0 }, .bytes_per_macropixel =
{ 4, 8, 0 }, .hsub = 2, .vsub = 1, },
{ .format = DRM_FORMAT_YUYV,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_YVYU,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index e04613d..6ac5282 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,14 @@ extern "C" {
#define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /*
non-subsampled Cb:Cr plane */
/*
+ * 2 plane 10 bit per component YCbCr
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cb:Cr plane, [63:0] x:Cb2:Cr2:Cb1:x:Cr1:Cb0:Cr0
2:10:10:10:2:10:10:10 little endian
+ */
+#define DRM_FORMAT_XV15fourcc_code('X', 'V', '1', '5') /* 2x2
subsampled Cb:Cr plane 2:10:10:10 */
+#define DRM_FORMAT_XV20fourcc_code('X', 'V', '2', '0') /* 2x1
subsampled Cb:Cr plane 2:10:10:10 */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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[PATCH RFC v3 0/6] Support of non-byte aligned formats in drm
Hi, Following up on v1 [1] and v2 [2], this series is to address non-byte aligned formats in drm. Based on the comments, the set is getting simplified, and any further comment would be appreciated. Brief description: Patch 1 just changes comment style for change in patch 2 Patch 2 adds macro-pixel information to drm_format_info Patch 3 adds a drm function that uses the macro-pixel information Patch 4 adds new formats along with macro-pixel info Patch 5 shows the example of driver integration Patch 6 includes additional format strings Thanks, -hyun [1] https://lists.freedesktop.org/archives/dri-devel/2017-November/158744.html [2] https://www.spinics.net/lists/dri-devel/msg163388.html Hyun Kwon (6): drm: fourcc.h: Use inline kern-doc style for struct drm_format_info drm: drm_fourcc: Introduce macro-pixel info to drm_format_info drm: fourcc: Add drm_format_plane_width_bytes() drm: drm_fourcc: Add new formats for Xilinx IPs drm: xlnx: zynqmp: Add XV15 and XV20 formats drm: fourcc: Add new formats needed by Xilinx IP drivers/gpu/drm/drm_fb_cma_helper.c | 3 +- drivers/gpu/drm/drm_fourcc.c| 42 ++ drivers/gpu/drm/xlnx/zynqmp_disp.c | 22 +++- include/drm/drm_fourcc.h| 69 - include/uapi/drm/drm_fourcc.h | 15 5 files changed, 141 insertions(+), 10 deletions(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH RFC v3 3/6] drm: fourcc: Add drm_format_plane_width_bytes()
drm_format_plane_width_bytes() calculates and returns the number of bytes
for given width of specified format. The calculation uses @cpp
in drm format info for byte-aligned formats. If the format isn't
byte-aligned, @cpp should 0, and the macro pixel information is used.
This avoids bit level rounding.
Use this drm_fb_cma_get_gem_addr() for offset calculation.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v3
- Update according to member changes
- Use @cpp for byte-aligned formats, and macro-pixel for non byte-aligned ones
- Squash a change in drm_fb_cma_helper.c into this
v2
- This function is added
---
---
drivers/gpu/drm/drm_fb_cma_helper.c | 3 ++-
drivers/gpu/drm/drm_fourcc.c| 35 +++
include/drm/drm_fourcc.h| 2 ++
3 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
b/drivers/gpu/drm/drm_fb_cma_helper.c
index 186d00a..271175e 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -124,7 +124,8 @@ dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer
*fb,
return 0;
paddr = obj->paddr + fb->offsets[plane];
- paddr += fb->format->cpp[plane] * (state->src_x >> 16);
+ paddr += drm_format_plane_width_bytes(fb->format, plane,
+ state->src_x >> 16);
paddr += fb->pitches[plane] * (state->src_y >> 16);
return paddr;
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 9c0152d..ed95de2 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -348,3 +348,38 @@ int drm_format_plane_height(int height, uint32_t format,
int plane)
return height / info->vsub;
}
EXPORT_SYMBOL(drm_format_plane_height);
+
+/**
+ * drm_format_plane_width_bytes - bytes of the given width of the plane
+ * @info: DRM format information
+ * @plane: plane index
+ * @width: width to get the number of bytes
+ *
+ * This returns the number of bytes for given @width and @plane.
+ * The @cpp or macro pixel information should be valid.
+ *
+ * Returns:
+ * The bytes of @width of @plane. 0 for invalid format info.
+ */
+int drm_format_plane_width_bytes(const struct drm_format_info *info,
+int plane, int width)
+{
+ if (!info || plane >= info->num_planes)
+ return 0;
+
+ if (info->cpp[plane])
+ return info->cpp[plane] * width;
+
+ if (WARN_ON(!info->bytes_per_macropixel[plane] ||
+ !info->pixels_per_macropixel[plane])) {
+ struct drm_format_name_buf buf;
+
+ DRM_WARN("Either cpp or macro-pixel info should be valid: %s\n",
+drm_get_format_name(info->format, ));
+ return 0;
+ }
+
+ return DIV_ROUND_UP(width * info->bytes_per_macropixel[plane],
+ info->pixels_per_macropixel[plane]);
+}
+EXPORT_SYMBOL(drm_format_plane_width_bytes);
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index ce59329..8158290 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -119,6 +119,8 @@ int drm_format_horz_chroma_subsampling(uint32_t format);
int drm_format_vert_chroma_subsampling(uint32_t format);
int drm_format_plane_width(int width, uint32_t format, int plane);
int drm_format_plane_height(int height, uint32_t format, int plane);
+int drm_format_plane_width_bytes(const struct drm_format_info *info,
+int plane, int width);
const char *drm_get_format_name(uint32_t format, struct drm_format_name_buf
*buf);
#endif /* __DRM_FOURCC_H__ */
--
2.7.4
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[PATCH RFC v3 2/6] drm: drm_fourcc: Introduce macro-pixel info to drm_format_info
Multiple pixels can be grouped as a single unit and form a 'macro-pixel'.
This is to model formats where multiple non-byte aligned pixels are stored
together in a byte-aligned way. For example, if 3 - 10 bit
pixels are stored in 32 bit, the 32 bit stroage can be treated as
a single macro-pixel with 3 pixels. This aligns non-byte addressable
formats with drm core where each pixel / component is expected to be
byte aligned.
Add 'pixels_per_macro' to note how many pixels are in a macro-pixel.
'bytes_per_macro' specifies the size of a macro-pixel in bytes.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v3
- Rename members and rephrase descriptions
- Rephrase the commit message
- Use in-line style comments
v2
- Introduce macro-pixel over scaling factors
---
---
include/drm/drm_fourcc.h | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index b00bae4..ce59329 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -58,11 +58,33 @@ struct drm_format_info {
/**
* @cpp:
*
-* Number of bytes per pixel (per plane)
+* Number of bytes per pixel (per plane). @cpp shouldn't be used when
+* @pixels_per_macropixel and @bytes_per_macropixel are used.
*/
u8 cpp[3];
/**
+* @pixels_per_macropixel:
+*
+* Number of pixels per macro-pixel (per plane). A macro-pixel is
+* composed of multiple pixels, and there can be extra bits between
+* pixels. This must be used along with @bytes_per_macropixel, only
+* when single pixel size is not byte-aligned. In this case, @cpp
+* is not valid and should be 0.
+*/
+ u8 pixels_per_macropixel[3];
+
+ /*
+* @bytes_per_macropixel:
+*
+* Number of bytes per macro-pixel (per plane). A macro-pixel is
+* composed of multiple pixels. The size of single macro-pixel should
+* be byte-aligned. This should be used with @pixels_per_macropixel,
+* and @cpp should be 0.
+*/
+ u8 bytes_per_macropixel[3];
+
+ /**
* @hsub:
*
* Horizontal chroma subsampling factor
--
2.7.4
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[PATCH RFC v3 6/6] drm: fourcc: Add new formats needed by Xilinx IP
This adds packed YUV and grey scale format fourccs.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v3
- Update entries for changes
- Squash fourcc patch into this
- Note these don't have any reference in mainline
v2
- Split from the previous patch
---
---
drivers/gpu/drm/drm_fourcc.c | 5 +
include/uapi/drm/drm_fourcc.h | 7 +++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 36bff7a..cf35251 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -175,6 +175,11 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_VUY888, .depth = 0,
.num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XVUY,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XVUY2101010, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_Y8, .depth = 0,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_Y10, .depth = 0,
.num_planes = 1, .pixels_per_macropixel = { 3, 0, 0 }, .bytes_per_macropixel =
{ 4, 0, 0 }, .hsub = 1, .vsub = 1 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 6ac5282..7014a3d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -112,6 +112,13 @@ extern "C" {
#define DRM_FORMAT_VYUYfourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0]
Cr:Cb:Y 8:8:8 little endian */
+#define DRM_FORMAT_XVUYfourcc_code('X', 'V', '2', '4') /* [31:0]
x:Cr:Cb:Y 8:8:8:8 little endian */
+#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'Y', '3', '0') /* [31:0]
x:Cr:Cb:Y 2:10:10:10 little endian */
+
+/* Grey scale */
+#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8 Greyscale
*/
+#define DRM_FORMAT_Y10 fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale
*/
/*
* 2 plane RGB + A
--
2.7.4
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[PATCH RFC v3 1/6] drm: fourcc.h: Use inline kern-doc style for struct drm_format_info
Use the inline kern-doc style for struct drm_format_info for better
readability. This is just a preliminary change for further table update.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v3
- This is added
---
---
include/drm/drm_fourcc.h | 45 +
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 6942e84..b00bae4 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -30,21 +30,50 @@ struct drm_mode_fb_cmd2;
/**
* struct drm_format_info - information about a DRM format
- * @format: 4CC format identifier (DRM_FORMAT_*)
- * @depth: Color depth (number of bits per pixel excluding padding bits),
- * valid for a subset of RGB formats only. This is a legacy field, do not
- * use in new code and set to 0 for new formats.
- * @num_planes: Number of color planes (1 to 3)
- * @cpp: Number of bytes per pixel (per plane)
- * @hsub: Horizontal chroma subsampling factor
- * @vsub: Vertical chroma subsampling factor
*/
struct drm_format_info {
+ /**
+* @format:
+*
+* 4CC format identifier (DRM_FORMAT_*)
+*/
u32 format;
+
+ /**
+* @depth:
+*
+* Color depth (number of bits per pixel excluding padding bits),
+* valid for a subset of RGB formats only. This is a legacy field,
+* do not use in new code and set to 0 for new formats.
+*/
u8 depth;
+
+ /**
+* @num_planes:
+*
+* Number of color planes (1 to 3)
+*/
u8 num_planes;
+
+ /**
+* @cpp:
+*
+* Number of bytes per pixel (per plane)
+*/
u8 cpp[3];
+
+ /**
+* @hsub:
+*
+* Horizontal chroma subsampling factor
+*/
u8 hsub;
+
+ /**
+* @vsub:
+*
+* Vertical chroma subsampling factor
+*/
u8 vsub;
};
--
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[PATCH RFC v3 5/6] drm: xlnx: zynqmp: Add XV15 and XV20 formats
Use drm_format_width_bytes() to support non-byte aligned formats.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v3
- 2 patches are squashed
---
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index e47d77d..13053fc 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -968,6 +968,24 @@ static const struct zynqmp_disp_fmt av_buf_vid_fmts[] = {
.sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
.sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
.sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt= DRM_FORMAT_XV15,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10,
+ .rgb= false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ }, {
+ .drm_fmt= DRM_FORMAT_XV20,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
+ .rgb= false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
}
};
@@ -2133,6 +2151,7 @@ static int zynqmp_disp_plane_mode_set(struct drm_plane
*plane,
for (i = 0; i < info->num_planes; i++) {
unsigned int width = src_w / (i ? info->hsub : 1);
unsigned int height = src_h / (i ? info->vsub : 1);
+ int width_bytes;
paddr = drm_fb_cma_get_gem_addr(fb, plane->state, i);
if (!paddr) {
@@ -2141,7 +2160,8 @@ static int zynqmp_disp_plane_mode_set(struct drm_plane
*plane,
}
layer->dma[i].xt.numf = height;
- layer->dma[i].sgl[0].size = width * info->cpp[i];
+ width_bytes = drm_format_plane_width_bytes(info, i, width);
+ layer->dma[i].sgl[0].size = width_bytes;
layer->dma[i].sgl[0].icg = fb->pitches[i] -
layer->dma[i].sgl[0].size;
layer->dma[i].xt.src_start = paddr;
--
2.7.4
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Re: [RFC v2 02/10] drm: drm_fourcc: Introduce macro-pixel info to drm_format_info
Hi Daniel,
On Tue, 2018-01-30 at 02:27:07 -0800, Daniel Vetter wrote:
> On Thu, Jan 25, 2018 at 06:03:59PM -0800, Hyun Kwon wrote:
> > Multiple pixels can be grouped as a single unit and form a 'macro-pixel'.
> > This is to model formats where multiple pixels are stored together
> > in a specific way, likely byte-algined. For example, if 3 - 10 bit
> > pixels are stored in 32 bit, the 32 bit stroage can be treated as
> > a single macro-pixel with 3 pixels. This aligns non-byte addressable
> > formats with drm core where bpp is expected to be multiple of 8 bit.
> >
> > Add 'ppm', pixels per macro-pixel, to note how many pixels are grouped
> > in a macro-pixel. 'bpm', bits per macro-pixel, specifies how many bits
> > are in a macro-pixel as there can be some extra padding bits.
> >
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
>
> Another thought: If we require that a format description has either cpp or
> the macro-pixel stuff set (but not both), then we could avoid changing the
> entire table. Calculating the width in bytes would first use cpp, and if
> that's 0, try to compute the width using the macro-pixel stuff. And if
> that's also 0, then WARN_ON (since it's a kernel bug).
That certainly will minimize the change. Thanks a lot for suggestion! I will
address your comments in next version.
Thanks,
-hyun
> -Daniel
>
> > ---
> > v2
> > - Introduce macro-pixel over scaling factors
> > ---
> > ---
> > drivers/gpu/drm/drm_fourcc.c | 136
> > +--
> > include/drm/drm_fourcc.h | 9 +++
> > 2 files changed, 77 insertions(+), 68 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index b891fe0..8fc1e35 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -105,74 +105,74 @@ EXPORT_SYMBOL(drm_get_format_name);
> > const struct drm_format_info *__drm_format_info(u32 format)
> > {
> > static const struct drm_format_info formats[] = {
> > - { .format = DRM_FORMAT_C8, .depth = 8,
> > .num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGB332, .depth = 8,
> > .num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGR233, .depth = 8,
> > .num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_XRGB,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_XBGR,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGBX,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGRX,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_ARGB,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_ABGR,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGBA,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGRA,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_XRGB1555,.depth = 15,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_XBGR1555,.depth = 15,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGBX5551,.depth = 15,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGRX5551,.depth = 15,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_ARGB1555,.depth = 15,
> > .nu
Re: [RFC v2 02/10] drm: drm_fourcc: Introduce macro-pixel info to drm_format_info
Hi Daniel,
On Tue, 2018-01-30 at 02:22:40 -0800, Daniel Vetter wrote:
> On Thu, Jan 25, 2018 at 06:03:59PM -0800, Hyun Kwon wrote:
> > Multiple pixels can be grouped as a single unit and form a 'macro-pixel'.
> > This is to model formats where multiple pixels are stored together
> > in a specific way, likely byte-algined. For example, if 3 - 10 bit
> > pixels are stored in 32 bit, the 32 bit stroage can be treated as
> > a single macro-pixel with 3 pixels. This aligns non-byte addressable
> > formats with drm core where bpp is expected to be multiple of 8 bit.
> >
> > Add 'ppm', pixels per macro-pixel, to note how many pixels are grouped
> > in a macro-pixel. 'bpm', bits per macro-pixel, specifies how many bits
> > are in a macro-pixel as there can be some extra padding bits.
>
> Should we mandate that macro-pixels are always byte-aligned? This would
> mean cpm for characters per macro-pixel would be more meaningful.
>
Agreed. That would simplify stuff and be more clean.
> >
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > ---
> > v2
> > - Introduce macro-pixel over scaling factors
> > ---
> > ---
> > drivers/gpu/drm/drm_fourcc.c | 136
> > +--
> > include/drm/drm_fourcc.h | 9 +++
> > 2 files changed, 77 insertions(+), 68 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> > index b891fe0..8fc1e35 100644
> > --- a/drivers/gpu/drm/drm_fourcc.c
> > +++ b/drivers/gpu/drm/drm_fourcc.c
> > @@ -105,74 +105,74 @@ EXPORT_SYMBOL(drm_get_format_name);
> > const struct drm_format_info *__drm_format_info(u32 format)
> > {
> > static const struct drm_format_info formats[] = {
> > - { .format = DRM_FORMAT_C8, .depth = 8,
> > .num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGB332, .depth = 8,
> > .num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGR233, .depth = 8,
> > .num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_XRGB,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_XBGR,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGBX,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGRX,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_ARGB,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_ABGR,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_RGBA,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
> > - { .format = DRM_FORMAT_BGRA,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub
> > = 1 },
[snip]
> + { .format = DRM_FORMAT_NV16,.depth = 0,
> .num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0
> }, .bpm = { 8, 16, 0 }, .hsub = 2, .vsub = 1 },
> > + { .format = DRM_FORMAT_NV61,.depth = 0,
> > .num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0
> > }, .bpm = { 8, 16, 0 }, .hsub = 2, .vsub = 1 },
> > + { .format = DRM_FORMAT_NV24,.depth = 0,
> > .num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0
> > }, .bpm = { 8, 16, 0 }, .hsub = 1, .vsub = 1 },
> > + { .format = DRM_FORMAT_NV42,.depth = 0,
> > .num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0
> > }, .bpm = { 8, 16, 0 }, .hsub = 1, .vsub = 1 },
> > + { .format = DRM_FORMAT_YUYV,.depth = 0,
> > .num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .ppm = { 1, 0, 0
> > }, .bpm = { 16, 0, 0 }, .hsub = 2, .vsub = 1 },
> > +
[PATCH v5 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
This driver creates DRM encoder and connector for ZynqMP DisplayPort. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v2 - Change the SPDX identifier format - Split drm properties into a separate patch --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738 ++ drivers/gpu/drm/xlnx/zynqmp_dp.h | 37 + 2 files changed, 1775 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c new file mode 100644 index 000..9c9f4df --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -0,0 +1,1738 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP DisplayPort Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "zynqmp_disp.h" +#include "zynqmp_dpsub.h" + +static uint zynqmp_dp_aux_timeout_ms = 50; +module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); + +/* + * Some sink requires a delay after power on request + */ +static uint zynqmp_dp_power_on_delay_ms = 4; +module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); + +/* Link configuration registers */ +#define ZYNQMP_DP_TX_LINK_BW_SET 0x0 +#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4 +#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8 +#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc +#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE0x14 +#define ZYNQMP_DP_TX_DOWNSPREAD_CTL0x18 +#define ZYNQMP_DP_TX_SW_RESET 0x1c +#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0) +#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1) +#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2) +#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3) +#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7) +#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM2 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM3 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM4 | \ + ZYNQMP_DP_TX_SW_RESET_AUX) + +/* Core enable registers */ +#define ZYNQMP_DP_TX_ENABLE0x80 +#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM0x84 +#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0 +#define ZYNQMP_DP_TX_VERSION 0xf8 +#define ZYNQMP_DP_TX_VERSION_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_VERSION_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12) +#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT12 +#define ZYNQMP_DP_TX_VERSION_PATCH_MASKGENMASK(11, 8) +#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8 +#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0) +#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT0 + +/* Core ID registers */ +#define ZYNQMP_DP_TX_CORE_ID 0xfc +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8) +#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT8 +#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1) + +/* AUX channel interface registers */ +#define ZYNQMP_DP_TX_AUX_COMMAND 0x100 +#define
[PATCH v5 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
Xilinx ZynqMP has a hardened display pipeline. The pipeline can be logically partitioned into 2 parts: display controller and DisplayPort encoder / transmitter. This driver handles the display controller part of the pipeline that handles buffer management and blending. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v4 - Use drm_crtc_funcs for vblank - Remove child nodes for layer v3 - Fix a small typo v2 - Use drm_fb_cma_get_gem_addr() - Use drm_crtc_arm_vblank_event() - Split drm properties into a separate patch - Remove dummy funcs - Don't add offset as it's already done by a new helper - Change the SPDX identifier format - Minor change of a commit message --- --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 2676 drivers/gpu/drm/xlnx/zynqmp_disp.h | 36 + 2 files changed, 2712 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c new file mode 100644 index 000..e47d77d --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -0,0 +1,2676 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP Display Controller Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xlnx_crtc.h" +#include "xlnx_fb.h" +#include "zynqmp_disp.h" +#include "zynqmp_dp.h" +#include "zynqmp_dpsub.h" + +/* + * Overview + * + * + * The display part of ZynqMP DP subsystem. Internally, the device + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio. + * The driver creates the DRM crtc and plane objectes and maps the DRM + * interface into those 3 blocks. In high level, the driver is layered + * in the following way: + * + * zynqmp_disp_crtc & zynqmp_disp_plane + * |->zynqmp_disp + * |->zynqmp_disp_aud + * |->zynqmp_disp_blend + * |->zynqmp_disp_av_buf + * + * The driver APIs are used externally by + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver + * - zynqmp_dp: ZynqMP DP driver + * - xlnx_crtc: Xilinx DRM specific crtc functions + */ + +/* Blender registers */ +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 +#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18 +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3
[PATCH v5 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 155
drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 28 +++
4 files changed, 197 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h
diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
index 19fd7cd..7c5529c 100644
--- a/drivers/gpu/drm/xlnx/Kconfig
+++ b/drivers/gpu/drm/xlnx/Kconfig
@@ -10,3 +10,14 @@ config DRM_XLNX
display pipeline using Xilinx IPs in FPGA. This module
provides the kernel mode setting functionalities
for Xilinx display drivers.
+
+config DRM_ZYNQMP_DPSUB
+ tristate "ZynqMP DP Subsystem Driver"
+ depends on ARCH_ZYNQMP && OF && DRM_XLNX && COMMON_CLK
+ select DMA_ENGINE
+ select GENERIC_PHY
+ help
+ DRM KMS driver for ZynqMP DP Subsystem controller. Choose
+ this option if you have a Xilinx ZynqMP SoC with DisplayPort
+ subsystem. The driver provides the kernel mode setting
+ functionlaities for ZynqMP DP subsystem.
diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile
index c60a281..064a05a 100644
--- a/drivers/gpu/drm/xlnx/Makefile
+++ b/drivers/gpu/drm/xlnx/Makefile
@@ -1,2 +1,5 @@
xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o
obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o
+
+zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
+obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
new file mode 100644
index 000..5aaf9fb
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DP Subsystem Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.k...@xilinx.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "xlnx_drv.h"
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+static int
+zynqmp_dpsub_bind(struct device *dev, struct device *master, void *data)
+{
+ int ret;
+
+ ret = zynqmp_disp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ /* zynqmp_disp should bind first, so zynqmp_dp encoder can find crtc */
+ ret = zynqmp_dp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+zynqmp_dpsub_unbind(struct device *dev, struct device *master, void *data)
+{
+ zynqmp_dp_unbind(dev, master, data);
+ zynqmp_disp_unbind(dev, master, data);
+}
+
+static const struct component_ops zynqmp_dpsub_component_ops = {
+ .bind = zynqmp_dpsub_bind,
+ .unbind = zynqmp_dpsub_unbind,
+};
+
+static int zynqmp_dpsub_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ int ret;
+
+ dpsub = devm_kzalloc(>dev, sizeof(*dpsub), GFP_KERNEL);
+ if (!dpsub)
+ return -ENOMEM;
+
+ /* Sub-driver will access dpsub from drvdata */
+ platform_set_drvdata(pdev, dpsub);
+ pm_runtime_enable(>dev);
+
+ /*
+* DP should be probed first so that the zynqmp_disp can set the output
+* format accordingly.
+*/
+ ret = zynqmp_dp_probe(pdev);
+ if (ret)
+ goto err_pm;
+
+ ret = zynqmp_disp_probe(pdev);
+ if (ret)
+ goto err_dp;
+
+ ret = component_add(>dev, _dpsub_component_ops);
+ if (ret)
+ goto err_disp;
+
+ /* Populate the sound child nodes */
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
+ if (ret) {
+ dev_err(>dev, "failed to populate child nodes\n");
+ goto err_component;
+ }
+
+ dev_info(>dev, "ZynqMP DisplayPort Subsystem driver probed");
+
+ dpsub->master = xlnx_drm_pipeline_init(pdev);
+
+ return 0;
+
+err_component:
+
[PATCH v5 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under 'ports'
- Replace linux specific terms with generic hardware descriptions
---
---
.../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
diff --git
a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
new file mode 100644
index 000..f4a2e6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
@@ -0,0 +1,67 @@
+Xilinx ZynqMP DisplayPort subsystem
+---
+
+Required properties:
+
+- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
+
+- reg: Physical base address and length of the registers set for the device.
+- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register
+ partitions.
+
+- interrupts: Interrupt number.
+- interrupts-parent: phandle for interrupt controller.
+
+- clocks: phandles for axi, audio, non-live video, and live video clocks.
+ axi clock is required. Audio clock is optional. If not present, audio will
+ be disabled. One of non-live or live video clock should be present.
+- clock-names: The identification strings are required. "aclk" for axi clock.
+ "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock.
+ "dp_live_video_in_clk" for live video clock (clock from programmable logic).
+
+- phys: phandles for phy specifier. The number of lanes is configurable
+ between 1 and 2. The number of phandles should be 1 or 2.
+- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
+ For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0"
+ and "dp-phy1" are required where "dp-phy0" is the primary lane.
+
+- power-domains: phandle for the corresponding power domain
+
+- dmas: phandles for DMA channels as defined in
+ Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names: The identifier strings are required. "gfx0" for graphics layer
+ dma channel. "vid" followed by index (0 - 2) for video layer dma channels.
+
+Optional child node
+
+- The driver populates any child device node in this node. This can be used,
+ for example, to populate the sound device from the DisplayPort subsystem
+ driver.
+
+Example:
+ zynqmp-display-subsystem@fd4a {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ reg = <0x0 0xfd4a 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_live_video_in_clk";
+ clocks = <_aclk>, < 17>, <_1>;
+
+ phys = <>, <>;
+ phy-names = "dp-phy0", "dp-phy1";
+
+ power-domains = <_dp>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <_dpdma 0>,
+ <_dpdma 1>,
+ <_dpdma 2>,
+ <_dpdma 3>;
+ };
+};
+
--
2.7.4
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[PATCH v5 1/5] drm: xlnx: Xilinx DRM KMS module
Xilinx has various platforms for display, where users can create using multiple IPs in the programmable FPGA fabric, or where some hardened piepline is available on the chip. Furthermore, hardened pipeline can also interact with soft logics in FPGA. The Xilinx DRM KMS module is to integrate multiple subdevices and to represent the entire pipeline as a single DRM device. The module includes helper (ex, framebuffer and gem helpers) and glue logic (ex, crtc interface) functions. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v5 - Redefine xlnx_pipeline_init() v4 - Fix a bug in of graph binding handling - Remove vblank callbacks from xlnx_crtc - Remove the dt binding. This module becomes more like a library. - Rephrase the commit message v3 - Add Laurent as a maintainer - Fix multiple-reference on gem objects v2 - Change the SPDX identifier format - Merge patches(crtc, gem, fb) into single one v2 of xlnx_drv - Rename kms to display in xlnx_drv - Replace some xlnx specific fb helper with common helpers in xlnx_drv - Don't set the commit tail callback in xlnx_drv - Support 'ports' graph binding in xlnx_drv v2 of xlnx_fb - Remove wrappers in xlnx_fb - Replace some functions with drm core helpers in xlnx_fb --- --- MAINTAINERS | 9 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/xlnx/Kconfig | 12 + drivers/gpu/drm/xlnx/Makefile| 2 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 177 ++ drivers/gpu/drm/xlnx/xlnx_crtc.h | 70 ++ drivers/gpu/drm/xlnx/xlnx_drv.c | 501 +++ drivers/gpu/drm/xlnx/xlnx_drv.h | 33 +++ drivers/gpu/drm/xlnx/xlnx_fb.c | 298 +++ drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++ drivers/gpu/drm/xlnx/xlnx_gem.c | 47 drivers/gpu/drm/xlnx/xlnx_gem.h | 26 ++ 13 files changed, 1211 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h diff --git a/MAINTAINERS b/MAINTAINERS index 5bc088f..07c0e73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4789,6 +4789,15 @@ F: drivers/gpu/drm/etnaviv/ F: include/uapi/drm/etnaviv_drm.h F: Documentation/devicetree/bindings/display/etnaviv/ +DRM DRIVERS FOR XILINX +M: Hyun Kwon <hyun.k...@xilinx.com> +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/xlnx/ +F: Documentation/devicetree/bindings/display/xlnx/ +T: git git://anongit.freedesktop.org/drm/drm-misc + DRM DRIVERS FOR ZTE ZX M: Shawn Guo <shawn...@kernel.org> L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index deeefa7..5a3ec66 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -289,6 +289,8 @@ source "drivers/gpu/drm/pl111/Kconfig" source "drivers/gpu/drm/tve200/Kconfig" +source "drivers/gpu/drm/xlnx/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 50093ff..f93557e 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -103,3 +103,4 @@ obj-$(CONFIG_DRM_MXSFB) += mxsfb/ obj-$(CONFIG_DRM_TINYDRM) += tinydrm/ obj-$(CONFIG_DRM_PL111) += pl111/ obj-$(CONFIG_DRM_TVE200) += tve200/ +obj-$(CONFIG_DRM_XLNX) += xlnx/ diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig new file mode 100644 index 000..19fd7cd --- /dev/null +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -0,0 +1,12 @@ +config DRM_XLNX + tristate "Xilinx DRM KMS Driver" + depends on DRM && OF + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + help + Xilinx DRM KMS driver. Choose this option if you have + a Xilinx SoCs with hardened display pipeline or soft + display pipeline using Xilinx IPs in FPGA. This module + provides the kernel mode setting functionalities + for Xilinx display drivers. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile new file mode 100644 index 000..c60a281 --- /dev/null +++ b/drivers/gpu/drm/xlnx/Makefile @@ -0,0 +1,2 @@ +xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o +obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o diff --git a/drivers/gpu/drm/xlnx/xlnx_crtc.c b/drivers/gpu/drm/xlnx/xlnx_crtc.c new fi
[RFC v2 07/10] drm: drm_fourcc: Add new 10bit formats to drm_format_info table
Add information for DRM_FORMAT_XV15 and DRM_FORMAT_XV20 to
the drm format table.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Accomodate macro pixel changes
---
---
drivers/gpu/drm/drm_fourcc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 2070276..2f6c9eb 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -168,6 +168,8 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_NV61,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0 },
.bpm = { 8, 16, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_NV24,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0 },
.bpm = { 8, 16, 0 }, .hsub = 1, .vsub = 1 },
{ .format = DRM_FORMAT_NV42,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 8, 16, 0 }, .ppm = { 1, 1, 0 },
.bpm = { 8, 16, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XV15,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 10, 20, 0 }, .ppm = { 3, 3, 0 },
.bpm = { 32, 64, 0 }, .hsub = 2, .vsub = 2, },
+ { .format = DRM_FORMAT_XV20,.depth = 0,
.num_planes = 2, .cpp = { 1, 2, 0 }, .bpp = { 10, 20, 0 }, .ppm = { 3, 3, 0 },
.bpm = { 32, 64, 0 }, .hsub = 2, .vsub = 1, },
{ .format = DRM_FORMAT_YUYV,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 16, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_YVYU,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 16, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 16, 0, 0 }, .hsub = 2, .vsub = 1 },
--
2.7.4
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[RFC v2 00/10] Support for formats with non-byte aligned components
Hi, This is RFC to follow up on adding new formats to DRM core. Previous discussion can be found in [1]. These new formats are not byte addressable, whereas in many places in DRM core, the assumption is that format bpp is byte aligned. Thus, in order to support these formats correctly, additiona handling is needed. Initial approach was to add the scaling factors to the format info. Those values were multiplied directly to address extra bits in color components and gaps between components. On the other hand, this series attempts to simplify such handling by adding the macro-pixel concept with some additional helper function, based on the previous discussion. Still not entirely sure if this is best / simpliest approach, so any feedback would be appreciated. This series includes some patches from downstream, but upstreaming on going, drivers [2] to demonstrate how it can be used. Patch 1 - 3 add additional information such as bpp, macro-pixel, and a helper. Patch 4 - 5 are to demonstrate how additional information can be used. Patch 6 - 7 add new formats to DRM core. New formats are added next to existing formats as it turned out those are not insance enough for a separate section Patch 8 adds new formats to the client driver as an example. Patch 9 - 10 add more fourccs which are used by downstream drivers currently in development. Thanks, -hyun [1] https://lists.freedesktop.org/archives/dri-devel/2017-November/158744.html [2] https://lists.freedesktop.org/archives/dri-devel/2018-January/162559.html Hyun Kwon (9): drm: drm:fourcc: Add bpp information to struct drm_format_info drm: drm_fourcc: Introduce macro-pixel info to drm_format_info drm: fourcc: Add drm_format_plane_width_bytes() drm: xlnx: zynqmp: use drm_format_width_bytes drm: fb_cma_helper: Use drm_format_plane_width_bytes() drm: drm_fourcc: Add new 10bit formats to drm_format_info table drm: xlnx: zynqmp: Add XV15 and XV20 formats uapi: drm: drm_fourcc: Add new formats for Xilinx IPs drm: drm_fourcc: Add new formats to the drm format table Jeffrey Mouroux (1): uapi: drm: New fourcc codes needed by Xilinx Video IP drivers/gpu/drm/drm_fb_cma_helper.c | 3 +- drivers/gpu/drm/drm_fourcc.c| 193 +++- drivers/gpu/drm/xlnx/zynqmp_disp.c | 22 +++- include/drm/drm_fourcc.h| 14 +++ include/uapi/drm/drm_fourcc.h | 15 +++ 5 files changed, 177 insertions(+), 70 deletions(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC v2 03/10] drm: fourcc: Add drm_format_plane_width_bytes()
drm_format_plane_width_bytes() calculates and returns
the number of bytes for given width of specified format.
The calculation uses the macro pixel information to avoid
bit level rounding.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- This function is added
---
---
drivers/gpu/drm/drm_fourcc.c | 22 ++
include/drm/drm_fourcc.h | 2 ++
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 8fc1e35..2070276 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -376,3 +376,25 @@ int drm_format_plane_height(int height, uint32_t format,
int plane)
return height / info->vsub;
}
EXPORT_SYMBOL(drm_format_plane_height);
+
+/**
+ * drm_format_plane_width_bytes - bytes of the given width of the plane
+ * @info: DRM format information
+ * @plane: plane index
+ * @width: width to get the number of bytes
+ *
+ * Returns:
+ * The bytes of @width of @plane.
+ */
+int drm_format_plane_width_bytes(const struct drm_format_info *info,
+int plane, int width)
+{
+ int width_bits;
+
+ if (!info || plane >= info->num_planes)
+ return 0;
+
+ width_bits = DIV_ROUND_UP(width * info->bpm[plane], info->ppm[plane]);
+ return DIV_ROUND_UP(width_bits, 8);
+}
+EXPORT_SYMBOL(drm_format_plane_width_bytes);
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 64038e9..1eafeb9 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -80,6 +80,8 @@ int drm_format_horz_chroma_subsampling(uint32_t format);
int drm_format_vert_chroma_subsampling(uint32_t format);
int drm_format_plane_width(int width, uint32_t format, int plane);
int drm_format_plane_height(int height, uint32_t format, int plane);
+int drm_format_plane_width_bytes(const struct drm_format_info *info,
+int plane, int width);
const char *drm_get_format_name(uint32_t format, struct drm_format_name_buf
*buf);
#endif /* __DRM_FOURCC_H__ */
--
2.7.4
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[RFC v2 01/10] drm: drm:fourcc: Add bpp information to struct drm_format_info
'cpp' doesn't work for any format where component size is not byte aligned.
Add 'bpp' to have a bit level information. Add a meesage to
drm_format_plane_cpp() to indicate that the returned cpp would be
rounded for non byte aligned formats.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Introduce bpp
---
---
drivers/gpu/drm/drm_fourcc.c | 164 +--
include/drm/drm_fourcc.h | 3 +
2 files changed, 99 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 9c0152d..b891fe0 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -105,74 +105,74 @@ EXPORT_SYMBOL(drm_get_format_name);
const struct drm_format_info *__drm_format_info(u32 format)
{
static const struct drm_format_info formats[] = {
- { .format = DRM_FORMAT_C8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGB332, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGR233, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XRGB,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XBGR,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGBX,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGRX,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_ARGB,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_ABGR,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGBA,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGRA,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XRGB1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XBGR1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGBX5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGRX5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_ARGB1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_ABGR1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGBA5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGRA5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGB565, .depth = 16,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGR565, .depth = 16,
.num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGB888, .depth = 24,
.num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGR888, .depth = 24,
.num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XRGB,.depth = 24,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XBGR,.depth = 24,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGBX,.depth = 24,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGRX,.depth = 24,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGB565_A8, .depth = 24,
.num_planes = 2, .cpp = { 2, 1, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_BGR565_A8, .depth = 24,
.num_planes = 2, .cpp = { 2, 1, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XRGB2101010, .depth = 30,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_XBGR2101010, .depth = 30,
.num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
- { .format = DRM_FORMAT_RGBX1010102, .depth = 30,
.num_planes = 1
[RFC v2 04/10] drm: xlnx: zynqmp: use drm_format_width_bytes
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index d2e1034..fd6ddfe 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -2138,6 +2138,7 @@ static int zynqmp_disp_plane_mode_set(struct drm_plane
*plane,
for (i = 0; i < info->num_planes; i++) {
unsigned int width = src_w / (i ? info->hsub : 1);
unsigned int height = src_h / (i ? info->vsub : 1);
+ int width_bytes;
paddr = drm_fb_cma_get_gem_addr(fb, plane->state, i);
if (!paddr) {
@@ -2146,7 +2147,8 @@ static int zynqmp_disp_plane_mode_set(struct drm_plane
*plane,
}
layer->dma[i].xt.numf = height;
- layer->dma[i].sgl[0].size = width * info->cpp[i];
+ width_bytes = drm_format_plane_width_bytes(info, i, width);
+ layer->dma[i].sgl[0].size = width_bytes;
layer->dma[i].sgl[0].icg = fb->pitches[i] -
layer->dma[i].sgl[0].size;
layer->dma[i].xt.src_start = paddr;
--
2.7.4
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[RFC v2 10/10] drm: drm_fourcc: Add new formats to the drm format table
This adds new formats (packed YUV and grey scale) to
the drm format table.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Split from previous patch
---
---
drivers/gpu/drm/drm_fourcc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 2f6c9eb..420d043 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -175,6 +175,11 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 16, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 16, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .bpp = { 32, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 32, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_VUY888, .depth = 0,
.num_planes = 1, .cpp = { 3, 0, 0 }, .bpp = { 24, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 24, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XVUY,.depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .bpp = { 32, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 32, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_XVUY2101010, .depth = 0,
.num_planes = 1, .cpp = { 4, 0, 0 }, .bpp = { 32, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 32, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_Y8, .depth = 0,
.num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .ppm = { 1, 0, 0 },
.bpm = { 8, 0, 0 }, .hsub = 1, .vsub = 1 },
+ { .format = DRM_FORMAT_Y10, .depth = 0,
.num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 10, 0, 0 }, .ppm = { 3, 0, 0 },
.bpm = { 32, 0, 0 }, .hsub = 1, .vsub = 1 },
};
unsigned int i;
--
2.7.4
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[RFC v2 02/10] drm: drm_fourcc: Introduce macro-pixel info to drm_format_info
Multiple pixels can be grouped as a single unit and form a 'macro-pixel'.
This is to model formats where multiple pixels are stored together
in a specific way, likely byte-algined. For example, if 3 - 10 bit
pixels are stored in 32 bit, the 32 bit stroage can be treated as
a single macro-pixel with 3 pixels. This aligns non-byte addressable
formats with drm core where bpp is expected to be multiple of 8 bit.
Add 'ppm', pixels per macro-pixel, to note how many pixels are grouped
in a macro-pixel. 'bpm', bits per macro-pixel, specifies how many bits
are in a macro-pixel as there can be some extra padding bits.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Introduce macro-pixel over scaling factors
---
---
drivers/gpu/drm/drm_fourcc.c | 136 +--
include/drm/drm_fourcc.h | 9 +++
2 files changed, 77 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index b891fe0..8fc1e35 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -105,74 +105,74 @@ EXPORT_SYMBOL(drm_get_format_name);
const struct drm_format_info *__drm_format_info(u32 format)
{
static const struct drm_format_info formats[] = {
- { .format = DRM_FORMAT_C8, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGB332, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGR233, .depth = 8,
.num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_XRGB,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_XBGR,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGBX,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGRX,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_ARGB,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_ABGR,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGBA,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGRA,.depth = 0,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_XRGB1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_XBGR1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGBX5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGRX5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_ARGB1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_ABGR1555,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGBA5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGRA5551,.depth = 15,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGB565, .depth = 16,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGR565, .depth = 16,
.num_planes = 1, .cpp = { 2, 0, 0 }, .bpp = { 16, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_RGB888, .depth = 24,
.num_planes = 1, .cpp = { 3, 0, 0 }, .bpp = { 24, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_BGR888, .depth = 24,
.num_planes = 1, .cpp = { 3, 0, 0 }, .bpp = { 24, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_XRGB,.depth = 24,
.num_planes = 1, .cpp = { 1, 0, 0 }, .bpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1
},
- { .format = DRM_FORMAT_XBGR,.dept
[RFC v2 06/10] uapi: drm: New fourcc codes needed by Xilinx Video IP
From: Jeffrey Mouroux <jmour...@xilinx.com>
The Xilinx Video Mixer andn Xilinx Video Framebuffer DMA IP
support video memory formats that are not represented in the
current DRM fourcc library. This patch adds those missing
fourcc codes.
Signed-off-by: Jeffrey Mouroux <jmour...@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Add detailed descriptions
- Remove formats with no user
---
---
include/uapi/drm/drm_fourcc.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index e04613d..6ac5282 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,14 @@ extern "C" {
#define DRM_FORMAT_NV42fourcc_code('N', 'V', '4', '2') /*
non-subsampled Cb:Cr plane */
/*
+ * 2 plane 10 bit per component YCbCr
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cb:Cr plane, [63:0] x:Cb2:Cr2:Cb1:x:Cr1:Cb0:Cr0
2:10:10:10:2:10:10:10 little endian
+ */
+#define DRM_FORMAT_XV15fourcc_code('X', 'V', '1', '5') /* 2x2
subsampled Cb:Cr plane 2:10:10:10 */
+#define DRM_FORMAT_XV20fourcc_code('X', 'V', '2', '0') /* 2x1
subsampled Cb:Cr plane 2:10:10:10 */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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[RFC v2 09/10] uapi: drm: drm_fourcc: Add new formats for Xilinx IPs
This adds packed YUV and grey scale format fourccs.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Split from the previous patch
---
---
include/uapi/drm/drm_fourcc.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 6ac5282..7014a3d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -112,6 +112,13 @@ extern "C" {
#define DRM_FORMAT_VYUYfourcc_code('V', 'Y', 'U', 'Y') /*
[31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUVfourcc_code('A', 'Y', 'U', 'V') /*
[31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0]
Cr:Cb:Y 8:8:8 little endian */
+#define DRM_FORMAT_XVUYfourcc_code('X', 'V', '2', '4') /* [31:0]
x:Cr:Cb:Y 8:8:8:8 little endian */
+#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'Y', '3', '0') /* [31:0]
x:Cr:Cb:Y 2:10:10:10 little endian */
+
+/* Grey scale */
+#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8 Greyscale
*/
+#define DRM_FORMAT_Y10 fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale
*/
/*
* 2 plane RGB + A
--
2.7.4
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[RFC v2 08/10] drm: xlnx: zynqmp: Add XV15 and XV20 formats
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c
b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index fd6ddfe..b1aaa71 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -968,6 +968,24 @@ static const struct zynqmp_disp_fmt av_buf_vid_fmts[] = {
.sf[0] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
.sf[1] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
.sf[2] = ZYNQMP_DISP_AV_BUF_8BIT_SF,
+ }, {
+ .drm_fmt= DRM_FORMAT_XV15,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10,
+ .rgb= false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ }, {
+ .drm_fmt= DRM_FORMAT_XV20,
+ .disp_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
+ .rgb= false,
+ .swap = false,
+ .chroma_sub = true,
+ .sf[0] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[1] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
+ .sf[2] = ZYNQMP_DISP_AV_BUF_10BIT_SF,
}
};
--
2.7.4
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[RFC v2 05/10] drm: fb_cma_helper: Use drm_format_plane_width_bytes()
In order to handle non byte aligned formats, use drm_format_plane_width_bytes(). Use of 'cpp' can result in incorrect number of bytes from bit level rounding. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> --- v2 - This patch is added. --- --- drivers/gpu/drm/drm_fb_cma_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c index 186d00a..271175e 100644 --- a/drivers/gpu/drm/drm_fb_cma_helper.c +++ b/drivers/gpu/drm/drm_fb_cma_helper.c @@ -124,7 +124,8 @@ dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb, return 0; paddr = obj->paddr + fb->offsets[plane]; - paddr += fb->format->cpp[plane] * (state->src_x >> 16); + paddr += drm_format_plane_width_bytes(fb->format, plane, + state->src_x >> 16); paddr += fb->pitches[plane] * (state->src_y >> 16); return paddr; -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [PATCH v3 2/8] drm: xlnx: Xilinx DRM KMS driver
Hi Daniel, > -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Wednesday, January 17, 2018 12:20 AM > To: Hyun Kwon <hy...@xilinx.com> > Cc: dri-devel@lists.freedesktop.org; devicet...@vger.kernel.org; Michal > Simek <michal.si...@xilinx.com>; Rob Herring <r...@kernel.org>; Daniel > Vetter <daniel.vet...@ffwll.ch>; Laurent Pinchart > <laurent.pinch...@ideasonboard.com> > Subject: Re: [PATCH v3 2/8] drm: xlnx: Xilinx DRM KMS driver > > On Mon, Jan 15, 2018 at 05:57:05PM -0800, Hyun Kwon wrote: > > Xilinx has various platforms for display, where users can create > > using multiple IPs in the programmable FPGA fabric, or where > > some hardened piepline is available on the chip. Furthermore, > > hardened pipeline can also interact with soft logics in FPGA. > > > > The Xilinx DRM KMS is to integrate multiple subdevices and to represent > > the entire pipeline as a single DRM device. The driver includes helpers > > (ex, framebuffer and gem helpers) and glue logics (ex, crtc interface). > > > > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> > > --- > > v3 > > - Add Laurent as a maintainer > > - Fix multiple-reference on gem objects > > v2 > > - Change the SPDX identifier format > > - Merge patches(crtc, gem, fb) into single one > > v2 of xlnx_drv > > - Rename kms to display in xlnx_drv > > - Replace some xlnx specific fb helper with common helpers in xlnx_drv > > - Don't set the commit tail callback in xlnx_drv > > - Support 'ports' graph binding in xlnx_drv > > v2 of xlnx_fb > > - Remove wrappers in xlnx_fb > > - Replace some functions with drm core helpers in xlnx_fb > > --- > > --- > > MAINTAINERS | 9 + > > drivers/gpu/drm/Kconfig | 2 + > > drivers/gpu/drm/Makefile | 1 + > > drivers/gpu/drm/xlnx/Kconfig | 12 ++ > > drivers/gpu/drm/xlnx/Makefile| 2 + > > drivers/gpu/drm/xlnx/xlnx_crtc.c | 203 ++ > > drivers/gpu/drm/xlnx/xlnx_crtc.h | 78 +++ > > drivers/gpu/drm/xlnx/xlnx_drv.c | 447 > +++ > > drivers/gpu/drm/xlnx/xlnx_drv.h | 30 +++ > > drivers/gpu/drm/xlnx/xlnx_fb.c | 298 ++ > > drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++ > > drivers/gpu/drm/xlnx/xlnx_gem.c | 47 > > drivers/gpu/drm/xlnx/xlnx_gem.h | 26 +++ > > 13 files changed, 1188 insertions(+) > > create mode 100644 drivers/gpu/drm/xlnx/Kconfig > > create mode 100644 drivers/gpu/drm/xlnx/Makefile > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c > > create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 2811a21..dc84346 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -4682,6 +4682,15 @@ F: drivers/gpu/drm/etnaviv/ > > F: include/uapi/drm/etnaviv_drm.h > > F: Documentation/devicetree/bindings/display/etnaviv/ > > > > +DRM DRIVERS FOR XILINX > > +M: Hyun Kwon <hyun.k...@xilinx.com> > > +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> > > +L: dri-devel@lists.freedesktop.org > > +S: Maintained > > +F: drivers/gpu/drm/xlnx/ > > +F: Documentation/devicetree/bindings/display/xlnx/ > > +T: git git://anongit.freedesktop.org/drm/drm-misc > > Ok, I scrolled through the patches again and besides the one nit for the > enable/disable_vblank callback it looks all good. On patches 2 and 4-6: > > Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> > > These are ready for merging. The 2 dt patches need an ack from Rob > Herring. The final 2 patches with the new properties need the usual uapi > work and userspace enabling per > > https://dri.freedesktop.org/docs/drm/gpu/drm-uapi.html#open-source- > userspace-requirements > > Since Laurent is listed as co-maintainer, and Laurent is already drm-misc > committer I think it's indeed best to maintain it in there. Please request > a new account per > > https://www.freedesktop.org/wiki/AccountRequests/ > > and check out quickstart in > > https://01.org/linuxgraphics/gfx-docs
[PATCH v4 4/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
This driver creates DRM encoder and connector for ZynqMP DisplayPort. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v2 - Change the SPDX identifier format - Split drm properties into a separate patch --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738 ++ drivers/gpu/drm/xlnx/zynqmp_dp.h | 37 + 2 files changed, 1775 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c new file mode 100644 index 000..9c9f4df --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -0,0 +1,1738 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP DisplayPort Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "zynqmp_disp.h" +#include "zynqmp_dpsub.h" + +static uint zynqmp_dp_aux_timeout_ms = 50; +module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); + +/* + * Some sink requires a delay after power on request + */ +static uint zynqmp_dp_power_on_delay_ms = 4; +module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); + +/* Link configuration registers */ +#define ZYNQMP_DP_TX_LINK_BW_SET 0x0 +#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4 +#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8 +#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc +#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE0x14 +#define ZYNQMP_DP_TX_DOWNSPREAD_CTL0x18 +#define ZYNQMP_DP_TX_SW_RESET 0x1c +#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0) +#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1) +#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2) +#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3) +#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7) +#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM2 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM3 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM4 | \ + ZYNQMP_DP_TX_SW_RESET_AUX) + +/* Core enable registers */ +#define ZYNQMP_DP_TX_ENABLE0x80 +#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM0x84 +#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0 +#define ZYNQMP_DP_TX_VERSION 0xf8 +#define ZYNQMP_DP_TX_VERSION_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_VERSION_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12) +#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT12 +#define ZYNQMP_DP_TX_VERSION_PATCH_MASKGENMASK(11, 8) +#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8 +#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0) +#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT0 + +/* Core ID registers */ +#define ZYNQMP_DP_TX_CORE_ID 0xfc +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8) +#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT8 +#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1) + +/* AUX channel interface registers */ +#define ZYNQMP_DP_TX_AUX_COMMAND 0x100 +#define
[PATCH v4 5/5] drm: xlnx: ZynqMP DP subsystem DRM KMS driver
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
---
v4
- Use the newly added xlnx pipeline calls to initialize drm device
v2
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 155
drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 28 +++
4 files changed, 197 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h
diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
index 19fd7cd..7c5529c 100644
--- a/drivers/gpu/drm/xlnx/Kconfig
+++ b/drivers/gpu/drm/xlnx/Kconfig
@@ -10,3 +10,14 @@ config DRM_XLNX
display pipeline using Xilinx IPs in FPGA. This module
provides the kernel mode setting functionalities
for Xilinx display drivers.
+
+config DRM_ZYNQMP_DPSUB
+ tristate "ZynqMP DP Subsystem Driver"
+ depends on ARCH_ZYNQMP && OF && DRM_XLNX && COMMON_CLK
+ select DMA_ENGINE
+ select GENERIC_PHY
+ help
+ DRM KMS driver for ZynqMP DP Subsystem controller. Choose
+ this option if you have a Xilinx ZynqMP SoC with DisplayPort
+ subsystem. The driver provides the kernel mode setting
+ functionlaities for ZynqMP DP subsystem.
diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile
index c60a281..064a05a 100644
--- a/drivers/gpu/drm/xlnx/Makefile
+++ b/drivers/gpu/drm/xlnx/Makefile
@@ -1,2 +1,5 @@
xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o
obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o
+
+zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
+obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
new file mode 100644
index 000..5aaf9fb
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DP Subsystem Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.k...@xilinx.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "xlnx_drv.h"
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+static int
+zynqmp_dpsub_bind(struct device *dev, struct device *master, void *data)
+{
+ int ret;
+
+ ret = zynqmp_disp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ /* zynqmp_disp should bind first, so zynqmp_dp encoder can find crtc */
+ ret = zynqmp_dp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+zynqmp_dpsub_unbind(struct device *dev, struct device *master, void *data)
+{
+ zynqmp_dp_unbind(dev, master, data);
+ zynqmp_disp_unbind(dev, master, data);
+}
+
+static const struct component_ops zynqmp_dpsub_component_ops = {
+ .bind = zynqmp_dpsub_bind,
+ .unbind = zynqmp_dpsub_unbind,
+};
+
+static int zynqmp_dpsub_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ int ret;
+
+ dpsub = devm_kzalloc(>dev, sizeof(*dpsub), GFP_KERNEL);
+ if (!dpsub)
+ return -ENOMEM;
+
+ /* Sub-driver will access dpsub from drvdata */
+ platform_set_drvdata(pdev, dpsub);
+ pm_runtime_enable(>dev);
+
+ /*
+* DP should be probed first so that the zynqmp_disp can set the output
+* format accordingly.
+*/
+ ret = zynqmp_dp_probe(pdev);
+ if (ret)
+ goto err_pm;
+
+ ret = zynqmp_disp_probe(pdev);
+ if (ret)
+ goto err_dp;
+
+ ret = component_add(>dev, _dpsub_component_ops);
+ if (ret)
+ goto err_disp;
+
+ /* Populate the sound child nodes */
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
+ if (ret) {
+ dev_err(>dev, "failed to populate child nodes\n");
+ goto err_component;
+ }
+
+ dev_info(>dev, "ZynqMP DisplayPort Subsystem driver probed");
+
+ dpsub->master = xlnx_drm_pipeline_init(pdev);
+
+ return 0;
+
+err_component:
+
[PATCH v4 2/5] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
This add a dt binding for ZynqMP DP subsystem.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v4
- Specify phy related descriptions
- Specify dma related descriptions
- Remove ports
- Remove child nodes for layers
- Update the example accordingly
v2
- Group multiple ports under 'ports'
- Replace linux specific terms with generic hardware descriptions
---
---
.../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 67 ++
1 file changed, 67 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
diff --git
a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
new file mode 100644
index 000..f4a2e6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
@@ -0,0 +1,67 @@
+Xilinx ZynqMP DisplayPort subsystem
+---
+
+Required properties:
+
+- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
+
+- reg: Physical base address and length of the registers set for the device.
+- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register
+ partitions.
+
+- interrupts: Interrupt number.
+- interrupts-parent: phandle for interrupt controller.
+
+- clocks: phandles for axi, audio, non-live video, and live video clocks.
+ axi clock is required. Audio clock is optional. If not present, audio will
+ be disabled. One of non-live or live video clock should be present.
+- clock-names: The identification strings are required. "aclk" for axi clock.
+ "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock.
+ "dp_live_video_in_clk" for live video clock (clock from programmable logic).
+
+- phys: phandles for phy specifier. The number of lanes is configurable
+ between 1 and 2. The number of phandles should be 1 or 2.
+- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1.
+ For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0"
+ and "dp-phy1" are required where "dp-phy0" is the primary lane.
+
+- power-domains: phandle for the corresponding power domain
+
+- dmas: phandles for DMA channels as defined in
+ Documentation/devicetree/bindings/dma/dma.txt.
+- dma-names: The identifier strings are required. "gfx0" for graphics layer
+ dma channel. "vid" followed by index (0 - 2) for video layer dma channels.
+
+Optional child node
+
+- The driver populates any child device node in this node. This can be used,
+ for example, to populate the sound device from the DisplayPort subsystem
+ driver.
+
+Example:
+ zynqmp-display-subsystem@fd4a {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ reg = <0x0 0xfd4a 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_live_video_in_clk";
+ clocks = <_aclk>, < 17>, <_1>;
+
+ phys = <>, <>;
+ phy-names = "dp-phy0", "dp-phy1";
+
+ power-domains = <_dp>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <_dpdma 0>,
+ <_dpdma 1>,
+ <_dpdma 2>,
+ <_dpdma 3>;
+ };
+};
+
--
2.7.4
___
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[PATCH v4 3/5] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
Xilinx ZynqMP has a hardened display pipeline. The pipeline can be logically partitioned into 2 parts: display controller and DisplayPort encoder / transmitter. This driver handles the display controller part of the pipeline that handles buffer management and blending. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v4 - Use drm_crtc_funcs for vblank - Remove child nodes for layer v3 - Fix a small typo v2 - Use drm_fb_cma_get_gem_addr() - Use drm_crtc_arm_vblank_event() - Split drm properties into a separate patch - Remove dummy funcs - Don't add offset as it's already done by a new helper - Change the SPDX identifier format - Minor change of a commit message --- --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 2676 drivers/gpu/drm/xlnx/zynqmp_disp.h | 36 + 2 files changed, 2712 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c new file mode 100644 index 000..e47d77d --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -0,0 +1,2676 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP Display Controller Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xlnx_crtc.h" +#include "xlnx_fb.h" +#include "zynqmp_disp.h" +#include "zynqmp_dp.h" +#include "zynqmp_dpsub.h" + +/* + * Overview + * + * + * The display part of ZynqMP DP subsystem. Internally, the device + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio. + * The driver creates the DRM crtc and plane objectes and maps the DRM + * interface into those 3 blocks. In high level, the driver is layered + * in the following way: + * + * zynqmp_disp_crtc & zynqmp_disp_plane + * |->zynqmp_disp + * |->zynqmp_disp_aud + * |->zynqmp_disp_blend + * |->zynqmp_disp_av_buf + * + * The driver APIs are used externally by + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver + * - zynqmp_dp: ZynqMP DP driver + * - xlnx_crtc: Xilinx DRM specific crtc functions + */ + +/* Blender registers */ +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 +#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18 +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3
[PATCH v4 1/5] drm: xlnx: Xilinx DRM KMS module
Xilinx has various platforms for display, where users can create using multiple IPs in the programmable FPGA fabric, or where some hardened piepline is available on the chip. Furthermore, hardened pipeline can also interact with soft logics in FPGA. The Xilinx DRM KMS module is to integrate multiple subdevices and to represent the entire pipeline as a single DRM device. The module includes helper (ex, framebuffer and gem helpers) and glue logic (ex, crtc interface) functions. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- v4 - Fix a bug in of graph binding handling - Remove vblank callbacks from xlnx_crtc - Remove the dt binding. This module becomes more like a library. - Rephrase the commit message v3 - Add Laurent as a maintainer - Fix multiple-reference on gem objects v2 - Change the SPDX identifier format - Merge patches(crtc, gem, fb) into single one v2 of xlnx_drv - Rename kms to display in xlnx_drv - Replace some xlnx specific fb helper with common helpers in xlnx_drv - Don't set the commit tail callback in xlnx_drv - Support 'ports' graph binding in xlnx_drv v2 of xlnx_fb - Remove wrappers in xlnx_fb - Replace some functions with drm core helpers in xlnx_fb --- --- MAINTAINERS | 9 + drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/xlnx/Kconfig | 12 + drivers/gpu/drm/xlnx/Makefile| 2 + drivers/gpu/drm/xlnx/xlnx_crtc.c | 177 + drivers/gpu/drm/xlnx/xlnx_crtc.h | 70 + drivers/gpu/drm/xlnx/xlnx_drv.c | 546 +++ drivers/gpu/drm/xlnx/xlnx_drv.h | 33 +++ drivers/gpu/drm/xlnx/xlnx_fb.c | 298 + drivers/gpu/drm/xlnx/xlnx_fb.h | 33 +++ drivers/gpu/drm/xlnx/xlnx_gem.c | 47 drivers/gpu/drm/xlnx/xlnx_gem.h | 26 ++ 13 files changed, 1256 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/Kconfig create mode 100644 drivers/gpu/drm/xlnx/Makefile create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_crtc.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_drv.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_fb.h create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.c create mode 100644 drivers/gpu/drm/xlnx/xlnx_gem.h diff --git a/MAINTAINERS b/MAINTAINERS index 5bc088f..07c0e73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4789,6 +4789,15 @@ F: drivers/gpu/drm/etnaviv/ F: include/uapi/drm/etnaviv_drm.h F: Documentation/devicetree/bindings/display/etnaviv/ +DRM DRIVERS FOR XILINX +M: Hyun Kwon <hyun.k...@xilinx.com> +M: Laurent Pinchart <laurent.pinch...@ideasonboard.com> +L: dri-devel@lists.freedesktop.org +S: Maintained +F: drivers/gpu/drm/xlnx/ +F: Documentation/devicetree/bindings/display/xlnx/ +T: git git://anongit.freedesktop.org/drm/drm-misc + DRM DRIVERS FOR ZTE ZX M: Shawn Guo <shawn...@kernel.org> L: dri-devel@lists.freedesktop.org diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index deeefa7..5a3ec66 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -289,6 +289,8 @@ source "drivers/gpu/drm/pl111/Kconfig" source "drivers/gpu/drm/tve200/Kconfig" +source "drivers/gpu/drm/xlnx/Kconfig" + # Keep legacy drivers last menuconfig DRM_LEGACY diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 50093ff..f93557e 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -103,3 +103,4 @@ obj-$(CONFIG_DRM_MXSFB) += mxsfb/ obj-$(CONFIG_DRM_TINYDRM) += tinydrm/ obj-$(CONFIG_DRM_PL111) += pl111/ obj-$(CONFIG_DRM_TVE200) += tve200/ +obj-$(CONFIG_DRM_XLNX) += xlnx/ diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig new file mode 100644 index 000..19fd7cd --- /dev/null +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -0,0 +1,12 @@ +config DRM_XLNX + tristate "Xilinx DRM KMS Driver" + depends on DRM && OF + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + help + Xilinx DRM KMS driver. Choose this option if you have + a Xilinx SoCs with hardened display pipeline or soft + display pipeline using Xilinx IPs in FPGA. This module + provides the kernel mode setting functionalities + for Xilinx display drivers. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile new file mode 100644 index 000..c60a281 --- /dev/null +++ b/drivers/gpu/drm/xlnx/Makefile @@ -0,0 +1,2 @@ +xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o +obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o diff --git a/drivers/gpu/drm/xlnx/xlnx_crtc.c b/drivers/gpu/drm/xlnx/xlnx_crtc.c new file mode 100644 index 000..de83905 -
RE: [PATCH v3 3/8] dt-bindings: display: xlnx: Add ZynqMP DP subsystem bindings
Hi Rob,
Thanks for the review.
> -Original Message-
> From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> Of Rob Herring
> Sent: Friday, January 19, 2018 4:31 PM
> To: Hyun Kwon <hy...@xilinx.com>
> Cc: devicet...@vger.kernel.org; Laurent Pinchart
> <laurent.pinch...@ideasonboard.com>; Michal Simek
> <michal.si...@xilinx.com>; dri-devel@lists.freedesktop.org; Daniel Vetter
> <daniel.vet...@ffwll.ch>
> Subject: Re: [PATCH v3 3/8] dt-bindings: display: xlnx: Add ZynqMP DP
> subsystem bindings
>
> On Mon, Jan 15, 2018 at 05:57:06PM -0800, Hyun Kwon wrote:
> > This add a dt binding for ZynqMP DP subsystem.
> >
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > ---
> > v2
> > - Group multiple ports under 'ports'
> > - Replace linux specific terms with generic hardware descriptions
> > ---
> > ---
> > .../bindings/display/xlnx/xlnx,zynqmp-dpsub.txt| 98
> ++
> > 1 file changed, 98 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt
> >
> > diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-
> dpsub.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-
> dpsub.txt
> > new file mode 100644
> > index 000..dbcbde5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-
> dpsub.txt
> > @@ -0,0 +1,98 @@
> > +Xilinx ZynqMP DisplayPort subsystem
> > +---
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "xlnx,zynqmp-dpsub-1.7".
> > +
> > +- reg: Physical base address and length of the registers set for the
> > device.
> > +- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical
> register
> > + partitions.
> > +
> > +- interrupts: Interrupt number.
> > +- interrupts-parent: phandle for interrupt controller.
> > +
> > +- clocks: phandles for axi, audio, non-live video, and live video clocks.
> > + axi clock is required. Audio clock is optional. If not present, audio
> > will
> > + be disabled. One of non-live or live video clock should be present.
> > +- clock-names: The identification strings are required. "aclk" for axi
> > clock.
> > + "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video
> clock.
> > + "dp_live_video_in_clk" for live video clock (clock from programmable
> logic).
> > +
> > +- phys: phandles for phy specifier.
>
> phandles? How many?
>
Configurable between 1 or 2 lanes. Will add more details.
> > +- phy-names: The identifier strings. "dp-phy" followed by index.
> > +
> > +- power-domains: phandle for the corresponding power domain
> > +
> > +- ports: There are 2 logical blocks in the IP: display controller and
> > + DisplayPort encoder. Each block can be used / connected independently
> with
>
> I'm confused. The block described in this doc is just DisplayPort
> encoder or both display controller and DisplayPort? Or something else?
>
The DP subsystem includes both block, protocol indipendent controller in front
and the DisplayPort transmitter in the back. I'll try to elaborate / clarify
better.
> > + external device, hence ports for each block are required using DT
> bindings
> > + defined in Documentation/devicetree/bindings/graph.txt. Refer to
> > + ./xlnx,display.txt for how topology for entire pipeline is described.
> > +
> > +- vid-layer, gfx-layer: Required to represent available layers
> > +
> > +Required layer properties
> > +
> > +- dmas: phandles for DMA channels as defined in
> > + Documentation/devicetree/bindings/dma/dma.txt.
> > +- dma-names: The identifier strings are required. "graphics0" for graphics
> > + layer. "video" followed by index for video layer
> > +
> > +Optional child node
> > +
> > +- The driver populates any child device node in this node. This can be
> used,
> > + for example, to populate the sound device from the DisplayPort
> subsystem
> > + driver.
> > +
> > +Example:
> > + zynqmp_dpsub: zynqmp_dpsub@fd4a {
>
> video-codec@... if this the DP encoder.
>
> > + compatible = "xlnx,zynqmp-dpsub-1.7";
> > + reg = <0x0 0xfd4a 0x0 0x1000>,
> > + <0x0 0xfd4aa000 0x0 0x1000>,
> > + <0x0
RE: [PATCH v3 1/8] dt-bindings: display: xlnx: Add bindings for Xilinx display pipeline
Hi Rob,
Thanks for the review.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Friday, January 19, 2018 3:33 PM
> To: Hyun Kwon <hy...@xilinx.com>
> Cc: dri-devel@lists.freedesktop.org; devicet...@vger.kernel.org; Michal
> Simek <michal.si...@xilinx.com>; Daniel Vetter <daniel.vet...@ffwll.ch>;
> Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> Subject: Re: [PATCH v3 1/8] dt-bindings: display: xlnx: Add bindings for
> Xilinx display pipeline
>
> On Mon, Jan 15, 2018 at 05:57:04PM -0800, Hyun Kwon wrote:
> > The dt binding for Xilinx display pipeline. The pipeline can be
> > composed with multiple and different types of sub-devices. This node
> > is to represent the entire pipeline as a single entity.
> >
> > Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
> > ---
> > v2
> > - Remove linux specific terms
> > - Elaborate details, ex regarding port binding
> > - Rename xlnx,kms to xlnx,display
> > - Rename the file name to xlnx,display.txt
> > - Add examples of hardware blocks
> > ---
> > ---
> > .../bindings/display/xlnx/xlnx,display.txt | 68
> ++
> > 1 file changed, 68 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/display/xlnx/xlnx,display.txt
> >
> > diff --git
> a/Documentation/devicetree/bindings/display/xlnx/xlnx,display.txt
> b/Documentation/devicetree/bindings/display/xlnx/xlnx,display.txt
> > new file mode 100644
> > index 000..fde1a35
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,display.txt
> > @@ -0,0 +1,68 @@
> > +Xilinx Display Pipeline
> > +---
> > +
> > +Xilinx display pipeline can be designed with various types of multiple IPs:
> > +IPs hardened on chip, ob board IPs, and soft IPs in programmable logic.
>
> s/ob board/on-board/
>
Will fix it.
> > +While each component would need its own node, this node represents
> > +a whole display pipeline as a single entity by integrating individual
> subdevice
> > +with glue logics.
> > +
> > +The following illustrates some examples of topology:
> > +
> > +A linear pipeline with multiple blocks:
> > +
> > + SoC DMA -> SoC display controller -> SoC display enc
> > +or,
> > + FPGA DMA -> FPGA display controller -> FPGA display enc
> > +
> > +A pipeline with branches:
> > +
> > + SoC DMA -> SoC display controller -> SoC display enc
> > + |
> > + FPGA DMA->
> > +or,
> > + SoC DMA -> SoC display controller -> SoC display enc
> > + |
> > + -> FPAG display enc
>
> s/FPAG/FPGA/
>
Will fix.
> > +
> > +or,
> > +
> > + SoC DMA -> SoC display controller -> SoC display enc
> > + | |
> > + FPGA display controller ->-> FPGA display
> > enc
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "xlnx,display".
> > +
> > +- ports: phandles for ports of display controller subdevice.
> > + In the display controller port nodes, topology for entire pipeline
> > + should be described using the DT bindings defined in
> > + Documentation/devicetree/bindings/graph.txt.
> > +
> > +Example:
> > +
> > + xlnx_display {
> > + compatible = "xlnx,display";
> > + ports = <_controller_port>;
>
> I still don't think you need this node. Match the DRM driver with the
> display controller node.
>
With that approach, it becomes tricky as multiple devices can form a single
DRM device (single pipeline). For example, the SoC display controller would
match the DRM driver when it's used alone. There can be a standalone FPGA
display controller which will match the DRM driver. But there can also be
a design where both controllers are connected together and share some block,
ex DisplayPort transmitter. There it's not clear which one to match
the DRM driver. Thus this logical node helps to represent fragmented devices
as a single device display pipeline. If this is not acceptable, I'll try to
find other options.
> > + };
> > +
> > + display_controller {
>
> display-controller@???
>
> Please show at least the compatible and reg in the example.
>
Sure will do.
> > + ...
> > + display_controller_port: port@0 {
>
> Unit address is not needed here. If you have a unit address, then you
> should have a reg property (and #size-cells and #address-cells in the
> parent).
>
Will fix.
Thanks,
-hyun
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[PATCH v3 6/8] drm: xlnx: ZynqMP DP subsystem DRM KMS driver
This is a wrapper around the ZynqMP Display and DisplayPort drivers.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
- Change the SPDX identifier format
---
---
drivers/gpu/drm/xlnx/Kconfig| 11 +++
drivers/gpu/drm/xlnx/Makefile | 3 +
drivers/gpu/drm/xlnx/zynqmp_dpsub.c | 149
drivers/gpu/drm/xlnx/zynqmp_dpsub.h | 27 +++
4 files changed, 190 insertions(+)
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.c
create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dpsub.h
diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig
index 19fd7cd..7c5529c 100644
--- a/drivers/gpu/drm/xlnx/Kconfig
+++ b/drivers/gpu/drm/xlnx/Kconfig
@@ -10,3 +10,14 @@ config DRM_XLNX
display pipeline using Xilinx IPs in FPGA. This module
provides the kernel mode setting functionalities
for Xilinx display drivers.
+
+config DRM_ZYNQMP_DPSUB
+ tristate "ZynqMP DP Subsystem Driver"
+ depends on ARCH_ZYNQMP && OF && DRM_XLNX && COMMON_CLK
+ select DMA_ENGINE
+ select GENERIC_PHY
+ help
+ DRM KMS driver for ZynqMP DP Subsystem controller. Choose
+ this option if you have a Xilinx ZynqMP SoC with DisplayPort
+ subsystem. The driver provides the kernel mode setting
+ functionlaities for ZynqMP DP subsystem.
diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile
index c60a281..064a05a 100644
--- a/drivers/gpu/drm/xlnx/Makefile
+++ b/drivers/gpu/drm/xlnx/Makefile
@@ -1,2 +1,5 @@
xlnx_drm-objs += xlnx_crtc.o xlnx_drv.o xlnx_fb.o xlnx_gem.o
obj-$(CONFIG_DRM_XLNX) += xlnx_drm.o
+
+zynqmp-dpsub-objs += zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o
+obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
new file mode 100644
index 000..517b492
--- /dev/null
+++ b/drivers/gpu/drm/xlnx/zynqmp_dpsub.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP DP Subsystem Driver
+ *
+ * Copyright (C) 2017 - 2018 Xilinx, Inc.
+ *
+ * Author: Hyun Woo Kwon <hyun.k...@xilinx.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "zynqmp_disp.h"
+#include "zynqmp_dp.h"
+#include "zynqmp_dpsub.h"
+
+static int
+zynqmp_dpsub_bind(struct device *dev, struct device *master, void *data)
+{
+ int ret;
+
+ ret = zynqmp_disp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ /* zynqmp_disp should bind first, so zynqmp_dp encoder can find crtc */
+ ret = zynqmp_dp_bind(dev, master, data);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+zynqmp_dpsub_unbind(struct device *dev, struct device *master, void *data)
+{
+ zynqmp_dp_unbind(dev, master, data);
+ zynqmp_disp_unbind(dev, master, data);
+}
+
+static const struct component_ops zynqmp_dpsub_component_ops = {
+ .bind = zynqmp_dpsub_bind,
+ .unbind = zynqmp_dpsub_unbind,
+};
+
+static int zynqmp_dpsub_probe(struct platform_device *pdev)
+{
+ struct zynqmp_dpsub *dpsub;
+ int ret;
+
+ dpsub = devm_kzalloc(>dev, sizeof(*dpsub), GFP_KERNEL);
+ if (!dpsub)
+ return -ENOMEM;
+
+ /* Sub-driver will access dpsub from drvdata */
+ platform_set_drvdata(pdev, dpsub);
+ pm_runtime_enable(>dev);
+
+ /*
+* DP should be probed first so that the zynqmp_disp can set the output
+* format accordingly.
+*/
+ ret = zynqmp_dp_probe(pdev);
+ if (ret)
+ goto err_pm;
+
+ ret = zynqmp_disp_probe(pdev);
+ if (ret)
+ goto err_dp;
+
+ ret = component_add(>dev, _dpsub_component_ops);
+ if (ret)
+ goto err_disp;
+
+ /* Populate the sound child nodes */
+ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
+ if (ret) {
+ dev_err(>dev, "failed to populate child nodes\n");
+ goto err_component;
+ }
+
+ dev_info(>dev, "ZynqMP DisplayPort Subsystem driver probed");
+
+ return 0;
+
+err_component:
+ component_del(>dev, _dpsub_component_ops);
+err_disp:
+ zynqmp_disp_remove(pdev);
+err_dp:
+ zynqmp_dp_remove(pdev);
+err_pm:
+ pm_runtime_disable(>dev);
+ return ret;
+}
+
+stat
[PATCH v3 5/8] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DisplayPort
This driver creates DRM encoder and connector for ZynqMP DisplayPort. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> --- v2 - Change the SPDX identifier format - Split drm properties into a separate patch --- --- drivers/gpu/drm/xlnx/zynqmp_dp.c | 1738 ++ drivers/gpu/drm/xlnx/zynqmp_dp.h | 37 + 2 files changed, 1775 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_dp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c new file mode 100644 index 000..9c9f4df --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -0,0 +1,1738 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP DisplayPort Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "zynqmp_disp.h" +#include "zynqmp_dpsub.h" + +static uint zynqmp_dp_aux_timeout_ms = 50; +module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); + +/* + * Some sink requires a delay after power on request + */ +static uint zynqmp_dp_power_on_delay_ms = 4; +module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); +MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); + +/* Link configuration registers */ +#define ZYNQMP_DP_TX_LINK_BW_SET 0x0 +#define ZYNQMP_DP_TX_LANE_CNT_SET 0x4 +#define ZYNQMP_DP_TX_ENHANCED_FRAME_EN 0x8 +#define ZYNQMP_DP_TX_TRAINING_PATTERN_SET 0xc +#define ZYNQMP_DP_TX_SCRAMBLING_DISABLE0x14 +#define ZYNQMP_DP_TX_DOWNSPREAD_CTL0x18 +#define ZYNQMP_DP_TX_SW_RESET 0x1c +#define ZYNQMP_DP_TX_SW_RESET_STREAM1 BIT(0) +#define ZYNQMP_DP_TX_SW_RESET_STREAM2 BIT(1) +#define ZYNQMP_DP_TX_SW_RESET_STREAM3 BIT(2) +#define ZYNQMP_DP_TX_SW_RESET_STREAM4 BIT(3) +#define ZYNQMP_DP_TX_SW_RESET_AUX BIT(7) +#define ZYNQMP_DP_TX_SW_RESET_ALL (ZYNQMP_DP_TX_SW_RESET_STREAM1 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM2 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM3 | \ + ZYNQMP_DP_TX_SW_RESET_STREAM4 | \ + ZYNQMP_DP_TX_SW_RESET_AUX) + +/* Core enable registers */ +#define ZYNQMP_DP_TX_ENABLE0x80 +#define ZYNQMP_DP_TX_ENABLE_MAIN_STREAM0x84 +#define ZYNQMP_DP_TX_FORCE_SCRAMBLER_RESET 0xc0 +#define ZYNQMP_DP_TX_VERSION 0xf8 +#define ZYNQMP_DP_TX_VERSION_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_VERSION_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_VERSION_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_VERSION_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_VERSION_REVISION_MASK GENMASK(15, 12) +#define ZYNQMP_DP_TX_VERSION_REVISION_SHIFT12 +#define ZYNQMP_DP_TX_VERSION_PATCH_MASKGENMASK(11, 8) +#define ZYNQMP_DP_TX_VERSION_PATCH_SHIFT 8 +#define ZYNQMP_DP_TX_VERSION_INTERNAL_MASK GENMASK(7, 0) +#define ZYNQMP_DP_TX_VERSION_INTERNAL_SHIFT0 + +/* Core ID registers */ +#define ZYNQMP_DP_TX_CORE_ID 0xfc +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_MASKGENMASK(31, 24) +#define ZYNQMP_DP_TX_CORE_ID_MAJOR_SHIFT 24 +#define ZYNQMP_DP_TX_CORE_ID_MINOR_MASKGENMASK(23, 16) +#define ZYNQMP_DP_TX_CORE_ID_MINOR_SHIFT 16 +#define ZYNQMP_DP_TX_CORE_ID_REVISION_MASK GENMASK(15, 8) +#define ZYNQMP_DP_TX_CORE_ID_REVISION_SHIFT8 +#define ZYNQMP_DP_TX_CORE_ID_DIRECTION GENMASK(1) + +/* AUX channel interface registers */ +#define ZYNQMP_DP_TX_AUX_COMMAND 0x100 +#define ZYNQMP_DP_TX_AUX_COMMAND_CMD_SHIFT 8 +#define Z
[PATCH v3 4/8] drm: xlnx: DRM KMS driver for Xilinx ZynqMP DP subsystem display
Xilinx ZynqMP has a hardened display pipeline. The pipeline can be logically partitioned into 2 parts: display controller and DisplayPort encoder / transmitter. This driver handles the display controller part of the pipeline that handles buffer management and blending. Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com> --- v3 - Fix a small typo v2 - Use drm_fb_cma_get_gem_addr() - Use drm_crtc_arm_vblank_event() - Split drm properties into a separate patch - Remove dummy funcs - Don't add offset as it's already done by a new helper - Change the SPDX identifier format - Minor change of a commit message --- --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 2680 drivers/gpu/drm/xlnx/zynqmp_disp.h | 36 + 2 files changed, 2716 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.c create mode 100644 drivers/gpu/drm/xlnx/zynqmp_disp.h diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c new file mode 100644 index 000..65519ca --- /dev/null +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -0,0 +1,2680 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ZynqMP Display Controller Driver + * + * Copyright (C) 2017 - 2018 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.k...@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xlnx_crtc.h" +#include "xlnx_fb.h" +#include "zynqmp_disp.h" +#include "zynqmp_dp.h" +#include "zynqmp_dpsub.h" + +/* + * Overview + * + * + * The display part of ZynqMP DP subsystem. Internally, the device + * is partitioned into 3 blocks: AV buffer manager, Blender, Audio. + * The driver creates the DRM crtc and plane objectes and maps the DRM + * interface into those 3 blocks. In high level, the driver is layered + * in the following way: + * + * zynqmp_disp_crtc & zynqmp_disp_plane + * |->zynqmp_disp + * |->zynqmp_disp_aud + * |->zynqmp_disp_blend + * |->zynqmp_disp_av_buf + * + * The driver APIs are used externally by + * - zynqmp_dpsub: Top level ZynqMP DP subsystem driver + * - zynqmp_dp: ZynqMP DP driver + * - xlnx_crtc: Xilinx DRM specific crtc functions + */ + +/* Blender registers */ +#define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 +#define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 +#define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MASK 0x1fe +#define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_MAX 0xff +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4440x1 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR4220x2 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 +#define ZYNQMP_DISP_V_BLEND_OUTPUT_EN_DOWNSAMPLE BIT(4) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL 0x18 +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_USBIT(0) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) +#define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) +#define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF0 0x20 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF1 0x24 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF2 0x28 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF3 0x2c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF4 0x30 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF5 0x34 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF6 0x38 +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF7 0x3c +#define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF8 0x40 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF0 0x44 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF1 0x48 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF2 0x4c +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF3 0x50 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF4 0x54 +#define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF5
[PATCH v3 8/8] drm: xlnx: zynqmp_dp: Add drm properties
Add drm properties for DisplayPort synchronous mode and bpc
configurations.
Signed-off-by: Hyun Kwon <hyun.k...@xilinx.com>
---
v2
- Split from the original patch
---
---
drivers/gpu/drm/xlnx/zynqmp_dp.c | 116 ++-
1 file changed, 114 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
index 9c9f4df..e1e8237 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
@@ -302,6 +302,8 @@ struct zynqmp_dp_config {
* struct zynqmp_dp - Xilinx DisplayPort core
* @encoder: the drm encoder structure
* @connector: the drm connector structure
+ * @sync_prop: synchronous mode property
+ * @bpc_prop: bpc mode property
* @dev: device structure
* @dpsub: Display subsystem
* @drm: DRM core
@@ -323,6 +325,8 @@ struct zynqmp_dp_config {
struct zynqmp_dp {
struct drm_encoder encoder;
struct drm_connector connector;
+ struct drm_property *sync_prop;
+ struct drm_property *bpc_prop;
struct device *dev;
struct zynqmp_dpsub *dpsub;
struct drm_device *drm;
@@ -1116,6 +1120,37 @@ static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
}
/**
+ * zynqmp_dp_set_sync_mode - Set the sync mode bit in the software misc state
+ * @dp: DisplayPort IP core structure
+ * @mode: flag if the sync mode should be on or off
+ *
+ * Set the bit in software misc state. To apply to hardware,
+ * zynqmp_dp_update_misc() should be called.
+ */
+static void zynqmp_dp_set_sync_mode(struct zynqmp_dp *dp, bool mode)
+{
+ struct zynqmp_dp_config *config = >config;
+
+ if (mode)
+ config->misc0 |= ZYNQMP_DP_TX_MAIN_STREAM_MISC0_SYNC;
+ else
+ config->misc0 &= ~ZYNQMP_DP_TX_MAIN_STREAM_MISC0_SYNC;
+}
+
+/**
+ * zynqmp_dp_get_sync_mode - Get the sync mode state
+ * @dp: DisplayPort IP core structure
+ *
+ * Return: true if the sync mode is on, or false
+ */
+static bool zynqmp_dp_get_sync_mode(struct zynqmp_dp *dp)
+{
+ struct zynqmp_dp_config *config = >config;
+
+ return !!(config->misc0 & ZYNQMP_DP_TX_MAIN_STREAM_MISC0_SYNC);
+}
+
+/**
* zynqmp_dp_set_bpc - Set bpc value in software misc state
* @dp: DisplayPort IP core structure
* @bpc: bits per component
@@ -1165,6 +1200,17 @@ static u8 zynqmp_dp_set_bpc(struct zynqmp_dp *dp, u8 bpc)
}
/**
+ * zynqmp_dp_get_bpc - Set bpc value from software state
+ * @dp: DisplayPort IP core structure
+ *
+ * Return: current bpc value
+ */
+static u8 zynqmp_dp_get_bpc(struct zynqmp_dp *dp)
+{
+ return dp->config.bpc;
+}
+
+/**
* zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
* @dp: DisplayPort IP core structure
* @mode: requested display mode
@@ -1368,6 +1414,51 @@ static void zynqmp_dp_connector_destroy(struct
drm_connector *connector)
drm_connector_cleanup(connector);
}
+static int
+zynqmp_dp_connector_atomic_set_property(struct drm_connector *connector,
+ struct drm_connector_state *state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct zynqmp_dp *dp = connector_to_dp(connector);
+ int ret;
+
+ if (property == dp->sync_prop) {
+ zynqmp_dp_set_sync_mode(dp, val);
+ } else if (property == dp->bpc_prop) {
+ u8 bpc;
+
+ bpc = zynqmp_dp_set_bpc(dp, val);
+ if (bpc) {
+ drm_object_property_set_value(>base,
+ property, bpc);
+ ret = -EINVAL;
+ }
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+zynqmp_dp_connector_atomic_get_property(struct drm_connector *connector,
+ const struct drm_connector_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct zynqmp_dp *dp = connector_to_dp(connector);
+
+ if (property == dp->sync_prop)
+ *val = zynqmp_dp_get_sync_mode(dp);
+ else if (property == dp->bpc_prop)
+ *val = zynqmp_dp_get_bpc(dp);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
static const struct drm_connector_funcs zynqmp_dp_connector_funcs = {
.detect = zynqmp_dp_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
@@ -1375,6 +1466,8 @@ static const struct drm_connector_funcs
zynqmp_dp_connector_funcs = {
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.reset = drm_atomic_helpe
