from:"Jitao Shi"

[PATCH v7 2/8] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

2019-10-11 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 713 ++
 3 files changed, 723 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d9d931aa6e26..afcadb3585fb 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -18,6 +18,15 @@ config DRM_PANEL_ARM_VERSATILE
  reference designs. The panel is detected using special registers
  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index fb0cb3aaa9e6..bd26b6ac039e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += 
panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..af68236ea0e8
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,713 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+struct panel_desc {
+   const struct drm_display_mode *modes;
+   unsigned int bpc;
+
+   /**
+* @width_mm: width of the panel's active display area
+* @height_mm: height of the panel's active display area
+*/
+   struct {
+   unsigned int width_mm;
+   unsigned int height_mm;
+   } size;
+
+   unsigned long mode_flags;
+   enum mipi_dsi_pixel_format format;
+   const struct panel_init_cmd *init_cmds;
+   unsigned int lanes;
+};
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   const struct panel_desc *desc;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09),
+   _INIT_DCS_CMD(0xC5, 0x09),
+   _INIT_DCS_CMD(0xD8, 0x0A),
+   _INIT_DCS_CMD(0xD9, 0x0A),
+   _INIT_DCS_CMD(0xC2, 0x0B),
+   _INIT_DCS_CMD(0xC3, 0x0B),
+   _INIT_DCS_CMD(0xD6, 0x0C

[PATCH v7 5/5] drm/mediatek: config mipitx impedance with calibration data

2019-09-20 Thread Jitao Shi

Config mipitx impedance with calibration data to make sure their impedance
are 100ohm.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 63 +++
 2 files changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index eea44327fe9f..a1b6292145de 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -28,6 +28,7 @@ struct mtk_mipi_tx {
void __iomem *regs;
u32 data_rate;
u32 mipitx_drive;
+   u32 rt_code[5];
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 5bda8355145f..9ca90dee095a 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@
  */
 
 #include "mtk_mipi_tx.h"
+#include 
+#include 
 
 #define MIPITX_LANE_CON0x000c
 #define RG_DSI_CPHY_T1DRV_EN   BIT(0)
@@ -28,6 +30,7 @@
 #define MIPITX_PLL_CON40x003c
 #define RG_DSI_PLL_IBIAS   (3 << 10)
 
+#define MIPITX_D2P_RTCODE  0x0100
 #define MIPITX_D2_SW_CTL_EN0x0144
 #define MIPITX_D0_SW_CTL_EN0x0244
 #define MIPITX_CK_CKMODE_EN0x0328
@@ -108,6 +111,64 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = {
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 };
 
+static int mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+   u32 *buf = NULL;
+   int i, j;
+   struct nvmem_cell *cell;
+   struct device *dev = mipi_tx->dev;
+   size_t len;
+
+   cell = nvmem_cell_get(dev, "calibration-data");
+   if (IS_ERR(cell)) {
+   dev_warn(dev, "nvmem_cell_get fail\n");
+   return -EINVAL;
+   }
+
+   buf = (u32 *)nvmem_cell_read(cell, &len);
+
+   nvmem_cell_put(cell);
+
+   if (IS_ERR(buf)) {
+   dev_warn(dev, "can't get data\n");
+   return -EINVAL;
+   }
+
+   if (len < 3 * sizeof(u32)) {
+   dev_warn(dev, "invalid calibration data\n");
+   kfree(buf);
+   return -EINVAL;
+   }
+
+   mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1F) << 5) |
+ (buf[0] >> 11 & 0x1F);
+   mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1F) << 5) |
+ (buf[0] >> 1 & 0x1F);
+   mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1F) << 5) |
+ (buf[1] >> 22 & 0x1F);
+   mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1F) << 5) |
+ (buf[1] >> 12 & 0x1F);
+   mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1F) << 5) |
+ (buf[1] >> 2 & 0x1F);
+
+   for (i = 0; i < 5; i++) {
+   if ((mipi_tx->rt_code[i] & 0x1F) == 0)
+   mipi_tx->rt_code[i] |= 0x10;
+
+   if ((mipi_tx->rt_code[i] >> 5 & 0x1F) == 0)
+   mipi_tx->rt_code[i] |= 0x10 << 5;
+
+   for (j = 0; j < 10; j++) {
+   mtk_mipi_tx_update_bits(mipi_tx,
+   MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+   1, mipi_tx->rt_code[i] >> j & 1);
+   }
+   }
+
+   kfree(buf);
+   return 0;
+}
+
 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 {
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +191,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
RG_DSI_HSTX_LDO_REF_SEL,
mipi_tx->mipitx_drive << 6);
 
+   mtk_mipi_tx_config_calibration_data(mipi_tx);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0

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[PATCH v7 3/5] drm/mediatek: add mipi_tx driver for mt8183

2019-09-20 Thread Jitao Shi

This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c|   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|   1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 150 ++
 4 files changed, 154 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
  mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 77b9a185e970..e4d34484ecc8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -175,6 +175,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
  .data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
  .data = &mt8173_mipitx_data },
+   { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 4f905313564f..413f35d86219 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -44,5 +44,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
 
 extern const struct mtk_mipitx_data mt2701_mipitx_data;
 extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
 
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..db13ebdbe262
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi 
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN   BIT(0)
+#define RG_DSI_ANA_CK_SEL  BIT(1)
+#define RG_DSI_PHY_CK_SEL  BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN   BIT(6)
+#define RG_DSI_BG_CORE_EN  BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS   (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN   BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN  BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON  BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN  BIT(1)
+
+#define RG_DSI_PLL_EN  BIT(4)
+#define RG_DSI_PLL_POSDIV  (0x7 << 8)
+
+static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
+{
+   struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+   unsigned int txdiv, txdiv0;
+   u64 pcw;
+
+   dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
+
+   if (mipi_tx->data_rate >= 20) {
+   txdiv = 1;
+   txdiv0 = 0;
+   } else if (mipi_tx->data_rate >= 10) {
+   txdiv = 2;
+   txdiv0 = 1;
+   } else if (mipi_tx->data_rate >= 5) {
+   txdiv = 4;
+   txdiv0 = 2;
+   } else if (mipi_tx->data_rate > 25000) {
+   txdiv = 8;
+   txdiv0 = 3;
+   } else if (mipi_tx->data_rate >= 12500) {
+   txdiv = 16;
+   txdiv0 = 4;
+   } else {
+   return -EINVAL;
+   }
+
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+   mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+   udelay(1);
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+   pcw = div_u64(((u64)mipi_tx->data_rate * txdiv)

[PATCH v7 4/5] drm/mediatek: add the mipitx driving control in device tree

2019-09-20 Thread Jitao Shi

Add a property in device tree to control the driving by different
board.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 6 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h| 1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 7 +++
 3 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index e4d34484ecc8..ec8406c86bfb 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -125,6 +125,12 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
return ret;
}
 
+   ret = of_property_read_u32(dev->of_node, "mipitx-current-drive",
+  &mipi_tx->mipitx_drive);
+   /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
+   if (ret < 0)
+   mipi_tx->mipitx_drive = 0x8;
+
ref_clk_name = __clk_get_name(ref_clk);
 
ret = of_property_read_string(dev->of_node, "clock-output-names",
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 413f35d86219..eea44327fe9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -27,6 +27,7 @@ struct mtk_mipi_tx {
struct device *dev;
void __iomem *regs;
u32 data_rate;
+   u32 mipitx_drive;
const struct mtk_mipitx_data *driver_data;
struct clk_hw pll_hw;
struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index db13ebdbe262..5bda8355145f 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -17,6 +17,9 @@
 #define RG_DSI_BG_CORE_EN  BIT(7)
 #define RG_DSI_PAD_TIEL_SELBIT(8)
 
+#define MIPITX_VOLTAGE_SEL 0x0010
+#define RG_DSI_HSTX_LDO_REF_SEL(0xf << 6)
+
 #define MIPITX_PLL_PWR 0x0028
 #define MIPITX_PLL_CON00x002c
 #define MIPITX_PLL_CON10x0030
@@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
 
+   mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
+   RG_DSI_HSTX_LDO_REF_SEL,
+   mipi_tx->mipitx_drive << 6);
+
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }
 
-- 
2.21.0

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[PATCH v7 0/5] Support mipitx for mt8183

2019-09-20 Thread Jitao Shi

Changes since v6:
 - add the mipitx driving control in device tree.
 - config mipitx impedance with calibration data.

Changes since v5:
 - remove mipi_tx->ref_clk
 - remove mt8183 pll prepare unprepare

Changes since v4:
 - fine tune the mipi_tx->ref_clk and mipi_tx->pll sequence
   1. Prepare mipi_tx->ref_clk
   2. Prepare mipi_tx->pll
   3. Enable mipi_tx->ref_clk
   4. Enable mipi_tx->pll

Changes since v3:
 - turn off PLL before setting PLL parameters.

Changes since v2:
 - update Acked-by: Rob Herring 
 - update mt8183 max bit rate support

Changes since v1:
 - update dt-bindings document for mt8183 mipitx.
 - remove mtk_mipitx_clk_get_ops and assign clk_ops in probe.
 - fix the lincence
 - remove txdiv1 from mtk_mipi_tx_pll_prepare

Jitao Shi (5):
  dt-bindings: display: mediatek: update dsi supported chips
  drm/mediatek: separate mipi_tx to different file
  drm/mediatek: add mipi_tx driver for mt8183
  drm/mediatek: add the mipitx driving control in device tree
  drm/mediatek: config mipitx impedance with calibration data

 .../display/mediatek/mediatek,dsi.txt |  15 +-
 drivers/gpu/drm/mediatek/Makefile |   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 344 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  51 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 220 +++
 6 files changed, 603 insertions(+), 318 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

-- 
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[PATCH v7 2/5] drm/mediatek: separate mipi_tx to different file

2019-09-20 Thread Jitao Shi

Different IC has different mipi_tx setting of dsi.
This patch separates the mipi_tx hardware relate part for mt8173.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 336 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  48 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++
 4 files changed, 359 insertions(+), 315 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 82ae49c64221..2c8de1f5a5ee 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,6 +12,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_drm_plane.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
+ mtk_mt8173_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 1842dc2caae9..77b9a185e970 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -3,292 +3,39 @@
  * Copyright (c) 2015 MediaTek Inc.
  */
 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define MIPITX_DSI_CON 0x00
-#define RG_DSI_LDOCORE_EN  BIT(0)
-#define RG_DSI_CKG_LDOOUT_EN   BIT(1)
-#define RG_DSI_BCLK_SEL(3 << 2)
-#define RG_DSI_LD_IDX_SEL  (7 << 4)
-#define RG_DSI_PHYCLK_SEL  (2 << 8)
-#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
-#define RG_DSI_LPTX_CLMP_ENBIT(11)
-
-#define MIPITX_DSI_CLOCK_LANE  0x04
-#define MIPITX_DSI_DATA_LANE0  0x08
-#define MIPITX_DSI_DATA_LANE1  0x0c
-#define MIPITX_DSI_DATA_LANE2  0x10
-#define MIPITX_DSI_DATA_LANE3  0x14
-#define RG_DSI_LNTx_LDOOUT_EN  BIT(0)
-#define RG_DSI_LNTx_CKLANE_EN  BIT(1)
-#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2)
-#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3)
-#define RG_DSI_LNTx_LPTX_IMINUSBIT(4)
-#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
-#define RG_DSI_LNTx_LPCD_IMINUSBIT(6)
-#define RG_DSI_LNTx_RT_CODE(0xf << 8)
-
-#define MIPITX_DSI_TOP_CON 0x40
-#define RG_DSI_LNT_INTR_EN BIT(0)
-#define RG_DSI_LNT_HS_BIAS_EN  BIT(1)
-#define RG_DSI_LNT_IMP_CAL_EN  BIT(2)
-#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
-#define RG_DSI_PAD_TIE_LOW_EN  BIT(11)
-#define RG_DSI_DEBUG_INPUT_EN  BIT(12)
-#define RG_DSI_PRESERVE(7 << 13)
-
-#define MIPITX_DSI_BG_CON  0x44
-#define RG_DSI_BG_CORE_EN  BIT(0)
-#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV  (0x3 << 2)
-#define RG_DSI_BG_FAST_CHARGE  BIT(4)
-#define RG_DSI_VOUT_MSK(0x3 << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL(7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL(7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM  (0xf << 24)
-#define RG_DSI_BG_R2_TRIM  (0xf << 28)
-
-#define MIPITX_DSI_PLL_CON00x50
-#define RG_DSI_MPPLL_PLL_ENBIT(0)
-#define RG_DSI_MPPLL_DIV_MSK   (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV(3 << 1)
-#define RG_DSI_MPPLL_TXDIV0(3 << 3)
-#define RG_DSI_MPPLL_TXDIV1(3 << 5)
-#define RG_DSI_MPPLL_POSDIV(7 << 7)
-#define RG_DSI_MPPLL_MONVC_EN  BIT(10)
-#define RG_DSI_MPPLL_MONREF_EN BIT(11)
-#define RG_DSI_MPPLL_VOD_ENBIT(12)
-
-#define MIPITX_DSI_PLL_CON10x54
-#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0)
-#define RG_DSI_MPPLL_SDM_SSC_PH_INIT   BIT(1)
-#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD   (0x << 16)
-
-#define MIPITX_DSI_PLL_CON20x58
-
-#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE  (0xff << 8)
-
-#define MIPITX_DSI_PLL_PWR 0x68
-#define RG_DSI_MPPLL_SDM_PWR_ONBIT(0)
-#define RG_DSI_MPPLL_SDM_ISO_ENBIT(1)
-#define RG_DSI_MPPLL_SDM_PWR_ACK   BIT(8)
-
-#define MIPITX_DSI_SW_CTRL 0x80
-#define SW_CTRL_EN BIT(0)
-
-#define MIPITX_DSI_SW_CTRL_CON00x84
-#define SW_LNTC_LPTX_PRE_OE

[PATCH v7 1/5] dt-bindings: display: mediatek: update dsi supported chips

2019-09-20 Thread Jitao Shi

Update device tree binding documentation for the dsi for
Mediatek MT8183 SoCs.

Signed-off-by: Jitao Shi 
Acked-by: Rob Herring 
---
 .../bindings/display/mediatek/mediatek,dsi.txt| 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index fadf327c7cdf..993ff079ac09 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
 
 Required properties:
 - compatible: "mediatek,-dsi"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks
@@ -26,22 +26,31 @@ The MIPI TX configuration module controls the MIPI D-PHY.
 
 Required properties:
 - compatible: "mediatek,-mipi-tx"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - clocks: PLL reference clock
 - clock-output-names: name of the output clock line to the DSI encoder
 - #clock-cells: must be <0>;
 - #phy-cells: must be <0>.
 
+Optional properties:
+- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
+   unspecified default values shall be used.
+- nvmem-cell-names: Should be "calibration-data"
+- mipitx-current-drive: adjust driving current, should be 1 ~ 0xF
+
 Example:
 
 mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
clocks = <&clk26m>;
-   clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
+   clock-output-names = "mipi_tx0_pll";
+   nvmem-cells= <&mipi_tx_calibration>;
+   nvmem-cell-names = "calibration-data";
+   mipitx-current-drive = <0x8>;
 };
 
 dsi0: dsi@1401b000 {
-- 
2.21.0

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[PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence

2019-09-19 Thread Jitao Shi

mtk_mipi_tx is the phy of mtk_dsi.
mtk_dsi get the phy(mtk_mipi_tx) in probe().

So,  mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
defer to wait mtk_mipi_tx probe done.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 945bc20f1d33..7f072cc98530 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -677,8 +677,8 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
-   &mtk_dsi_driver,
&mtk_mipi_tx_driver,
+   &mtk_dsi_driver,
 };
 
 static int __init mtk_drm_init(void)
-- 
2.21.0

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[PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number

2019-09-19 Thread Jitao Shi

Add dphy reset after setting lanes number to avoid dphy fifo effor.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b02373b04848..8c2620ea18d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -37,6 +37,7 @@
 #define DSI_CON_CTRL   0x10
 #define DSI_RESET  BIT(0)
 #define DSI_EN BIT(1)
+#define DPHY_RESET BIT(2)
 
 #define DSI_MODE_CTRL  0x14
 #define MODE   (3)
@@ -280,6 +281,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 }
 
+static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
+{
+   mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
+   mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
+}
+
 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
@@ -650,6 +657,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_phy_timconfig(dsi);
 
mtk_dsi_rxtx_control(dsi);
+   usleep_range(30, 100);
+   mtk_dsi_reset_dphy(dsi);
mtk_dsi_ps_control_vact(dsi);
mtk_dsi_set_vm_cmd(dsi);
mtk_dsi_config_vdo_timing(dsi);
-- 
2.21.0

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[PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method

2019-09-18 Thread Jitao Shi

Change the method of frame rate calc which can get more accurate
frame rate.

data rate = pixel_clock * bit_per_pixel / lanes
Adjust hfp_wc to adapt the additional phy_data

if MIPI_DSI_MODE_VIDEO_BURST
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
else
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;

Note:
//(2: 1 for sync, 1 for phy idle)
data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;

bpp: bit per pixel

Signed-off-by: Jitao Shi 
Tested-by: Ryan Case 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 118 -
 1 file changed, 81 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b3676426aeb5..b02373b04848 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -136,12 +136,6 @@
 #define DATA_0 (0xff << 16)
 #define DATA_1 (0xff << 24)
 
-#define T_LPX  5
-#define T_HS_PREP  6
-#define T_HS_TRAIL 8
-#define T_HS_EXIT  7
-#define T_HS_ZERO  10
-
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
 
 #define MTK_DSI_HOST_IS_READ(type) \
@@ -150,6 +144,25 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
 
+struct mtk_phy_timing {
+   u32 lpx;
+   u32 da_hs_prepare;
+   u32 da_hs_zero;
+   u32 da_hs_trail;
+
+   u32 ta_go;
+   u32 ta_sure;
+   u32 ta_get;
+   u32 da_hs_exit;
+
+   u32 clk_hs_zero;
+   u32 clk_hs_trail;
+
+   u32 clk_hs_prepare;
+   u32 clk_hs_post;
+   u32 clk_hs_exit;
+};
+
 struct phy;
 
 struct mtk_dsi_driver_data {
@@ -180,6 +193,7 @@ struct mtk_dsi {
enum mipi_dsi_pixel_format format;
unsigned int lanes;
struct videomode vm;
+   struct mtk_phy_timing phy_timing;
int refcount;
bool enabled;
u32 irq_data;
@@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 {
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
+
+   ui = DIV_ROUND_UP(10, dsi->data_rate);
+   cycle_time = div_u64(80ULL, dsi->data_rate);
+
+   timing->lpx = NS_TO_CYCLE(60, cycle_time);
+   timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
+   timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
+   timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
 
-   ui = 1000 / dsi->data_rate + 0x01;
-   cycle_time = 8000 / dsi->data_rate + 0x01;
+   timing->ta_go = 4 * timing->lpx;
+   timing->ta_sure = 3 * timing->lpx / 2;
+   timing->ta_get = 5 * timing->lpx;
+   timing->da_hs_exit = 2 * timing->lpx;
 
-   timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
-   timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
- T_HS_EXIT << 24;
-   timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
-   timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
+   timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
+   timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
+
+   timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
+   timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
+   timing->clk_hs_exit = 2 * timing->lpx;
+
+   timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
+ timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+   timcon1 = timing->ta_go | timing->ta_sure << 8 |
+ timing->ta_get << 16 | timing->da_hs_exit << 24;
+   timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
+ timing->clk_hs_trail << 24;
+   timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
+ timing->clk_hs_exit << 16;
 
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
-   u32 dsi_tmp_buf_bpp;
+   u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
 
struct videomode *vm = &dsi->vm;
 
@@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *

[PATCH v7 5/9] drm/mediatek: add frame size control

2019-09-18 Thread Jitao Shi

Our new DSI chip has frame size control.
So add the driver data to control for different chips.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 314bfb1c827b..68794edecf96 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -70,6 +70,7 @@
 #define DSI_VBP_NL 0x24
 #define DSI_VFP_NL 0x28
 #define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON   0x38
 #define DSI_HSA_WC 0x50
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58
@@ -154,6 +155,7 @@ struct phy;
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+   bool has_size_ctl;
 };
 
 struct mtk_dsi {
@@ -422,6 +424,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 
+   if (dsi->driver_data->has_size_ctl)
+   writel(vm->vactive << 16 | vm->hactive,
+  dsi->regs + DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-- 
2.21.0

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[PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support

2019-09-18 Thread Jitao Shi

Add mt8183 dsi driver data. Enable size control and
reg commit control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 68794edecf96..b3676426aeb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1227,11 +1227,19 @@ static const struct mtk_dsi_driver_data 
mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
 };
 
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+   .has_shadow_ctl = true,
+   .has_size_ctl = true,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
  .data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
  .data = &mt8173_dsi_driver_data },
+   { .compatible = "mediatek,mt8183-dsi",
+ .data = &mt8183_dsi_driver_data },
{ },
 };
 
-- 
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[PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control

2019-09-18 Thread Jitao Shi

New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.

This fucntion is defualt on. But this driver doesn't use this
function. So add the disable control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ac8e80e379f7..314bfb1c827b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,6 +123,10 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
+#define DSI_SHADOW_DEBUG   0x190U
+#define FORCE_COMMIT   BIT(0)
+#define BYPASS_SHADOW  BIT(1)
+
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -149,6 +153,7 @@ struct phy;
 
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+   bool has_shadow_ctl;
 };
 
 struct mtk_dsi {
@@ -586,6 +591,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
 
mtk_dsi_enable(dsi);
+
+   if (dsi->driver_data->has_shadow_ctl)
+   writel(FORCE_COMMIT | BYPASS_SHADOW,
+  dsi->regs + DSI_SHADOW_DEBUG);
+
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
 
-- 
2.21.0

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[PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask()

2019-09-18 Thread Jitao Shi

The writeb() is unavailable in mt8173. Because the mt8173 dsi module
doesn't support 8bit mode access.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 7e24d03cdccc..ac8e80e379f7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -960,7 +960,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
}
 
for (i = 0; i < msg->tx_len; i++)
-   writeb(tx_buf[i], dsi->regs + reg_cmdq_off + cmdq_off + i);
+   mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
 
mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
-- 
2.21.0

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[PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701

2019-09-18 Thread Jitao Shi

Config the different CMDQ reg address in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 27 ++-
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 52b49daeed9f..7e24d03cdccc 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,7 +123,6 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
-#define DSI_CMDQ0  0x180
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -148,6 +147,10 @@
 
 struct phy;
 
+struct mtk_dsi_driver_data {
+   const u32 reg_cmdq_off;
+};
+
 struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -174,6 +177,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+   const struct mtk_dsi_driver_data *driver_data;
 };
 
 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -936,6 +940,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+   u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
 
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -955,9 +960,9 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
}
 
for (i = 0; i < msg->tx_len; i++)
-   writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+   writeb(tx_buf[i], dsi->regs + reg_cmdq_off + cmdq_off + i);
 
-   mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+   mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 }
 
@@ -1101,6 +1106,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
 
+   dsi->driver_data = of_device_get_match_data(dev);
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1194,9 +1201,19 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
 }
 
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+   .reg_cmdq_off = 0x180,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
-   { .compatible = "mediatek,mt2701-dsi" },
-   { .compatible = "mediatek,mt8173-dsi" },
+   { .compatible = "mediatek,mt2701-dsi",
+ .data = &mt2701_dsi_driver_data },
+   { .compatible = "mediatek,mt8173-dsi",
+ .data = &mt8173_dsi_driver_data },
{ },
 };
 
-- 
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[PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe

2019-09-18 Thread Jitao Shi

DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.

If mipi_dsi_host_register is not in probe, dsi panel will
probe more delay.

So move the mipi_dsi_host_register to probe from bind.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 53 +-
 1 file changed, 31 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b91c4616644a..52b49daeed9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -520,7 +520,7 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, 
u8 irq_flag, u32 t)
 
 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 {
-   struct device *dev = dsi->dev;
+   struct device *dev = dsi->host.dev;
int ret;
u64 pixel_clock, total_bits;
u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
@@ -1047,12 +1047,6 @@ static int mtk_dsi_bind(struct device *dev, struct 
device *master, void *data)
return ret;
}
 
-   ret = mipi_dsi_host_register(&dsi->host);
-   if (ret < 0) {
-   dev_err(dev, "failed to register DSI host: %d\n", ret);
-   goto err_ddp_comp_unregister;
-   }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1062,8 +1056,6 @@ static int mtk_dsi_bind(struct device *dev, struct device 
*master, void *data)
return 0;
 
 err_unregister:
-   mipi_dsi_host_unregister(&dsi->host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
return ret;
 }
@@ -1075,7 +1067,6 @@ static void mtk_dsi_unbind(struct device *dev, struct 
device *master,
struct mtk_dsi *dsi = dev_get_drvdata(dev);
 
mtk_dsi_destroy_conn_enc(dsi);
-   mipi_dsi_host_unregister(&dsi->host);
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
 }
 
@@ -1099,31 +1090,36 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 
dsi->host.ops = &mtk_dsi_ops;
dsi->host.dev = dev;
+   ret = mipi_dsi_host_register(&dsi->host);
+   if (ret < 0) {
+   dev_err(dev, "failed to register DSI host: %d\n", ret);
+   return ret;
+   }
 
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
  &dsi->panel, &dsi->bridge);
if (ret)
-   return ret;
+   goto err_unregister_host;
 
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1131,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
-   return comp_id;
+   ret = comp_id;
+   goto err_unregister_host;
}
 
ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
&mtk_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
irq_num = platform_get_irq(p

[PATCH v7 0/9] Support dsi for mt8183

2019-09-18 Thread Jitao Shi

Changes since v6:
 - add dphy reset to avoid dphy fifo error after lines number setting
 - separate dsi cmd reg setting from "fixes CMDQ reg address of mt8173
   is different with mt2701"

Changes since v5:
 - fine tune dphy timing.

Changes since v4:
 - move mipi_dsi_host_unregiter() to .remove()
 - fine tune add frame size control coding style
 - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL
 - use div_u64 when 80ULL / dsi->data_rate.

Changes since v3
 - add one more 'tab' for bitwise define.
 - add Tested-by: Ryan Case 
and Reviewed-by: CK Hu .
 - remove compare da_hs_zero to da_hs_prepare.

Changes since v2:
 - change the video timing calc method
 - fine the dsi and mipitx init sequence
 - fine tune commit msg

Changes since v1:
 - separate frame size and reg commit control independent patches.
 - fix some return values in probe
 - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" 

Jitao Shi (9):
  drm/mediatek: move mipi_dsi_host_register to probe
  drm/mediatek: fixes CMDQ reg address of mt8173 is different with
mt2701
  drm/mediatek: replace writeb() with mtk_dsi_mask()
  drm/mediatek: add dsi reg commit disable control
  drm/mediatek: add frame size control
  drm/mediatek: add mt8183 dsi driver support
  drm/mediatek: change the dsi phytiming calculate method
  drm: mediatek: adjust dsi and mipi_tx probe sequence
  drm/mediatek: add dphy reset after setting lanes number

 drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +-
 drivers/gpu/drm/mediatek/mtk_dsi.c | 233 ++---
 2 files changed, 170 insertions(+), 65 deletions(-)

-- 
2.21.0

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[PATCH v6 4/8] drm/panel: support for auo, kd101n80-45na wuxga dsi video mode panel

2019-09-18 Thread Jitao Shi

Auo,kd101n80-45na's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,kd101n80-45na and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |  6 +-
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 86 ---
 2 files changed, 75 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index afcadb3585fb..0e887c978796 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -19,13 +19,13 @@ config DRM_PANEL_ARM_VERSATILE
  in the Versatile family syscon registers.
 
 config DRM_PANEL_BOE_TV101WUM_NL6
-   tristate "BOE TV101WUM 1200x1920 panel"
+   tristate "BOE TV101WUM and AUO KD101N80 45NA 1200x1920 panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
- Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
- DSI Video Mode panel
+ Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
+ 45NA WUXGA PANEL DSI Video Mode panel
 
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index e27529b80d78..f80974778360 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -35,6 +35,7 @@ struct panel_desc {
enum mipi_dsi_pixel_format format;
const struct panel_init_cmd *init_cmds;
unsigned int lanes;
+   bool discharge_on_disable;
 };
 
 struct boe_panel {
@@ -372,6 +373,15 @@ static const struct panel_init_cmd boe_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0x11),
+   _INIT_DELAY_CMD(120),
+   _INIT_DCS_CMD(0x29),
+   _INIT_DELAY_CMD(120),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -449,20 +459,30 @@ static int boe_panel_unprepare(struct drm_panel *panel)
if (!boe->prepared)
return 0;
 
-   ret = boe_panel_off(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
-   return ret;
+   if (boe->desc->discharge_on_disable) {
+   msleep(150);
+   regulator_disable(boe->avee);
+   regulator_disable(boe->avdd);
+   usleep_range(5000, 7000);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(5000, 7000);
+   regulator_disable(boe->pp1800);
+   } else {
+   ret = boe_panel_off(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n",
+   ret);
+   return ret;
+   }
+   msleep(150);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(500, 1000);
+   regulator_disable(boe->avee);
+   regulator_disable(boe->avdd);
+   usleep_range(5000, 7000);
+   regulator_disable(boe->pp1800);
}
 
-   msleep(150);
-   gpiod_set_value(boe->enable_gpio, 0);
-   usleep_range(500, 1000);
-   regulator_disable(boe->avee);
-   regulator_disable(boe->avdd);
-   usleep_range(5000, 7000);
-   regulator_disable(boe->pp1800);
-
boe->prepared = false;
 
return 0;
@@ -492,10 +512,14 @@ static int boe_panel_prepare(struct drm_panel *panel)
if (ret < 0)
goto poweroffavdd;
 
-   msleep(100);
+   usleep_range(5000, 1);
 
gpiod_set_value(boe->enable_gpio, 1);
-   usleep_range(1, 12000);
+   usleep_range(1000, 2000);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(1000, 2000);
+   gpiod_set_value(boe->enable_gpio, 1);
+   usleep_range(6000, 1);
 
ret = boe_panel_init(boe);
if (ret < 0) {
@@ -527,6 +551,8 @@ static int boe_panel_enable(struct drm_panel *panel)
if (boe->enabled)
return 0;
 
+   msleep(70);
+
ret = backlight_enable(boe->backlight);
if (ret) {
dev_err(panel->dev, "Failed to enable backlight %d\n",
@@ -564,6 +590,35 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  MIPI_DSI_MODE_LPM,
.init_cmds = boe_init_cmd,
+   .discharge_on_disable = false,
+};
+
+static const struct drm_display_m

[PATCH v6 7/8] dt-bindings: display: panel: add AUO auo, b101uan08.3 panel documentation

2019-09-18 Thread Jitao Shi

Add dcumentation for auo,b101uan08.3, which is mipi dsi video panel
and resolution is 1200x1920.

Signed-off-by: Jitao Shi 
---
 .../display/panel/auo,b101uan08.3.yaml| 67 +++
 1 file changed, 67 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.yaml 
b/Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.yaml
new file mode 100644
index ..96125d7d1fe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/auo,b101uan08.3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AUO B101UAN08.3 DSI Display Panel
+
+maintainers:
+  - Thierry Reding 
+  - Sam Ravnborg 
+  - Rob Herring 
+ 
+properties:
+  compatible:
+const: auo,b101uan08.3
+
+  reg:
+description: the virtual channel number of a DSI peripheral
+
+  enable-gpios:
+description: a GPIO spec for the enable pin
+
+  pp1800-supply:
+description: core voltage supply
+
+  avdd-supply:
+description: phandle of the regulator that provides positive voltage
+
+  avee-supply:
+description: phandle of the regulator that provides negative voltage
+
+  backlight:
+description: phandle of the backlight device attached to the panel
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
+ - backlight
+
+additionalProperties: false
+
+examples:
+  - |
+&dsi {
+panel@0 {
+compatible = "auo,b101uan08.3";
+reg = <0>;
+enable-gpios = <&pio 45 0>;
+avdd-supply = <&ppvarn_lcd>;
+avee-supply = <&ppvarp_lcd>;
+pp1800-supply = <&pp1800_lcd>;
+backlight = <&backlight_lcd0>;
+status = "okay";
+port {
+panel_in: endpoint {
+remote-endpoint = <&dsi_out>;
+};
+};
+};
+};
+
+...
\ No newline at end of file
-- 
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[PATCH v6 8/8] drm/panel: support for auo, b101uan08.3 wuxga dsi video mode panel

2019-09-18 Thread Jitao Shi

Auo,auo,b101uan08.3's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,b101uan08.3 and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 78 +++
 1 file changed, 78 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index c757035ac09c..40dcb61ef423 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -382,6 +382,53 @@ static const struct panel_init_cmd 
auo_kd101n80_45na_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xC0, 0x48),
+   _INIT_DCS_CMD(0xC1, 0x48),
+   _INIT_DCS_CMD(0xC2, 0x47),
+   _INIT_DCS_CMD(0xC3, 0x47),
+   _INIT_DCS_CMD(0xC4, 0x46),
+   _INIT_DCS_CMD(0xC5, 0x46),
+   _INIT_DCS_CMD(0xC6, 0x45),
+   _INIT_DCS_CMD(0xC7, 0x45),
+   _INIT_DCS_CMD(0xC8, 0x64),
+   _INIT_DCS_CMD(0xC9, 0x64),
+   _INIT_DCS_CMD(0xCA, 0x4F),
+   _INIT_DCS_CMD(0xCB, 0x4F),
+   _INIT_DCS_CMD(0xCC, 0x40),
+   _INIT_DCS_CMD(0xCD, 0x40),
+   _INIT_DCS_CMD(0xCE, 0x66),
+   _INIT_DCS_CMD(0xCF, 0x66),
+   _INIT_DCS_CMD(0xD0, 0x4F),
+   _INIT_DCS_CMD(0xD1, 0x4F),
+   _INIT_DCS_CMD(0xD2, 0x41),
+   _INIT_DCS_CMD(0xD3, 0x41),
+   _INIT_DCS_CMD(0xD4, 0x48),
+   _INIT_DCS_CMD(0xD5, 0x48),
+   _INIT_DCS_CMD(0xD6, 0x47),
+   _INIT_DCS_CMD(0xD7, 0x47),
+   _INIT_DCS_CMD(0xD8, 0x46),
+   _INIT_DCS_CMD(0xD9, 0x46),
+   _INIT_DCS_CMD(0xDA, 0x45),
+   _INIT_DCS_CMD(0xDB, 0x45),
+   _INIT_DCS_CMD(0xDC, 0x64),
+   _INIT_DCS_CMD(0xDD, 0x64),
+   _INIT_DCS_CMD(0xDE, 0x4F),
+   _INIT_DCS_CMD(0xDF, 0x4F),
+   _INIT_DCS_CMD(0xE0, 0x40),
+   _INIT_DCS_CMD(0xE1, 0x40),
+   _INIT_DCS_CMD(0xE2, 0x66),
+   _INIT_DCS_CMD(0xE3, 0x66),
+   _INIT_DCS_CMD(0xE4, 0x4F),
+   _INIT_DCS_CMD(0xE5, 0x4F),
+   _INIT_DCS_CMD(0xE6, 0x41),
+   _INIT_DCS_CMD(0xE7, 0x41),
+   _INIT_DELAY_CMD(150),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -649,6 +696,34 @@ static const struct panel_desc boe_tv101wum_n53_desc = {
.init_cmds = boe_init_cmd,
 };
 
+static const struct drm_display_mode auo_b101uan08_3_default_mode = {
+   .clock = 159667,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 60,
+   .hsync_end = 1200 + 60 + 4,
+   .htotal = 1200 + 60 + 4 + 80,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 34,
+   .vsync_end = 1920 + 34 + 2,
+   .vtotal = 1920 + 34 + 2 + 24,
+   .vrefresh = 60,
+   .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc auo_b101uan08_3_desc = {
+   .modes = &auo_b101uan08_3_default_mode,
+   .bpc = 8,
+   .size = {
+   .width_mm = 135,
+   .height_mm = 216,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = auo_b101uan08_3_init_cmd,
+};
+
 static int boe_panel_get_modes(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
@@ -778,6 +853,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "boe,tv101wum-n53",
  .data = &boe_tv101wum_n53_desc
},
+   { .compatible = "auo,b101uan08.3",
+ .data = &auo_b101uan08_3_desc
+   },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, boe_of_match);
-- 
2.21.0

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[PATCH v6 3/8] dt-bindings: display: panel: add auo kd101n80-45na panel bindings

2019-09-18 Thread Jitao Shi

Add documentation for auo kd101n80-45na panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/auo,kd101n80-45na.yaml  | 67 +++
 1 file changed, 67 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.yaml 
b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.yaml
new file mode 100644
index ..caf82765fa0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/auo,kd101n80-45na.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AUO KD101N80-45NA DSI Display Panel
+
+maintainers:
+  - Thierry Reding 
+  - Sam Ravnborg 
+  - Rob Herring 
+ 
+properties:
+  compatible:
+const: auo,kd101n80-45na
+
+  reg:
+description: the virtual channel number of a DSI peripheral
+
+  enable-gpios:
+description: a GPIO spec for the enable pin
+
+  pp1800-supply:
+description: core voltage supply
+
+  avdd-supply:
+description: phandle of the regulator that provides positive voltage
+
+  avee-supply:
+description: phandle of the regulator that provides negative voltage
+
+  backlight:
+description: phandle of the backlight device attached to the panel
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
+ - backlight
+
+additionalProperties: false
+
+examples:
+  - |
+&dsi {
+panel@0 {
+compatible = "auo,kd101n80-45na";
+reg = <0>;
+enable-gpios = <&pio 45 0>;
+avdd-supply = <&ppvarn_lcd>;
+avee-supply = <&ppvarp_lcd>;
+pp1800-supply = <&pp1800_lcd>;
+backlight = <&backlight_lcd0>;
+status = "okay";
+port {
+panel_in: endpoint {
+remote-endpoint = <&dsi_out>;
+};
+};
+};
+};
+
+...
\ No newline at end of file
-- 
2.21.0

[PATCH v6 5/8] dt-bindings: display: panel: add boe tv101wum-n53 panel documentation

2019-09-18 Thread Jitao Shi

Add dcumentation for boe,tv101wum-n53, which is mipi dsi video panel
and resolution is 1200x1920.

Signed-off-by: Jitao Shi 
---
 .../display/panel/boe,tv101wum-n53.yaml   | 67 +++
 1 file changed, 67 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.yaml 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.yaml
new file mode 100644
index ..f541446fc70c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/boe,tv101wum-n53.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BOE TV101WUM-N53 DSI Display Panel
+
+maintainers:
+  - Thierry Reding 
+  - Sam Ravnborg 
+  - Rob Herring 
+ 
+properties:
+  compatible:
+const: boe,tv101wum-n53
+
+  reg:
+description: the virtual channel number of a DSI peripheral
+
+  enable-gpios:
+description: a GPIO spec for the enable pin
+
+  pp1800-supply:
+description: core voltage supply
+
+  avdd-supply:
+description: phandle of the regulator that provides positive voltage
+
+  avee-supply:
+description: phandle of the regulator that provides negative voltage
+
+  backlight:
+description: phandle of the backlight device attached to the panel
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
+ - backlight
+
+additionalProperties: false
+
+examples:
+  - |
+&dsi {
+panel@0 {
+compatible = "boe,tv101wum-n53";
+reg = <0>;
+enable-gpios = <&pio 45 0>;
+avdd-supply = <&ppvarn_lcd>;
+avee-supply = <&ppvarp_lcd>;
+pp1800-supply = <&pp1800_lcd>;
+backlight = <&backlight_lcd0>;
+status = "okay";
+port {
+panel_in: endpoint {
+remote-endpoint = <&dsi_out>;
+};
+};
+};
+};
+
+...
\ No newline at end of file
-- 
2.21.0

[PATCH v6 6/8] drm/panel: support for boe, tv101wum-n53 wuxga dsi video mode panel

2019-09-18 Thread Jitao Shi

Boe,tv101wum-n53's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So boe,tv101wum-n53 and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index f80974778360..c757035ac09c 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -621,6 +621,34 @@ static const struct panel_desc auo_kd101n80_45na_desc = {
.discharge_on_disable = true,
 };
 
+static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
+   .clock = 159833,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 114,
+   .hsync_end = 1200 + 114 + 10,
+   .htotal = 1200 + 114 + 10 + 40,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 19,
+   .vsync_end = 1920 + 19 + 4,
+   .vtotal = 1920 + 19 + 4 + 10,
+   .vrefresh = 60,
+   .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc boe_tv101wum_n53_desc = {
+   .modes = &boe_tv101wum_n53_default_mode,
+   .bpc = 8,
+   .size = {
+   .width_mm = 135,
+   .height_mm = 216,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = boe_init_cmd,
+};
+
 static int boe_panel_get_modes(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
@@ -747,6 +775,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "auo,kd101n80-45na",
  .data = &auo_kd101n80_45na_desc
},
+   { .compatible = "boe,tv101wum-n53",
+ .data = &boe_tv101wum_n53_desc
+   },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, boe_of_match);
-- 
2.21.0

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[PATCH v6 0/8] add driver for "boe, tv101wum-nl6", "boe, tv101wum-n53", "auo, kd101n80-45na" and "auo, b101uan08.3" panels

2019-09-18 Thread Jitao Shi

Changes since v5:
 - covert the documents to yaml
 - fine tune boe, tv101wum-n53 panel video timine

Changes since v4:
 - add auo,b101uan08.3 panel for this driver.
 - add boe,tv101wum-n53 panel for this driver.

Changes since v3:
 - remove check enable_gpio.
 - fine tune the auo,kd101n80-45na panel's power on timing.

Changes since v2:
 - correct the panel size
 - remove blank line in Kconfig
 - move auo,kd101n80-45na panel driver in this series.

Changes since v1:

 - update typo nl6 -> n16.
 - update new panel config and makefile are added in alphabetically order.
 - add the panel mode and panel info in driver data.
 - merge auo,kd101n80-45a and boe,tv101wum-nl6 in one driver

Jitao Shi (8):
  dt-bindings: display: panel: Add BOE tv101wum-n16 panel bindings
  drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel
  dt-bindings: display: panel: add auo kd101n80-45na panel bindings
  drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel
  dt-bindings: display: panel: add boe tv101wum-n53 panel documentation
  drm/panel: support for boe,tv101wum-n53 wuxga dsi video mode panel
  dt-bindings: display: panel: add AUO auo,b101uan08.3 panel
documentation
  drm/panel: support for auo,b101uan08.3 wuxga dsi video mode panel

 .../display/panel/auo,b101uan08.3.yaml|  67 ++
 .../display/panel/auo,kd101n80-45na.yaml  |  67 ++
 .../display/panel/boe,tv101wum-n53.yaml   |  67 ++
 .../display/panel/boe,tv101wum-nl6.yaml   |  67 ++
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 876 ++
 7 files changed, 1154 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.yaml
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

-- 
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[PATCH v6 1/8] dt-bindings: display: panel: Add BOE tv101wum-n16 panel bindings

2019-09-18 Thread Jitao Shi

Add documentation for boe tv101wum-n16 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/boe,tv101wum-nl6.yaml   | 67 +++
 1 file changed, 67 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
new file mode 100644
index ..31d394054181
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/boe,tv101wum-nl6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BOE TV101WUM-Nl6 DSI Display Panel
+
+maintainers:
+  - Thierry Reding 
+  - Sam Ravnborg 
+  - Rob Herring 
+ 
+properties:
+  compatible:
+const: boe,tv101wum-nl6
+
+  reg:
+description: the virtual channel number of a DSI peripheral
+
+  enable-gpios:
+description: a GPIO spec for the enable pin
+
+  pp1800-supply:
+description: core voltage supply
+
+  avdd-supply:
+description: phandle of the regulator that provides positive voltage
+
+  avee-supply:
+description: phandle of the regulator that provides negative voltage
+
+  backlight:
+description: phandle of the backlight device attached to the panel
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
+ - backlight
+
+additionalProperties: false
+
+examples:
+  - |
+&dsi {
+panel@0 {
+compatible = "boe,tv101wum-nl6";
+reg = <0>;
+enable-gpios = <&pio 45 0>;
+avdd-supply = <&ppvarn_lcd>;
+avee-supply = <&ppvarp_lcd>;
+pp1800-supply = <&pp1800_lcd>;
+backlight = <&backlight_lcd0>;
+status = "okay";
+port {
+panel_in: endpoint {
+remote-endpoint = <&dsi_out>;
+};
+};
+};
+};
+
+...
\ No newline at end of file
-- 
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[PATCH v6 2/8] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

2019-09-18 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 709 ++
 3 files changed, 719 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d9d931aa6e26..afcadb3585fb 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -18,6 +18,15 @@ config DRM_PANEL_ARM_VERSATILE
  reference designs. The panel is detected using special registers
  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index fb0cb3aaa9e6..bd26b6ac039e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += 
panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..e27529b80d78
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+struct panel_desc {
+   const struct drm_display_mode *modes;
+   unsigned int bpc;
+
+   /**
+* @width_mm: width of the panel's active display area
+* @height_mm: height of the panel's active display area
+*/
+   struct {
+   unsigned int width_mm;
+   unsigned int height_mm;
+   } size;
+
+   unsigned long mode_flags;
+   enum mipi_dsi_pixel_format format;
+   const struct panel_init_cmd *init_cmds;
+   unsigned int lanes;
+};
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   const struct panel_desc *desc;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09),
+   _INIT_DCS_CMD(0xC5, 0x09),
+   _INIT_DCS_CMD(0xD8, 0x0A),
+   _INIT_DCS_CMD(0xD9, 0x0A),
+   _INIT_DCS_CMD(0xC2, 0x0B),
+   _INIT_DCS_CMD(0xC3, 0x0B),
+   _INIT_DCS_CMD(0xD6, 0x0C

[PATCH v5 5/8] dt-bindings: display: panel: add boe tv101wum-n53 panel documentation

2019-09-15 Thread Jitao Shi

Add dcumentation for boe,tv101wum-n53, which is mipi dsi video panel
and resolution is 1200x1920.

Signed-off-by: Jitao Shi 
---
 .../display/panel/boe,tv101wum-n53.txt| 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.txt 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.txt
new file mode 100644
index ..145a0b2a80a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.txt
@@ -0,0 +1,34 @@
+BOE Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,tv101wum-n53"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "boe,tv101wum-n53";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

[PATCH v5 8/8] drm/panel: support for auo,b101uan08.3 wuxga dsi video mode panel

2019-09-15 Thread Jitao Shi

Auo,auo,b101uan08.3's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,b101uan08.3 and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 78 +++
 1 file changed, 78 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index eac480ba19cc..e238deb18c86 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -382,6 +382,53 @@ static const struct panel_init_cmd 
auo_kd101n80_45na_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_b101uan08_3_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xC0, 0x48),
+   _INIT_DCS_CMD(0xC1, 0x48),
+   _INIT_DCS_CMD(0xC2, 0x47),
+   _INIT_DCS_CMD(0xC3, 0x47),
+   _INIT_DCS_CMD(0xC4, 0x46),
+   _INIT_DCS_CMD(0xC5, 0x46),
+   _INIT_DCS_CMD(0xC6, 0x45),
+   _INIT_DCS_CMD(0xC7, 0x45),
+   _INIT_DCS_CMD(0xC8, 0x64),
+   _INIT_DCS_CMD(0xC9, 0x64),
+   _INIT_DCS_CMD(0xCA, 0x4F),
+   _INIT_DCS_CMD(0xCB, 0x4F),
+   _INIT_DCS_CMD(0xCC, 0x40),
+   _INIT_DCS_CMD(0xCD, 0x40),
+   _INIT_DCS_CMD(0xCE, 0x66),
+   _INIT_DCS_CMD(0xCF, 0x66),
+   _INIT_DCS_CMD(0xD0, 0x4F),
+   _INIT_DCS_CMD(0xD1, 0x4F),
+   _INIT_DCS_CMD(0xD2, 0x41),
+   _INIT_DCS_CMD(0xD3, 0x41),
+   _INIT_DCS_CMD(0xD4, 0x48),
+   _INIT_DCS_CMD(0xD5, 0x48),
+   _INIT_DCS_CMD(0xD6, 0x47),
+   _INIT_DCS_CMD(0xD7, 0x47),
+   _INIT_DCS_CMD(0xD8, 0x46),
+   _INIT_DCS_CMD(0xD9, 0x46),
+   _INIT_DCS_CMD(0xDA, 0x45),
+   _INIT_DCS_CMD(0xDB, 0x45),
+   _INIT_DCS_CMD(0xDC, 0x64),
+   _INIT_DCS_CMD(0xDD, 0x64),
+   _INIT_DCS_CMD(0xDE, 0x4F),
+   _INIT_DCS_CMD(0xDF, 0x4F),
+   _INIT_DCS_CMD(0xE0, 0x40),
+   _INIT_DCS_CMD(0xE1, 0x40),
+   _INIT_DCS_CMD(0xE2, 0x66),
+   _INIT_DCS_CMD(0xE3, 0x66),
+   _INIT_DCS_CMD(0xE4, 0x4F),
+   _INIT_DCS_CMD(0xE5, 0x4F),
+   _INIT_DCS_CMD(0xE6, 0x41),
+   _INIT_DCS_CMD(0xE7, 0x41),
+   _INIT_DELAY_CMD(150),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -649,6 +696,34 @@ static const struct panel_desc boe_tv101wum_n53_desc = {
.init_cmds = boe_init_cmd,
 };
 
+static const struct drm_display_mode auo_b101uan08_3_default_mode = {
+   .clock = 159667,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 60,
+   .hsync_end = 1200 + 60 + 4,
+   .htotal = 1200 + 60 + 4 + 80,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 34,
+   .vsync_end = 1920 + 34 + 2,
+   .vtotal = 1920 + 34 + 2 + 24,
+   .vrefresh = 60,
+   .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc auo_b101uan08_3_desc = {
+   .modes = &auo_b101uan08_3_default_mode,
+   .bpc = 8,
+   .size = {
+   .width_mm = 135,
+   .height_mm = 216,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = auo_b101uan08_3_init_cmd,
+};
+
 static int boe_panel_get_modes(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
@@ -778,6 +853,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "boe,tv101wum-n53",
  .data = &boe_tv101wum_n53_desc
},
+   { .compatible = "auo,b101uan08.3",
+ .data = &auo_b101uan08_3_desc
+   },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, boe_of_match);
-- 
2.21.0

[PATCH v5 7/8] dt-bindings: display: panel: add AUO auo,b101uan08.3 panel documentation

2019-09-15 Thread Jitao Shi

Add dcumentation for auo,b101uan08.3, which is mipi dsi video panel
and resolution is 1200x1920.

Signed-off-by: Jitao Shi 
---
 .../display/panel/auo,b101uan08.3.txt | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.txt 
b/Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.txt
new file mode 100644
index ..7a31cfe534ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.txt
@@ -0,0 +1,34 @@
+AUO Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,b101uan08.3"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "auo,b101uan08.3";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

[PATCH v5 4/8] drm/panel: support for auo, kd101n80-45na wuxga dsi video mode panel

2019-09-15 Thread Jitao Shi

Auo,kd101n80-45na's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,kd101n80-45na and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |  6 +-
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 86 ---
 2 files changed, 75 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index afcadb3585fb..0e887c978796 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -19,13 +19,13 @@ config DRM_PANEL_ARM_VERSATILE
  in the Versatile family syscon registers.
 
 config DRM_PANEL_BOE_TV101WUM_NL6
-   tristate "BOE TV101WUM 1200x1920 panel"
+   tristate "BOE TV101WUM and AUO KD101N80 45NA 1200x1920 panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
- Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
- DSI Video Mode panel
+ Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
+ 45NA WUXGA PANEL DSI Video Mode panel
 
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index e27529b80d78..f80974778360 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -35,6 +35,7 @@ struct panel_desc {
enum mipi_dsi_pixel_format format;
const struct panel_init_cmd *init_cmds;
unsigned int lanes;
+   bool discharge_on_disable;
 };
 
 struct boe_panel {
@@ -372,6 +373,15 @@ static const struct panel_init_cmd boe_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0x11),
+   _INIT_DELAY_CMD(120),
+   _INIT_DCS_CMD(0x29),
+   _INIT_DELAY_CMD(120),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -449,20 +459,30 @@ static int boe_panel_unprepare(struct drm_panel *panel)
if (!boe->prepared)
return 0;
 
-   ret = boe_panel_off(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
-   return ret;
+   if (boe->desc->discharge_on_disable) {
+   msleep(150);
+   regulator_disable(boe->avee);
+   regulator_disable(boe->avdd);
+   usleep_range(5000, 7000);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(5000, 7000);
+   regulator_disable(boe->pp1800);
+   } else {
+   ret = boe_panel_off(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n",
+   ret);
+   return ret;
+   }
+   msleep(150);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(500, 1000);
+   regulator_disable(boe->avee);
+   regulator_disable(boe->avdd);
+   usleep_range(5000, 7000);
+   regulator_disable(boe->pp1800);
}
 
-   msleep(150);
-   gpiod_set_value(boe->enable_gpio, 0);
-   usleep_range(500, 1000);
-   regulator_disable(boe->avee);
-   regulator_disable(boe->avdd);
-   usleep_range(5000, 7000);
-   regulator_disable(boe->pp1800);
-
boe->prepared = false;
 
return 0;
@@ -492,10 +512,14 @@ static int boe_panel_prepare(struct drm_panel *panel)
if (ret < 0)
goto poweroffavdd;
 
-   msleep(100);
+   usleep_range(5000, 1);
 
gpiod_set_value(boe->enable_gpio, 1);
-   usleep_range(1, 12000);
+   usleep_range(1000, 2000);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(1000, 2000);
+   gpiod_set_value(boe->enable_gpio, 1);
+   usleep_range(6000, 1);
 
ret = boe_panel_init(boe);
if (ret < 0) {
@@ -527,6 +551,8 @@ static int boe_panel_enable(struct drm_panel *panel)
if (boe->enabled)
return 0;
 
+   msleep(70);
+
ret = backlight_enable(boe->backlight);
if (ret) {
dev_err(panel->dev, "Failed to enable backlight %d\n",
@@ -564,6 +590,35 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  MIPI_DSI_MODE_LPM,
.init_cmds = boe_init_cmd,
+   .discharge_on_disable = false,
+};
+
+static const struct drm_display_m

[PATCH v5 2/8] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

2019-09-15 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 709 ++
 3 files changed, 719 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d9d931aa6e26..afcadb3585fb 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -18,6 +18,15 @@ config DRM_PANEL_ARM_VERSATILE
  reference designs. The panel is detected using special registers
  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index fb0cb3aaa9e6..bd26b6ac039e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += 
panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..e27529b80d78
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+struct panel_desc {
+   const struct drm_display_mode *modes;
+   unsigned int bpc;
+
+   /**
+* @width_mm: width of the panel's active display area
+* @height_mm: height of the panel's active display area
+*/
+   struct {
+   unsigned int width_mm;
+   unsigned int height_mm;
+   } size;
+
+   unsigned long mode_flags;
+   enum mipi_dsi_pixel_format format;
+   const struct panel_init_cmd *init_cmds;
+   unsigned int lanes;
+};
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   const struct panel_desc *desc;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09),
+   _INIT_DCS_CMD(0xC5, 0x09),
+   _INIT_DCS_CMD(0xD8, 0x0A),
+   _INIT_DCS_CMD(0xD9, 0x0A),
+   _INIT_DCS_CMD(0xC2, 0x0B),
+   _INIT_DCS_CMD(0xC3, 0x0B),
+   _INIT_DCS_CMD(0xD6, 0x0C

[PATCH v5 1/8] dt-bindings: display: panel: Add BOE tv101wum-n16 panel bindings

2019-09-15 Thread Jitao Shi

Add documentation for boe tv101wum-n16 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/boe,tv101wum-nl6.txt| 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
new file mode 100644
index ..4746ed153507
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
@@ -0,0 +1,34 @@
+Boe Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,tv101wum-nl6"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a gpio spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "boe,tv101wum-nl6";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[PATCH v5 6/8] drm/panel: support for boe, tv101wum-n53 wuxga dsi video mode panel

2019-09-15 Thread Jitao Shi

Boe,tv101wum-n53's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So boe,tv101wum-n53 and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index f80974778360..eac480ba19cc 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -621,6 +621,34 @@ static const struct panel_desc auo_kd101n80_45na_desc = {
.discharge_on_disable = true,
 };
 
+static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
+   .clock = 159260,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 60,
+   .hsync_end = 1200 + 60 + 24,
+   .htotal = 1200 + 60 + 24 + 80,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 14,
+   .vsync_end = 1920 + 14 + 2,
+   .vtotal = 1920 + 14 + 2 + 10,
+   .vrefresh = 60,
+   .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc boe_tv101wum_n53_desc = {
+   .modes = &boe_tv101wum_n53_default_mode,
+   .bpc = 8,
+   .size = {
+   .width_mm = 135,
+   .height_mm = 216,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = boe_init_cmd,
+};
+
 static int boe_panel_get_modes(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
@@ -747,6 +775,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "auo,kd101n80-45na",
  .data = &auo_kd101n80_45na_desc
},
+   { .compatible = "boe,tv101wum-n53",
+ .data = &boe_tv101wum_n53_desc
+   },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, boe_of_match);
-- 
2.21.0

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[PATCH v5 3/8] dt-bindings: display: panel: add auo kd101n80-45na panel bindings

2019-09-15 Thread Jitao Shi

Add documentation for auo kd101n80-45na panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/auo,kd101n80-45na.txt   | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt 
b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
new file mode 100644
index ..994c2a13f942
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
@@ -0,0 +1,34 @@
+AUO Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,kd101n80-45na"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "auo,kd101n80-45na";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[PATCH v5 0/8] add driver for boe, tv101wum-nl6, boe, tv101wum-n53, auo, kd101n80-45na and auo, b101uan08.3 panels

2019-09-15 Thread Jitao Shi

Changes since v4:
 - add auo,b101uan08.3 panel for this driver.
 - add boe,tv101wum-n53 panel for this driver.

Changes since v3:
 - remove check enable_gpio.
 - fine tune the auo,kd101n80-45na panel's power on timing.

Changes since v2:
 - correct the panel size
 - remove blank line in Kconfig
 - move auo,kd101n80-45na panel driver in this series.

Changes since v1:

 - update typo nl6 -> n16.
 - update new panel config and makefile are added in alphabetically order.
 - add the panel mode and panel info in driver data.
 - merge auo,kd101n80-45a and boe,tv101wum-nl6 in one driver

Jitao Shi (8):
  dt-bindings: display: panel: Add BOE tv101wum-n16 panel bindings
  drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel
  dt-bindings: display: panel: add auo kd101n80-45na panel bindings
  drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel
  dt-bindings: display: panel: add boe tv101wum-n53 panel documentation
  drm/panel: support for boe,tv101wum-n53 wuxga dsi video mode panel
  dt-bindings: display: panel: add AUO auo,b101uan08.3 panel
documentation
  drm/panel: support for auo,b101uan08.3 wuxga dsi video mode panel

 .../display/panel/auo,b101uan08.3.txt |  34 +
 .../display/panel/auo,kd101n80-45na.txt   |  34 +
 .../display/panel/boe,tv101wum-n53.txt|  34 +
 .../display/panel/boe,tv101wum-nl6.txt|  34 +
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 876 ++
 7 files changed, 1022 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,b101uan08.3.txt
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-n53.txt
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

-- 
2.21.0

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[PATCH 3/3] drm/panel: panel-innolux: Add support for P097PFZ behind SSD2858

2019-09-12 Thread Jitao Shi

Add driver to setup P097PFZ behing SSD2858 (4 to 8 lanes bridge).

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/panel-innolux-p079zca.c | 103 +-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-innolux-p079zca.c 
b/drivers/gpu/drm/panel/panel-innolux-p079zca.c
index 8db404fb5eeb..a658ccba30a0 100644
--- a/drivers/gpu/drm/panel/panel-innolux-p079zca.c
+++ b/drivers/gpu/drm/panel/panel-innolux-p079zca.c
@@ -138,7 +138,7 @@ static int innolux_panel_prepare(struct drm_panel *panel)
if (!innolux->enable_gpio[i])
break;
 
-   /* p079zca: t2 (20ms), p097pfg: t4 (15ms) */
+   /* p079zca: t2 (20ms), p097pfg: t4 (15ms); ssd2858: 20ms */
usleep_range(2, 21000);
gpiod_set_value_cansleep(innolux->enable_gpio[i], 1);
}
@@ -162,6 +162,18 @@ static int innolux_panel_prepare(struct drm_panel *panel)
goto poweroff;
}
 
+   /*
+* If the command list contains exit sleep mode or set
+* display on, wait the appropriate time (needed for
+* displays behind a bridge).
+*/
+   /* T6: 120ms - 1000ms*/
+   if (cmd->data[0] == MIPI_DCS_EXIT_SLEEP_MODE)
+   msleep(120);
+/* T7: 5ms */
+   if (cmd->data[0] == MIPI_DCS_SET_DISPLAY_ON)
+   usleep_range(5000, 6000);
+
/*
 * Included by random guessing, because without this
 * (or at least, some delay), the panel sometimes
@@ -410,6 +422,92 @@ static const struct panel_desc innolux_p097pfg_panel_desc 
= {
.sleep_mode_delay = 100, /* T15 */
 };
 
+static const char * const innolux_p097pfg_ssd2858_supply_names[] = {
+   "avdd",
+   "avee",
+   "pp1800",
+   "pp3300",
+   "pp1200-bridge",
+   "vddio-bridge",
+};
+
+static const struct drm_display_mode innolux_p097pfg_ssd2858_mode = {
+   .clock = 211660,
+   .hdisplay = 1536,
+   .hsync_start = 1536 + 140,
+   .hsync_end = 1536 + 140 + 10,
+   .htotal = 1536 + 140 + 10 + 10,
+   .vdisplay = 2048,
+   .vsync_start = 2048 + 20,
+   .vsync_end = 2048 + 20 + 2,
+   .vtotal = 2048 + 20 + 2 + 10,
+   .vrefresh = 60,
+};
+
+static const struct panel_init_cmd innolux_p097pfg_ssd2858_init_cmds[] = {
+   /* SSD2858 config */
+   _INIT_CMD(0xff, 0x00),
+   /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2), MULT=0x49
+* 27 Mhz => 985.5 Mhz
+*/
+   _INIT_CMD(0x00, 0x08, 0x01, 0xf4, 0x01, 0x49),
+   /* MTXDIV=1, SYSDIV=3 (=> 4) */
+   _INIT_CMD(0x00, 0x0c, 0x00, 0x00, 0x00, 0x03),
+   /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1
+* MRXEE=1
+*/
+   _INIT_CMD(0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f),
+   _INIT_CMD(0x00, 0x20, 0x15, 0x92, 0x56, 0x7d),
+   _INIT_CMD(0x00, 0x24, 0x00, 0x00, 0x30, 0x00),
+
+   _INIT_CMD(0x10, 0x08, 0x01, 0x20, 0x08, 0x45),
+   _INIT_CMD(0x10, 0x1c, 0x00, 0x00, 0x00, 0x00),
+   _INIT_CMD(0x20, 0x0c, 0x00, 0x00, 0x00, 0x04),
+   /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
+   _INIT_CMD(0x20, 0x10, 0x00, 0x4b, 0x00, 0x49),
+   _INIT_CMD(0x20, 0xa0, 0x00, 0x00, 0x00, 0x00),
+   /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */
+   _INIT_CMD(0x60, 0x08, 0x00, 0xd9, 0x00, 0x08),
+   _INIT_CMD(0x60, 0x14, 0x01, 0x00, 0x01, 0x06),
+   /* DSI0 enable (default: probably not needed) */
+   _INIT_CMD(0x60, 0x80, 0x00, 0x00, 0x00, 0x0f),
+   /* DSI1 enable */
+   _INIT_CMD(0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f),
+
+   /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */
+   _INIT_CMD(0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18),
+   /* VACT= 0x800 (2048), VFP= 0x14, HFP=0x50 */
+   _INIT_CMD(0x60, 0x10, 0x08, 0x00, 0x14, 0x50),
+   /* HACT=0x300 (768) */
+   _INIT_CMD(0x60, 0x84, 0x00, 0x00, 0x03, 0x00),
+   _INIT_CMD(0x60, 0xa4, 0x00, 0x00, 0x03, 0x00),
+
+   /* Take panel out of sleep. */
+   _INIT_CMD(0xff, 0x01),
+   _INIT_CMD(0x11),
+   _INIT_CMD(0x29),
+   _INIT_CMD(0xff, 0x00),
+
+   {},
+};
+
+static const struct panel_desc innolux_p097pfg_ssd2858_panel_desc = {
+   .mode = &innolux_p097pfg_ssd2858_mode,
+   .bpc = 8,
+   .size = {
+   .width = 147,
+   .height = 196,
+   },
+   .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+MIPI_DSI_MODE_LPM,
+   .format = MIPI_DSI_FMT_RGB888,
+   .init_cmds = innolux_p097pfg_ssd2858_init_cmds,
+   .lanes = 4,
+   .suppl

[PATCH 1/3] drm/panel: panel-innolux: Allow 2 reset pins for panel

2019-09-12 Thread Jitao Shi

This is useful when there is a bridge between the SoC and the
panel.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/panel-innolux-p079zca.c | 39 ---
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-innolux-p079zca.c 
b/drivers/gpu/drm/panel/panel-innolux-p079zca.c
index d92d1c98878c..8db404fb5eeb 100644
--- a/drivers/gpu/drm/panel/panel-innolux-p079zca.c
+++ b/drivers/gpu/drm/panel/panel-innolux-p079zca.c
@@ -54,7 +54,7 @@ struct innolux_panel {
 
struct backlight_device *backlight;
struct regulator_bulk_data *supplies;
-   struct gpio_desc *enable_gpio;
+   struct gpio_desc *enable_gpio[2];
 
bool prepared;
bool enabled;
@@ -82,7 +82,7 @@ static int innolux_panel_disable(struct drm_panel *panel)
 static int innolux_panel_unprepare(struct drm_panel *panel)
 {
struct innolux_panel *innolux = to_innolux_panel(panel);
-   int err;
+   int err, i;
 
if (!innolux->prepared)
return 0;
@@ -102,7 +102,8 @@ static int innolux_panel_unprepare(struct drm_panel *panel)
if (innolux->desc->sleep_mode_delay)
msleep(innolux->desc->sleep_mode_delay);
 
-   gpiod_set_value_cansleep(innolux->enable_gpio, 0);
+   for (i = 0; i < ARRAY_SIZE(innolux->enable_gpio); i++)
+   gpiod_set_value_cansleep(innolux->enable_gpio[i], 0);
 
if (innolux->desc->power_down_delay)
msleep(innolux->desc->power_down_delay);
@@ -120,22 +121,27 @@ static int innolux_panel_unprepare(struct drm_panel 
*panel)
 static int innolux_panel_prepare(struct drm_panel *panel)
 {
struct innolux_panel *innolux = to_innolux_panel(panel);
-   int err;
+   int err, i;
 
if (innolux->prepared)
return 0;
 
-   gpiod_set_value_cansleep(innolux->enable_gpio, 0);
+   for (i = 0; i < ARRAY_SIZE(innolux->enable_gpio); i++)
+   gpiod_set_value_cansleep(innolux->enable_gpio[i], 0);
 
err = regulator_bulk_enable(innolux->desc->num_supplies,
innolux->supplies);
if (err < 0)
return err;
 
-   /* p079zca: t2 (20ms), p097pfg: t4 (15ms) */
-   usleep_range(2, 21000);
+   for (i = 0; i < ARRAY_SIZE(innolux->enable_gpio); i++) {
+   if (!innolux->enable_gpio[i])
+   break;
 
-   gpiod_set_value_cansleep(innolux->enable_gpio, 1);
+   /* p079zca: t2 (20ms), p097pfg: t4 (15ms) */
+   usleep_range(2, 21000);
+   gpiod_set_value_cansleep(innolux->enable_gpio[i], 1);
+   }
 
/* p079zca: t4, p097pfg: t5 */
usleep_range(2, 21000);
@@ -195,7 +201,8 @@ static int innolux_panel_prepare(struct drm_panel *panel)
return 0;
 
 poweroff:
-   gpiod_set_value_cansleep(innolux->enable_gpio, 0);
+   for (i = 0; i < ARRAY_SIZE(innolux->enable_gpio); i++)
+   gpiod_set_value_cansleep(innolux->enable_gpio[i], 0);
regulator_bulk_disable(innolux->desc->num_supplies, innolux->supplies);
 
return err;
@@ -475,12 +482,14 @@ static int innolux_panel_add(struct mipi_dsi_device *dsi,
if (err < 0)
return err;
 
-   innolux->enable_gpio = devm_gpiod_get_optional(dev, "enable",
-  GPIOD_OUT_HIGH);
-   if (IS_ERR(innolux->enable_gpio)) {
-   err = PTR_ERR(innolux->enable_gpio);
-   dev_dbg(dev, "failed to get enable gpio: %d\n", err);
-   innolux->enable_gpio = NULL;
+   for (i = 0; i < ARRAY_SIZE(innolux->enable_gpio); i++) {
+   innolux->enable_gpio[i] = devm_gpiod_get_index_optional(dev,
+   "enable", i, GPIOD_OUT_HIGH);
+   if (IS_ERR(innolux->enable_gpio[i])) {
+   err = PTR_ERR(innolux->enable_gpio[i]);
+   dev_err(dev, "failed to get enable gpio: %d\n", err);
+   innolux->enable_gpio[i] = NULL;
+   }
}
 
innolux->backlight = devm_of_find_backlight(dev);
-- 
2.21.0

[PATCH 2/3] dt-bindings: display: Add documentation for innolux, p097pfg_ssd2858 panel

2019-09-12 Thread Jitao Shi

This adds documentation for innolux,p097pfg panel with bridge chip
ssd2858.

Signed-off-by: Jitao Shi 
---
 .../display/panel/innolux,p097pfg_ssd2858.txt | 39 +++
 1 file changed, 39 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/innolux,p097pfg_ssd2858.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/innolux,p097pfg_ssd2858.txt 
b/Documentation/devicetree/bindings/display/panel/innolux,p097pfg_ssd2858.txt
new file mode 100644
index ..4ce55e889ad2
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/display/panel/innolux,p097pfg_ssd2858.txt
@@ -0,0 +1,39 @@
+SSD2858 bridge + Innolux P097PFG 9.7" 1536x2048 TFT LCD panel
+
+Required properties:
+- compatible: should be "innolux,p097pfg_ssd2858"
+- reg: DSI virtual channel of the peripheral
+- avdd-supply: phandle of the regulator that provides panel positive voltage
+- avee-supply: phandle of the regulator that provides panel negative voltage
+- pp1800-supply: phandle of the regulator that provides panel 1.8V IO power
+- pp3300-supply: phandle of the regulator that provides ssd2858 3.3V URAM power
+- pp1200-bridge-supply: phandle of the regulator that provides ssd2858 1.2V 
core power
+- vddio-bridge-supply: phandle of the regulator that provides ssd2858 1.8V IO 
power
+- enable-gpios: panel enable gpio
+
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+
+Example:
+
+   &dsi0 {
+   panel: panel@0 {
+   compatible = "innolux,p097pfg_ssd2858";
+   reg = <0>;
+   enable-gpios = <&pio 45 0 &pio 73 0>;
+   avdd-supply = <...>;
+   avee-supply = <...>;
+   pp1800-supply = <...>;
+   pp3300-supply = <...>;
+   pp1200-bridge-supply = <...>;
+   vddio-bridge-supply = <...>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+
+   };
-- 
2.21.0

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[PATCH 0/3] add panel driver for innolux,p097pfg with ssd2825 bridge

2019-09-12 Thread Jitao Shi

Add driver to support panel innolux,p097pfg with bridge ssd2858.
SSD2858 can spilt dsi 4 lanes to 8 lanes.

Jitao Shi (3):
  drm/panel: panel-innolux: Allow 2 reset pins for panel
  dt-bindings: display: Add documentation for innolux,p097pfg_ssd2858
panel
  drm/panel: panel-innolux: Add support for P097PFZ behind SSD2858

 .../display/panel/innolux,p097pfg_ssd2858.txt |  39 +
 drivers/gpu/drm/panel/panel-innolux-p079zca.c | 140 --
 2 files changed, 164 insertions(+), 15 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/innolux,p097pfg_ssd2858.txt

-- 
2.21.0

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[PATCH v6 7/7] drm: mediatek: adjust dsi and mipi_tx probe sequence

2019-08-11 Thread Jitao Shi

mtk_mipi_tx is the phy of mtk_dsi.
mtk_dsi get the phy(mtk_mipi_tx) in probe().

So,  mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
defer to wait mtk_mipi_tx probe done.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 95fdbd0fbcac..a762fd9111ff 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -630,8 +630,8 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
-   &mtk_dsi_driver,
&mtk_mipi_tx_driver,
+   &mtk_dsi_driver,
 };
 
 static int __init mtk_drm_init(void)
-- 
2.21.0

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[PATCH v6 1/7] drm/mediatek: move mipi_dsi_host_register to probe

2019-08-11 Thread Jitao Shi

DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.

If mipi_dsi_host_register is not in probe, dsi panel will
probe more delay.

So move the mipi_dsi_host_register to probe from bind.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 53 +-
 1 file changed, 31 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b91c4616644a..52b49daeed9f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -520,7 +520,7 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, 
u8 irq_flag, u32 t)
 
 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 {
-   struct device *dev = dsi->dev;
+   struct device *dev = dsi->host.dev;
int ret;
u64 pixel_clock, total_bits;
u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
@@ -1047,12 +1047,6 @@ static int mtk_dsi_bind(struct device *dev, struct 
device *master, void *data)
return ret;
}
 
-   ret = mipi_dsi_host_register(&dsi->host);
-   if (ret < 0) {
-   dev_err(dev, "failed to register DSI host: %d\n", ret);
-   goto err_ddp_comp_unregister;
-   }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1062,8 +1056,6 @@ static int mtk_dsi_bind(struct device *dev, struct device 
*master, void *data)
return 0;
 
 err_unregister:
-   mipi_dsi_host_unregister(&dsi->host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
return ret;
 }
@@ -1075,7 +1067,6 @@ static void mtk_dsi_unbind(struct device *dev, struct 
device *master,
struct mtk_dsi *dsi = dev_get_drvdata(dev);
 
mtk_dsi_destroy_conn_enc(dsi);
-   mipi_dsi_host_unregister(&dsi->host);
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
 }
 
@@ -1099,31 +1090,36 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 
dsi->host.ops = &mtk_dsi_ops;
dsi->host.dev = dev;
+   ret = mipi_dsi_host_register(&dsi->host);
+   if (ret < 0) {
+   dev_err(dev, "failed to register DSI host: %d\n", ret);
+   return ret;
+   }
 
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
  &dsi->panel, &dsi->bridge);
if (ret)
-   return ret;
+   goto err_unregister_host;
 
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1131,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
-   return comp_id;
+   ret = comp_id;
+   goto err_unregister_host;
}
 
ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
&mtk_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
irq_num = platform_get_irq(p

[PATCH v6 6/7] drm/mediatek: change the dsi phytiming calculate method

2019-08-11 Thread Jitao Shi

Change the method of frame rate calc which can get more accurate
frame rate.

data rate = pixel_clock * bit_per_pixel / lanes
Adjust hfp_wc to adapt the additional phy_data

if MIPI_DSI_MODE_VIDEO_BURST
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
else
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;

Note:
//(2: 1 for sync, 1 for phy idle)
data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;

bpp: bit per pixel

Signed-off-by: Jitao Shi 
Tested-by: Ryan Case 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 118 -
 1 file changed, 81 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b3676426aeb5..4d98ea08635a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -136,12 +136,6 @@
 #define DATA_0 (0xff << 16)
 #define DATA_1 (0xff << 24)
 
-#define T_LPX  5
-#define T_HS_PREP  6
-#define T_HS_TRAIL 8
-#define T_HS_EXIT  7
-#define T_HS_ZERO  10
-
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
 
 #define MTK_DSI_HOST_IS_READ(type) \
@@ -150,6 +144,25 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
 
+struct mtk_phy_timing {
+   u32 lpx;
+   u32 da_hs_prepare;
+   u32 da_hs_zero;
+   u32 da_hs_trail;
+
+   u32 ta_go;
+   u32 ta_sure;
+   u32 ta_get;
+   u32 da_hs_exit;
+
+   u32 clk_hs_zero;
+   u32 clk_hs_trail;
+
+   u32 clk_hs_prepare;
+   u32 clk_hs_post;
+   u32 clk_hs_exit;
+};
+
 struct phy;
 
 struct mtk_dsi_driver_data {
@@ -180,6 +193,7 @@ struct mtk_dsi {
enum mipi_dsi_pixel_format format;
unsigned int lanes;
struct videomode vm;
+   struct mtk_phy_timing phy_timing;
int refcount;
bool enabled;
u32 irq_data;
@@ -213,17 +227,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 {
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
+
+   ui = DIV_ROUND_UP(10, dsi->data_rate);
+   cycle_time = div_u64(80ULL, dsi->data_rate);
+
+   timing->lpx = NS_TO_CYCLE(60, cycle_time);
+   timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
+   timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
+   timing->da_hs_trail = NS_TO_CYCLE(90 + 4 * ui, cycle_time);
 
-   ui = 1000 / dsi->data_rate + 0x01;
-   cycle_time = 8000 / dsi->data_rate + 0x01;
+   timing->ta_go = 4 * timing->lpx;
+   timing->ta_sure = 3 * timing->lpx / 2;
+   timing->ta_get = 5 * timing->lpx;
+   timing->da_hs_exit = 2 * timing->lpx;
 
-   timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
-   timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
- T_HS_EXIT << 24;
-   timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
-   timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
+   timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
+   timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
+
+   timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
+   timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
+   timing->clk_hs_exit = 2 * timing->lpx;
+
+   timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
+ timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+   timcon1 = timing->ta_go | timing->ta_sure << 8 |
+ timing->ta_get << 16 | timing->da_hs_exit << 24;
+   timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
+ timing->clk_hs_trail << 24;
+   timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
+ timing->clk_hs_exit << 16;
 
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -410,7 +443,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
-   u32 dsi_tmp_buf_bpp;
+   u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
 
struct videomode *vm = &dsi->vm;
 
@@ -437,7 +471,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *

[PATCH v6 4/7] drm/mediatek: add frame size control

2019-08-11 Thread Jitao Shi

Our new DSI chip has frame size control.
So add the driver data to control for different chips.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 314bfb1c827b..68794edecf96 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -70,6 +70,7 @@
 #define DSI_VBP_NL 0x24
 #define DSI_VFP_NL 0x28
 #define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON   0x38
 #define DSI_HSA_WC 0x50
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58
@@ -154,6 +155,7 @@ struct phy;
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+   bool has_size_ctl;
 };
 
 struct mtk_dsi {
@@ -422,6 +424,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 
+   if (dsi->driver_data->has_size_ctl)
+   writel(vm->vactive << 16 | vm->hactive,
+  dsi->regs + DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-- 
2.21.0

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[PATCH v6 2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701

2019-08-11 Thread Jitao Shi

Config the different CMDQ reg address in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 52b49daeed9f..ac8e80e379f7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,7 +123,6 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
-#define DSI_CMDQ0  0x180
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -148,6 +147,10 @@
 
 struct phy;
 
+struct mtk_dsi_driver_data {
+   const u32 reg_cmdq_off;
+};
+
 struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -174,6 +177,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+   const struct mtk_dsi_driver_data *driver_data;
 };
 
 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -936,6 +940,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+   u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
 
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -955,9 +960,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
}
 
for (i = 0; i < msg->tx_len; i++)
-   writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+   mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
 
-   mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+   mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 }
 
@@ -1101,6 +1108,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
 
+   dsi->driver_data = of_device_get_match_data(dev);
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1194,9 +1203,19 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
 }
 
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+   .reg_cmdq_off = 0x180,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
-   { .compatible = "mediatek,mt2701-dsi" },
-   { .compatible = "mediatek,mt8173-dsi" },
+   { .compatible = "mediatek,mt2701-dsi",
+ .data = &mt2701_dsi_driver_data },
+   { .compatible = "mediatek,mt8173-dsi",
+ .data = &mt8173_dsi_driver_data },
{ },
 };
 
-- 
2.21.0

[PATCH v6 3/7] drm/mediatek: add dsi reg commit disable control

2019-08-11 Thread Jitao Shi

New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.

This fucntion is defualt on. But this driver doesn't use this
function. So add the disable control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ac8e80e379f7..314bfb1c827b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -123,6 +123,10 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
+#define DSI_SHADOW_DEBUG   0x190U
+#define FORCE_COMMIT   BIT(0)
+#define BYPASS_SHADOW  BIT(1)
+
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -149,6 +153,7 @@ struct phy;
 
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+   bool has_shadow_ctl;
 };
 
 struct mtk_dsi {
@@ -586,6 +591,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
 
mtk_dsi_enable(dsi);
+
+   if (dsi->driver_data->has_shadow_ctl)
+   writel(FORCE_COMMIT | BYPASS_SHADOW,
+  dsi->regs + DSI_SHADOW_DEBUG);
+
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
 
-- 
2.21.0

[PATCH v6 5/7] drm/mediatek: add mt8183 dsi driver support

2019-08-11 Thread Jitao Shi

Add mt8183 dsi driver data. Enable size control and
reg commit control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 68794edecf96..b3676426aeb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1227,11 +1227,19 @@ static const struct mtk_dsi_driver_data 
mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
 };
 
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+   .has_shadow_ctl = true,
+   .has_size_ctl = true,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
  .data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
  .data = &mt8173_dsi_driver_data },
+   { .compatible = "mediatek,mt8183-dsi",
+ .data = &mt8183_dsi_driver_data },
{ },
 };
 
-- 
2.21.0

[PATCH v6 0/7] Support dsi for mt8183

2019-08-11 Thread Jitao Shi

Change since v5:
 - fine tune dphy timing.

Change since v4:
 - move mipi_dsi_host_unregiter() to .remove()
 - fine tune add frame size control coding style
 - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL
 - use div_u64 when 80ULL / dsi->data_rate.

Changes since v3
 - add one more 'tab' for bitwise define.
 - add Tested-by: Ryan Case 
and Reviewed-by: CK Hu .
 - remove compare da_hs_zero to da_hs_prepare.

Changes since v2:
 - change the video timing calc method
 - fine the dsi and mipitx init sequence
 - fine tune commit msg

Changes since v1:
 - separate frame size and reg commit control independent patches.
 - fix some return values in probe
 - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" 

Jitao Shi (7):
  drm/mediatek: move mipi_dsi_host_register to probe
  drm/mediatek: fixes CMDQ reg address of mt8173 is different with
mt2701
  drm/mediatek: add dsi reg commit disable control
  drm/mediatek: add frame size control
  drm/mediatek: add mt8183 dsi driver support
  drm/mediatek: change the dsi phytiming calculate method
  drm: mediatek: adjust dsi and mipi_tx probe sequence

 drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +-
 drivers/gpu/drm/mediatek/mtk_dsi.c | 224 ++---
 2 files changed, 161 insertions(+), 65 deletions(-)

-- 
2.21.0

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[PATCH v4 1/4] dt-bindings: display: panel: Add BOE tv101wum-n16 panel bindings

2019-08-11 Thread Jitao Shi

Add documentation for boe tv101wum-n16 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/boe,tv101wum-nl6.txt| 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
new file mode 100644
index ..bd44af636390
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
@@ -0,0 +1,34 @@
+Boe Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,tv101wum-nl6"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "boe,tv101wum-nl6";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[PATCH v4 0/4] Add drivers for auo, kd101n80-45na and boe, tv101wum-nl6 panels

2019-08-11 Thread Jitao Shi

Changes since v3:
 - remove check enable_gpio.
 - fine tune the auo,kd101n80-45na panel's power on timing.

Changes since v2:
 - correct the panel size
 - remove blank line in Kconfig
 - move auo,kd101n80-45na panel driver in this series.

Changes since v1:

 - update typo nl6 -> n16.
 - update new panel config and makefile are added in alphabetically order.
 - add the panel mode and panel info in driver data.
 - merge auo,kd101n80-45a and boe,tv101wum-nl6 in one driver

Jitao Shi (4):
  dt-bindings: display: panel: Add BOE tv101wum-n16 panel bindings
  drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel
  dt-bindings: display: panel: add auo kd101n80-45na panel bindings
  drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel

 .../display/panel/auo,kd101n80-45na.txt   |  34 +
 .../display/panel/boe,tv101wum-nl6.txt|  34 +
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 761 ++
 5 files changed, 839 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

-- 
2.21.0

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[PATCH wn 2/4] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

2019-08-11 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 709 ++
 3 files changed, 719 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index d9d931aa6e26..afcadb3585fb 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -18,6 +18,15 @@ config DRM_PANEL_ARM_VERSATILE
  reference designs. The panel is detected using special registers
  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index fb0cb3aaa9e6..bd26b6ac039e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += 
panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..c0e27f0b2713
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+struct panel_desc {
+   const struct drm_display_mode *modes;
+   unsigned int bpc;
+
+   /**
+* @width_mm: width of the panel's active display area
+* @height_mm: height of the panel's active display area
+*/
+   struct {
+   unsigned int width_mm;
+   unsigned int height_mm;
+   } size;
+
+   unsigned long mode_flags;
+   enum mipi_dsi_pixel_format format;
+   const struct panel_init_cmd *init_cmds;
+   unsigned int lanes;
+};
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   const struct panel_desc *desc;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09),
+   _INIT_DCS_CMD(0xC5, 0x09),
+   _INIT_DCS_CMD(0xD8, 0x0A),
+   _INIT_DCS_CMD(0xD9, 0x0A),
+   _INIT_DCS_CMD(0xC2, 0x0B),
+   _INIT_DCS_CMD(0xC3, 0x0B),
+   _INIT_DCS_CMD(0xD6, 0x0C

[PATCH wn 3/4] dt-bindings: display: panel: add auo kd101n80-45na panel bindings

2019-08-11 Thread Jitao Shi

Add documentation for auo kd101n80-45na panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/auo,kd101n80-45na.txt   | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt 
b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
new file mode 100644
index ..994c2a13f942
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
@@ -0,0 +1,34 @@
+AUO Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,kd101n80-45na"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "auo,kd101n80-45na";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[PATCH wn 4/4] drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel

2019-08-11 Thread Jitao Shi

Auo,kd101n80-45na's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,kd101n80-45na and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |  6 +-
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 76 ---
 2 files changed, 67 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index afcadb3585fb..0e887c978796 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -19,13 +19,13 @@ config DRM_PANEL_ARM_VERSATILE
  in the Versatile family syscon registers.
 
 config DRM_PANEL_BOE_TV101WUM_NL6
-   tristate "BOE TV101WUM 1200x1920 panel"
+   tristate "BOE TV101WUM and AUO KD101N80 45NA 1200x1920 panel"
depends on OF
depends on DRM_MIPI_DSI
depends on BACKLIGHT_CLASS_DEVICE
help
- Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
- DSI Video Mode panel
+ Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
+ 45NA WUXGA PANEL DSI Video Mode panel
 
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index c0e27f0b2713..aef4f8034c5b 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -35,6 +35,7 @@ struct panel_desc {
enum mipi_dsi_pixel_format format;
const struct panel_init_cmd *init_cmds;
unsigned int lanes;
+   bool discharge_on_disable;
 };
 
 struct boe_panel {
@@ -372,6 +373,15 @@ static const struct panel_init_cmd boe_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0x11),
+   _INIT_DELAY_CMD(120),
+   _INIT_DCS_CMD(0x29),
+   _INIT_DELAY_CMD(120),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -449,20 +459,30 @@ static int boe_panel_unprepare(struct drm_panel *panel)
if (!boe->prepared)
return 0;
 
-   ret = boe_panel_off(boe);
-   if (ret < 0) {
-   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
-   return ret;
+   if (boe->desc->discharge_on_disable) {
+   msleep(150);
+   regulator_disable(boe->avee);
+   regulator_disable(boe->avdd);
+   usleep_range(5000, 7000);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(5000, 7000);
+   regulator_disable(boe->pp1800);
+   } else {
+   ret = boe_panel_off(boe);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n",
+   ret);
+   return ret;
+   }
+   msleep(150);
+   gpiod_set_value(boe->enable_gpio, 0);
+   usleep_range(500, 1000);
+   regulator_disable(boe->avee);
+   regulator_disable(boe->avdd);
+   usleep_range(5000, 7000);
+   regulator_disable(boe->pp1800);
}
 
-   msleep(150);
-   gpiod_set_value(boe->enable_gpio, 0);
-   usleep_range(500, 1000);
-   regulator_disable(boe->avee);
-   regulator_disable(boe->avdd);
-   usleep_range(5000, 7000);
-   regulator_disable(boe->pp1800);
-
boe->prepared = false;
 
return 0;
@@ -564,6 +584,35 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
  MIPI_DSI_MODE_LPM,
.init_cmds = boe_init_cmd,
+   .discharge_on_disable = false,
+};
+
+static const struct drm_display_mode auo_default_mode = {
+   .clock = 157000,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 80,
+   .hsync_end = 1200 + 80 + 24,
+   .htotal = 1200 + 80 + 24 + 36,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 16,
+   .vsync_end = 1920 + 16 + 4,
+   .vtotal = 1920 + 16 + 4 + 16,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc auo_kd101n80_45na_desc = {
+   .modes = &auo_default_mode,
+   .bpc = 8,
+   .size = {
+   .width_mm = 135,
+   .height_mm = 216,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = auo_init_cmd,
+   .discharge_on_disable = true,
 };
 
 static int boe_panel_get_modes(struct drm_pane

[PATCH v6 2/3] drm/mediatek: separate mipi_tx to different file

2019-08-07 Thread Jitao Shi

Different IC has different mipi_tx setting of dsi.
This patch separates the mipi_tx hardware relate part for mt8173.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 336 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  48 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++
 4 files changed, 359 insertions(+), 315 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 82ae49c64221..2c8de1f5a5ee 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,6 +12,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_drm_plane.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
+ mtk_mt8173_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 1842dc2caae9..77b9a185e970 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -3,292 +3,39 @@
  * Copyright (c) 2015 MediaTek Inc.
  */
 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define MIPITX_DSI_CON 0x00
-#define RG_DSI_LDOCORE_EN  BIT(0)
-#define RG_DSI_CKG_LDOOUT_EN   BIT(1)
-#define RG_DSI_BCLK_SEL(3 << 2)
-#define RG_DSI_LD_IDX_SEL  (7 << 4)
-#define RG_DSI_PHYCLK_SEL  (2 << 8)
-#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
-#define RG_DSI_LPTX_CLMP_ENBIT(11)
-
-#define MIPITX_DSI_CLOCK_LANE  0x04
-#define MIPITX_DSI_DATA_LANE0  0x08
-#define MIPITX_DSI_DATA_LANE1  0x0c
-#define MIPITX_DSI_DATA_LANE2  0x10
-#define MIPITX_DSI_DATA_LANE3  0x14
-#define RG_DSI_LNTx_LDOOUT_EN  BIT(0)
-#define RG_DSI_LNTx_CKLANE_EN  BIT(1)
-#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2)
-#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3)
-#define RG_DSI_LNTx_LPTX_IMINUSBIT(4)
-#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
-#define RG_DSI_LNTx_LPCD_IMINUSBIT(6)
-#define RG_DSI_LNTx_RT_CODE(0xf << 8)
-
-#define MIPITX_DSI_TOP_CON 0x40
-#define RG_DSI_LNT_INTR_EN BIT(0)
-#define RG_DSI_LNT_HS_BIAS_EN  BIT(1)
-#define RG_DSI_LNT_IMP_CAL_EN  BIT(2)
-#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
-#define RG_DSI_PAD_TIE_LOW_EN  BIT(11)
-#define RG_DSI_DEBUG_INPUT_EN  BIT(12)
-#define RG_DSI_PRESERVE(7 << 13)
-
-#define MIPITX_DSI_BG_CON  0x44
-#define RG_DSI_BG_CORE_EN  BIT(0)
-#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV  (0x3 << 2)
-#define RG_DSI_BG_FAST_CHARGE  BIT(4)
-#define RG_DSI_VOUT_MSK(0x3 << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL(7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL(7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM  (0xf << 24)
-#define RG_DSI_BG_R2_TRIM  (0xf << 28)
-
-#define MIPITX_DSI_PLL_CON00x50
-#define RG_DSI_MPPLL_PLL_ENBIT(0)
-#define RG_DSI_MPPLL_DIV_MSK   (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV(3 << 1)
-#define RG_DSI_MPPLL_TXDIV0(3 << 3)
-#define RG_DSI_MPPLL_TXDIV1(3 << 5)
-#define RG_DSI_MPPLL_POSDIV(7 << 7)
-#define RG_DSI_MPPLL_MONVC_EN  BIT(10)
-#define RG_DSI_MPPLL_MONREF_EN BIT(11)
-#define RG_DSI_MPPLL_VOD_ENBIT(12)
-
-#define MIPITX_DSI_PLL_CON10x54
-#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0)
-#define RG_DSI_MPPLL_SDM_SSC_PH_INIT   BIT(1)
-#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD   (0x << 16)
-
-#define MIPITX_DSI_PLL_CON20x58
-
-#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE  (0xff << 8)
-
-#define MIPITX_DSI_PLL_PWR 0x68
-#define RG_DSI_MPPLL_SDM_PWR_ONBIT(0)
-#define RG_DSI_MPPLL_SDM_ISO_ENBIT(1)
-#define RG_DSI_MPPLL_SDM_PWR_ACK   BIT(8)
-
-#define MIPITX_DSI_SW_CTRL 0x80
-#define SW_CTRL_EN BIT(0)
-
-#define MIPITX_DSI_SW_CTRL_CON00x84
-#define SW_LNTC_LPTX_PRE_OE

[PATCH v6 0/3] Support mipitx for mt8183

2019-08-07 Thread Jitao Shi

Change since v5:
 - remove mipi_tx->ref_clk
 - remove mt8183 pll prepare unprepare

Change since v4:
 - fine tune the mipi_tx->ref_clk and mipi_tx->pll sequence
   1. Prepare mipi_tx->ref_clk
   2. Prepare mipi_tx->pll
   3. Enable mipi_tx->ref_clk
   4. Enable mipi_tx->pll

Changes since v3:
 - turn off PLL before setting PLL parameters.

Changes since v2:
 - update Acked-by: Rob Herring 
 - update mt8183 max bit rate support

Changes since v1:
 - update dt-bindings document for mt8183 mipitx.
 - remove mtk_mipitx_clk_get_ops and assign clk_ops in probe.
 - fix the lincence
 - remove txdiv1 from mtk_mipi_tx_pll_prepare

Jitao Shi (3):
  dt-bindings: display: mediatek: update dsi supported chips
  drm/mediatek: separate mipi_tx to different file
  drm/mediatek: add mipi_tx driver for mt8183

 .../display/mediatek/mediatek,dsi.txt |   4 +-
 drivers/gpu/drm/mediatek/Makefile |   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 338 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  49 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 150 
 6 files changed, 515 insertions(+), 317 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

-- 
2.21.0

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[PATCH v6 1/3] dt-bindings: display: mediatek: update dsi supported chips

2019-08-07 Thread Jitao Shi

Update device tree binding documentation for the dsi for
Mediatek MT8183 SoCs.

Signed-off-by: Jitao Shi 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index fadf327c7cdf..a19a6cc375ed 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
 
 Required properties:
 - compatible: "mediatek,-dsi"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
 
 Required properties:
 - compatible: "mediatek,-mipi-tx"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - clocks: PLL reference clock
 - clock-output-names: name of the output clock line to the DSI encoder
-- 
2.21.0

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[PATCH v6 3/3] drm/mediatek: add mipi_tx driver for mt8183

2019-08-07 Thread Jitao Shi

This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c|   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|   1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 150 ++
 4 files changed, 154 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
  mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 77b9a185e970..e4d34484ecc8 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -175,6 +175,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
  .data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
  .data = &mt8173_mipitx_data },
+   { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 4f905313564f..413f35d86219 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -44,5 +44,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
 
 extern const struct mtk_mipitx_data mt2701_mipitx_data;
 extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
 
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..db13ebdbe262
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi 
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN   BIT(0)
+#define RG_DSI_ANA_CK_SEL  BIT(1)
+#define RG_DSI_PHY_CK_SEL  BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN   BIT(6)
+#define RG_DSI_BG_CORE_EN  BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS   (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN   BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN  BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON  BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN  BIT(1)
+
+#define RG_DSI_PLL_EN  BIT(4)
+#define RG_DSI_PLL_POSDIV  (0x7 << 8)
+
+static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
+{
+   struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+   unsigned int txdiv, txdiv0;
+   u64 pcw;
+
+   dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
+
+   if (mipi_tx->data_rate >= 20) {
+   txdiv = 1;
+   txdiv0 = 0;
+   } else if (mipi_tx->data_rate >= 10) {
+   txdiv = 2;
+   txdiv0 = 1;
+   } else if (mipi_tx->data_rate >= 5) {
+   txdiv = 4;
+   txdiv0 = 2;
+   } else if (mipi_tx->data_rate > 25000) {
+   txdiv = 8;
+   txdiv0 = 3;
+   } else if (mipi_tx->data_rate >= 12500) {
+   txdiv = 16;
+   txdiv0 = 4;
+   } else {
+   return -EINVAL;
+   }
+
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+   mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+   udelay(1);
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+   pcw = div_u64(((u64)mipi_tx->data_rate * txdiv)

[PATCH v5 2/4] drm/mediatek: dpi dual edge support

2019-08-06 Thread Jitao Shi

DPI sample the data both rising and falling edge.
It can reduce half data io pins.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index bacd989cc9aa..743230864ba0 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -72,6 +72,7 @@ struct mtk_dpi {
enum mtk_dpi_out_bit_num bit_num;
enum mtk_dpi_out_channel_swap channel_swap;
int refcount;
+   bool dual_edge;
 };
 
 static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
@@ -345,6 +346,13 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi 
*dpi)
mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
+static void mtk_dpi_enable_dual_edge(struct mtk_dpi *dpi)
+{
+   mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE,
+DDR_EN | DDR_4PHASE);
+   mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, EDGE_SEL, EDGE_SEL);
+}
+
 static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)
 {
@@ -436,7 +444,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
pll_rate = clk_get_rate(dpi->tvd_clk);
 
vm.pixelclock = pll_rate / factor;
-   clk_set_rate(dpi->pixel_clk, vm.pixelclock);
+   clk_set_rate(dpi->pixel_clk,
+vm.pixelclock * (dpi->dual_edge ? 2 : 1));
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
 
dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
@@ -501,6 +510,8 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
mtk_dpi_config_color_format(dpi, dpi->color_format);
mtk_dpi_config_2n_h_fre(dpi);
mtk_dpi_config_disable_edge(dpi);
+   if (dpi->dual_edge)
+   mtk_dpi_enable_dual_edge(dpi);
mtk_dpi_sw_reset(dpi, false);
 
return 0;
@@ -686,6 +697,7 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 
dpi->dev = dev;
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
+   dpi->dual_edge = of_property_read_bool(dev->of_node, "dpi_dual_edge");
 
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dpi->regs = devm_ioremap_resource(dev, mem);
-- 
2.21.0

[PATCH v5 3/4] drm/mediatek: add mt8183 dpi clock factor

2019-08-06 Thread Jitao Shi

The factor depends on the divider of DPI in MT8183, therefore,
we should fix this factor to the right and new one.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 743230864ba0..4f2700cbfdb7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -672,6 +672,16 @@ static unsigned int mt2701_calculate_factor(int clock)
return 1;
 }
 
+static unsigned int mt8183_calculate_factor(int clock)
+{
+   if (clock <= 27000)
+   return 8;
+   else if (clock <= 167000)
+   return 4;
+   else
+   return 2;
+}
+
 static const struct mtk_dpi_conf mt8173_conf = {
.cal_factor = mt8173_calculate_factor,
.reg_h_fre_con = 0xe0,
@@ -683,6 +693,11 @@ static const struct mtk_dpi_conf mt2701_conf = {
.edge_sel_en = true,
 };
 
+static const struct mtk_dpi_conf mt8183_conf = {
+   .cal_factor = mt8183_calculate_factor,
+   .reg_h_fre_con = 0xe0,
+};
+
 static int mtk_dpi_probe(struct platform_device *pdev)
 {
struct device *dev = &pdev->dev;
@@ -779,6 +794,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
{ .compatible = "mediatek,mt8173-dpi",
  .data = &mt8173_conf,
},
+   { .compatible = "mediatek,mt8183-dpi",
+ .data = &mt8183_conf,
+   },
{ },
 };
 
-- 
2.21.0

[PATCH v5 0/4] add mt8183 dpi driver

2019-08-06 Thread Jitao Shi

Changes since v4:
 - move pin mode control and dual edge control to deveice tree.
 - update dt-bindings document for pin mode swap and dual edge control.

Changes since v3:
 - add dpi pin mode control when dpi on or off.
 - update dpi dual edge comment.

Changes since v2:
 - update dt-bindings document for mt8183 dpi.
 - separate dual edge modfication as independent patch.

Jitao Shi (4):
  dt-bindings: display: mediatek: update dpi  supported chips
  drm/mediatek: dpi dual edge support
  drm/mediatek: add mt8183 dpi clock factor
  drm/mediatek: control dpi pins dpi or gpio mode in on or off

 .../display/mediatek/mediatek,dpi.txt | 11 +++
 drivers/gpu/drm/mediatek/mtk_dpi.c| 71 ++-
 2 files changed, 80 insertions(+), 2 deletions(-)

-- 
2.21.0

[PATCH v5 1/4] dt-bindings: display: mediatek: update dpi supported chips

2019-08-06 Thread Jitao Shi

Add decriptions about supported chips, including MT2701 & MT8173 &
mt8183

Signed-off-by: Jitao Shi 
---
 .../bindings/display/mediatek/mediatek,dpi.txt| 11 +++
 1 file changed, 11 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
index b6a7e7397b8b..cd6a1469c8b7 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt
@@ -7,6 +7,7 @@ output bus.
 
 Required properties:
 - compatible: "mediatek,-dpi"
+  the supported chips are mt2701 , mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks
@@ -16,6 +17,11 @@ Required properties:
   Documentation/devicetree/bindings/graph.txt. This port should be connected
   to the input port of an attached HDMI or LVDS encoder chip.
 
+Optional properties:
+- dpi_pin_mode_swap: Swap the pin mode between dpi mode and gpio mode.
+- pinctrl-names: Contain "gpiomode" and "dpimode".
+- dpi_dual_edge: Control the RGB 24bit data on 12 pins or 24 pins.
+
 Example:
 
 dpi0: dpi@1401d000 {
@@ -26,6 +32,11 @@ dpi0: dpi@1401d000 {
 <&mmsys CLK_MM_DPI_ENGINE>,
 <&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
+   dpi_dual_edge;
+   dpi_pin_mode_swap;
+   pinctrl-names = "gpiomode", "dpimode";
+   pinctrl-0 = <&dpi_pin_gpio>;
+   pinctrl-1 = <&dpi_pin_func>;
 
port {
dpi0_out: endpoint {
-- 
2.21.0

[PATCH v5 4/4] drm/mediatek: control dpi pins dpi or gpio mode in on or off

2019-08-06 Thread Jitao Shi

Pull dpi pins low when dpi has nothing to display. Aovid leakage
current from some dpi pins (Hsync Vsync DE ... ).

Some chips have dpi pins, but there are some chip don't have pins.
So this function is controlled by device tree.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 39 +-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c 
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 4f2700cbfdb7..83fb0d753f72 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -9,10 +9,12 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
+#include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -71,8 +73,12 @@ struct mtk_dpi {
enum mtk_dpi_out_yc_map yc_map;
enum mtk_dpi_out_bit_num bit_num;
enum mtk_dpi_out_channel_swap channel_swap;
+   struct pinctrl *pinctrl;
+   struct pinctrl_state *pins_gpio;
+   struct pinctrl_state *pins_dpi;
int refcount;
bool dual_edge;
+   bool dpi_pin_ctrl;
 };
 
 static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
@@ -384,6 +390,9 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
if (--dpi->refcount != 0)
return;
 
+   if (dpi->dpi_pin_ctrl)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
+
mtk_dpi_disable(dpi);
clk_disable_unprepare(dpi->pixel_clk);
clk_disable_unprepare(dpi->engine_clk);
@@ -408,6 +417,9 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
goto err_pixel;
}
 
+   if (dpi->dpi_pin_ctrl)
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
+
mtk_dpi_enable(dpi);
return 0;
 
@@ -713,6 +725,31 @@ static int mtk_dpi_probe(struct platform_device *pdev)
dpi->dev = dev;
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
dpi->dual_edge = of_property_read_bool(dev->of_node, "dpi_dual_edge");
+   dpi->dpi_pin_ctrl = of_property_read_bool(dev->of_node,
+ "dpi_pin_mode_swap");
+
+   if (dpi->dpi_pin_ctrl) {
+   dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
+   if (IS_ERR(dpi->pinctrl)) {
+   dev_err(&pdev->dev, "Cannot find pinctrl!\n");
+   return PTR_ERR(dpi->pinctrl);
+   }
+
+   dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl,
+ "gpiomode");
+   if (IS_ERR(dpi->pins_gpio)) {
+   dev_err(&pdev->dev, "Cannot find pinctrl gpiomode!\n");
+   return PTR_ERR(dpi->pins_gpio);
+   }
+
+   pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
+
+   dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "dpimode");
+   if (IS_ERR(dpi->pins_dpi)) {
+   dev_err(&pdev->dev, "Cannot find pinctrl dpimode!\n");
+   return PTR_ERR(dpi->pins_dpi);
+   }
+   }
 
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
dpi->regs = devm_ioremap_resource(dev, mem);
-- 
2.21.0

[v5 7/7] drm: mediatek: adjust dsi and mipi_tx probe sequence

2019-06-27 Thread Jitao Shi

mtk_mipi_tx is the phy of mtk_dsi.
mtk_dsi get the phy(mtk_mipi_tx) in probe().

So,  mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
defer to wait mtk_mipi_tx probe done.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 57ce4708ef1b..fc809a61fab9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -640,8 +640,8 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
-   &mtk_dsi_driver,
&mtk_mipi_tx_driver,
+   &mtk_dsi_driver,
 };
 
 static int __init mtk_drm_init(void)
-- 
2.21.0

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[v5 5/7] drm/mediatek: add mt8183 dsi driver support

2019-06-27 Thread Jitao Shi

Add mt8183 dsi driver data. Enable size control and
reg commit control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 45e331055842..1621e8cdacc2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1225,11 +1225,19 @@ static const struct mtk_dsi_driver_data 
mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
 };
 
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+   .has_shadow_ctl = true,
+   .has_size_ctl = true,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
  .data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
  .data = &mt8173_dsi_driver_data },
+   { .compatible = "mediatek,mt8183-dsi",
+ .data = &mt8183_dsi_driver_data },
{ },
 };
 
-- 
2.21.0

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[v5 2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701

2019-06-27 Thread Jitao Shi

Config the different CMDQ reg address in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 595b3b047c7b..bd37d823c762 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -131,7 +131,6 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
-#define DSI_CMDQ0  0x180
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -156,6 +155,10 @@
 
 struct phy;
 
+struct mtk_dsi_driver_data {
+   const u32 reg_cmdq_off;
+};
+
 struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -182,6 +185,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+   const struct mtk_dsi_driver_data *driver_data;
 };
 
 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -934,6 +938,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+   u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
 
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -953,9 +958,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
}
 
for (i = 0; i < msg->tx_len; i++)
-   writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+   mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
 
-   mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+   mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 }
 
@@ -1099,6 +1106,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
 
+   dsi->driver_data = of_device_get_match_data(dev);
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1192,9 +1201,19 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
 }
 
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+   .reg_cmdq_off = 0x180,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
-   { .compatible = "mediatek,mt2701-dsi" },
-   { .compatible = "mediatek,mt8173-dsi" },
+   { .compatible = "mediatek,mt2701-dsi",
+ .data = &mt2701_dsi_driver_data },
+   { .compatible = "mediatek,mt8173-dsi",
+ .data = &mt8173_dsi_driver_data },
{ },
 };
 
-- 
2.21.0

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[v5 6/7] drm/mediatek: change the dsi phytiming calculate method

2019-06-27 Thread Jitao Shi

Change the method of frame rate calc which can get more accurate
frame rate.

data rate = pixel_clock * bit_per_pixel / lanes
Adjust hfp_wc to adapt the additional phy_data

if MIPI_DSI_MODE_VIDEO_BURST
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
else
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;

Note:
//(2: 1 for sync, 1 for phy idle)
data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;

bpp: bit per pixel

Signed-off-by: Jitao Shi 
Tested-by: Ryan Case 
Reviewed-by: CK Hu phy_timing;
+
+   ui = 10 / dsi->data_rate;
+   cycle_time = div_u64(80ULL, dsi->data_rate);
+
+   timing->lpx = NS_TO_CYCLE(60, cycle_time);
+   timing->da_hs_prepare = NS_TO_CYCLE(40 + 5 * ui, cycle_time);
+   timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
+   timing->da_hs_trail = NS_TO_CYCLE(80 + 4 * ui, cycle_time);
 
-   ui = 1000 / dsi->data_rate + 0x01;
-   cycle_time = 8000 / dsi->data_rate + 0x01;
+   timing->ta_go = 4 * timing->lpx;
+   timing->ta_sure = 3 * timing->lpx / 2;
+   timing->ta_get = 5 * timing->lpx;
+   timing->da_hs_exit = 2 * timing->lpx;
 
-   timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
-   timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
- T_HS_EXIT << 24;
-   timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
-   timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
+   timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
+   timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
+
+   timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
+   timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
+   timing->clk_hs_exit = 2 * timing->lpx;
+
+   timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
+ timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+   timcon1 = timing->ta_go | timing->ta_sure << 8 |
+ timing->ta_get << 16 | timing->da_hs_exit << 24;
+   timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
+ timing->clk_hs_trail << 24;
+   timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
+ timing->clk_hs_exit << 16;
 
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -418,7 +451,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
-   u32 dsi_tmp_buf_bpp;
+   u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
 
struct videomode *vm = &dsi->vm;
 
@@ -445,7 +479,34 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
dsi_tmp_buf_bpp - 10);
 
-   horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
+   data_phy_cycles = timing->lpx + timing->da_hs_prepare +
+ timing->da_hs_zero + timing->da_hs_exit + 2;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+   if (vm->hfront_porch * dsi_tmp_buf_bpp >
+   data_phy_cycles * dsi->lanes + 18) {
+   horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp -
+data_phy_cycles *
+dsi->lanes - 18;
+   } else {
+   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
+   horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp;
+   }
+   } else {
+   if (vm->hfront_porch * dsi_tmp_buf_bpp >
+   data_phy_cycles * dsi->lanes + 12) {
+   horizontal_frontporch_byte = vm->hfront_porch *
+dsi_tmp_buf_bpp -
+data_phy_cycles *
+dsi->lanes - 12;
+   } else {
+   DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
+   horizontal_frontporch_byte = vm->hfront_porch *
+

[v5 3/7] drm/mediatek: add dsi reg commit disable control

2019-06-27 Thread Jitao Shi

New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.

This fucntion is defualt on. But this driver doesn't use this
function. So add the disable control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index bd37d823c762..6b6550926db6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -131,6 +131,10 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
+#define DSI_SHADOW_DEBUG   0x190U
+#define FORCE_COMMIT   BIT(0)
+#define BYPASS_SHADOW  BIT(1)
+
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -157,6 +161,7 @@ struct phy;
 
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+   bool has_shadow_ctl;
 };
 
 struct mtk_dsi {
@@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
 
mtk_dsi_enable(dsi);
+
+   if (dsi->driver_data->has_shadow_ctl)
+   writel(FORCE_COMMIT | BYPASS_SHADOW,
+  dsi->regs + DSI_SHADOW_DEBUG);
+
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
 
-- 
2.21.0

[v5 1/7] drm/mediatek: move mipi_dsi_host_register to probe

2019-06-27 Thread Jitao Shi

DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.

If mipi_dsi_host_register is not in probe, dsi panel will
probe more delay.

So move the mipi_dsi_host_register to probe from bind.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 53 +-
 1 file changed, 31 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b00eb2d2e086..595b3b047c7b 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -528,7 +528,7 @@ static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, 
u8 irq_flag, u32 t)
 
 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 {
-   struct device *dev = dsi->dev;
+   struct device *dev = dsi->->host.dev;
int ret;
u64 pixel_clock, total_bits;
u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
@@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct 
device *master, void *data)
return ret;
}
 
-   ret = mipi_dsi_host_register(&dsi->host);
-   if (ret < 0) {
-   dev_err(dev, "failed to register DSI host: %d\n", ret);
-   goto err_ddp_comp_unregister;
-   }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct device 
*master, void *data)
return 0;
 
 err_unregister:
-   mipi_dsi_host_unregister(&dsi->host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
return ret;
 }
@@ -1073,7 +1065,6 @@ static void mtk_dsi_unbind(struct device *dev, struct 
device *master,
struct mtk_dsi *dsi = dev_get_drvdata(dev);
 
mtk_dsi_destroy_conn_enc(dsi);
-   mipi_dsi_host_unregister(&dsi->host);
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
 }
 
@@ -1097,31 +1088,36 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 
dsi->host.ops = &mtk_dsi_ops;
dsi->host.dev = dev;
+   ret = mipi_dsi_host_register(&dsi->host);
+   if (ret < 0) {
+   dev_err(dev, "failed to register DSI host: %d\n", ret);
+   return ret;
+   }
 
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
  &dsi->panel, &dsi->bridge);
if (ret)
-   return ret;
+   goto err_unregister_host;
 
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1129,33 +1125,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
-   return comp_id;
+   ret = comp_id;
+   goto err_unregister_host;
}
 
ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
&mtk_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
irq_num = platform_get_ir

[v5 4/7] drm/mediatek: add frame size control

2019-06-27 Thread Jitao Shi

Our new DSI chip has frame size control.
So add the driver data to control for different chips.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 6b6550926db6..45e331055842 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -78,6 +78,7 @@
 #define DSI_VBP_NL 0x24
 #define DSI_VFP_NL 0x28
 #define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON   0x38
 #define DSI_HSA_WC 0x50
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58
@@ -162,6 +163,7 @@ struct phy;
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+   bool has_size_ctl;
 };
 
 struct mtk_dsi {
@@ -430,6 +432,10 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 
+   if (dsi->driver_data->has_size_ctl)
+   writel(vm->vactive << 16 | vm->hactive,
+  dsi->regs + DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-- 
2.21.0

[v5 0/7] Support dsi for mt8183

2019-06-27 Thread Jitao Shi

Change since v4:
 - move mipi_dsi_host_unregiter() to .remove()
 - fine tune add frame size control coding style
 - change the data type of data_rate as u32, and add DIV_ROUND_UP_ULL
 - use div_u64 when 80ULL / dsi->data_rate.

Changes since v3
 - add one more 'tab' for bitwise define.
 - add Tested-by: Ryan Case 
and Reviewed-by: CK Hu .
 - remove compare da_hs_zero to da_hs_prepare.

Changes since v2:
 - change the video timing calc method
 - fine the dsi and mipitx init sequence
 - fine tune commit msg

Changes since v1:
 - separate frame size and reg commit control independent patches.
 - fix some return values in probe
 - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" 

Jitao Shi (7):
  drm/mediatek: move mipi_dsi_host_register to probe
  drm/mediatek: fixes CMDQ reg address of mt8173 is different with
mt2701
  drm/mediatek: add dsi reg commit disable control
  drm/mediatek: add frame size control
  drm/mediatek: add mt8183 dsi driver support
  drm/mediatek: change the dsi phytiming calculate method
  drm: mediatek: adjust dsi and mipi_tx probe sequence

 drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +-
 drivers/gpu/drm/mediatek/mtk_dsi.c | 223 ++---
 2 files changed, 160 insertions(+), 65 deletions(-)

-- 
2.21.0

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[v5 2/3] drm/mediatek: separate mipi_tx to different file

2019-06-26 Thread Jitao Shi

Different IC has different mipi_tx setting of dsi.
This patch separates the mipi_tx hardware relate part for mt8173.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 343 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  49 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++
 4 files changed, 363 insertions(+), 319 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 82ae49c64221..2c8de1f5a5ee 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,6 +12,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_drm_plane.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
+ mtk_mt8173_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 90e913108950..cdc68b88cefd 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -11,292 +11,39 @@
  * GNU General Public License for more details.
  */
 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define MIPITX_DSI_CON 0x00
-#define RG_DSI_LDOCORE_EN  BIT(0)
-#define RG_DSI_CKG_LDOOUT_EN   BIT(1)
-#define RG_DSI_BCLK_SEL(3 << 2)
-#define RG_DSI_LD_IDX_SEL  (7 << 4)
-#define RG_DSI_PHYCLK_SEL  (2 << 8)
-#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
-#define RG_DSI_LPTX_CLMP_ENBIT(11)
-
-#define MIPITX_DSI_CLOCK_LANE  0x04
-#define MIPITX_DSI_DATA_LANE0  0x08
-#define MIPITX_DSI_DATA_LANE1  0x0c
-#define MIPITX_DSI_DATA_LANE2  0x10
-#define MIPITX_DSI_DATA_LANE3  0x14
-#define RG_DSI_LNTx_LDOOUT_EN  BIT(0)
-#define RG_DSI_LNTx_CKLANE_EN  BIT(1)
-#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2)
-#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3)
-#define RG_DSI_LNTx_LPTX_IMINUSBIT(4)
-#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
-#define RG_DSI_LNTx_LPCD_IMINUSBIT(6)
-#define RG_DSI_LNTx_RT_CODE(0xf << 8)
-
-#define MIPITX_DSI_TOP_CON 0x40
-#define RG_DSI_LNT_INTR_EN BIT(0)
-#define RG_DSI_LNT_HS_BIAS_EN  BIT(1)
-#define RG_DSI_LNT_IMP_CAL_EN  BIT(2)
-#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
-#define RG_DSI_PAD_TIE_LOW_EN  BIT(11)
-#define RG_DSI_DEBUG_INPUT_EN  BIT(12)
-#define RG_DSI_PRESERVE(7 << 13)
-
-#define MIPITX_DSI_BG_CON  0x44
-#define RG_DSI_BG_CORE_EN  BIT(0)
-#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV  (0x3 << 2)
-#define RG_DSI_BG_FAST_CHARGE  BIT(4)
-#define RG_DSI_VOUT_MSK(0x3 << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL(7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL(7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM  (0xf << 24)
-#define RG_DSI_BG_R2_TRIM  (0xf << 28)
-
-#define MIPITX_DSI_PLL_CON00x50
-#define RG_DSI_MPPLL_PLL_ENBIT(0)
-#define RG_DSI_MPPLL_DIV_MSK   (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV(3 << 1)
-#define RG_DSI_MPPLL_TXDIV0(3 << 3)
-#define RG_DSI_MPPLL_TXDIV1(3 << 5)
-#define RG_DSI_MPPLL_POSDIV(7 << 7)
-#define RG_DSI_MPPLL_MONVC_EN  BIT(10)
-#define RG_DSI_MPPLL_MONREF_EN BIT(11)
-#define RG_DSI_MPPLL_VOD_ENBIT(12)
-
-#define MIPITX_DSI_PLL_CON10x54
-#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0)
-#define RG_DSI_MPPLL_SDM_SSC_PH_INIT   BIT(1)
-#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD   (0x << 16)
-
-#define MIPITX_DSI_PLL_CON20x58
-
-#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE  (0xff << 8)
-
-#define MIPITX_DSI_PLL_PWR 0x68
-#define RG_DSI_MPPLL_SDM_PWR_ONBIT(0)
-#define RG_DSI_MPPLL_SDM_ISO_ENBIT(1)
-#define RG_DSI_MPPLL_SDM_PWR_ACK   BIT(8)
-
-#define MIPITX_DSI_SW_CTRL 0x80
-#define SW_CTRL_EN BIT(0)
-
-#define MIPITX_DSI_SW_CTRL_CON00x84
-#define SW_L

[v5 3/3] drm/mediatek: add mipi_tx driver for mt8183

2019-06-26 Thread Jitao Shi

This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c|   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|   1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 181 ++
 4 files changed, 185 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
  mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index cdc68b88cefd..ab0fbfba5572 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -182,6 +182,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
  .data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
  .data = &mt8173_mipitx_data },
+   { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 660726924992..3fd24563952e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -45,5 +45,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
 
 extern const struct mtk_mipitx_data mt2701_mipitx_data;
 extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
 
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..7758bc9c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi 
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN   BIT(0)
+#define RG_DSI_ANA_CK_SEL  BIT(1)
+#define RG_DSI_PHY_CK_SEL  BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN   BIT(6)
+#define RG_DSI_BG_CORE_EN  BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS   (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN   BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN  BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON  BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN  BIT(1)
+
+#define RG_DSI_PLL_EN  BIT(4)
+#define RG_DSI_PLL_POSDIV  (0x7 << 8)
+
+static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
+{
+   struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+   int ret = 0;
+
+   ret = clk_prepare(mipi_tx->ref_clk);
+   if (ret < 0)
+   dev_err(mipi_tx->dev,
+   "can't prepare mipi_tx ref_clk %d\n", ret);
+
+   return ret;
+}
+
+static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
+{
+   struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+   unsigned int txdiv, txdiv0;
+   u64 pcw;
+   int ret;
+
+   dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
+
+   if (mipi_tx->data_rate >= 20) {
+   txdiv = 1;
+   txdiv0 = 0;
+   } else if (mipi_tx->data_rate >= 10) {
+   txdiv = 2;
+   txdiv0 = 1;
+   } else if (mipi_tx->data_rate >= 5) {
+   txdiv = 4;
+   txdiv0 = 2;
+   } else if (mipi_tx->data_rate > 25000) {
+   txdiv = 8;
+   txdiv0 = 3;
+   } else if (mipi_tx->data_rate >= 12500) {
+   txdiv = 16;
+   txdiv0 = 4;
+   } else {
+   return

[v5 1/3] dt-bindings: display: mediatek: update dsi supported chips

2019-06-26 Thread Jitao Shi

Update device tree binding documentation for the dsi for
Mediatek MT8183 SoCs.

Signed-off-by: Jitao Shi 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index fadf327c7cdf..a19a6cc375ed 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
 
 Required properties:
 - compatible: "mediatek,-dsi"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - interrupts: The interrupt signal from the function block.
 - clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
 
 Required properties:
 - compatible: "mediatek,-mipi-tx"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - clocks: PLL reference clock
 - clock-output-names: name of the output clock line to the DSI encoder
-- 
2.21.0

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[v5 0/3] Support mipitx for mt8183

2019-06-26 Thread Jitao Shi

Change since v4:
 - fine tune the mipi_tx->ref_clk and mipi_tx->pll sequence
   1. Prepare mipi_tx->ref_clk
   2. Prepare mipi_tx->pll
   3. Enable mipi_tx->ref_clk
   4. Enable mipi_tx->pll

Changes since v3:
 - turn off PLL before setting PLL parameters.

Changes since v2:
 - update Acked-by: Rob Herring 
 - update mt8183 max bit rate support

Changes since v1:
 - update dt-bindings document for mt8183 mipitx.
 - remove mtk_mipitx_clk_get_ops and assign clk_ops in probe.
 - fix the lincence
 - remove txdiv1 from mtk_mipi_tx_pll_prepare

Jitao Shi (3):
  dt-bindings: display: mediatek: update dsi supported chips
  drm/mediatek: separate mipi_tx to different file
  drm/mediatek: add mipi_tx driver for mt8183

 .../display/mediatek/mediatek,dsi.txt |   4 +-
 drivers/gpu/drm/mediatek/Makefile |   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 345 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  50 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 +++
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 181 +
 6 files changed, 550 insertions(+), 321 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

-- 
2.21.0

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[v3 4/4] drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel

2019-06-25 Thread Jitao Shi

Auo,kd101n80-45na's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,kd101n80-45na and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 39 +++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index 30d1f53dcbaf..6ff49f900cd2 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -372,6 +372,15 @@ static const struct panel_init_cmd boe_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0x11),
+   _INIT_DELAY_CMD(120),
+   _INIT_DCS_CMD(0x29),
+   _INIT_DELAY_CMD(120),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -571,6 +580,33 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
.init_cmds = boe_init_cmd,
 };
 
+static const struct drm_display_mode auo_default_mode = {
+   .clock = 157000,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 80,
+   .hsync_end = 1200 + 80 + 24,
+   .htotal = 1200 + 80 + 24 + 36,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 16,
+   .vsync_end = 1920 + 16 + 4,
+   .vtotal = 1920 + 16 + 4 + 16,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc auo_kd101n80_45na_desc = {
+   .modes = &auo_default_mode,
+   .bpc = 8,
+   .size = {
+   .width = 135,
+   .height = 216,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = auo_init_cmd,
+};
+
 static int boe_panel_get_modes(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
@@ -694,6 +730,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "boe,tv101wum-nl6",
  .data = &boe_tv101wum_nl6_desc
},
+   { .compatible = "auo,kd101n80-45na",
+ .data = &auo_kd101n80_45na_desc
+   },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, boe_of_match);
-- 
2.21.0

[v3 2/4] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

2019-06-25 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 714 ++
 3 files changed, 724 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e36dbb4df867..706f6ff2b4fa 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
  reference designs. The panel is detected using special registers
  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 78e3dc376bdd..8d009223c44e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += 
panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..30d1f53dcbaf
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,714 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+struct panel_desc {
+   const struct drm_display_mode *modes;
+   unsigned int bpc;
+
+   /**
+* @width: width (in millimeters) of the panel's active display area
+* @height: height (in millimeters) of the panel's active display area
+*/
+   struct {
+   unsigned int width;
+   unsigned int height;
+   } size;
+
+   unsigned long mode_flags;
+   enum mipi_dsi_pixel_format format;
+   const struct panel_init_cmd *init_cmds;
+   unsigned int lanes;
+};
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   const struct panel_desc *desc;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09),
+   _INIT_DCS_CMD(0xC5, 0x09),
+   _INIT_DCS_CMD(0xD8, 0x0A),
+   _INIT_DCS_CMD(0xD9, 0x0A),
+   _INIT_DCS_CMD(0xC2, 0x0B),
+   _INIT_DCS_CMD(0xC3, 0x0B),
+   _INIT_DCS_CMD(0xD6, 0x0C

[v3 1/4] dt-bindngs: display: panel: Add BOE tv101wum-n16 panel bindings

2019-06-25 Thread Jitao Shi

Add documentation for boe tv101wum-n16 panel.

Signed-off-by: Jitao Shi 
---
 .../display/panel/boe,tv101wum-nl6.txt| 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
new file mode 100644
index ..bd44af636390
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
@@ -0,0 +1,34 @@
+Boe Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,tv101wum-nl6"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "boe,tv101wum-nl6";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[v3 0/4] Add drivers for auo, kd101n80-45na and boe, tv101wum-nl6 panels

2019-06-25 Thread Jitao Shi

Changes since v2:
 - correct the panel size
 - remove blank line in Kconfig
 - move auo,kd101n80-45na panel driver in this series.

Changes since v1:

 - update typo nl6 -> n16.
 - update new panel config and makefile are added in alphabetically order.
 - add the panel mode and panel info in driver data.
 - merge auo,kd101n80-45a and boe,tv101wum-nl6 in one driver

Jitao Shi (4):
  dt-bindngs: display: panel: Add BOE tv101wum-n16 panel bindings
  drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel
  dt-bindings: display: panel: add auo kd101n80-45na panel bindings
  drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel

 .../display/panel/auo,kd101n80-45na.txt   |  34 +
 .../display/panel/boe,tv101wum-nl6.txt|  34 +
 drivers/gpu/drm/panel/Kconfig |   9 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 753 ++
 5 files changed, 831 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

-- 
2.21.0

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[v3 3/4] dt-bindings: display: panel: add auo kd101n80-45na panel bindings

2019-06-25 Thread Jitao Shi

Add documentation for auo kd101n80-45na panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/auo,kd101n80-45na.txt   | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt 
b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
new file mode 100644
index ..994c2a13f942
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
@@ -0,0 +1,34 @@
+AUO Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,kd101n80-45na"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "auo,kd101n80-45na";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[v2 2/2] drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel

2019-06-24 Thread Jitao Shi

Auo,kd101n80-45na's connector is same as boe,tv101wum-nl6.
The most codes can be reuse.
So auo,kd101n80-45na and boe,tv101wum-nl6 use one driver file.
Add the different parts in driver data.

Signed-off-by: Jitao Shi 
---
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 40 +++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
index 6e06c8506623..d1ee43cfcbe2 100644
--- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -372,6 +372,15 @@ static const struct panel_init_cmd boe_init_cmd[] = {
{},
 };
 
+static const struct panel_init_cmd auo_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0x11),
+   _INIT_DELAY_CMD(120),
+   _INIT_DCS_CMD(0x29),
+   _INIT_DELAY_CMD(120),
+   {},
+};
+
 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
 {
return container_of(panel, struct boe_panel, base);
@@ -572,6 +581,34 @@ static const struct panel_desc boe_tv101wum_nl6_desc = {
.init_cmds = boe_init_cmd,
 };
 
+static const struct drm_display_mode auo_default_mode = {
+   .clock = 157000,
+   .hdisplay = 1200,
+   .hsync_start = 1200 + 80,
+   .hsync_end = 1200 + 80 + 24,
+   .htotal = 1200 + 80 + 24 + 36,
+   .vdisplay = 1920,
+   .vsync_start = 1920 + 16,
+   .vsync_end = 1920 + 16 + 4,
+   .vtotal = 1920 + 16 + 4 + 16,
+   .vrefresh = 60,
+   .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+};
+
+static const struct panel_desc auo_kd101n80_45na_desc = {
+   .modes = &auo_default_mode,
+   .bpc = 8,
+   .size = {
+   .width = 216,
+   .height = 135,
+   },
+   .lanes = 4,
+   .format = MIPI_DSI_FMT_RGB888,
+   .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+ MIPI_DSI_MODE_LPM,
+   .init_cmds = auo_init_cmd,
+};
+
 static int boe_panel_get_modes(struct drm_panel *panel)
 {
struct boe_panel *boe = to_boe_panel(panel);
@@ -695,6 +732,9 @@ static const struct of_device_id boe_of_match[] = {
{ .compatible = "boe,tv101wum-nl6",
  .data = &boe_tv101wum_nl6_desc
},
+   { .compatible = "auo,kd101n80-45na",
+ .data = &auo_kd101n80_45na_desc
+   },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, boe_of_match);
-- 
2.21.0

[v2 1/2] dt-bindings: display: panel: add auo kd101n80-45na panel bindings

2019-06-24 Thread Jitao Shi

Add documentation for auo kd101n80-45na panel.

Signed-off-by: Jitao Shi 
Reviewed-by: Sam Ravnborg 
---
 .../display/panel/auo,kd101n80-45na.txt   | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt 
b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
new file mode 100644
index ..994c2a13f942
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
@@ -0,0 +1,34 @@
+AUO Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,kd101n80-45na"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "auo,kd101n80-45na";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

[v2 0/2] add auo,kd101n80-45a panel driver

2019-06-24 Thread Jitao Shi

Changes since v1:
 - merge auo,kd101n80-45a and boe,tv101wum-nl6 in one driver

This patch is based on v5.2-rc1 and these patches:
https://patchwork.kernel.org/cover/11012355/
https://patchwork.kernel.org/patch/11012345/
https://patchwork.kernel.org/patch/11012349/

Jitao Shi (2):
  dt-bindings: display: panel: add auo kd101n80-45na panel bindings
  drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel

 .../display/panel/auo,kd101n80-45na.txt   | 34 
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 40 +++
 2 files changed, 74 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt

-- 
2.21.0

[v2 1/2] dt-bindngs: display: panel: Add BOE tv101wum-n16 panel bindings

2019-06-23 Thread Jitao Shi

Add documentation for boe tv101wum-n16 panel.

Signed-off-by: Jitao Shi 
---
 .../display/panel/boe,tv101wum-nl6.txt| 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
new file mode 100644
index ..bd44af636390
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
@@ -0,0 +1,34 @@
+Boe Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,tv101wum-nl6"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: phandle of the regulator that provides positive voltage
+- avee-supply: phandle of the regulator that provides negative voltage
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "boe,tv101wum-nl6";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

[v2 0/2] Add BOE tv101wum-nl6 panel driver

2019-06-23 Thread Jitao Shi

Changes since v1:

 - update typo nl6 -> n16.
 - update new panel config and makefile are added in alphabetically order.
 - add the panel mode and panel info in driver data.

Jitao Shi (2):
  dt-bindngs: display: panel: Add BOE tv101wum-n16 panel bindings
  drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

 .../display/panel/boe,tv101wum-nl6.txt|  34 +
 drivers/gpu/drm/panel/Kconfig |  10 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 715 ++
 4 files changed, 760 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

-- 
2.21.0

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[v2 2/2] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel

2019-06-23 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |  10 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 715 ++
 3 files changed, 726 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e36dbb4df867..2b055ce0700b 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
  reference designs. The panel is detected using special registers
  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 config DRM_PANEL_LVDS
tristate "Generic LVDS panel driver"
depends on OF
@@ -272,4 +281,5 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
help
  Say Y here if you want to enable support for Truly NT35597 WQXGA Dual 
DSI
  Video Mode panel
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 78e3dc376bdd..8d009223c44e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += 
panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..6e06c8506623
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,715 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+struct panel_desc {
+   const struct drm_display_mode *modes;
+   unsigned int bpc;
+
+   /**
+* @width: width (in millimeters) of the panel's active display area
+* @height: height (in millimeters) of the panel's active display area
+*/
+   struct {
+   unsigned int width;
+   unsigned int height;
+   } size;
+
+   unsigned long mode_flags;
+   enum mipi_dsi_pixel_format format;
+   const struct panel_init_cmd *init_cmds;
+   unsigned int lanes;
+};
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   const struct panel_desc *desc;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09

[1/2] dt-bindings: display: panel: add AUO kd101n80-45na panel bindings

2019-06-08 Thread Jitao Shi

Add documentation for auo kd101n80-45na panel.

Signed-off-by: Jitao Shi 
---
 .../display/panel/auo,kd101n80-45na.txt   | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt 
b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
new file mode 100644
index ..7715cf703431
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,kd101n80-45na.txt
@@ -0,0 +1,34 @@
+AUO Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,kd101n80-45na"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: 
+- avee-supply: 
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "auo,kd101n80-45na";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
-- 
2.21.0

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[2/2] drm/panel: support for AUO kd101n80-45na wuxga dsi video mode panel

2019-06-08 Thread Jitao Shi

Add driver for AUO kd101n80-45na panel.
This panel supports the resolution 1200x1920, dsi video mode
and 4 lanes.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |  10 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-auo-kd101n80-45na.c   | 352 ++
 3 files changed, 363 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-auo-kd101n80-45na.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e36dbb4df867..f5cd5af9ce42 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -272,4 +272,14 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
help
  Say Y here if you want to enable support for Truly NT35597 WQXGA Dual 
DSI
  Video Mode panel
+
+config DRM_PANEL_AUO_KD101N80_45NA
+   tristate "AUO KD101N80_45NA 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for AUO KD101N80_45NA WUXGA PANEL
+ DSI Video Mode panel
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 78e3dc376bdd..1056933bdf2e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += 
panel-sitronix-st7701.o
 obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
 obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
 obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
+obj-$(CONFIG_DRM_PANEL_AUO_KD101N80_45NA) += panel-auo-kd101n80-45na.o
diff --git a/drivers/gpu/drm/panel/panel-auo-kd101n80-45na.c 
b/drivers/gpu/drm/panel/panel-auo-kd101n80-45na.c
new file mode 100644
index ..ab7bfc059e8a
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-auo-kd101n80-45na.c
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct auo_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+static inline struct auo_panel *to_auo_panel(struct drm_panel *panel)
+{
+   return container_of(panel, struct auo_panel, base);
+}
+
+static int auo_panel_init(struct auo_panel *auo)
+{
+   struct drm_panel *panel = &auo->base;
+   int err;
+
+   err = mipi_dsi_dcs_exit_sleep_mode(auo->dsi);
+   if (err < 0) {
+   DRM_DEV_ERROR(panel->dev, "failed to exit sleep mode: %d\n",
+ err);
+   return err;
+   }
+
+   /* T3.1*/
+   msleep(120);
+
+   err = mipi_dsi_dcs_set_display_on(auo->dsi);
+   if (err < 0) {
+   DRM_DEV_ERROR(panel->dev, "failed to set display on: %d\n",
+ err);
+   }
+   /* T3.1 + T3.2: > 200ms */
+   msleep(120);
+
+   return err;
+}
+
+static int auo_panel_off(struct auo_panel *auo)
+{
+   struct mipi_dsi_device *dsi = auo->dsi;
+   int ret;
+
+   dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+   ret = mipi_dsi_dcs_set_display_off(dsi);
+   if (ret < 0)
+   return ret;
+
+   ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+   if (ret < 0)
+   return ret;
+
+   return 0;
+}
+
+static int auo_panel_disable(struct drm_panel *panel)
+{
+   struct auo_panel *auo = to_auo_panel(panel);
+
+   if (!auo->enabled)
+   return 0;
+
+   backlight_disable(auo->backlight);
+
+   auo->enabled = false;
+
+   return 0;
+}
+
+static int auo_panel_unprepare(struct drm_panel *panel)
+{
+   struct auo_panel *auo = to_auo_panel(panel);
+   int ret;
+
+   if (!auo->prepared)
+   return 0;
+
+   ret = auo_panel_off(auo);
+   if (ret < 0) {
+   dev_err(panel->dev, "failed to set panel off: %d\n", ret);
+   return ret;
+   }
+
+   msleep(150);
+   regulator_disable(auo->avee);
+   regulator_disable(auo->avdd);
+   usleep_range(5000, 7000);
+   regulator_disable(auo->pp1800);
+   if (auo->enable_gpio)
+   gpiod_set_value(auo->enable_gpio, 0);
+
+   auo->prepared = false;
+
+   return 0;
+}
+
+static int auo_panel_prepare(struct drm_panel *panel)
+{
+   struct auo_panel *auo = to_auo_panel(panel);
+   int ret;
+
+   if (auo->prepared)
+   return 0;
+
+   if (auo->enable_g

[2/2] drm/panel: support for BOE tv101wum-n16 wuxga dsi video mode panel

2019-06-08 Thread Jitao Shi

Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/panel/Kconfig |  10 +
 drivers/gpu/drm/panel/Makefile|   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c| 700 ++
 3 files changed, 711 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e36dbb4df867..5dad028e35f0 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -272,4 +272,14 @@ config DRM_PANEL_TRULY_NT35597_WQXGA
help
  Say Y here if you want to enable support for Truly NT35597 WQXGA Dual 
DSI
  Video Mode panel
+
+config DRM_PANEL_BOE_TV101WUM_NL6
+   tristate "BOE TV101WUM 1200x1920 panel"
+   depends on OF
+   depends on DRM_MIPI_DSI
+   depends on BACKLIGHT_CLASS_DEVICE
+   help
+ Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+ DSI Video Mode panel
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 78e3dc376bdd..fc5944231aa8 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -28,3 +28,4 @@ obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += 
panel-sitronix-st7701.o
 obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
 obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o
 obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c 
b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index ..19590664c337
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,700 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+struct boe_panel {
+   struct drm_panel base;
+   struct mipi_dsi_device *dsi;
+
+   struct backlight_device *backlight;
+   struct regulator *pp1800;
+   struct regulator *avee;
+   struct regulator *avdd;
+   struct gpio_desc *enable_gpio;
+
+   bool prepared;
+   bool enabled;
+
+   const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+   INIT_GENENIC_CMD,
+   INIT_DCS_CMD,
+   DELAY_CMD,
+};
+
+struct panel_init_cmd {
+   enum dsi_cmd_type type;
+   size_t len;
+   const char *data;
+};
+
+#define _INIT_CMD(...) { \
+   .type = INIT_GENENIC_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DCS_CMD(...) { \
+   .type = INIT_DCS_CMD, \
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+   .type = DELAY_CMD,\
+   .len = sizeof((char[]){__VA_ARGS__}), \
+   .data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+   _INIT_DELAY_CMD(24),
+   _INIT_DCS_CMD(0xB0, 0x05),
+   _INIT_DCS_CMD(0xB1, 0xE5),
+   _INIT_DCS_CMD(0xB3, 0x52),
+
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB3, 0x88),
+   _INIT_DCS_CMD(0xB0, 0x04),
+   _INIT_DCS_CMD(0xB8, 0x00),
+
+   _INIT_DCS_CMD(0xB0, 0x00),
+   _INIT_DCS_CMD(0xB6, 0x03),
+   _INIT_DCS_CMD(0xBA, 0x8B),
+   _INIT_DCS_CMD(0xBF, 0x1A),
+   _INIT_DCS_CMD(0xC0, 0x0F),
+   _INIT_DCS_CMD(0xC2, 0x0C),
+   _INIT_DCS_CMD(0xC3, 0x02),
+   _INIT_DCS_CMD(0xC4, 0x0C),
+   _INIT_DCS_CMD(0xC5, 0x02),
+
+   _INIT_DCS_CMD(0xB0, 0x01),
+   _INIT_DCS_CMD(0xE0, 0x26),
+   _INIT_DCS_CMD(0xE1, 0x26),
+   _INIT_DCS_CMD(0xDC, 0x00),
+   _INIT_DCS_CMD(0xDD, 0x00),
+   _INIT_DCS_CMD(0xCC, 0x26),
+   _INIT_DCS_CMD(0xCD, 0x26),
+   _INIT_DCS_CMD(0xC8, 0x00),
+   _INIT_DCS_CMD(0xC9, 0x00),
+   _INIT_DCS_CMD(0xD2, 0x03),
+   _INIT_DCS_CMD(0xD3, 0x03),
+   _INIT_DCS_CMD(0xE6, 0x04),
+   _INIT_DCS_CMD(0xE7, 0x04),
+   _INIT_DCS_CMD(0xC4, 0x09),
+   _INIT_DCS_CMD(0xC5, 0x09),
+   _INIT_DCS_CMD(0xD8, 0x0A),
+   _INIT_DCS_CMD(0xD9, 0x0A),
+   _INIT_DCS_CMD(0xC2, 0x0B),
+   _INIT_DCS_CMD(0xC3, 0x0B),
+   _INIT_DCS_CMD(0xD6, 0x0C),
+   _INIT_DCS_CMD(0xD7, 0x0C),
+   _INIT_DCS_CMD(0xC0, 0x05),
+   _INIT_DCS_CMD(0xC1, 0x05),
+   _INIT_DCS_CMD(0xD4, 0x06),
+   _INIT_DCS_CMD(0xD5, 0x06),
+   _INIT_DCS_CMD(0xCA, 0x07),
+   _INIT_DCS_CMD(0xCB, 0x07),
+   _INIT_DCS_CMD(0xDE, 0x08),
+   _INIT_DCS_CMD(0xDF, 0x08),
+
+   _INIT_DCS_CMD(0xB0, 0x02),
+   _INIT_DCS_CMD(0xC0, 0x00),
+   _INIT_DCS_CMD(0xC1, 0x0D),
+   _INIT_DCS_CMD(0xC2, 0x17),
+   _INIT_DCS_CMD(0xC3, 0x26),
+   _INIT_DCS

[1/2] dt-bindngs: display: panel: Add BOE tv101wum-nl6 panel bindings

2019-06-08 Thread Jitao Shi

Add documentation for boe tv101wum-n16 panel.

Signed-off-by: Jitao Shi 
---
 .../display/panel/boe,tv101wum-nl6.txt| 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt

diff --git 
a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt 
b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
new file mode 100644
index ..2a84735d742d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.txt
@@ -0,0 +1,34 @@
+Boe Corporation 10.1" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,tv101wum"
+- reg: the virtual channel number of a DSI peripheral
+- enable-gpios: a GPIO spec for the enable pin
+- pp1800-supply: core voltage supply
+- avdd-supply: 
+- avee-supply: 
+- backlight: phandle of the backlight device attached to the panel
+
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
+
+Example:
+&dsi {
+   ...
+   panel@0 {
+   compatible = "boe,tv101wum-nl6";
+   reg = <0>;
+   enable-gpios = <&pio 45 0>;
+   avdd-supply = <&ppvarn_lcd>;
+   avee-supply = <&ppvarp_lcd>;
+   pp1800-supply = <&pp1800_lcd>;
+   backlight = <&backlight_lcd0>;
+   status = "okay";
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+   };
+};
\ No newline at end of file
-- 
2.21.0

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[v4 3/3] drm/mediatek: add mipi_tx driver for mt8183

2019-06-01 Thread Jitao Shi

This patch add mt8183 mipi_tx driver.
And also support other chips that use the same binding and driver.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c|   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|   1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 162 ++
 4 files changed, 166 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 2c8de1f5a5ee..8067a4be8311 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -13,6 +13,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
  mtk_mt8173_mipi_tx.o \
+ mtk_mt8183_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index cdc68b88cefd..ab0fbfba5572 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -182,6 +182,8 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
  .data = &mt2701_mipitx_data },
{ .compatible = "mediatek,mt8173-mipi-tx",
  .data = &mt8173_mipitx_data },
+   { .compatible = "mediatek,mt8183-mipi-tx",
+ .data = &mt8183_mipitx_data },
{ },
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index 660726924992..3fd24563952e 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -45,5 +45,6 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
 
 extern const struct mtk_mipitx_data mt2701_mipitx_data;
 extern const struct mtk_mipitx_data mt8173_mipitx_data;
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
 
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
new file mode 100644
index ..a9f893d8e409
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: jitao.shi 
+ */
+
+#include "mtk_mipi_tx.h"
+
+#define MIPITX_LANE_CON0x000c
+#define RG_DSI_CPHY_T1DRV_EN   BIT(0)
+#define RG_DSI_ANA_CK_SEL  BIT(1)
+#define RG_DSI_PHY_CK_SEL  BIT(2)
+#define RG_DSI_CPHY_EN BIT(3)
+#define RG_DSI_PHYCK_INV_ENBIT(4)
+#define RG_DSI_PWR04_ENBIT(5)
+#define RG_DSI_BG_LPF_EN   BIT(6)
+#define RG_DSI_BG_CORE_EN  BIT(7)
+#define RG_DSI_PAD_TIEL_SELBIT(8)
+
+#define MIPITX_PLL_PWR 0x0028
+#define MIPITX_PLL_CON00x002c
+#define MIPITX_PLL_CON10x0030
+#define MIPITX_PLL_CON20x0034
+#define MIPITX_PLL_CON30x0038
+#define MIPITX_PLL_CON40x003c
+#define RG_DSI_PLL_IBIAS   (3 << 10)
+
+#define MIPITX_D2_SW_CTL_EN0x0144
+#define MIPITX_D0_SW_CTL_EN0x0244
+#define MIPITX_CK_CKMODE_EN0x0328
+#define DSI_CK_CKMODE_EN   BIT(0)
+#define MIPITX_CK_SW_CTL_EN0x0344
+#define MIPITX_D1_SW_CTL_EN0x0444
+#define MIPITX_D3_SW_CTL_EN0x0544
+#define DSI_SW_CTL_EN  BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON  BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN  BIT(1)
+
+#define RG_DSI_PLL_EN  BIT(4)
+#define RG_DSI_PLL_POSDIV  (0x7 << 8)
+
+static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
+{
+   struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+   unsigned int txdiv, txdiv0;
+   u64 pcw;
+   int ret;
+
+   dev_dbg(mipi_tx->dev, "prepare: %u bps\n", mipi_tx->data_rate);
+
+   if (mipi_tx->data_rate >= 20) {
+   txdiv = 1;
+   txdiv0 = 0;
+   } else if (mipi_tx->data_rate >= 10) {
+   txdiv = 2;
+   txdiv0 = 1;
+   } else if (mipi_tx->data_rate >= 5) {
+   txdiv = 4;
+   txdiv0 = 2;
+   } else if (mipi_tx->data_rate > 25000) {
+   txdiv = 8;
+   txdiv0 = 3;
+   } else if (mipi_tx->data_rate >= 12500) {
+   txdiv = 16;
+   txdiv0 = 4;
+   } else {
+   return -EINVAL;
+   }
+
+   ret = clk_prepare_enable(mipi_tx->ref_clk);
+   if (ret < 0) {
+   dev_err(mipi_tx->dev,
+   "can't prepare and enable mipi_tx ref_clk %d\n", ret);
+   return ret;
+   }
+
+   mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+   mtk_mipi_tx_set

[v4 0/3] Support mipitx for mt8183

2019-06-01 Thread Jitao Shi

Changes since v3:
 - turn off PLL before setting PLL parameters.

Changes since v2:
 - update Acked-by: Rob Herring 
 - update mt8183 max bit rate support

Changes since v1:
 - update dt-bindings document for mt8183 mipitx.
 - remove mtk_mipitx_clk_get_ops and assign clk_ops in probe.
 - fix the lincence
 - remove txdiv1 from mtk_mipi_tx_pll_prepare

Jitao Shi (3):
  dt-bindings: display: mediatek: update dsi supported chips
  drm/mediatek: separate mipi_tx to different file
  drm/mediatek: add mipi_tx driver for mt8183

 .../bindings/display/mediatek/mediatek,dsi.txt |   2 +-
 drivers/gpu/drm/mediatek/Makefile  |   2 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 345 ++---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h |  50 +++
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c  | 289 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c  | 162 ++
 6 files changed, 530 insertions(+), 320 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c

-- 
2.12.5

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[v4 1/3] dt-bindings: display: mediatek: update dsi supported chips

2019-06-01 Thread Jitao Shi

Update device tree binding documentation for the dsi for
Mediatek MT8183 SoCs.

Signed-off-by: Jitao Shi 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index fadf327c7cdf..bb3dcd2d8571 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
 
 Required properties:
 - compatible: "mediatek,-mipi-tx"
-  the supported chips are mt2701 and mt8173.
+  the supported chips are mt2701, mt8173 and mt8183.
 - reg: Physical base address and length of the controller's registers
 - clocks: PLL reference clock
 - clock-output-names: name of the output clock line to the DSI encoder
-- 
2.12.5

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[v4 2/3] drm/mediatek: separate mipi_tx to different file

2019-06-01 Thread Jitao Shi

Different IC has different mipi_tx setting of dsi.
This patch separates the mipi_tx hardware relate part for mt8173.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/Makefile |   1 +
 drivers/gpu/drm/mediatek/mtk_mipi_tx.c| 343 ++
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h|  49 
 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c | 289 ++
 4 files changed, 363 insertions(+), 319 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mipi_tx.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_mt8173_mipi_tx.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 82ae49c64221..2c8de1f5a5ee 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -12,6 +12,7 @@ mediatek-drm-y := mtk_disp_color.o \
  mtk_drm_plane.o \
  mtk_dsi.o \
  mtk_mipi_tx.o \
+ mtk_mt8173_mipi_tx.o \
  mtk_dpi.o
 
 obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c 
b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 90e913108950..cdc68b88cefd 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -11,292 +11,39 @@
  * GNU General Public License for more details.
  */
 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define MIPITX_DSI_CON 0x00
-#define RG_DSI_LDOCORE_EN  BIT(0)
-#define RG_DSI_CKG_LDOOUT_EN   BIT(1)
-#define RG_DSI_BCLK_SEL(3 << 2)
-#define RG_DSI_LD_IDX_SEL  (7 << 4)
-#define RG_DSI_PHYCLK_SEL  (2 << 8)
-#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
-#define RG_DSI_LPTX_CLMP_ENBIT(11)
-
-#define MIPITX_DSI_CLOCK_LANE  0x04
-#define MIPITX_DSI_DATA_LANE0  0x08
-#define MIPITX_DSI_DATA_LANE1  0x0c
-#define MIPITX_DSI_DATA_LANE2  0x10
-#define MIPITX_DSI_DATA_LANE3  0x14
-#define RG_DSI_LNTx_LDOOUT_EN  BIT(0)
-#define RG_DSI_LNTx_CKLANE_EN  BIT(1)
-#define RG_DSI_LNTx_LPTX_IPLUS1BIT(2)
-#define RG_DSI_LNTx_LPTX_IPLUS2BIT(3)
-#define RG_DSI_LNTx_LPTX_IMINUSBIT(4)
-#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
-#define RG_DSI_LNTx_LPCD_IMINUSBIT(6)
-#define RG_DSI_LNTx_RT_CODE(0xf << 8)
-
-#define MIPITX_DSI_TOP_CON 0x40
-#define RG_DSI_LNT_INTR_EN BIT(0)
-#define RG_DSI_LNT_HS_BIAS_EN  BIT(1)
-#define RG_DSI_LNT_IMP_CAL_EN  BIT(2)
-#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE(0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
-#define RG_DSI_PAD_TIE_LOW_EN  BIT(11)
-#define RG_DSI_DEBUG_INPUT_EN  BIT(12)
-#define RG_DSI_PRESERVE(7 << 13)
-
-#define MIPITX_DSI_BG_CON  0x44
-#define RG_DSI_BG_CORE_EN  BIT(0)
-#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV  (0x3 << 2)
-#define RG_DSI_BG_FAST_CHARGE  BIT(4)
-#define RG_DSI_VOUT_MSK(0x3 << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL(7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL(7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM  (0xf << 24)
-#define RG_DSI_BG_R2_TRIM  (0xf << 28)
-
-#define MIPITX_DSI_PLL_CON00x50
-#define RG_DSI_MPPLL_PLL_ENBIT(0)
-#define RG_DSI_MPPLL_DIV_MSK   (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV(3 << 1)
-#define RG_DSI_MPPLL_TXDIV0(3 << 3)
-#define RG_DSI_MPPLL_TXDIV1(3 << 5)
-#define RG_DSI_MPPLL_POSDIV(7 << 7)
-#define RG_DSI_MPPLL_MONVC_EN  BIT(10)
-#define RG_DSI_MPPLL_MONREF_EN BIT(11)
-#define RG_DSI_MPPLL_VOD_ENBIT(12)
-
-#define MIPITX_DSI_PLL_CON10x54
-#define RG_DSI_MPPLL_SDM_FRA_ENBIT(0)
-#define RG_DSI_MPPLL_SDM_SSC_PH_INIT   BIT(1)
-#define RG_DSI_MPPLL_SDM_SSC_ENBIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD   (0x << 16)
-
-#define MIPITX_DSI_PLL_CON20x58
-
-#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE  (0xff << 8)
-
-#define MIPITX_DSI_PLL_PWR 0x68
-#define RG_DSI_MPPLL_SDM_PWR_ONBIT(0)
-#define RG_DSI_MPPLL_SDM_ISO_ENBIT(1)
-#define RG_DSI_MPPLL_SDM_PWR_ACK   BIT(8)
-
-#define MIPITX_DSI_SW_CTRL 0x80
-#define SW_CTRL_EN BIT(0)
-
-#define MIPITX_DSI_SW_CTR

[v4 4/7] drm/mediatek: add frame size control

2019-06-01 Thread Jitao Shi

Our new DSI chip has frame size control.
So add the driver data to control for different chips.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index eea47294079e..18a192656a89 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -78,6 +78,7 @@
 #define DSI_VBP_NL 0x24
 #define DSI_VFP_NL 0x28
 #define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON   0x38
 #define DSI_HSA_WC 0x50
 #define DSI_HBP_WC 0x54
 #define DSI_HFP_WC 0x58
@@ -162,6 +163,7 @@ struct phy;
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
bool has_shadow_ctl;
+   bool has_size_ctl;
 };
 
 struct mtk_dsi {
@@ -430,6 +432,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 
+   if (dsi->driver_data->has_size_ctl)
+   writel(vm->vactive << 16 | vm->hactive, dsi->regs + 
DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
-- 
2.21.0

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[v4 2/7] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701

2019-06-01 Thread Jitao Shi

Config the different CMDQ reg address in driver data.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 6c4ac37f983d..a48db056df6c 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -131,7 +131,6 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
-#define DSI_CMDQ0  0x180
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -156,6 +155,10 @@
 
 struct phy;
 
+struct mtk_dsi_driver_data {
+   const u32 reg_cmdq_off;
+};
+
 struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -182,6 +185,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+   const struct mtk_dsi_driver_data *driver_data;
 };
 
 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -934,6 +938,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+   u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
 
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -953,9 +958,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct 
mipi_dsi_msg *msg)
}
 
for (i = 0; i < msg->tx_len; i++)
-   writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+   mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
 
-   mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+   mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 }
 
@@ -1101,6 +1108,8 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
 
+   dsi->driver_data = of_device_get_match_data(dev);
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1193,9 +1202,19 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
 }
 
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+   .reg_cmdq_off = 0x180,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
-   { .compatible = "mediatek,mt2701-dsi" },
-   { .compatible = "mediatek,mt8173-dsi" },
+   { .compatible = "mediatek,mt2701-dsi",
+ .data = &mt2701_dsi_driver_data },
+   { .compatible = "mediatek,mt8173-dsi",
+ .data = &mt8173_dsi_driver_data },
{ },
 };
 
-- 
2.21.0

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[v4 6/7] drm/mediatek: change the dsi phytiming calculate method

2019-06-01 Thread Jitao Shi

Change the method of frame rate calc which can get more accurate
frame rate.

data rate = pixel_clock * bit_per_pixel / lanes
Adjust hfp_wc to adapt the additional phy_data

if MIPI_DSI_MODE_VIDEO_BURST
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6;
else
hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12;

Note:
//(2: 1 for sync, 1 for phy idle)
data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2;

bpp: bit per pixel

Signed-off-by: Jitao Shi 
Tested-by: Ryan Case 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 122 -
 1 file changed, 83 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index abf6ddec5db6..558727c60ba3 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -144,12 +144,6 @@
 #define DATA_0 (0xff << 16)
 #define DATA_1 (0xff << 24)
 
-#define T_LPX  5
-#define T_HS_PREP  6
-#define T_HS_TRAIL 8
-#define T_HS_EXIT  7
-#define T_HS_ZERO  10
-
 #define NS_TO_CYCLE(n, c)((n) / (c) + (((n) % (c)) ? 1 : 0))
 
 #define MTK_DSI_HOST_IS_READ(type) \
@@ -158,6 +152,25 @@
(type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
(type == MIPI_DSI_DCS_READ))
 
+struct mtk_phy_timing {
+   u32 lpx;
+   u32 da_hs_prepare;
+   u32 da_hs_zero;
+   u32 da_hs_trail;
+
+   u32 ta_go;
+   u32 ta_sure;
+   u32 ta_get;
+   u32 da_hs_exit;
+
+   u32 clk_hs_zero;
+   u32 clk_hs_trail;
+
+   u32 clk_hs_prepare;
+   u32 clk_hs_post;
+   u32 clk_hs_exit;
+};
+
 struct phy;
 
 struct mtk_dsi_driver_data {
@@ -182,12 +195,13 @@ struct mtk_dsi {
struct clk *digital_clk;
struct clk *hs_clk;
 
-   u32 data_rate;
+   u64 data_rate;
 
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
unsigned int lanes;
struct videomode vm;
+   struct mtk_phy_timing phy_timing;
int refcount;
bool enabled;
u32 irq_data;
@@ -221,17 +235,36 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 {
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
+
+   ui = 10 / dsi->data_rate;
+   cycle_time = 80 / dsi->data_rate;
+
+   timing->lpx = NS_TO_CYCLE(60, cycle_time);
+   timing->da_hs_prepare = NS_TO_CYCLE(40 + 5 * ui, cycle_time);
+   timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
+   timing->da_hs_trail = NS_TO_CYCLE(80 + 4 * ui, cycle_time);
 
-   ui = 1000 / dsi->data_rate + 0x01;
-   cycle_time = 8000 / dsi->data_rate + 0x01;
+   timing->ta_go = 4 * timing->lpx;
+   timing->ta_sure = 3 * timing->lpx / 2;
+   timing->ta_get = 5 * timing->lpx;
+   timing->da_hs_exit = 2 * timing->lpx;
 
-   timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
-   timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
- T_HS_EXIT << 24;
-   timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
- (NS_TO_CYCLE(0x150, cycle_time) << 16);
-   timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
- NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
+   timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
+   timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
+
+   timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
+   timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
+   timing->clk_hs_exit = 2 * timing->lpx;
+
+   timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
+ timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
+   timcon1 = timing->ta_go | timing->ta_sure << 8 |
+ timing->ta_get << 16 | timing->da_hs_exit << 24;
+   timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
+ timing->clk_hs_trail << 24;
+   timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
+ timing->clk_hs_exit << 16;
 
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
@@ -418,7 +451,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
u32 horizontal_sync_active_byte;
u32 horizontal_backporch_byte;
u32 horizontal_frontporch_byte;
-   u32 dsi_tmp_buf_bpp;
+   u32 dsi_tmp_buf_bpp, data_phy_cycles;
+   struct mtk_phy_timing *timing = &dsi->phy_timing;
 
struct videomode *vm = &dsi->vm;
 
@@ -433,7 +467,8 @@ static void mtk_dsi_config_

[v4 3/7] drm/mediatek: add dsi reg commit disable control

2019-06-01 Thread Jitao Shi

New DSI IP has shadow register and working reg. The register
values are writen to shadow register. And then trigger with
commit reg, the register values will be moved working register.

This fucntion is defualt on. But this driver doesn't use this
function. So add the disable control.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index a48db056df6c..eea47294079e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -131,6 +131,10 @@
 #define VM_CMD_EN  BIT(0)
 #define TS_VFP_EN  BIT(5)
 
+#define DSI_SHADOW_DEBUG   0x190U
+#define FORCE_COMMIT   BIT(0)
+#define BYPASS_SHADOW  BIT(1)
+
 #define CONFIG (0xff << 0)
 #define SHORT_PACKET   0
 #define LONG_PACKET2
@@ -157,6 +161,7 @@ struct phy;
 
 struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+   bool has_shadow_ctl;
 };
 
 struct mtk_dsi {
@@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
 
mtk_dsi_enable(dsi);
+
+   if (dsi->driver_data->has_shadow_ctl)
+   writel(FORCE_COMMIT | BYPASS_SHADOW,
+  dsi->regs + DSI_SHADOW_DEBUG);
+
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
 
-- 
2.21.0

[v4 0/7] Support dsi for mt8183

2019-06-01 Thread Jitao Shi

changes since v3
 - add one more 'tab' for bitwise define.
 - add Tested-by: Ryan Case 
and Reviewed-by: CK Hu .
 - remove compare da_hs_zero to da_hs_prepare.

Changes since v2:
 - change the video timing calc method
 - fine the dsi and mipitx init sequence
 - fine tune commit msg

Changes since v1:
 - separate frame size and reg commit control independent patches.
 - fix some return values in probe
 - remove DSI_CMDW0 in "CMDQ reg address of mt8173 is different with mt2701" 

Jitao Shi (7):
  drm/mediatek: move mipi_dsi_host_register to probe
  drm/mediatek: fixes CMDQ reg address of mt8173 is different with
mt2701
  drm/mediatek: add dsi reg commit disable control
  drm/mediatek: add frame size control
  drm/mediatek: add mt8183 dsi driver support
  drm/mediatek: change the dsi phytiming calculate method
  drm: mediatek: adjust dsi and mipi_tx probe sequence

 drivers/gpu/drm/mediatek/mtk_drm_drv.c |   2 +-
 drivers/gpu/drm/mediatek/mtk_dsi.c | 222 ++---
 2 files changed, 160 insertions(+), 64 deletions(-)

-- 
2.21.0

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[v4 1/7] drm/mediatek: move mipi_dsi_host_register to probe

2019-06-01 Thread Jitao Shi

DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.

If mipi_dsi_host_register is not in probe, dsi panel will
probe more delay.

So move the mipi_dsi_host_register to probe from bind.

Signed-off-by: Jitao Shi 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 50 ++
 1 file changed, 30 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b00eb2d2e086..6c4ac37f983d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct 
device *master, void *data)
return ret;
}
 
-   ret = mipi_dsi_host_register(&dsi->host);
-   if (ret < 0) {
-   dev_err(dev, "failed to register DSI host: %d\n", ret);
-   goto err_ddp_comp_unregister;
-   }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct device 
*master, void *data)
return 0;
 
 err_unregister:
-   mipi_dsi_host_unregister(&dsi->host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
return ret;
 }
@@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 
dsi->host.ops = &mtk_dsi_ops;
dsi->host.dev = dev;
+   dsi->dev = dev;
+   ret = mipi_dsi_host_register(&dsi->host);
+   if (ret < 0) {
+   dev_err(dev, "failed to register DSI host: %d\n", ret);
+   return ret;
+   }
 
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
  &dsi->panel, &dsi->bridge);
if (ret)
-   return ret;
+   goto err_unregister_host;
 
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1129,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
-   return comp_id;
+   ret = comp_id;
+   goto err_unregister_host;
}
 
ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
&mtk_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
-   return ret;
+   goto err_unregister_host;
}
 
irq_num = platform_get_irq(pdev, 0);
if (irq_num < 0) {
-   dev_err(&pdev->dev, "failed to request dsi irq resource\n");
-   return -EPROBE_DEFER;
+   dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
+   ret = irq_num;
+   goto err_unregister_host;
}
 
irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
@@ -1163,14 +1163,24 @@ static int mtk_dsi_probe(struct platform_device *pdev)
   IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
if (ret) {
dev_err(&pdev->dev, "failed to request mediatek dsi irq

[v4 7/7] drm: mediatek: adjust dsi and mipi_tx probe sequence

2019-06-01 Thread Jitao Shi

mtk_mipi_tx is the phy of mtk_dsi.
mtk_dsi get the phy(mtk_mipi_tx) in probe().

So,  mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will
defer to wait mtk_mipi_tx probe done.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 57ce4708ef1b..fc809a61fab9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -640,8 +640,8 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
-   &mtk_dsi_driver,
&mtk_mipi_tx_driver,
+   &mtk_dsi_driver,
 };
 
 static int __init mtk_drm_init(void)
-- 
2.21.0

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[v4 5/7] drm/mediatek: add mt8183 dsi driver support

2019-06-01 Thread Jitao Shi

Add mt8183 dsi driver data. Enable size control and
reg commit control.

Signed-off-by: Jitao Shi 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_dsi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c 
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 18a192656a89..abf6ddec5db6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1225,11 +1225,19 @@ static const struct mtk_dsi_driver_data 
mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
 };
 
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+   .reg_cmdq_off = 0x200,
+   .has_shadow_ctl = true,
+   .has_size_ctl = true,
+};
+
 static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
  .data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
  .data = &mt8173_dsi_driver_data },
+   { .compatible = "mediatek,mt8183-dsi",
+ .data = &mt8183_dsi_driver_data },
{ },
 };
 
-- 
2.21.0

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