[PATCH v5 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 217 ++
1 file changed, 217 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..275c14ad173a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+ opp_table: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+power-domains:
+ minItems: 5
+ maxItems: 5
+
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+ gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-microvolt = <668750>,
+ <75>;
+ };
+
+ opp-60500 {
+ opp-hz = /bits/ 64 <60500>;
+ opp-microvolt = <681250>,
+ <75>;
+ };
+
+ opp-64700 {
+ opp-hz = /bits/ 64 <64700>;
+ opp-microvolt = <693750>,
+ <75>;
+ };
+
+ opp-68800 {
+ opp-hz = /bits/ 64 <68800>;
+ opp-microvolt = <706250>,
+ <
Re: [PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Thanks for your review.
These are fixed in v5 as following link.
https://lore.kernel.org/patchwork/patch/1372271/
Nick Fan
On Thu, 2021-01-14 at 14:14 -0600, Rob Herring wrote:
> On Tue, Jan 12, 2021 at 02:49:32PM +0800, Nick Fan wrote:
> > Add devicetree schema for Arm Mali Valhall GPU
> >
> > Define a compatible string for the Mali Valhall GPU
> > for Mediatek's SoC platform.
> >
> > Signed-off-by: Nick Fan
> > ---
> > .../bindings/gpu/arm,mali-valhall.yaml| 252 ++
> > 1 file changed, 252 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > new file mode 100644
> > index ..ecf249a58435
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
> > @@ -0,0 +1,252 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2020 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: ARM Mali Valhall GPU
> > +
> > +maintainers:
> > + - Rob Herring
> > +
> > +properties:
> > + $nodename:
> > +pattern: '^gpu@[a-f0-9]+$'
> > +
> > + compatible:
> > +items:
> > + - enum:
> > + - mediatek,mt8192-mali
> > + - const: arm,mali-valhall
> > +
> > + reg:
> > +maxItems: 1
> > +
> > + interrupts:
> > +items:
> > + - description: GPU interrupt
> > + - description: MMU interrupt
> > + - description: Job interrupt
> > +
> > + interrupt-names:
> > +items:
> > + - const: gpu
> > + - const: mmu
> > + - const: job
> > +
> > + clocks:
> > +minItems: 1
> > +
> > + power-domains:
> > +minItems: 1
> > +maxItems: 5
> > +
> > + mali-supply: true
> > + sram-supply: true
> > +
> > + operating-points-v2: true
> > +
> > + "#cooling-cells":
> > +const: 2
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +allOf:
> > + - if:
> > + properties:
> > +compatible:
> > + contains:
> > +const: mediatek,mt8192-mali
> > +then:
> > + properties:
> > +sram-supply: true
> > +power-domains:
> > + description:
> > +List of phandle and PM domain specifier as documented in
> > +Documentation/devicetree/bindings/power/power_domain.txt
> > + minItems: 5
> > + maxItems: 5
> > +power-domain-names:
> > + items:
> > +- const: core0
> > +- const: core1
> > +- const: core2
> > +- const: core3
> > +- const: core4
> > +
> > + required:
> > +- sram-supply
> > +- power-domains
> > +
> > +examples:
> > + - |
> > +#include
> > +#include
> > +
> > +gpu@1300 {
> > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
> > + reg = <0x1300 0x4000>;
> > + interrupts =
> > + ,
> > + ,
> > + ;
> > + interrupt-names =
> > + "gpu",
> > + "mmu",
> > + "job";
> > +
> > + clocks = < 0>;
> > +
> > + power-domains =
> > + < 4>,
> > + < 5>,
> > + < 6>,
> > + < 7>,
> > + < 8>;
> > +
> > + operating-points-v2 = <_opp_table>;
> > + mali-supply = <_7_vbuck1>;
> > + sram-supply = <_vsram_others_ldo_reg>;
> > +};
> > +
> > +gpu_opp_table: opp_table0 {
>
> Make this a child node of the gpu node.
>
> > + compatible = "operating-points-v2";
> > + opp
[PATCH v5 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 140
2 files changed, 147 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..d0e812791185 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,146 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <482
Re: [PATCH v2 2/2] arm64: dts: mt8192: Add node for the Mali GPU
On Fri, 2021-01-08 at 15:58 +, Steven Price wrote:
> On 05/01/2021 05:36, Nick Fan wrote:
> > Add a basic GPU node for mt8192.
> >
> > Signed-off-by: Nick Fan
> > ---
> > This patch depends on Mediatek power and regulator support.
> >
> > Listed as following.
> >
> > [1]https://lore.kernel.org/patchwork/patch/1336293/
> > [2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
> > [3]https://lore.kernel.org/patchwork/patch/1356037/
> > [4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
> > [5]https://lore.kernel.org/patchwork/patch/1356175/
> > [6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
> > [7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
> > ---
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi| 176
> > 2 files changed, 183 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
> > index 6c1e2b3e8a60..48c0e240dd92 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
> > @@ -5,6 +5,7 @@
> >*/
> > /dts-v1/;
> > #include "mt8192.dtsi"
> > +#include "mt6359.dtsi"
> >
> > / {
> > model = "MediaTek MT8192 evaluation board";
> > @@ -70,6 +71,12 @@
> > };
> > };
> >
> > + {
> > + supply-names = "mali","sram";
> > + mali-supply = <_7_vbuck1>;
> > + sram-supply = <_vsram_others_ldo_reg>;
> > +};
> > +
> >{
> > status = "okay";
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index d6a4ad242a33..de166ea750af 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -822,6 +822,182 @@
> > #clock-cells = <1>;
> > };
> >
> > + gpu: mali@1300 {
> > + compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
> > + reg = <0 0x1300 0 0x4000>;
> > + interrupts =
> > + ,
> > + ,
> > + ,
> > + ,
> > + ;
> > + interrupt-names =
> > + "GPU",
> > + "MMU",
> > + "JOB",
> > + "EVENT",
> > + "PWR";
>
> These interrupt names don't match the binding you've posted (GPU, MMU,
> JOB are upper case here, lower case in the binding). Also EVENT and PWR
> are not mentioned in the binding - should they be?
>
> I know there are differences here between kbase's requirements and the
> existing upstream bindings (case specifically), but I haven't seen a
> binding containing EVENT and PWR before.
>
> Steve
>
Thanks for your comment.
Yes, the EVENT and PWR should be removed.
And the rest of interrupt names are corrected to lower case.
Please check my updated version 4 for this.
https://lore.kernel.org/patchwork/patch/1363862/
Nick Fan
> > +
> > + clocks =
> > + < CLK_APMIXED_MFGPLL>,
> > + < CLK_TOP_MFG_PLL_SEL>,
> > + < CLK_TOP_MFG_REF_SEL>,
> > + < CLK_MFG_BG3D>;
> > + clock-names =
> > + "clk_main_parent",
> > + "clk_mux",
> > + "clk_sub_parent",
> > + "subsys_mfg_cg";
> > +
> > + power-domains =
> > + < MT8192_POWER_DOMAIN_MFG2>,
> > + < MT8192_POWER_DOMAIN_MFG3>,
> > + < MT8192_POWER_DOMAIN_MFG4>,
> > + < MT8192_POWER_DOMAIN_MFG5>,
> > + < MT81
[PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..ecf249a58435
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+/bits/ 64 <56400>;
+
[PATCH v4 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 172
2 files changed, 179 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..9abba13df68e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,178 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+ /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+ /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+
[PATCH v3 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..ecf249a58435
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+/bits/ 64 <56400>;
+
[PATCH v3 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 176
2 files changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..725c5976d17d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,182 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ;
+ interrupt-names =
+ "GPU",
+ "MMU",
+ "JOB",
+ "EVENT",
+ "PWR";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+ /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+ /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+
[PATCH v2 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 176
2 files changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..de166ea750af 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,182 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ;
+ interrupt-names =
+ "GPU",
+ "MMU",
+ "JOB",
+ "EVENT",
+ "PWR";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+ /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+ /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+
[PATCH v2 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..436294c032ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+/bits/ 64 <56400>;
+
[PATCH v1 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema
Convert the Arm Valhall GPU binding to DT schema format.
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..436294c032ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+/bits/ 64 <56400>;
+
[PATCH v1 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 176
2 files changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..de166ea750af 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,182 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ;
+ interrupt-names =
+ "GPU",
+ "MMU",
+ "JOB",
+ "EVENT",
+ "PWR";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+ /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+ /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+
[PATCH 2/2] arm64: dts: mt8192: Add node for the Mali GPU
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
[3]https://lore.kernel.org/patchwork/patch/1356037/
[4]https://patchwork.kernel.org/project/linux-mediatek/list/?series=405777
[5]https://lore.kernel.org/patchwork/patch/1356175/
[6]https://patchwork.kernel.org/project/linux-mediatek/patch/1605700894-32699-6-git-send-email-hsin-hsiung.w...@mediatek.com/
[7]https://patchwork.kernel.org/project/linux-mediatek/patch/1608104827-7937-10-git-send-email-hsin-hsiung.w...@mediatek.com/
---
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 176
2 files changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 6c1e2b3e8a60..48c0e240dd92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
@@ -70,6 +71,12 @@
};
};
+ {
+ supply-names = "mali","sram";
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
{
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d6a4ad242a33..de166ea750af 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -822,6 +822,182 @@
#clock-cells = <1>;
};
+ gpu: mali@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0 0x1300 0 0x4000>;
+ interrupts =
+ ,
+ ,
+ ,
+ ,
+ ;
+ interrupt-names =
+ "GPU",
+ "MMU",
+ "JOB",
+ "EVENT",
+ "PWR";
+
+ clocks =
+ < CLK_APMIXED_MFGPLL>,
+ < CLK_TOP_MFG_PLL_SEL>,
+ < CLK_TOP_MFG_REF_SEL>,
+ < CLK_MFG_BG3D>;
+ clock-names =
+ "clk_main_parent",
+ "clk_mux",
+ "clk_sub_parent",
+ "subsys_mfg_cg";
+
+ power-domains =
+ < MT8192_POWER_DOMAIN_MFG2>,
+ < MT8192_POWER_DOMAIN_MFG3>,
+ < MT8192_POWER_DOMAIN_MFG4>,
+ < MT8192_POWER_DOMAIN_MFG5>,
+ < MT8192_POWER_DOMAIN_MFG6>;
+ power-domain-names = "core0",
+"core1",
+"core2",
+"core3",
+"core4";
+
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+ /bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+ /bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+
[PATCH 1/2] dt-bindings: Convert Arm Mali Valhall GPU to DT schema
Convert the Arm Valhall GPU binding to DT schema format.
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index ..3dba202bec95
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,252 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-vallhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring
+
+properties:
+ $nodename:
+pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall # Mali Valhall GPU model/revision is fully
discoverable
+
+ reg:
+maxItems: 1
+
+ interrupts:
+items:
+ - description: GPU interrupt
+ - description: MMU interrupt
+ - description: Job interrupt
+
+ interrupt-names:
+items:
+ - const: gpu
+ - const: mmu
+ - const: job
+
+ clocks:
+minItems: 1
+
+ power-domains:
+minItems: 1
+maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+
+ "#cooling-cells":
+const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: mediatek,mt8192-mali
+then:
+ properties:
+sram-supply: true
+power-domains:
+ description:
+List of phandle and PM domain specifier as documented in
+Documentation/devicetree/bindings/power/power_domain.txt
+ minItems: 5
+ maxItems: 5
+power-domain-names:
+ items:
+- const: core0
+- const: core1
+- const: core2
+- const: core3
+- const: core4
+
+ required:
+- sram-supply
+- power-domains
+
+examples:
+ - |
+#include
+#include
+
+gpu@1300 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x1300 0x4000>;
+ interrupts =
+ ,
+ ,
+ ;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = < 0>;
+
+ power-domains =
+ < 4>,
+ < 5>,
+ < 6>,
+ < 7>,
+ < 8>;
+
+ operating-points-v2 = <_opp_table>;
+ mali-supply = <_7_vbuck1>;
+ sram-supply = <_vsram_others_ldo_reg>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-35800 {
+ opp-hz = /bits/ 64 <35800>;
+ opp-hz-real = /bits/ 64 <35800>,
+/bits/ 64 <35800>;
+ opp-microvolt = <606250>,
+ <75>;
+ };
+
+ opp-39900 {
+ opp-hz = /bits/ 64 <39900>;
+ opp-hz-real = /bits/ 64 <39900>,
+/bits/ 64 <39900>;
+ opp-microvolt = <618750>,
+ <75>;
+ };
+
+ opp-44000 {
+ opp-hz = /bits/ 64 <44000>;
+ opp-hz-real = /bits/ 64 <44000>,
+/bits/ 64 <44000>;
+ opp-microvolt = <631250>,
+ <75>;
+ };
+
+ opp-48200 {
+ opp-hz = /bits/ 64 <48200>;
+ opp-hz-real = /bits/ 64 <48200>,
+/bits/ 64 <48200>;
+ opp-microvolt = <643750>,
+ <75>;
+ };
+
+ opp-52300 {
+ opp-hz = /bits/ 64 <52300>;
+ opp-hz-real = /bits/ 64 <52300>,
+/bits/ 64 <52300>;
+ opp-microvolt = <656250>,
+ <75>;
+ };
+
+ opp-56400 {
+ opp-hz = /bits/ 64 <56400>;
+ opp-hz-real = /bits/ 64 <56400>,
+
Re: [PATCH v4 1/7] dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
On Fri, 2020-03-06 at 14:43 +, Steven Price wrote:
> On Fri, Mar 06, 2020 at 02:13:08PM +, Rob Herring wrote:
> > On Thu, Mar 5, 2020 at 8:34 PM Nick Fan wrote:
> > >
> > > Sorry for my late reply.
> > > I have checked internally.
> > > The MT8183_POWER_DOMAIN_MFG_2D is just a legacy name, not really 2D
> > > domain.
> > >
> > > If the naming too confusing, we can change this name to
> > > MT8183_POWER_DOMAIN_MFG_CORE2 for consistency.
> >
> > Can you clarify what's in each domain? Are there actually 3 shader
> > cores (IIRC, that should be discoverable)?
>
> The cover letter from Nicolas includes:
>
> > [ 501.321752] panfrost 1304.gpu: shader_present=0x7 l2_present=0x1
>
> 0x7 is three bits set, so it certainly looks like there are 3 shader
> cores. Of course I wouldn't guarantee that it is as simple as each power
> domain has a shader core in. The job manager and tiler also need to be
> powered somehow, so they are either sharing with a shader core or
> there's something more complex going on.
>
> Steve
>
There are actually five power domains in total for MT8183 GPU.
There are 3 shader cores in MT8183.
They can be listed as following for each power domain:
1.MT8183_POWER_DOMAIN_MFG_ASYNC : SOC bus logic
2.MT8183_POWER_DOMAIN_MFG : GPU job manager & tiler
3.MT8183_POWER_DOMAIN_MFG_CORE0 : GPU shader core 0
4.MT8183_POWER_DOMAIN_MFG_CORE1 : GPU shader core 1
5.MT8183_POWER_DOMAIN_MFG_2D : GPU shader core 2
There are other power domain dependency can be reference in the
following link.
https://lkml.org/lkml/2019/2/1/166
You can check the power domain dependencies as following
==
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
==
Thanks
Nick Fan
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v4 1/7] dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
Sorry for my late reply.
I have checked internally.
The MT8183_POWER_DOMAIN_MFG_2D is just a legacy name, not really 2D
domain.
If the naming too confusing, we can change this name to
MT8183_POWER_DOMAIN_MFG_CORE2 for consistency.
Thanks
Nick Fan
On Wed, 2020-02-26 at 08:55 +0800, Nicolas Boichat wrote:
> +Nick Fan +Sj Huang @ MTK
>
> On Wed, Feb 26, 2020 at 1:16 AM Rob Herring wrote:
> >
> > On Fri, Feb 07, 2020 at 01:26:21PM +0800, Nicolas Boichat wrote:
> > > Define a compatible string for the Mali Bifrost GPU found in
> > > Mediatek's MT8183 SoCs.
> > >
> > > Signed-off-by: Nicolas Boichat
> > > Reviewed-by: Alyssa Rosenzweig
> > > ---
> > >
> > > v4:
> > > - Add power-domain-names description
> > >(kept Alyssa's reviewed-by as the change is minor)
> > > v3:
> > > - No change
> > >
> > > .../bindings/gpu/arm,mali-bifrost.yaml| 25 +++
> > > 1 file changed, 25 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > index 4ea6a8789699709..0d93b3981445977 100644
> > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
> > > @@ -17,6 +17,7 @@ properties:
> > > items:
> > >- enum:
> > >- amlogic,meson-g12a-mali
> > > + - mediatek,mt8183-mali
> > >- realtek,rtd1619-mali
> > >- rockchip,px30-mali
> > >- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is
> > > fully discoverable
> > > @@ -62,6 +63,30 @@ allOf:
> > >minItems: 2
> > >required:
> > > - resets
> > > + - if:
> > > + properties:
> > > +compatible:
> > > + contains:
> > > +const: mediatek,mt8183-mali
> > > +then:
> > > + properties:
> > > +sram-supply: true
> > > +power-domains:
> > > + description:
> > > +List of phandle and PM domain specifier as documented in
> > > +Documentation/devicetree/bindings/power/power_domain.txt
> > > + minItems: 3
> > > + maxItems: 3
> > > +power-domain-names:
> > > + items:
> > > +- const: core0
> > > +- const: core1
> > > +- const: 2d
> >
> > AFAIK, there's no '2d' block in bifrost GPUs. A power domain for each
> > core group is correct though.
>
> Good question... Hopefully Nick/SJ@MTK can comment, the non-upstream DTS has:
> gpu: mali@1304 {
> compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
> power-domains = < MT8183_POWER_DOMAIN_MFG_CORE0>;
> ...
> }
>
> gpu_core1: mali_gpu_core1 {
> compatible = "mediatek,gpu_core1";
> power-domains = < MT8183_POWER_DOMAIN_MFG_CORE1>;
> };
>
> gpu_core2: mali_gpu_core2 {
> compatible = "mediatek,gpu_core2";
> power-domains = < MT8183_POWER_DOMAIN_MFG_2D>;
> };
>
> So I picked core0/core1/2d as names, but looking at this, it's likely
> core2 is more appropriate (and MT8183_POWER_DOMAIN_MFG_2D might just
> be a internal/legacy name, if there is no real 2d domain).
>
> Thanks.
>
> > Rob
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
