Re: [PATCH v10 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Hi Laurent,
Thanks for the detailed review
I have addressed the review comments
and sent v11 of this series
On 15:32-20230102, Laurent Pinchart wrote:
> Hi Rahul,
>
> Thank you for the patch.
>
> On Mon, Jan 02, 2023 at 03:39:42PM +0530, Rahul T R wrote:
> > Add support for wrapper settings for DSI bridge on
> > j721e. Also enable DPI0
> >
> > --- ---
> > | ---| |--- |
> > | DSS | DPI2 |->| DPI0 | DSI Wrapper |
> > | ---| |--- |
> > --- ---
> >
> > As shown above DPI2 output of DSS is connected
> > to DPI0 input of DSI Wrapper, DSI wrapper
> > gives control wheather to enable/disable DPI0
> > input. In j721e above is the only configuration
> > supported
>
> You can also go up to 72 characters per line here :-)
>
> > Signed-off-by: Rahul T R
> > Reviewed-by: Tomi Valkeinen
> > ---
> > drivers/gpu/drm/bridge/cadence/Kconfig| 10
> > drivers/gpu/drm/bridge/cadence/Makefile | 1 +
> > .../gpu/drm/bridge/cadence/cdns-dsi-core.c| 35 -
> > .../gpu/drm/bridge/cadence/cdns-dsi-core.h| 13 +
> > .../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
> > .../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 ++
> > 6 files changed, 125 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> > create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> >
> > diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
> > b/drivers/gpu/drm/bridge/cadence/Kconfig
> > index 8fbb46c66094..f8ea0393fe8a 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> > +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> > @@ -36,3 +36,13 @@ config DRM_CDNS_DSI
> > help
> > Support Cadence DPI to DSI bridge. This is an internal
> > bridge and is meant to be directly embedded in a SoC.
> > +
> > +if DRM_CDNS_DSI
> > +
> > +config DRM_CDNS_DSI_J721E
> > + bool "J721E Cadence DSI wrapper support"
> > + default y
> > + help
> > + Support J721E Cadence DSI wrapper. The wrapper manages
> > + the routing of the DSS DPI signal to the Cadence DSI.
> > +endif
> > diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
> > b/drivers/gpu/drm/bridge/cadence/Makefile
> > index e3d8e9a40784..4cffc8ff71c4 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Makefile
> > +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> > @@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> > cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
> > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> > cdns-dsi-y := cdns-dsi-core.o
> > +cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > index cba91247ab26..a5b5dfbf09a0 100644
> > --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > @@ -15,12 +15,16 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > #include
> >
> > #include "cdns-dsi-core.h"
> > +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> > +#include "cdns-dsi-j721e.h"
> > +#endif
> >
> > static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
> > {
> > @@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
> > *bridge)
> >
> > val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
> > writel(val, dsi->regs + MCTL_MAIN_EN);
> > +
> > + if (dsi->platform_ops && dsi->platform_ops->disable)
> > + dsi->platform_ops->disable(dsi);
> > +
> > pm_runtime_put(dsi->base.dev);
> > }
> >
> > @@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
> > *bridge)
> > if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
> > return;
> >
> > + if (dsi->platform_ops && dsi->platform_ops->enable)
> > + dsi->platform_ops->enable(dsi);
> > +
> > mode = &bridge->encoder->crtc->state->adjusted_mode;
> > nlanes = output->dev->lanes;
> >
> > @@ -800
[PATCH v11 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
Move the cadence dsi bridge under drm/bridge/cadence directory, to
prepare for adding j721e wrapper support
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/Kconfig| 11 ---
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +++
drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
.../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c}| 0
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 57946d80b02d..8b2226f72b24 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_CDNS_DSI
- tristate "Cadence DPI/DSI bridge"
- select DRM_KMS_HELPER
- select DRM_MIPI_DSI
- select DRM_PANEL_BRIDGE
- select GENERIC_PHY_MIPI_DPHY
- depends on OF
- help
- Support Cadence DPI to DSI bridge. This is an internal
- bridge and is meant to be directly embedded in a SoC.
-
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1884803c6860..52f6e8b4a821 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..5f39859dcfdd 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -1,4 +1,15 @@
# SPDX-License-Identifier: GPL-2.0-only
+config DRM_CDNS_DSI
+ tristate "Cadence DPI/DSI bridge"
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ depends on OF
+ help
+ Support Cadence DPI to DSI bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+
config DRM_CDNS_MHDP8546
tristate "Cadence DPI/DP bridge"
select DRM_DISPLAY_DP_HELPER
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..9e2f34c84480 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+cdns-dsi-y := cdns-dsi-core.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
similarity index 100%
rename from drivers/gpu/drm/bridge/cdns-dsi.c
rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
--
2.39.0
[PATCH v11 1/5] dt-bindings: display: bridge: Convert cdns, dsi.txt to yaml
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++
2 files changed, 157 insertions(+), 112 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
deleted file mode 100644
index 525a4bfd8634..
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-Cadence DSI bridge
-==
-
-The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
-
-Required properties:
-- compatible: should be set to "cdns,dsi".
-- reg: physical base address and length of the controller's registers.
-- interrupts: interrupt line connected to the DSI bridge.
-- clocks: DSI bridge clocks.
-- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy".
-- #address-cells: must be set to 1.
-- #size-cells: must be set to 0.
-
-Optional properties:
-- resets: DSI reset lines.
-- reset-names: can contain "dsi_p_rst".
-
-Required subnodes:
-- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
- 2 ports are available:
- * port 0: this port is only needed if some of your DSI devices are
- controlled through an external bus like I2C or SPI. Can have at
- most 4 endpoints. The endpoint number is directly encoding the
- DSI virtual channel used by this device.
- * port 1: represents the DPI input.
- Other ports will be added later to support the new kind of inputs.
-
-- one subnode per DSI device connected on the DSI bus. Each DSI device should
- contain a reg property encoding its virtual channel.
-
-Example:
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy0>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
-
- panel: dsi-dev@0 {
- compatible = "";
- reg = <0>;
- };
- };
-
-or
-
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy1>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_panel_input>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
- };
-
- i2c@xxx {
- panel: panel@59 {
- compatible = "";
- reg = <0x59>;
-
- port {
- dsi_panel_input: endpoint {
- remote-endpoint = <&dsi0_output&
[PATCH v11 4/5] drm/bridge: cdns-dsi: Create a header file
Create a header file for cdns dsi and move structure definations to
prepare for adding j721e wrapper support
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 48 +-
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 64 +++
2 files changed, 66 insertions(+), 46 deletions(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index 20bece84ff8c..058349bfeb67 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -6,10 +6,7 @@
*/
#include
-#include
#include
-#include
-#include
#include
#include
@@ -23,9 +20,10 @@
#include
#include
-#include
#include
+#include "cdns-dsi-core.h"
+
#define IP_CONF0x0
#define SP_HS_FIFO_DEPTH(x)(((x) & GENMASK(30, 26)) >> 26)
#define SP_LP_FIFO_DEPTH(x)(((x) & GENMASK(25, 21)) >> 21)
@@ -424,48 +422,6 @@
#define DSI_NULL_FRAME_OVERHEAD6
#define DSI_EOT_PKT_SIZE 4
-struct cdns_dsi_output {
- struct mipi_dsi_device *dev;
- struct drm_panel *panel;
- struct drm_bridge *bridge;
- union phy_configure_opts phy_opts;
-};
-
-enum cdns_dsi_input_id {
- CDNS_SDI_INPUT,
- CDNS_DPI_INPUT,
- CDNS_DSC_INPUT,
-};
-
-struct cdns_dsi_cfg {
- unsigned int hfp;
- unsigned int hsa;
- unsigned int hbp;
- unsigned int hact;
- unsigned int htotal;
-};
-
-struct cdns_dsi_input {
- enum cdns_dsi_input_id id;
- struct drm_bridge bridge;
-};
-
-struct cdns_dsi {
- struct mipi_dsi_host base;
- void __iomem *regs;
- struct cdns_dsi_input input;
- struct cdns_dsi_output output;
- unsigned int direct_cmd_fifo_depth;
- unsigned int rx_fifo_depth;
- struct completion direct_cmd_comp;
- struct clk *dsi_p_clk;
- struct reset_control *dsi_p_rst;
- struct clk *dsi_sys_clk;
- bool link_initialized;
- bool phy_initialized;
- struct phy *dphy;
-};
-
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
return container_of(input, struct cdns_dsi, input);
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
new file mode 100644
index ..d5bb5caf77b1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright: 2017 Cadence Design Systems, Inc.
+ *
+ * Author: Boris Brezillon
+ */
+
+#ifndef __CDNS_DSI_H__
+#define __CDNS_DSI_H__
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+struct clk;
+struct reset_control;
+
+struct cdns_dsi_output {
+ struct mipi_dsi_device *dev;
+ struct drm_panel *panel;
+ struct drm_bridge *bridge;
+ union phy_configure_opts phy_opts;
+};
+
+enum cdns_dsi_input_id {
+ CDNS_SDI_INPUT,
+ CDNS_DPI_INPUT,
+ CDNS_DSC_INPUT,
+};
+
+struct cdns_dsi_cfg {
+ unsigned int hfp;
+ unsigned int hsa;
+ unsigned int hbp;
+ unsigned int hact;
+ unsigned int htotal;
+};
+
+struct cdns_dsi_input {
+ enum cdns_dsi_input_id id;
+ struct drm_bridge bridge;
+};
+
+struct cdns_dsi {
+ struct mipi_dsi_host base;
+ void __iomem *regs;
+ struct cdns_dsi_input input;
+ struct cdns_dsi_output output;
+ unsigned int direct_cmd_fifo_depth;
+ unsigned int rx_fifo_depth;
+ struct completion direct_cmd_comp;
+ struct clk *dsi_p_clk;
+ struct reset_control *dsi_p_rst;
+ struct clk *dsi_sys_clk;
+ bool link_initialized;
+ bool phy_initialized;
+ struct phy *dphy;
+};
+
+#endif /* !__CDNS_DSI_H__ */
--
2.39.0
[PATCH v11 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Add support for wrapper settings for DSI bridge on j721e. Also enable
DPI0
--- ---
| ---| |--- |
| DSS | DPI2 |->| DPI0 | DSI Wrapper |
| ---| |--- |
--- ---
As shown above DPI2 output of DSS is connected to DPI0 input of DSI
Wrapper, DSI wrapper gives control wheather to enable/disable DPI0
input. In j721e above is the only configuration supported
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/cadence/Kconfig| 10
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 35 -
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 20
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 ++
6 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 5f39859dcfdd..ec35215a2003 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -10,6 +10,16 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DSI wrapper. The wrapper manages
+ the routing of the DSS DPI signal to the Cadence DSI.
+endif
+
config DRM_CDNS_MHDP8546
tristate "Cadence DPI/DP bridge"
select DRM_DISPLAY_DP_HELPER
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 9e2f34c84480..c95fd5b81d13 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index 058349bfeb67..5dbfc7226b31 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -23,6 +24,9 @@
#include
#include "cdns-dsi-core.h"
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+#include "cdns-dsi-j721e.h"
+#endif
#define IP_CONF0x0
#define SP_HS_FIFO_DEPTH(x)(((x) & GENMASK(30, 26)) >> 26)
@@ -665,6 +669,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
*bridge)
val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
writel(val, dsi->regs + MCTL_MAIN_EN);
+
+ if (dsi->platform_ops && dsi->platform_ops->disable)
+ dsi->platform_ops->disable(dsi);
+
pm_runtime_put(dsi->base.dev);
}
@@ -760,6 +768,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
*bridge)
if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
return;
+ if (dsi->platform_ops && dsi->platform_ops->enable)
+ dsi->platform_ops->enable(dsi);
+
mode = &bridge->encoder->crtc->state->adjusted_mode;
nlanes = output->dev->lanes;
@@ -1200,6 +1211,8 @@ static int cdns_dsi_drm_probe(struct platform_device
*pdev)
goto err_disable_pclk;
}
+ dsi->platform_ops = of_device_get_match_data(&pdev->dev);
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
@@ -1235,14 +1248,27 @@ static int cdns_dsi_drm_probe(struct platform_device
*pdev)
dsi->base.dev = &pdev->dev;
dsi->base.ops = &cdns_dsi_ops;
+ if (dsi->platform_ops && dsi->platform_ops->init) {
+ ret = dsi->platform_ops->init(dsi);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "platform initialization failed:
%d\n",
+ ret);
+ goto err_disable_runtime_pm;
+ }
+ }
+
ret = mipi_dsi_host_register(&dsi->base);
[PATCH v11 2/5] dt-bindings: display: bridge: cdns, dsi: Add compatible for dsi on j721e
Add compatible to support dsi bridge on j721e Signed-off-by: Rahul T R Reviewed-by: Rob Herring Reviewed-by: Laurent Pinchart --- .../bindings/display/bridge/cdns,dsi.yaml | 25 ++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 3161c33093c1..23060324d16e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -16,9 +16,15 @@ properties: compatible: enum: - cdns,dsi + - ti,j721e-dsi reg: -maxItems: 1 +minItems: 1 +items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. clocks: items: @@ -67,6 +73,23 @@ properties: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: ti,j721e-dsi +then: + properties: +reg: + minItems: 2 + maxItems: 2 +power-domains: + maxItems: 1 +else: + properties: +reg: + maxItems: 1 + required: - compatible - reg -- 2.39.0
[PATCH v11 0/5] Add support for CDNS DSI J721E wrapper
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v11:
- Wrap commmit messages at 72 chars
- Fix the order in Kconfig and Makefile
- Clean up the includes, move macros and some headers to .c file
- Add missing forward declarations
- Add __ prefix to header gaurds
- Change dsi_platform_ops to cdns_dsi_platform_ops
- Add documentation to struct cdns_dsi_platform_ops
v10:
- Rebased to v6.2-rc1
- Accumulated the Reviewed-by acks
v9:
- Fixed below based on review comments in v8
- Added more info on wrapper in the commit message
- Fixed the description in Kconfig
- Fixed the formatting of of_match table
- exit -> deinit in platform ops
- Remove duplicate of struct declaration in cdns-dsi-j721e.h
v8:
- Rebased to 6.1-rc1
v7:
- Rebased to next-20220920
- Accumulated the Reviewed-by acks
v6:
- Dropped generic definations for properties like reg, resets etc..
- Fixed the defination for port@0 and port@1
- removed the ti,sn65dsi86 node from the example, which is not related
v5:
- Remove power-domain property in the conversion commit
- Add power-domain only for j721e compatible
- Fix white space error in one of the commit
v4:
- split conversion txt to yaml
- seperate commit for addinig new compatible
- conditionally limit the items for reg property, based on the compatible
v3:
- Convert cdns-dsi.txt binding to yaml
- Move the bridge under display/bridge/cadence
- Add new compatible to enable the wrapper module
v2:
- Moved setting DPI0 to bridge_enable, since it
should be done after pm_runtime_get
Rahul T R (5):
dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on
j721e
drm/bridge: cdns-dsi: Move to drm/bridge/cadence
drm/bridge: cdns-dsi: Create a header file
drm/bridge: cdns-dsi: Add support for J721E wrapper
.../bindings/display/bridge/cdns,dsi.txt | 112 ---
.../bindings/display/bridge/cdns,dsi.yaml | 180 ++
drivers/gpu/drm/bridge/Kconfig| 11 --
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 21 ++
drivers/gpu/drm/bridge/cadence/Makefile | 3 +
.../{cdns-dsi.c => cadence/cdns-dsi-core.c} | 83
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 84
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 ++
10 files changed, 391 insertions(+), 171 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (97%)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
--
2.39.0
[PATCH v10 0/5] Add support for CDNS DSI J721E wrapper
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v10:
- Rebased to v6.2-rc1
- Accumulated the Reviewed-by acks
v9:
- Fixed below based on review comments in v8
- Added more info on wrapper in the commit message
- Fixed the description in Kconfig
- Fixed the formatting of of_match table
- exit -> deinit in platform ops
- Remove duplicate of struct declaration in cdns-dsi-j721e.h
v8:
- Rebased to 6.1-rc1
v7:
- Rebased to next-20220920
- Accumulated the Reviewed-by acks
v6:
- Dropped generic definations for properties like reg, resets etc..
- Fixed the defination for port@0 and port@1
- removed the ti,sn65dsi86 node from the example, which is not related
v5:
- Remove power-domain property in the conversion commit
- Add power-domain only for j721e compatible
- Fix white space error in one of the commit
v4:
- split conversion txt to yaml
- seperate commit for addinig new compatible
- conditionally limit the items for reg property, based on the compatible
v3:
- Convert cdns-dsi.txt binding to yaml
- Move the bridge under display/bridge/cadence
- Add new compatible to enable the wrapper module
v2:
- Moved setting DPI0 to bridge_enable, since it
should be done after pm_runtime_get
Rahul T R (5):
dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on
j721e
drm/bridge: cdns-dsi: Move to drm/bridge/cadence
drm/bridge: cdns-dsi: Create a header file
drm/bridge: cdns-dsi: Add support for J721E wrapper
.../bindings/display/bridge/cdns,dsi.txt | 112
.../bindings/display/bridge/cdns,dsi.yaml | 180 +++
drivers/gpu/drm/bridge/Kconfig| 11 -
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 21 +
drivers/gpu/drm/bridge/cadence/Makefile | 3 +
.../{cdns-dsi.c => cadence/cdns-dsi-core.c} | 481 ++
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 471 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 ++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 +
10 files changed, 777 insertions(+), 570 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (65%)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
--
2.39.0
[PATCH v10 2/5] dt-bindings: display: bridge: cdns, dsi: Add compatible for dsi on j721e
Add compatible to support dsi bridge on j721e Signed-off-by: Rahul T R Reviewed-by: Rob Herring --- .../bindings/display/bridge/cdns,dsi.yaml | 25 ++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 3161c33093c1..23060324d16e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -16,9 +16,15 @@ properties: compatible: enum: - cdns,dsi + - ti,j721e-dsi reg: -maxItems: 1 +minItems: 1 +items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. clocks: items: @@ -67,6 +73,23 @@ properties: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: ti,j721e-dsi +then: + properties: +reg: + minItems: 2 + maxItems: 2 +power-domains: + maxItems: 1 +else: + properties: +reg: + maxItems: 1 + required: - compatible - reg -- 2.39.0
[PATCH v10 4/5] drm/bridge: cdns-dsi: Create a header file
Create a header file for cdns dsi and move register offsets and structure to header, to prepare for adding j721e wrapper support Signed-off-by: Rahul T R Reviewed-by: Tomi Valkeinen --- .../gpu/drm/bridge/cadence/cdns-dsi-core.c| 446 + .../gpu/drm/bridge/cadence/cdns-dsi-core.h| 458 ++ 2 files changed, 459 insertions(+), 445 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index 20bece84ff8c..cba91247ab26 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -6,10 +6,7 @@ */ #include -#include #include -#include -#include #include #include @@ -23,448 +20,7 @@ #include #include -#include -#include - -#define IP_CONF0x0 -#define SP_HS_FIFO_DEPTH(x)(((x) & GENMASK(30, 26)) >> 26) -#define SP_LP_FIFO_DEPTH(x)(((x) & GENMASK(25, 21)) >> 21) -#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16) -#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13) -#define SDI_IFACE_32 BIT(12) -#define INTERNAL_DATAPATH_32 (0 << 10) -#define INTERNAL_DATAPATH_16 (1 << 10) -#define INTERNAL_DATAPATH_8(3 << 10) -#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10)) -#define NUM_IFACE(x) x) & GENMASK(9, 8)) >> 8) + 1) -#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6) -#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0)) - -#define MCTL_MAIN_DATA_CTL 0x4 -#define TE_MIPI_POLLING_EN BIT(25) -#define TE_HW_POLLING_EN BIT(24) -#define DISP_EOT_GEN BIT(18) -#define HOST_EOT_GEN BIT(17) -#define DISP_GEN_CHECKSUM BIT(16) -#define DISP_GEN_ECC BIT(15) -#define BTA_EN BIT(14) -#define READ_ENBIT(13) -#define REG_TE_EN BIT(12) -#define IF_TE_EN(x)BIT(8 + (x)) -#define TVG_SELBIT(6) -#define VID_EN BIT(5) -#define IF_VID_SELECT(x) ((x) << 2) -#define IF_VID_SELECT_MASK GENMASK(3, 2) -#define IF_VID_MODEBIT(1) -#define LINK_ENBIT(0) - -#define MCTL_MAIN_PHY_CTL 0x8 -#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2)) -#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2)) -#define HS_INVERT_CLK BIT(17) -#define SWAP_PINS_CLK BIT(16) -#define HS_SKEWCAL_EN BIT(15) -#define WAIT_BURST_TIME(x) ((x) << 10) -#define DATA_ULPM_EN(x)BIT(6 + (x)) -#define CLK_ULPM_ENBIT(5) -#define CLK_CONTINUOUS BIT(4) -#define DATA_LANE_EN(x)BIT((x) - 1) - -#define MCTL_MAIN_EN 0xc -#define DATA_FORCE_STOPBIT(17) -#define CLK_FORCE_STOP BIT(16) -#define IF_EN(x) BIT(13 + (x)) -#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l)) -#define CLK_LANE_ULPM_REQ BIT(8) -#define DATA_LANE_START(x) BIT(4 + (x)) -#define CLK_LANE_ENBIT(3) -#define PLL_START BIT(0) - -#define MCTL_DPHY_CFG0 0x10 -#define DPHY_C_RSTBBIT(20) -#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16) -#define DPHY_PLL_PDN BIT(10) -#define DPHY_CMN_PDN BIT(9) -#define DPHY_C_PDN BIT(8) -#define DPHY_D_PDN(x) GENMASK(3 + (x), 4) -#define DPHY_ALL_D_PDN GENMASK(7, 4) -#define DPHY_PLL_PSO BIT(1) -#define DPHY_CMN_PSO BIT(0) - -#define MCTL_DPHY_TIMEOUT1 0x14 -#define HSTX_TIMEOUT(x)((x) << 4) -#define HSTX_TIMEOUT_MAX GENMASK(17, 0) -#define CLK_DIV(x) (x) -#define CLK_DIV_MAXGENMASK(3, 0) - -#define MCTL_DPHY_TIMEOUT2 0x18 -#define LPRX_TIMEOUT(x)(x) - -#define MCTL_ULPOUT_TIME 0x1c -#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9) -#define CLK_LANE_ULPOUT_TIME(x)(x) - -#define MCTL_3DVIDEO_CTL 0x20 -#define VID_VSYNC_3D_ENBIT(7) -#define VID_VSYNC_3D_LRBIT(5) -#define VID_VSYNC_3D_SECOND_EN BIT(4) -#define VID_VSYNC_3DFORMAT_LINE(0 << 2) -#define VID_VSYNC_3DFORMAT_FRAM
[PATCH v10 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Add support for wrapper settings for DSI bridge on
j721e. Also enable DPI0
--- ---
| ---| |--- |
| DSS | DPI2 |->| DPI0 | DSI Wrapper |
| ---| |--- |
--- ---
As shown above DPI2 output of DSS is connected
to DPI0 input of DSI Wrapper, DSI wrapper
gives control wheather to enable/disable DPI0
input. In j721e above is the only configuration
supported
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/cadence/Kconfig| 10
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 35 -
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 13 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 ++
6 files changed, 125 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 8fbb46c66094..f8ea0393fe8a 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -36,3 +36,13 @@ config DRM_CDNS_DSI
help
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DSI wrapper. The wrapper manages
+ the routing of the DSS DPI signal to the Cadence DSI.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index e3d8e9a40784..4cffc8ff71c4 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index cba91247ab26..a5b5dfbf09a0 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -15,12 +15,16 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include "cdns-dsi-core.h"
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+#include "cdns-dsi-j721e.h"
+#endif
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
@@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
*bridge)
val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
writel(val, dsi->regs + MCTL_MAIN_EN);
+
+ if (dsi->platform_ops && dsi->platform_ops->disable)
+ dsi->platform_ops->disable(dsi);
+
pm_runtime_put(dsi->base.dev);
}
@@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
*bridge)
if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
return;
+ if (dsi->platform_ops && dsi->platform_ops->enable)
+ dsi->platform_ops->enable(dsi);
+
mode = &bridge->encoder->crtc->state->adjusted_mode;
nlanes = output->dev->lanes;
@@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
goto err_disable_pclk;
}
+ dsi->platform_ops = of_device_get_match_data(&pdev->dev);
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
@@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device
*pdev)
dsi->base.dev = &pdev->dev;
dsi->base.ops = &cdns_dsi_ops;
+ if (dsi->platform_ops && dsi->platform_ops->init) {
+ ret = dsi->platform_ops->init(dsi);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "platform initialization failed:
%d\n",
+ ret);
+ goto err_disable_runtime_pm;
+ }
+ }
+
ret = mipi_dsi_host_register(&dsi->base);
if (ret)
- goto err_disable_runtime_pm;
+ goto err_deinit_platform;
clk_disable_unprepare(dsi->dsi_p_clk);
return 0;
+err_deinit_platform:
+ if (dsi->platform_ops && dsi->platform_ops->dein
[PATCH v10 1/5] dt-bindings: display: bridge: Convert cdns, dsi.txt to yaml
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++
2 files changed, 157 insertions(+), 112 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
deleted file mode 100644
index 525a4bfd8634..
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-Cadence DSI bridge
-==
-
-The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
-
-Required properties:
-- compatible: should be set to "cdns,dsi".
-- reg: physical base address and length of the controller's registers.
-- interrupts: interrupt line connected to the DSI bridge.
-- clocks: DSI bridge clocks.
-- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy".
-- #address-cells: must be set to 1.
-- #size-cells: must be set to 0.
-
-Optional properties:
-- resets: DSI reset lines.
-- reset-names: can contain "dsi_p_rst".
-
-Required subnodes:
-- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
- 2 ports are available:
- * port 0: this port is only needed if some of your DSI devices are
- controlled through an external bus like I2C or SPI. Can have at
- most 4 endpoints. The endpoint number is directly encoding the
- DSI virtual channel used by this device.
- * port 1: represents the DPI input.
- Other ports will be added later to support the new kind of inputs.
-
-- one subnode per DSI device connected on the DSI bus. Each DSI device should
- contain a reg property encoding its virtual channel.
-
-Example:
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy0>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
-
- panel: dsi-dev@0 {
- compatible = "";
- reg = <0>;
- };
- };
-
-or
-
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy1>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_panel_input>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
- };
-
- i2c@xxx {
- panel: panel@59 {
- compatible = "";
- reg = <0x59>;
-
- port {
- dsi_panel_input: endpoint {
- remote-endpoint = <&dsi0_output>;
-
[PATCH v10 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
Move the cadence dsi bridge under drm/bridge/cadence
directory, to prepare for adding j721e wrapper
support
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/Kconfig| 11 ---
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +++
drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
.../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c}| 0
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 57946d80b02d..8b2226f72b24 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_CDNS_DSI
- tristate "Cadence DPI/DSI bridge"
- select DRM_KMS_HELPER
- select DRM_MIPI_DSI
- select DRM_PANEL_BRIDGE
- select GENERIC_PHY_MIPI_DPHY
- depends on OF
- help
- Support Cadence DPI to DSI bridge. This is an internal
- bridge and is meant to be directly embedded in a SoC.
-
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1884803c6860..52f6e8b4a821 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..8fbb46c66094 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -25,3 +25,14 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_DSI
+ tristate "Cadence DPI/DSI bridge"
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ depends on OF
+ help
+ Support Cadence DPI to DSI bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..e3d8e9a40784 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,3 +2,5 @@
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+cdns-dsi-y := cdns-dsi-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
similarity index 100%
rename from drivers/gpu/drm/bridge/cdns-dsi.c
rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
--
2.39.0
[PATCH] drm/bridge: cdns-dsi: Fix issue with phy init
Phy is not being initialized after suspend resume. Fix this by setting phy_initialized flag to false in suspend callback Signed-off-by: Rahul T R --- drivers/gpu/drm/bridge/cdns-dsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c b/drivers/gpu/drm/bridge/cdns-dsi.c index 20bece84ff8c..1a988f53424a 100644 --- a/drivers/gpu/drm/bridge/cdns-dsi.c +++ b/drivers/gpu/drm/bridge/cdns-dsi.c @@ -1187,6 +1187,7 @@ static int __maybe_unused cdns_dsi_suspend(struct device *dev) clk_disable_unprepare(dsi->dsi_p_clk); reset_control_assert(dsi->dsi_p_rst); dsi->link_initialized = false; + dsi->phy_initialized = false; return 0; } -- 2.38.0
Re: [PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Hi Tomi,
On 09:12-20221026, Tomi Valkeinen wrote:
> Hi,
>
> On 21/10/2022 20:18, Rahul T R wrote:
> > Add support for wrapper settings for DSI bridge on
> > j721e. Also set the DPI input to DPI0
>
> I think a few more words on the HW layout would be nice. What does the
> wrapper do and how is it connected to the DSS.
>
> > Signed-off-by: Rahul T R
> > ---
> > drivers/gpu/drm/bridge/cadence/Kconfig| 10
> > drivers/gpu/drm/bridge/cadence/Makefile | 1 +
> > .../gpu/drm/bridge/cadence/cdns-dsi-core.c| 37 +-
> > .../gpu/drm/bridge/cadence/cdns-dsi-core.h| 13 +
> > .../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
> > .../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +++
> > 6 files changed, 129 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
> > create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
> >
> > diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
> > b/drivers/gpu/drm/bridge/cadence/Kconfig
> > index 8fbb46c66094..663a02d96420 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> > +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> > @@ -36,3 +36,13 @@ config DRM_CDNS_DSI
> > help
> > Support Cadence DPI to DSI bridge. This is an internal
> > bridge and is meant to be directly embedded in a SoC.
> > +
> > +if DRM_CDNS_DSI
> > +
> > +config DRM_CDNS_DSI_J721E
> > + bool "J721E Cadence DPI/DSI wrapper support"
> > + default y
> > + help
> > + Support J721E Cadence DPI/DSI wrapper. This wrapper adds
> > + support to select which DPI input to use for the bridge.
>
> I'm not sure if the above is quite necessary here. If I understand right,
> there's only one way on J721E to mux the DPI signal going to the DSI. If you
> write "adds support to select DPI input" it sounds like there's something to
> select, and this config somehow enables that selection for the user.
>
> Perhaps instead just say something like "Support J721E Cadence DPI/DSI
> wrapper. The wrapper manages the routing of the DSS DPI signal to the
> Cadence DSI.", or something along those lines.
>
> Also, you say "DPI/DSI wrapper". How does this wrap DPI? Isn't this just a
> DSI wrapper?
>
> > +endif
> > diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
> > b/drivers/gpu/drm/bridge/cadence/Makefile
> > index e3d8e9a40784..4cffc8ff71c4 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Makefile
> > +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> > @@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> > cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
> > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
> > cdns-dsi-y := cdns-dsi-core.o
> > +cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > index cba91247ab26..4b7de38ef1b0 100644
> > --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
> > @@ -15,12 +15,16 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > #include
> > #include "cdns-dsi-core.h"
> > +#ifdef CONFIG_DRM_CDNS_DSI_J721E
> > +#include "cdns-dsi-j721e.h"
> > +#endif
> > static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
> > {
> > @@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
> > *bridge)
> > val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
> > writel(val, dsi->regs + MCTL_MAIN_EN);
> > +
> > + if (dsi->platform_ops && dsi->platform_ops->disable)
> > + dsi->platform_ops->disable(dsi);
> > +
> > pm_runtime_put(dsi->base.dev);
> > }
> > @@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
> > *bridge)
> > if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
> > return;
> > + if (dsi->platform_ops && dsi->platform_ops->enable)
> > + dsi->platform_ops->enable(dsi);
> > +
> > mode = &bridge->encoder->crtc->state->adjusted_mode;
> > nlanes = output->dev->lanes;
> > @@ -800,6 +811,8 @@
[PATCH v9 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
Move the cadence dsi bridge under drm/bridge/cadence
directory, to prepare for adding j721e wrapper
support
Signed-off-by: Rahul T R
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/Kconfig| 11 ---
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +++
drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
.../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c}| 0
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 57946d80b02d..8b2226f72b24 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_CDNS_DSI
- tristate "Cadence DPI/DSI bridge"
- select DRM_KMS_HELPER
- select DRM_MIPI_DSI
- select DRM_PANEL_BRIDGE
- select GENERIC_PHY_MIPI_DPHY
- depends on OF
- help
- Support Cadence DPI to DSI bridge. This is an internal
- bridge and is meant to be directly embedded in a SoC.
-
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1884803c6860..52f6e8b4a821 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..8fbb46c66094 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -25,3 +25,14 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_DSI
+ tristate "Cadence DPI/DSI bridge"
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ depends on OF
+ help
+ Support Cadence DPI to DSI bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..e3d8e9a40784 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,3 +2,5 @@
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+cdns-dsi-y := cdns-dsi-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
similarity index 100%
rename from drivers/gpu/drm/bridge/cdns-dsi.c
rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
--
2.38.0
[PATCH v9 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Add support for wrapper settings for DSI bridge on
j721e. Also enable DPI0
--- ---
| ---| |--- |
| DSS | DPI2 |->| DPI0 | DSI Wrapper |
| ---| |--- |
--- ---
As shown above DPI2 output of DSS is connected
to DPI0 input of DSI Wrapper, DSI wrapper
gives control wheather to enable/disable DPI0
input. In j721e above is the only configuration
supported
Signed-off-by: Rahul T R
---
drivers/gpu/drm/bridge/cadence/Kconfig| 10
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 35 -
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 13 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 ++
6 files changed, 125 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 8fbb46c66094..f8ea0393fe8a 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -36,3 +36,13 @@ config DRM_CDNS_DSI
help
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DSI wrapper. The wrapper manages
+ the routing of the DSS DPI signal to the Cadence DSI.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index e3d8e9a40784..4cffc8ff71c4 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index cba91247ab26..a5b5dfbf09a0 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -15,12 +15,16 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include "cdns-dsi-core.h"
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+#include "cdns-dsi-j721e.h"
+#endif
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
@@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
*bridge)
val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
writel(val, dsi->regs + MCTL_MAIN_EN);
+
+ if (dsi->platform_ops && dsi->platform_ops->disable)
+ dsi->platform_ops->disable(dsi);
+
pm_runtime_put(dsi->base.dev);
}
@@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
*bridge)
if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
return;
+ if (dsi->platform_ops && dsi->platform_ops->enable)
+ dsi->platform_ops->enable(dsi);
+
mode = &bridge->encoder->crtc->state->adjusted_mode;
nlanes = output->dev->lanes;
@@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
goto err_disable_pclk;
}
+ dsi->platform_ops = of_device_get_match_data(&pdev->dev);
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
@@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device
*pdev)
dsi->base.dev = &pdev->dev;
dsi->base.ops = &cdns_dsi_ops;
+ if (dsi->platform_ops && dsi->platform_ops->init) {
+ ret = dsi->platform_ops->init(dsi);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "platform initialization failed:
%d\n",
+ ret);
+ goto err_disable_runtime_pm;
+ }
+ }
+
ret = mipi_dsi_host_register(&dsi->base);
if (ret)
- goto err_disable_runtime_pm;
+ goto err_deinit_platform;
clk_disable_unprepare(dsi->dsi_p_clk);
return 0;
+err_deinit_platform:
+ if (dsi->platform_ops && dsi->platform_ops->deinit)
+ dsi->
[PATCH v9 2/5] dt-bindings: display: bridge: cdns, dsi: Add compatible for dsi on j721e
Add compatible to support dsi bridge on j721e Signed-off-by: Rahul T R Reviewed-by: Rob Herring --- .../bindings/display/bridge/cdns,dsi.yaml | 25 ++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 3161c33093c1..23060324d16e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -16,9 +16,15 @@ properties: compatible: enum: - cdns,dsi + - ti,j721e-dsi reg: -maxItems: 1 +minItems: 1 +items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. clocks: items: @@ -67,6 +73,23 @@ properties: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: ti,j721e-dsi +then: + properties: +reg: + minItems: 2 + maxItems: 2 +power-domains: + maxItems: 1 +else: + properties: +reg: + maxItems: 1 + required: - compatible - reg -- 2.38.0
[PATCH v9 4/5] drm/bridge: cdns-dsi: Create a header file
Create a header file for cdns dsi and move register offsets and structure to header, to prepare for adding j721e wrapper support Signed-off-by: Rahul T R Reviewed-by: Tomi Valkeinen --- .../gpu/drm/bridge/cadence/cdns-dsi-core.c| 446 + .../gpu/drm/bridge/cadence/cdns-dsi-core.h| 458 ++ 2 files changed, 459 insertions(+), 445 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index 20bece84ff8c..cba91247ab26 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -6,10 +6,7 @@ */ #include -#include #include -#include -#include #include #include @@ -23,448 +20,7 @@ #include #include -#include -#include - -#define IP_CONF0x0 -#define SP_HS_FIFO_DEPTH(x)(((x) & GENMASK(30, 26)) >> 26) -#define SP_LP_FIFO_DEPTH(x)(((x) & GENMASK(25, 21)) >> 21) -#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16) -#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13) -#define SDI_IFACE_32 BIT(12) -#define INTERNAL_DATAPATH_32 (0 << 10) -#define INTERNAL_DATAPATH_16 (1 << 10) -#define INTERNAL_DATAPATH_8(3 << 10) -#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10)) -#define NUM_IFACE(x) x) & GENMASK(9, 8)) >> 8) + 1) -#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6) -#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0)) - -#define MCTL_MAIN_DATA_CTL 0x4 -#define TE_MIPI_POLLING_EN BIT(25) -#define TE_HW_POLLING_EN BIT(24) -#define DISP_EOT_GEN BIT(18) -#define HOST_EOT_GEN BIT(17) -#define DISP_GEN_CHECKSUM BIT(16) -#define DISP_GEN_ECC BIT(15) -#define BTA_EN BIT(14) -#define READ_ENBIT(13) -#define REG_TE_EN BIT(12) -#define IF_TE_EN(x)BIT(8 + (x)) -#define TVG_SELBIT(6) -#define VID_EN BIT(5) -#define IF_VID_SELECT(x) ((x) << 2) -#define IF_VID_SELECT_MASK GENMASK(3, 2) -#define IF_VID_MODEBIT(1) -#define LINK_ENBIT(0) - -#define MCTL_MAIN_PHY_CTL 0x8 -#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2)) -#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2)) -#define HS_INVERT_CLK BIT(17) -#define SWAP_PINS_CLK BIT(16) -#define HS_SKEWCAL_EN BIT(15) -#define WAIT_BURST_TIME(x) ((x) << 10) -#define DATA_ULPM_EN(x)BIT(6 + (x)) -#define CLK_ULPM_ENBIT(5) -#define CLK_CONTINUOUS BIT(4) -#define DATA_LANE_EN(x)BIT((x) - 1) - -#define MCTL_MAIN_EN 0xc -#define DATA_FORCE_STOPBIT(17) -#define CLK_FORCE_STOP BIT(16) -#define IF_EN(x) BIT(13 + (x)) -#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l)) -#define CLK_LANE_ULPM_REQ BIT(8) -#define DATA_LANE_START(x) BIT(4 + (x)) -#define CLK_LANE_ENBIT(3) -#define PLL_START BIT(0) - -#define MCTL_DPHY_CFG0 0x10 -#define DPHY_C_RSTBBIT(20) -#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16) -#define DPHY_PLL_PDN BIT(10) -#define DPHY_CMN_PDN BIT(9) -#define DPHY_C_PDN BIT(8) -#define DPHY_D_PDN(x) GENMASK(3 + (x), 4) -#define DPHY_ALL_D_PDN GENMASK(7, 4) -#define DPHY_PLL_PSO BIT(1) -#define DPHY_CMN_PSO BIT(0) - -#define MCTL_DPHY_TIMEOUT1 0x14 -#define HSTX_TIMEOUT(x)((x) << 4) -#define HSTX_TIMEOUT_MAX GENMASK(17, 0) -#define CLK_DIV(x) (x) -#define CLK_DIV_MAXGENMASK(3, 0) - -#define MCTL_DPHY_TIMEOUT2 0x18 -#define LPRX_TIMEOUT(x)(x) - -#define MCTL_ULPOUT_TIME 0x1c -#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9) -#define CLK_LANE_ULPOUT_TIME(x)(x) - -#define MCTL_3DVIDEO_CTL 0x20 -#define VID_VSYNC_3D_ENBIT(7) -#define VID_VSYNC_3D_LRBIT(5) -#define VID_VSYNC_3D_SECOND_EN BIT(4) -#define VID_VSYNC_3DFORMAT_LINE(0 << 2) -#define VID_VSYNC_3DFORMAT_FRAM
[PATCH v9 0/5] Add support for CDNS DSI J721E wrapper
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v9:
- Fixed below based on review comments in v8
- Added more info on wrapper in the commit message
- Fixed the description in Kconfig
- Fixed the formatting of of_match table
- exit -> deinit in platform ops
- Remove duplicate of struct declaration in cdns-dsi-j721e.h
v8:
- Rebased to 6.1-rc1
v7:
- Rebased to next-20220920
- Accumulated the Reviewed-by acks
v6:
- Dropped generic definations for properties like reg, resets etc..
- Fixed the defination for port@0 and port@1
- removed the ti,sn65dsi86 node from the example, which is not related
v5:
- Remove power-domain property in the conversion commit
- Add power-domain only for j721e compatible
- Fix white space error in one of the commit
v4:
- split conversion txt to yaml
- seperate commit for addinig new compatible
- conditionally limit the items for reg property, based on the compatible
v3:
- Convert cdns-dsi.txt binding to yaml
- Move the bridge under display/bridge/cadence
- Add new compatible to enable the wrapper module
v2:
- Moved setting DPI0 to bridge_enable, since it
should be done after pm_runtime_get
Rahul T R (5):
dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on
j721e
drm/bridge: cdns-dsi: Move to drm/bridge/cadence
drm/bridge: cdns-dsi: Create a header file
drm/bridge: cdns-dsi: Add support for J721E wrapper
.../bindings/display/bridge/cdns,dsi.txt | 112
.../bindings/display/bridge/cdns,dsi.yaml | 180 +++
drivers/gpu/drm/bridge/Kconfig| 11 -
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 21 +
drivers/gpu/drm/bridge/cadence/Makefile | 3 +
.../{cdns-dsi.c => cadence/cdns-dsi-core.c} | 481 ++
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 471 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 ++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 16 +
10 files changed, 777 insertions(+), 570 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (65%)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
--
2.38.0
[PATCH v9 1/5] dt-bindings: display: bridge: Convert cdns, dsi.txt to yaml
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++
2 files changed, 157 insertions(+), 112 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
deleted file mode 100644
index 525a4bfd8634..
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-Cadence DSI bridge
-==
-
-The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
-
-Required properties:
-- compatible: should be set to "cdns,dsi".
-- reg: physical base address and length of the controller's registers.
-- interrupts: interrupt line connected to the DSI bridge.
-- clocks: DSI bridge clocks.
-- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy".
-- #address-cells: must be set to 1.
-- #size-cells: must be set to 0.
-
-Optional properties:
-- resets: DSI reset lines.
-- reset-names: can contain "dsi_p_rst".
-
-Required subnodes:
-- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
- 2 ports are available:
- * port 0: this port is only needed if some of your DSI devices are
- controlled through an external bus like I2C or SPI. Can have at
- most 4 endpoints. The endpoint number is directly encoding the
- DSI virtual channel used by this device.
- * port 1: represents the DPI input.
- Other ports will be added later to support the new kind of inputs.
-
-- one subnode per DSI device connected on the DSI bus. Each DSI device should
- contain a reg property encoding its virtual channel.
-
-Example:
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy0>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
-
- panel: dsi-dev@0 {
- compatible = "";
- reg = <0>;
- };
- };
-
-or
-
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy1>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_panel_input>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
- };
-
- i2c@xxx {
- panel: panel@59 {
- compatible = "";
- reg = <0x59>;
-
- port {
- dsi_panel_input: endpoint {
- remote-endpoint = <&dsi0_output>;
-
[PATCH v8 4/5] drm/bridge: cdns-dsi: Create a header file
Create a header file for cdns dsi and move register offsets and structure to header, to prepare for adding j721e wrapper support Signed-off-by: Rahul T R --- .../gpu/drm/bridge/cadence/cdns-dsi-core.c| 446 + .../gpu/drm/bridge/cadence/cdns-dsi-core.h| 458 ++ 2 files changed, 459 insertions(+), 445 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index 20bece84ff8c..cba91247ab26 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -6,10 +6,7 @@ */ #include -#include #include -#include -#include #include #include @@ -23,448 +20,7 @@ #include #include -#include -#include - -#define IP_CONF0x0 -#define SP_HS_FIFO_DEPTH(x)(((x) & GENMASK(30, 26)) >> 26) -#define SP_LP_FIFO_DEPTH(x)(((x) & GENMASK(25, 21)) >> 21) -#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16) -#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13) -#define SDI_IFACE_32 BIT(12) -#define INTERNAL_DATAPATH_32 (0 << 10) -#define INTERNAL_DATAPATH_16 (1 << 10) -#define INTERNAL_DATAPATH_8(3 << 10) -#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10)) -#define NUM_IFACE(x) x) & GENMASK(9, 8)) >> 8) + 1) -#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6) -#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0)) - -#define MCTL_MAIN_DATA_CTL 0x4 -#define TE_MIPI_POLLING_EN BIT(25) -#define TE_HW_POLLING_EN BIT(24) -#define DISP_EOT_GEN BIT(18) -#define HOST_EOT_GEN BIT(17) -#define DISP_GEN_CHECKSUM BIT(16) -#define DISP_GEN_ECC BIT(15) -#define BTA_EN BIT(14) -#define READ_ENBIT(13) -#define REG_TE_EN BIT(12) -#define IF_TE_EN(x)BIT(8 + (x)) -#define TVG_SELBIT(6) -#define VID_EN BIT(5) -#define IF_VID_SELECT(x) ((x) << 2) -#define IF_VID_SELECT_MASK GENMASK(3, 2) -#define IF_VID_MODEBIT(1) -#define LINK_ENBIT(0) - -#define MCTL_MAIN_PHY_CTL 0x8 -#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2)) -#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2)) -#define HS_INVERT_CLK BIT(17) -#define SWAP_PINS_CLK BIT(16) -#define HS_SKEWCAL_EN BIT(15) -#define WAIT_BURST_TIME(x) ((x) << 10) -#define DATA_ULPM_EN(x)BIT(6 + (x)) -#define CLK_ULPM_ENBIT(5) -#define CLK_CONTINUOUS BIT(4) -#define DATA_LANE_EN(x)BIT((x) - 1) - -#define MCTL_MAIN_EN 0xc -#define DATA_FORCE_STOPBIT(17) -#define CLK_FORCE_STOP BIT(16) -#define IF_EN(x) BIT(13 + (x)) -#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l)) -#define CLK_LANE_ULPM_REQ BIT(8) -#define DATA_LANE_START(x) BIT(4 + (x)) -#define CLK_LANE_ENBIT(3) -#define PLL_START BIT(0) - -#define MCTL_DPHY_CFG0 0x10 -#define DPHY_C_RSTBBIT(20) -#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16) -#define DPHY_PLL_PDN BIT(10) -#define DPHY_CMN_PDN BIT(9) -#define DPHY_C_PDN BIT(8) -#define DPHY_D_PDN(x) GENMASK(3 + (x), 4) -#define DPHY_ALL_D_PDN GENMASK(7, 4) -#define DPHY_PLL_PSO BIT(1) -#define DPHY_CMN_PSO BIT(0) - -#define MCTL_DPHY_TIMEOUT1 0x14 -#define HSTX_TIMEOUT(x)((x) << 4) -#define HSTX_TIMEOUT_MAX GENMASK(17, 0) -#define CLK_DIV(x) (x) -#define CLK_DIV_MAXGENMASK(3, 0) - -#define MCTL_DPHY_TIMEOUT2 0x18 -#define LPRX_TIMEOUT(x)(x) - -#define MCTL_ULPOUT_TIME 0x1c -#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9) -#define CLK_LANE_ULPOUT_TIME(x)(x) - -#define MCTL_3DVIDEO_CTL 0x20 -#define VID_VSYNC_3D_ENBIT(7) -#define VID_VSYNC_3D_LRBIT(5) -#define VID_VSYNC_3D_SECOND_EN BIT(4) -#define VID_VSYNC_3DFORMAT_LINE(0 << 2) -#define VID_VSYNC_3DFORMAT_FRAME (1 << 2) -#define V
[PATCH v8 1/5] dt-bindings: display: bridge: Convert cdns, dsi.txt to yaml
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++
2 files changed, 157 insertions(+), 112 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
deleted file mode 100644
index 525a4bfd8634..
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-Cadence DSI bridge
-==
-
-The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
-
-Required properties:
-- compatible: should be set to "cdns,dsi".
-- reg: physical base address and length of the controller's registers.
-- interrupts: interrupt line connected to the DSI bridge.
-- clocks: DSI bridge clocks.
-- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy".
-- #address-cells: must be set to 1.
-- #size-cells: must be set to 0.
-
-Optional properties:
-- resets: DSI reset lines.
-- reset-names: can contain "dsi_p_rst".
-
-Required subnodes:
-- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
- 2 ports are available:
- * port 0: this port is only needed if some of your DSI devices are
- controlled through an external bus like I2C or SPI. Can have at
- most 4 endpoints. The endpoint number is directly encoding the
- DSI virtual channel used by this device.
- * port 1: represents the DPI input.
- Other ports will be added later to support the new kind of inputs.
-
-- one subnode per DSI device connected on the DSI bus. Each DSI device should
- contain a reg property encoding its virtual channel.
-
-Example:
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy0>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
-
- panel: dsi-dev@0 {
- compatible = "";
- reg = <0>;
- };
- };
-
-or
-
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy1>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_panel_input>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
- };
-
- i2c@xxx {
- panel: panel@59 {
- compatible = "";
- reg = <0x59>;
-
- port {
- dsi_panel_input: endpoint {
- remote-endpoint = <&dsi0_output>;
-
[PATCH v8 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
Move the cadence dsi bridge under drm/bridge/cadence
directory, to prepare for adding j721e wrapper
support
Signed-off-by: Rahul T R
---
drivers/gpu/drm/bridge/Kconfig| 11 ---
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +++
drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
.../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c}| 0
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 57946d80b02d..8b2226f72b24 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_CDNS_DSI
- tristate "Cadence DPI/DSI bridge"
- select DRM_KMS_HELPER
- select DRM_MIPI_DSI
- select DRM_PANEL_BRIDGE
- select GENERIC_PHY_MIPI_DPHY
- depends on OF
- help
- Support Cadence DPI to DSI bridge. This is an internal
- bridge and is meant to be directly embedded in a SoC.
-
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1884803c6860..52f6e8b4a821 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..8fbb46c66094 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -25,3 +25,14 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_DSI
+ tristate "Cadence DPI/DSI bridge"
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ depends on OF
+ help
+ Support Cadence DPI to DSI bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..e3d8e9a40784 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,3 +2,5 @@
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+cdns-dsi-y := cdns-dsi-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
similarity index 100%
rename from drivers/gpu/drm/bridge/cdns-dsi.c
rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
--
2.38.0
[PATCH v8 0/5] Add support for CDNS DSI J721E wrapper
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v8:
- Rebased to 6.1-rc1
v7:
- Rebased to next-20220920
- Accumulated the Reviewed-by acks
v6:
- Dropped generic definations for properties like reg, resets etc..
- Fixed the defination for port@0 and port@1
- removed the ti,sn65dsi86 node from the example, which is not related
v5:
- Remove power-domain property in the conversion commit
- Add power-domain only for j721e compatible
- Fix white space error in one of the commit
v4:
- split conversion txt to yaml
- seperate commit for addinig new compatible
- conditionally limit the items for reg property, based on the compatible
v3:
- Convert cdns-dsi.txt binding to yaml
- Move the bridge under display/bridge/cadence
- Add new compatible to enable the wrapper module
v2:
- Moved setting DPI0 to bridge_enable, since it
should be done after pm_runtime_get
Rahul T R (5):
dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on
j721e
drm/bridge: cdns-dsi: Move to drm/bridge/cadence
drm/bridge: cdns-dsi: Create a header file
drm/bridge: cdns-dsi: Add support for J721E wrapper
.../bindings/display/bridge/cdns,dsi.txt | 112
.../bindings/display/bridge/cdns,dsi.yaml | 180 +++
drivers/gpu/drm/bridge/Kconfig| 11 -
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 21 +
drivers/gpu/drm/bridge/cadence/Makefile | 3 +
.../{cdns-dsi.c => cadence/cdns-dsi-core.c} | 483 ++
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 471 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 ++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +
10 files changed, 781 insertions(+), 570 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (65%)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
--
2.38.0
[PATCH v8 2/5] dt-bindings: display: bridge: cdns, dsi: Add compatible for dsi on j721e
Add compatible to support dsi bridge on j721e Signed-off-by: Rahul T R Reviewed-by: Rob Herring --- .../bindings/display/bridge/cdns,dsi.yaml | 25 ++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 3161c33093c1..23060324d16e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -16,9 +16,15 @@ properties: compatible: enum: - cdns,dsi + - ti,j721e-dsi reg: -maxItems: 1 +minItems: 1 +items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. clocks: items: @@ -67,6 +73,23 @@ properties: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: ti,j721e-dsi +then: + properties: +reg: + minItems: 2 + maxItems: 2 +power-domains: + maxItems: 1 +else: + properties: +reg: + maxItems: 1 + required: - compatible - reg -- 2.38.0
[PATCH v8 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Add support for wrapper settings for DSI bridge on
j721e. Also set the DPI input to DPI0
Signed-off-by: Rahul T R
---
drivers/gpu/drm/bridge/cadence/Kconfig| 10
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 37 +-
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 13 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +++
6 files changed, 129 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 8fbb46c66094..663a02d96420 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -36,3 +36,13 @@ config DRM_CDNS_DSI
help
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DPI/DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DSI wrapper. This wrapper adds
+ support to select which DPI input to use for the bridge.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index e3d8e9a40784..4cffc8ff71c4 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index cba91247ab26..4b7de38ef1b0 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -15,12 +15,16 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include "cdns-dsi-core.h"
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+#include "cdns-dsi-j721e.h"
+#endif
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
@@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
*bridge)
val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
writel(val, dsi->regs + MCTL_MAIN_EN);
+
+ if (dsi->platform_ops && dsi->platform_ops->disable)
+ dsi->platform_ops->disable(dsi);
+
pm_runtime_put(dsi->base.dev);
}
@@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
*bridge)
if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
return;
+ if (dsi->platform_ops && dsi->platform_ops->enable)
+ dsi->platform_ops->enable(dsi);
+
mode = &bridge->encoder->crtc->state->adjusted_mode;
nlanes = output->dev->lanes;
@@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
goto err_disable_pclk;
}
+ dsi->platform_ops = of_device_get_match_data(&pdev->dev);
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
@@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device
*pdev)
dsi->base.dev = &pdev->dev;
dsi->base.ops = &cdns_dsi_ops;
+ if (dsi->platform_ops && dsi->platform_ops->init) {
+ ret = dsi->platform_ops->init(dsi);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "platform initialization failed:
%d\n",
+ ret);
+ goto err_disable_runtime_pm;
+ }
+ }
+
ret = mipi_dsi_host_register(&dsi->base);
if (ret)
- goto err_disable_runtime_pm;
+ goto err_deinit_platform;
clk_disable_unprepare(dsi->dsi_p_clk);
return 0;
+err_deinit_platform:
+ if (dsi->platform_ops && dsi->platform_ops->exit)
+ dsi->platform_ops->exit(dsi);
+
err_disable_runtime_pm:
pm_runtime_disable(&pdev->dev);
@@ -857,6 +883,10 @@ static int cdns_dsi_drm_remove(struct platform_device
*pdev)
struct cdns_dsi *dsi = platform_get_drvdata(pdev);
mipi_dsi_host_unregister(&dsi->base);
+
+ if (dsi->platform_ops && dsi->platform_ops->exit)
+ dsi->platfo
Re: [PATCH 1/2] dt-bindings: dp-connector: Fix the property name for dp pwr
Hi Rob, On 09:14-20220930, Rob Herring wrote: > On Fri, Sep 30, 2022 at 8:29 AM Rahul T R wrote: > > > > Property name for DisplayPort regulator is not matching in > > the binding and the driver implementation. Fix the same > > in the binding > > > > Signed-off-by: Rahul T R > > Reported-by: Nishanth Menon > > --- > > .../devicetree/bindings/display/connector/dp-connector.yaml | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > NAK. The binding is correct. > > Are you confused that the regulator framework appends '-supply' for you? > > Rob Thanks for pointing this out I was confused about the difference in the property name now I get it Please ignore this set Regards Rahul T R
[PATCH 2/2] arm64: dts: ti: k3-j721e-*: Fix the property name for dp pwr
Fix the property name of displayport pwr in dp connector
nodes
Signed-off-by: Rahul T R
Reported-by: Nishanth Menon
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 +-
arch/arm64/boot/dts/ti/k3-j721e-sk.dts| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index b1691ac3442d..4cccb6653217 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -162,7 +162,7 @@ dp0: connector {
compatible = "dp-connector";
label = "DP0";
type = "full-size";
- dp-pwr-supply = <&dp_pwr_3v3>;
+ dp-pwr = <&dp_pwr_3v3>;
port {
dp_connector_in: endpoint {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 80358cba6954..0e295c661aab 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -217,7 +217,7 @@ dp0: connector {
compatible = "dp-connector";
label = "DP0";
type = "full-size";
- dp-pwr-supply = <&dp_pwr_3v3>;
+ dp-pwr = <&dp_pwr_3v3>;
port {
dp_connector_in: endpoint {
--
2.37.3
[PATCH 0/2] Fix dp-pwr property in dp-connector binding
Fix the miss match in the binding and driver implementation for dp power supply regulator property. Also fix it in the dp-connector node instances in dt files Rahul T R (2): dt-bindings: dp-connector: Fix the property name for dp pwr arm64: dts: ti: k3-j721e-*: Fix the property name for dp pwr .../devicetree/bindings/display/connector/dp-connector.yaml | 2 +- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) -- 2.37.3
[PATCH 1/2] dt-bindings: dp-connector: Fix the property name for dp pwr
Property name for DisplayPort regulator is not matching in the binding and the driver implementation. Fix the same in the binding Signed-off-by: Rahul T R Reported-by: Nishanth Menon --- .../devicetree/bindings/display/connector/dp-connector.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/connector/dp-connector.yaml b/Documentation/devicetree/bindings/display/connector/dp-connector.yaml index 22792a79e7ce..529d3f11ac16 100644 --- a/Documentation/devicetree/bindings/display/connector/dp-connector.yaml +++ b/Documentation/devicetree/bindings/display/connector/dp-connector.yaml @@ -24,7 +24,7 @@ properties: description: A GPIO line connected to HPD maxItems: 1 - dp-pwr-supply: + dp-pwr: description: Power supply for the DP_PWR pin port: -- 2.37.3
[PATCH v7 3/5] drm/bridge: cdns-dsi: Move to drm/bridge/cadence
Move the cadence dsi bridge under drm/bridge/cadence
directory, to prepare for adding j721e wrapper
support
Signed-off-by: Rahul T R
---
drivers/gpu/drm/bridge/Kconfig| 11 ---
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 11 +++
drivers/gpu/drm/bridge/cadence/Makefile | 2 ++
.../bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c}| 0
5 files changed, 13 insertions(+), 12 deletions(-)
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (100%)
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 57946d80b02d..8b2226f72b24 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -15,17 +15,6 @@ config DRM_PANEL_BRIDGE
menu "Display Interface Bridges"
depends on DRM && DRM_BRIDGE
-config DRM_CDNS_DSI
- tristate "Cadence DPI/DSI bridge"
- select DRM_KMS_HELPER
- select DRM_MIPI_DSI
- select DRM_PANEL_BRIDGE
- select GENERIC_PHY_MIPI_DPHY
- depends on OF
- help
- Support Cadence DPI to DSI bridge. This is an internal
- bridge and is meant to be directly embedded in a SoC.
-
config DRM_CHIPONE_ICN6211
tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1884803c6860..52f6e8b4a821 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 1d06182bea71..8fbb46c66094 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -25,3 +25,14 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_DSI
+ tristate "Cadence DPI/DSI bridge"
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select GENERIC_PHY_MIPI_DPHY
+ depends on OF
+ help
+ Support Cadence DPI to DSI bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index 4d2db8df1bc6..e3d8e9a40784 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -2,3 +2,5 @@
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
+cdns-dsi-y := cdns-dsi-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-dsi.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
similarity index 100%
rename from drivers/gpu/drm/bridge/cdns-dsi.c
rename to drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
--
2.37.3
[PATCH v7 4/5] drm/bridge: cdns-dsi: Create a header file
Create a header file for cdns dsi and move register offsets and structure to header, to prepare for adding j721e wrapper support Signed-off-by: Rahul T R --- .../gpu/drm/bridge/cadence/cdns-dsi-core.c| 446 + .../gpu/drm/bridge/cadence/cdns-dsi-core.h| 458 ++ 2 files changed, 459 insertions(+), 445 deletions(-) create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index 20bece84ff8c..cba91247ab26 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -6,10 +6,7 @@ */ #include -#include #include -#include -#include #include #include @@ -23,448 +20,7 @@ #include #include -#include -#include - -#define IP_CONF0x0 -#define SP_HS_FIFO_DEPTH(x)(((x) & GENMASK(30, 26)) >> 26) -#define SP_LP_FIFO_DEPTH(x)(((x) & GENMASK(25, 21)) >> 21) -#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16) -#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13) -#define SDI_IFACE_32 BIT(12) -#define INTERNAL_DATAPATH_32 (0 << 10) -#define INTERNAL_DATAPATH_16 (1 << 10) -#define INTERNAL_DATAPATH_8(3 << 10) -#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10)) -#define NUM_IFACE(x) x) & GENMASK(9, 8)) >> 8) + 1) -#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6) -#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0)) - -#define MCTL_MAIN_DATA_CTL 0x4 -#define TE_MIPI_POLLING_EN BIT(25) -#define TE_HW_POLLING_EN BIT(24) -#define DISP_EOT_GEN BIT(18) -#define HOST_EOT_GEN BIT(17) -#define DISP_GEN_CHECKSUM BIT(16) -#define DISP_GEN_ECC BIT(15) -#define BTA_EN BIT(14) -#define READ_ENBIT(13) -#define REG_TE_EN BIT(12) -#define IF_TE_EN(x)BIT(8 + (x)) -#define TVG_SELBIT(6) -#define VID_EN BIT(5) -#define IF_VID_SELECT(x) ((x) << 2) -#define IF_VID_SELECT_MASK GENMASK(3, 2) -#define IF_VID_MODEBIT(1) -#define LINK_ENBIT(0) - -#define MCTL_MAIN_PHY_CTL 0x8 -#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2)) -#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2)) -#define HS_INVERT_CLK BIT(17) -#define SWAP_PINS_CLK BIT(16) -#define HS_SKEWCAL_EN BIT(15) -#define WAIT_BURST_TIME(x) ((x) << 10) -#define DATA_ULPM_EN(x)BIT(6 + (x)) -#define CLK_ULPM_ENBIT(5) -#define CLK_CONTINUOUS BIT(4) -#define DATA_LANE_EN(x)BIT((x) - 1) - -#define MCTL_MAIN_EN 0xc -#define DATA_FORCE_STOPBIT(17) -#define CLK_FORCE_STOP BIT(16) -#define IF_EN(x) BIT(13 + (x)) -#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l)) -#define CLK_LANE_ULPM_REQ BIT(8) -#define DATA_LANE_START(x) BIT(4 + (x)) -#define CLK_LANE_ENBIT(3) -#define PLL_START BIT(0) - -#define MCTL_DPHY_CFG0 0x10 -#define DPHY_C_RSTBBIT(20) -#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16) -#define DPHY_PLL_PDN BIT(10) -#define DPHY_CMN_PDN BIT(9) -#define DPHY_C_PDN BIT(8) -#define DPHY_D_PDN(x) GENMASK(3 + (x), 4) -#define DPHY_ALL_D_PDN GENMASK(7, 4) -#define DPHY_PLL_PSO BIT(1) -#define DPHY_CMN_PSO BIT(0) - -#define MCTL_DPHY_TIMEOUT1 0x14 -#define HSTX_TIMEOUT(x)((x) << 4) -#define HSTX_TIMEOUT_MAX GENMASK(17, 0) -#define CLK_DIV(x) (x) -#define CLK_DIV_MAXGENMASK(3, 0) - -#define MCTL_DPHY_TIMEOUT2 0x18 -#define LPRX_TIMEOUT(x)(x) - -#define MCTL_ULPOUT_TIME 0x1c -#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9) -#define CLK_LANE_ULPOUT_TIME(x)(x) - -#define MCTL_3DVIDEO_CTL 0x20 -#define VID_VSYNC_3D_ENBIT(7) -#define VID_VSYNC_3D_LRBIT(5) -#define VID_VSYNC_3D_SECOND_EN BIT(4) -#define VID_VSYNC_3DFORMAT_LINE(0 << 2) -#define VID_VSYNC_3DFORMAT_FRAME (1 << 2) -#define V
[PATCH v7 1/5] dt-bindings: display: bridge: Convert cdns, dsi.txt to yaml
Convert cdns,dsi.txt binding to yaml format
Signed-off-by: Rahul T R
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,dsi.txt | 112 -
.../bindings/display/bridge/cdns,dsi.yaml | 157 ++
2 files changed, 157 insertions(+), 112 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
deleted file mode 100644
index 525a4bfd8634..
--- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-Cadence DSI bridge
-==
-
-The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
-
-Required properties:
-- compatible: should be set to "cdns,dsi".
-- reg: physical base address and length of the controller's registers.
-- interrupts: interrupt line connected to the DSI bridge.
-- clocks: DSI bridge clocks.
-- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
-- phys: phandle link to the MIPI D-PHY controller.
-- phy-names: must contain "dphy".
-- #address-cells: must be set to 1.
-- #size-cells: must be set to 0.
-
-Optional properties:
-- resets: DSI reset lines.
-- reset-names: can contain "dsi_p_rst".
-
-Required subnodes:
-- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
- 2 ports are available:
- * port 0: this port is only needed if some of your DSI devices are
- controlled through an external bus like I2C or SPI. Can have at
- most 4 endpoints. The endpoint number is directly encoding the
- DSI virtual channel used by this device.
- * port 1: represents the DPI input.
- Other ports will be added later to support the new kind of inputs.
-
-- one subnode per DSI device connected on the DSI bus. Each DSI device should
- contain a reg property encoding its virtual channel.
-
-Example:
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy0>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
-
- panel: dsi-dev@0 {
- compatible = "";
- reg = <0>;
- };
- };
-
-or
-
- dsi0: dsi@fd0c {
- compatible = "cdns,dsi";
- reg = <0x0 0xfd0c 0x0 0x1000>;
- clocks = <&pclk>, <&sysclk>;
- clock-names = "dsi_p_clk", "dsi_sys_clk";
- interrupts = <1>;
- phys = <&dphy1>;
- phy-names = "dphy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsi0_output: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_panel_input>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_dpi_input: endpoint {
- remote-endpoint = <&xxx_dpi_output>;
- };
- };
- };
- };
-
- i2c@xxx {
- panel: panel@59 {
- compatible = "";
- reg = <0x59>;
-
- port {
- dsi_panel_input: endpoint {
- remote-endpoint = <&dsi0_output>;
-
[PATCH v7 2/5] dt-bindings: display: bridge: cdns, dsi: Add compatible for dsi on j721e
Add compatible to support dsi bridge on j721e Signed-off-by: Rahul T R Reviewed-by: Rob Herring --- .../bindings/display/bridge/cdns,dsi.yaml | 25 ++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml index 3161c33093c1..23060324d16e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml @@ -16,9 +16,15 @@ properties: compatible: enum: - cdns,dsi + - ti,j721e-dsi reg: -maxItems: 1 +minItems: 1 +items: + - description: + Register block for controller's registers. + - description: + Register block for wrapper settings registers in case of TI J7 SoCs. clocks: items: @@ -67,6 +73,23 @@ properties: allOf: - $ref: ../dsi-controller.yaml# + - if: + properties: +compatible: + contains: +const: ti,j721e-dsi +then: + properties: +reg: + minItems: 2 + maxItems: 2 +power-domains: + maxItems: 1 +else: + properties: +reg: + maxItems: 1 + required: - compatible - reg -- 2.37.3
[PATCH v7 5/5] drm/bridge: cdns-dsi: Add support for J721E wrapper
Add support for wrapper settings for DSI bridge on
j721e. Also set the DPI input to DPI0
Signed-off-by: Rahul T R
---
drivers/gpu/drm/bridge/cadence/Kconfig| 10
drivers/gpu/drm/bridge/cadence/Makefile | 1 +
.../gpu/drm/bridge/cadence/cdns-dsi-core.c| 37 +-
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 13 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 +++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +++
6 files changed, 129 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
b/drivers/gpu/drm/bridge/cadence/Kconfig
index 8fbb46c66094..663a02d96420 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -36,3 +36,13 @@ config DRM_CDNS_DSI
help
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+
+if DRM_CDNS_DSI
+
+config DRM_CDNS_DSI_J721E
+ bool "J721E Cadence DPI/DSI wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DSI wrapper. This wrapper adds
+ support to select which DPI input to use for the bridge.
+endif
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
b/drivers/gpu/drm/bridge/cadence/Makefile
index e3d8e9a40784..4cffc8ff71c4 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -4,3 +4,4 @@ cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o
cdns-dsi-y := cdns-dsi-core.o
+cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
index cba91247ab26..4b7de38ef1b0 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
@@ -15,12 +15,16 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include "cdns-dsi-core.h"
+#ifdef CONFIG_DRM_CDNS_DSI_J721E
+#include "cdns-dsi-j721e.h"
+#endif
static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
{
@@ -265,6 +269,10 @@ static void cdns_dsi_bridge_disable(struct drm_bridge
*bridge)
val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
writel(val, dsi->regs + MCTL_MAIN_EN);
+
+ if (dsi->platform_ops && dsi->platform_ops->disable)
+ dsi->platform_ops->disable(dsi);
+
pm_runtime_put(dsi->base.dev);
}
@@ -360,6 +368,9 @@ static void cdns_dsi_bridge_enable(struct drm_bridge
*bridge)
if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
return;
+ if (dsi->platform_ops && dsi->platform_ops->enable)
+ dsi->platform_ops->enable(dsi);
+
mode = &bridge->encoder->crtc->state->adjusted_mode;
nlanes = output->dev->lanes;
@@ -800,6 +811,8 @@ static int cdns_dsi_drm_probe(struct platform_device *pdev)
goto err_disable_pclk;
}
+ dsi->platform_ops = of_device_get_match_data(&pdev->dev);
+
val = readl(dsi->regs + IP_CONF);
dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
@@ -835,14 +848,27 @@ static int cdns_dsi_drm_probe(struct platform_device
*pdev)
dsi->base.dev = &pdev->dev;
dsi->base.ops = &cdns_dsi_ops;
+ if (dsi->platform_ops && dsi->platform_ops->init) {
+ ret = dsi->platform_ops->init(dsi);
+ if (ret != 0) {
+ dev_err(&pdev->dev, "platform initialization failed:
%d\n",
+ ret);
+ goto err_disable_runtime_pm;
+ }
+ }
+
ret = mipi_dsi_host_register(&dsi->base);
if (ret)
- goto err_disable_runtime_pm;
+ goto err_deinit_platform;
clk_disable_unprepare(dsi->dsi_p_clk);
return 0;
+err_deinit_platform:
+ if (dsi->platform_ops && dsi->platform_ops->exit)
+ dsi->platform_ops->exit(dsi);
+
err_disable_runtime_pm:
pm_runtime_disable(&pdev->dev);
@@ -857,6 +883,10 @@ static int cdns_dsi_drm_remove(struct platform_device
*pdev)
struct cdns_dsi *dsi = platform_get_drvdata(pdev);
mipi_dsi_host_unregister(&dsi->base);
+
+ if (dsi->platform_ops && dsi->platform_ops->exit)
+ dsi->platfo
[PATCH v7 0/5] Add support for CDNS DSI J721E wrapper
Following series of patches adds supports for CDNS DSI
bridge on j721e.
v7:
- Rebased to next-20220920
- Accumulated the Reviewed-by acks
v6:
- Dropped generic definations for properties like reg, resets etc..
- Fixed the defination for port@0 and port@1
- removed the ti,sn65dsi86 node from the example, which is not related
v5:
- Remove power-domain property in the conversion commit
- Add power-domain only for j721e compatible
- Fix white space error in one of the commit
v4:
- split conversion txt to yaml
- seperate commit for addinig new compatible
- conditionally limit the items for reg property, based on the compatible
v3:
- Convert cdns-dsi.txt binding to yaml
- Move the bridge under display/bridge/cadence
- Add new compatible to enable the wrapper module
v2:
- Moved setting DPI0 to bridge_enable, since it
should be done after pm_runtime_get
Rahul T R (5):
dt-bindings: display: bridge: Convert cdns,dsi.txt to yaml
dt-bindings: display: bridge: cdns,dsi: Add compatible for dsi on
j721e
drm/bridge: cdns-dsi: Move to drm/bridge/cadence
drm/bridge: cdns-dsi: Create a header file
drm/bridge: cdns-dsi: Add support for J721E wrapper
.../bindings/display/bridge/cdns,dsi.txt | 112
.../bindings/display/bridge/cdns,dsi.yaml | 180 +++
drivers/gpu/drm/bridge/Kconfig| 11 -
drivers/gpu/drm/bridge/Makefile | 1 -
drivers/gpu/drm/bridge/cadence/Kconfig| 21 +
drivers/gpu/drm/bridge/cadence/Makefile | 3 +
.../{cdns-dsi.c => cadence/cdns-dsi-core.c} | 483 ++
.../gpu/drm/bridge/cadence/cdns-dsi-core.h| 471 +
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.c | 51 ++
.../gpu/drm/bridge/cadence/cdns-dsi-j721e.h | 18 +
10 files changed, 781 insertions(+), 570 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
rename drivers/gpu/drm/bridge/{cdns-dsi.c => cadence/cdns-dsi-core.c} (65%)
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-core.h
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cadence/cdns-dsi-j721e.h
--
2.37.3
[PATCH] drm/panel: simple: Initialize bpc in RK101II01D-CT panel descriptor
Initialize bpc while creating panel_desc structure for RK101II01D-CT
Below warning is triggered since bpc is not being initialized
WARNING: CPU: 2 PID: 47 at drivers/gpu/drm/panel/panel-simple.c:614
panel_simple_probe+0x1b0/0x3c8
Signed-off-by: Rahul T R
---
drivers/gpu/drm/panel/panel-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index dde033066f3d..32f775db5cb7 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3027,6 +3027,7 @@ static const struct drm_display_mode
rocktech_rk101ii01d_ct_mode = {
static const struct panel_desc rocktech_rk101ii01d_ct = {
.modes = &rocktech_rk101ii01d_ct_mode,
+ .bpc = 8,
.num_modes = 1,
.size = {
.width = 217,
--
2.17.1
