[PATCH] MAINTAINERS: add Raphael Gallais-Pou to DRM/STi maintainers
Add myself as a maintainer for STi driver changes. Signed-off-by: Raphael Gallais-Pou --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 71b739b40921..0e583aae590a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7477,6 +7477,7 @@ F:drivers/gpu/drm/rockchip/ DRM DRIVERS FOR STI M: Alain Volmat +M: Raphael Gallais-Pou L: dri-devel@lists.freedesktop.org S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git -- 2.45.2
Re: dw_mipi_dsi-stm.c:(.text+0x8db9a3): undefined reference to `clk_hw_unregister'
On 9/10/24 13:59, Maxime Ripard wrote: > On Tue, Sep 10, 2024 at 12:48:49PM GMT, Raphael Gallais-Pou wrote: >> On 9/9/24 10:45, Borislav Petkov wrote: >>> On Mon, Sep 09, 2024 at 08:57:57AM +0200, Raphael Gallais-Pou wrote: >>>> Arnd Bergmann sent a patch regarding this issue on x86 that I merged >>>> several >>>> weeks ago. >>>> >>>> https://lore.kernel.org/lkml/20240719075454.3595358-1-a...@kernel.org/ >>>> https://lore.kernel.org/all/c3d0757a-07c0-4f83-9f06-c3ad205aa...@foss.st.com/ >>> Thanks. >>> >>>> Now, I'm not familiar with PowerPC architecture and toolchains, but I think >>>> this patch should fix your problem. Do you have the above fixup in your >>>> tree ? If not please try it. >>> Not PowerPC - it is an x86 build. I do random config builds as part of build >>> testing and when a driver depends on COMPILE_TEST, it does gets built in >>> some >>> .configs. So some may fail, as in this case. >> Unless I am mistaken, the link you provided refers to a PowerPC linker error: >> >> [...] >> >> compiler: powerpc-linux-gcc (GCC) 14.1.0 >> >> [...] >>powerpc-linux-ld: drivers/gpu/drm/stm/dw_mipi_dsi-stm.o: in function >> `dw_mipi_dsi_stm_remove': >>dw_mipi_dsi-stm.c:(.text+0x664): undefined reference to >> `of_clk_del_provider' >>>> powerpc-linux-ld: dw_mipi_dsi-stm.c:(.text+0x66c): undefined reference to >>>> `clk_hw_unregister'powerpc-linux-ld: >>>> drivers/gpu/drm/stm/dw_mipi_dsi-stm.o: in function `dw_mipi_dsi_stm_probe': >>dw_mipi_dsi-stm.c:(.text+0x98c): undefined reference to `clk_hw_register' >> >>> So I think you should send that patch to Linus now so that such randconfig >>> builds do not fail anymore. >> What do you mean by 'sending it to Linus' ? If you meant to do a pull >> request, >> then no. This patch is already in the drm-misc tree, which means it will keep >> its usual pace of merging with the rest of the drm-misc tree. >> >> For more information about drm-misc tree: >> https://drm.pages.freedesktop.org/maintainer-tools/repositories/drm-misc.html#merge-timeline > That's not entirely correct. This should have been merged in > drm-misc-fixes to begin with. I've cherry-picked the patch and pushed > it. Hi Maxime, Oops I stand corrected, I effectively should have thought about sending this to drm-misc-fixes. Thank you for doing this. Regards, Raphaël > > Maxime
Re: dw_mipi_dsi-stm.c:(.text+0x8db9a3): undefined reference to `clk_hw_unregister'
On 9/9/24 10:45, Borislav Petkov wrote: > On Mon, Sep 09, 2024 at 08:57:57AM +0200, Raphael Gallais-Pou wrote: >> Arnd Bergmann sent a patch regarding this issue on x86 that I merged several >> weeks ago. >> >> https://lore.kernel.org/lkml/20240719075454.3595358-1-a...@kernel.org/ >> https://lore.kernel.org/all/c3d0757a-07c0-4f83-9f06-c3ad205aa...@foss.st.com/ > Thanks. > >> Now, I'm not familiar with PowerPC architecture and toolchains, but I think >> this patch should fix your problem. Do you have the above fixup in your >> tree ? If not please try it. > Not PowerPC - it is an x86 build. I do random config builds as part of build > testing and when a driver depends on COMPILE_TEST, it does gets built in some > .configs. So some may fail, as in this case. Unless I am mistaken, the link you provided refers to a PowerPC linker error: [...] compiler: powerpc-linux-gcc (GCC) 14.1.0 [...] powerpc-linux-ld: drivers/gpu/drm/stm/dw_mipi_dsi-stm.o: in function `dw_mipi_dsi_stm_remove': dw_mipi_dsi-stm.c:(.text+0x664): undefined reference to `of_clk_del_provider' >> powerpc-linux-ld: dw_mipi_dsi-stm.c:(.text+0x66c): undefined reference to >> `clk_hw_unregister'powerpc-linux-ld: >> drivers/gpu/drm/stm/dw_mipi_dsi-stm.o: in function `dw_mipi_dsi_stm_probe': dw_mipi_dsi-stm.c:(.text+0x98c): undefined reference to `clk_hw_register' > > So I think you should send that patch to Linus now so that such randconfig > builds do not fail anymore. What do you mean by 'sending it to Linus' ? If you meant to do a pull request, then no. This patch is already in the drm-misc tree, which means it will keep its usual pace of merging with the rest of the drm-misc tree. For more information about drm-misc tree: https://drm.pages.freedesktop.org/maintainer-tools/repositories/drm-misc.html#merge-timeline > > Unfortunately, I cannot test it right now because I've removed the triggering > randconfigs but when I hit it again, I'll make sure to apply yours. Thank you for this. Do not hesitate to reach if you encounter any problems with this patch. Regards, Raphaël > > Thx. >
Re: dw_mipi_dsi-stm.c:(.text+0x8db9a3): undefined reference to `clk_hw_unregister'
On 9/5/24 10:19, Borislav Petkov wrote: > Hi all, > > this fires in my randbuilds here: > > vmlinux.o: warning: objtool: adis16400_write_raw() falls through to next > function adis16400_show_serial_number() > ld: vmlinux.o: in function `dw_mipi_dsi_stm_remove': > dw_mipi_dsi-stm.c:(.text+0x8db9a3): undefined reference to `clk_hw_unregister' > ld: vmlinux.o: in function `dw_mipi_dsi_clk_register': > dw_mipi_dsi-stm.c:(.text+0x8db9f5): undefined reference to `clk_hw_register' > ld: vmlinux.o: in function `lvds_remove': > lvds.c:(.text+0x8dc605): undefined reference to `clk_hw_unregister' > make[2]: *** [scripts/Makefile.vmlinux:34: vmlinux] Error 1 > make[1]: *** [/home/amd/bpetkov/kernel/linux/Makefile:1156: vmlinux] Error 2 > make: *** [Makefile:224: __sub-make] Error 2 > > is there a fix somewhere? Hi Borislav, Arnd Bergmann sent a patch regarding this issue on x86 that I merged several weeks ago. https://lore.kernel.org/lkml/20240719075454.3595358-1-a...@kernel.org/ https://lore.kernel.org/all/c3d0757a-07c0-4f83-9f06-c3ad205aa...@foss.st.com/ > > People love to do > > depends on ... COMPILE_TEST > > but then if no one takes care of it in time: > > https://lore.kernel.org/oe-kbuild-all/202407212000.rpdh64jp-...@intel.com Now, I'm not familiar with PowerPC architecture and toolchains, but I think this patch should fix your problem. Do you have the above fixup in your tree ? If not please try it. Thanks, Regards, Raphaël > > that COMPILE_TEST thing is forcing me to simply blacklist it and is not really > helping. > > Thx. >
Re: [PATCH v2 40/86] drm/stm: Run DRM default client setup
On 8/21/24 14:59, Thomas Zimmermann wrote: > Call drm_client_setup_with-fourcc() to run the kernel's default client > setup for DRM. Set fbdev_probe in struct drm_driver, so that the client > setup can start the common fbdev client. > > v2: > - use drm_client_setup_with_fourcc() > > Signed-off-by: Thomas Zimmermann > Cc: Yannick Fertre > Cc: Raphael Gallais-Pou > Cc: Philippe Cornu > Cc: Maxime Coquelin > Cc: Alexandre Torgue > Acked-by: Raphael Gallais-Pou Hi Thomas, Thanks for this work. Again for v2: Acked-by: Raphael Gallais-Pou Regards, Raphaël
Re: [PATCH 40/86] drm/stm: Run DRM default client setup
On 8/16/24 14:23, Thomas Zimmermann wrote: > Call drm_client_setup() to run the kernel's default client setup > for DRM. Set fbdev_probe in struct drm_driver, so that the client > setup can start the common fbdev client. > > Signed-off-by: Thomas Zimmermann > Cc: Yannick Fertre > Cc: Raphael Gallais-Pou > Cc: Philippe Cornu > Cc: Maxime Coquelin > Cc: Alexandre Torgue Hi Thomas, Thanks, Acked-by: Raphael Gallais-Pou Regards, Raphaël
Re: [PATCH] drm/stm: add COMMON_CLK dependency
On 7/19/24 09:54, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The added lvds driver and a change in the dsi driver resulted in failed
> builds when COMMON_CLK is disabled:
>
> x86_64-linux-ld: drivers/gpu/drm/stm/dw_mipi_dsi-stm.o: in function
> `dw_mipi_dsi_stm_remove':
> dw_mipi_dsi-stm.c:(.text+0x51e): undefined reference to `clk_hw_unregister'
>
> x86_64-linux-ld: drivers/gpu/drm/stm/lvds.o: in function `lvds_remove':
> lvds.c:(.text+0xe3): undefined reference to `of_clk_del_provider'
> x86_64-linux-ld: lvds.c:(.text+0xec): undefined reference to
> `clk_hw_unregister'
> x86_64-linux-ld: drivers/gpu/drm/stm/lvds.o: in function `lvds_pll_config':
> lvds.c:(.text+0xb5d): undefined reference to `clk_hw_get_rate'
> x86_64-linux-ld: drivers/gpu/drm/stm/lvds.o: in function `lvds_probe':
> lvds.c:(.text+0x1476): undefined reference to `clk_hw_register'
> x86_64-linux-ld: lvds.c:(.text+0x148b): undefined reference to
> `of_clk_hw_simple_get'
> x86_64-linux-ld: lvds.c:(.text+0x1493): undefined reference to
> `of_clk_add_hw_provider'
> x86_64-linux-ld: lvds.c:(.text+0x1535): undefined reference to
> `clk_hw_unregister'
>
> Add this as a dependency for the stm driver itself, since it will be
> required in practice anyway.
>
> Fixes: 185f99b61442 ("drm/stm: dsi: expose DSI PHY internal clock")
> Fixes: aca1cbc1c986 ("drm/stm: lvds: add new STM32 LVDS Display Interface
> Transmitter driver")
> Signed-off-by: Arnd Bergmann
Hi Arnd
I've applied your patch to the drm-misc-next.
Thanks,
Raphaël
Re: [PATCH] drm/stm: ltdc: reset plane transparency after plane disable
On 7/12/24 15:13, Yannick Fertre wrote: > The plane's opacity should be reseted while the plane > is disabled. It prevents from seeing a possible global > or layer background color set earlier. > > Signed-off-by: Yannick Fertre Hi Yannick, Applied on drm-misc-next. Thanks, Raphaël
Re: [PATCH] drm/stm: ltdc: add mask for lxcr register
On 7/12/24 15:14, Yannick Fertre wrote: > The purpose of this mask is to simplify writing to the lxcr > register and not to forget any fields. > > Signed-off-by: Yannick Fertre Hi Yannick, Applied on drm-misc-next. Thanks, Raphaël
Re: [PATCH] drm/stm: ltdc: remove reload interrupt
On 7/12/24 15:14, Yannick Fertre wrote: > The reload interrupt is not used by the driver. To avoid > unnecessary calls of the interrupt routine, don't enable it. > Solve small typo and add mask to simplify the driver. > > Signed-off-by: Yannick Fertre Hi Yannick, Applied on drm-misc-next. Thanks, Raphaël
Re: [PATCH v4] drm/stm: Avoid use-after-free issues with crtc and plane
On 2/16/24 13:50, Katya Orlova wrote: > ltdc_load() calls functions drm_crtc_init_with_planes(), > drm_universal_plane_init() and drm_encoder_init(). These functions > should not be called with parameters allocated with devm_kzalloc() > to avoid use-after-free issues [1]. > > Use allocations managed by the DRM framework. > > Found by Linux Verification Center (linuxtesting.org). > > [1] > https://lore.kernel.org/lkml/u366i76e3qhh3ra5oxrtngjtm2u5lterkekcz6y2jkndhuxzli@diujon4h7qwb/ > > Signed-off-by: Katya Orlova Hi Katya, After some delay: applied on drm-misc-next. Thanks, Raphaël
Re: [PATCH] drm/stm: ltdc: Remove unused function plane_to_ltdc
On 6/24/24 04:41, Jiapeng Chong wrote: > The function are defined in the ltdc.c file, but not called > anywhere, so delete the unused function. > > drivers/gpu/drm/stm/ltdc.c:494:35: warning: unused function 'encoder_to_ltdc'. > > Reported-by: Abaci Robot > Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9403 > Signed-off-by: Jiapeng Chong Hi Jiapeng, Applied on drm-misc-next. Thanks, Raphaël
Re: [PATCH] drm/stm: ltdc: check memory returned by devm_kzalloc()
On 5/31/23 09:28, Claudiu Beznea wrote:
> devm_kzalloc() can fail and return NULL pointer. Check its return status.
> Identified with Coccinelle (kmerr.cocci script).
>
> Fixes: 484e72d3146b ("drm/stm: ltdc: add support of ycbcr pixel formats")
> Signed-off-by: Claudiu Beznea
> ---
>
> Hi,
>
> This has been addressed using kmerr.cocci script proposed for update
> at [1].
>
> Thank you,
> Claudiu Beznea
>
> [1]
> https://lore.kernel.org/all/20230530074044.1603426-1-claudiu.bez...@microchip.com/
>
Hi Claudiu,
After some delay: applied on drm-misc-next.
Thank,
Raphaël
[PATCH] MAINTAINERS: add myself to DRM/STi maintainers
In lights of recent events and my will to participate in the Linux kernel development I see this opportunity to add myself, and help Alain as maintainer for the DRM/STi drivers. Signed-off-by: Raphael Gallais-Pou --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 71b739b40921..0e583aae590a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7477,6 +7477,7 @@ F:drivers/gpu/drm/rockchip/ DRM DRIVERS FOR STI M: Alain Volmat +M: Raphael Gallais-Pou L: dri-devel@lists.freedesktop.org S: Maintained T: git https://gitlab.freedesktop.org/drm/misc/kernel.git -- 2.45.2
Re: [PATCH] drm/stm: Fix an error handling path in stm_drm_platform_probe()
On 1/6/24 17:54, Christophe JAILLET wrote:
> If drm_dev_register() fails, a call to drv_load() must be undone, as
> already done in the remove function.
>
> Fixes: b759012c5fa7 ("drm/stm: Add STM32 LTDC driver")
> Signed-off-by: Christophe JAILLET
Hi Christophe,
After some delay: applied on drm-misc-next.
Thanks,
Raphaël
Re: [PATCH] drm/stm: Remove unnecessary .owner for lvds_platform_driver
Hi Jiapeng,
On 7/1/24 08:23, Jiapeng Chong wrote:
> Remove .owner field if calls are used which set it automatically.
>
> ./drivers/gpu/drm/stm/lvds.c:1213:3-8: No need to set .owner here. The core
> will do it.
>
> Reported-by: Abaci Robot
> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9457
> Signed-off-by: Jiapeng Chong
> ---
> drivers/gpu/drm/stm/lvds.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c
> index 2fa2c81784e9..06f2d7a56cc9 100644
> --- a/drivers/gpu/drm/stm/lvds.c
> +++ b/drivers/gpu/drm/stm/lvds.c
> @@ -1210,7 +1210,6 @@ static struct platform_driver lvds_platform_driver = {
> .remove = lvds_remove,
> .driver = {
> .name = "stm32-display-lvds",
> - .owner = THIS_MODULE,
> .of_match_table = lvds_dt_ids,
> },
> };
Indeed, platform_driver_register() overrides the value of the owner.
Acked-by: Raphael Gallais-Pou
Thanks,
Raphaël
Re: [PATCH 21/21] drm/stm: Allow build with COMPILE_TEST=y
Hi Ville On 4/8/24 19:04, Ville Syrjala wrote: > From: Ville Syrjälä > > Allow stm to be built with COMPILE_TEST=y for greater > coverage. Builds fine on x86/x86_64 at least. > > Cc: Yannick Fertre > Cc: Raphael Gallais-Pou > Cc: Philippe Cornu > Signed-off-by: Ville Syrjälä Thank you for this ! :) Acked-by: Raphaël Gallais-Pou > --- > drivers/gpu/drm/stm/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig > index fa49cde43bb2..4c906d602825 100644 > --- a/drivers/gpu/drm/stm/Kconfig > +++ b/drivers/gpu/drm/stm/Kconfig > @@ -1,7 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0-only > config DRM_STM > tristate "DRM Support for STMicroelectronics SoC Series" > - depends on DRM && ARCH_STM32 > + depends on DRM && (ARCH_STM32 || COMPILE_TEST) > select DRM_KMS_HELPER > select DRM_GEM_DMA_HELPER > select DRM_PANEL_BRIDGE
Re: STM32 DSI controller driver: mode_valid clock tolerance
On 3/8/24 09:35, Sean Nyekjaer wrote: > Hi, Hi Sean, Sorry for not responding earlier. I've also added Antonio Borneo, which is the author of the implementation of the mode_valid() hook. > I’m using a stm32mp157 with a sn65dsi83 DSI2LVDS bridge. > The LVDS display is having a minimum clock of 25.2 MHz, typical of 27,2 MHz > and a max of 30,5 MHz. > > I will fail the mode_valid check with MODE_CLOCK_RANGE. > It will request 2720 Hz, but is getting 2725. Guess the display is > fine with this :) > > In this case it seems a bit harsh to fail if the output clock isn’t within 50 > Hz of the requested clock. > > If HDMI is requiring a tolerance of 50 Hz, would it be better to do the check > in the HDMI bridge driver? At the time when the driver was implemented, a large set of TVs/HDMI panels were tested, and it was the 'optimal' parameter found, even if the value is quite restrictive. As Maxime said earlier, it was also easier to implement this tolerance directly within the DSI driver, since only the display-controller and the driver itself have access to this clock. Eventually a device-tree parameter could be implemented, with default value to 50Hz, so that fine tuning can be done using other bridges. Hope this answer to your question. Regards, Raphaël > /Sean
Re: [PATCH v4] drm/stm: Avoid use-after-free issues with crtc and plane
On 2/16/24 13:50, Katya Orlova wrote: > ltdc_load() calls functions drm_crtc_init_with_planes(), > drm_universal_plane_init() and drm_encoder_init(). These functions > should not be called with parameters allocated with devm_kzalloc() > to avoid use-after-free issues [1]. > > Use allocations managed by the DRM framework. > > Found by Linux Verification Center (linuxtesting.org). > > [1] > https://lore.kernel.org/lkml/u366i76e3qhh3ra5oxrtngjtm2u5lterkekcz6y2jkndhuxzli@diujon4h7qwb/ > > Signed-off-by: Katya Orlova Hi Katya, Thanks for this submission. Acked-by: Raphaël Gallais-Pou Regards, Raphaël
[PATCH v6 2/3] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It is composed of three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- Changes in v6: - Fixes sparse symbols detected by kernel test robot Changes in v5: - Align compatible Changes in v4: - Explicitly include linux/platform_device.h, dependency introduced by ef175b29a242 of: Stop circularly including of_device.h and of_platform.h Changes in v3: - s/regroups/is composed of/ in commit log - Change the compatible to show SoC specificity Changes in v2: - Fixed Camel Case macros - Removed debug log --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1226 ++ 3 files changed, 1239 insertions(+) diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..bfc8cb13fbc5 --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Raphaël GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identificatio
[PATCH v6 3/3] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
Changes in v2:
- Fixed my address
- Fixed smatch warning
---
drivers/gpu/drm/stm/ltdc.c | 19 +++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..23011a8913bd 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1896,6 +1902,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1918,13 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ clk_disable_unprepare(ldev->pixel_clk);
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1981,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..4a60ce5b610c 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH v6 0/3] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Changes in v6: - [1/3] Added Conor's Reviewed-by - [2/3] Fixed kernel test robot warnings - Rebased on latest drm-misc-next Changes in v5: - Fixed path in MAINTAINERS - Fixed compatible in driver Changes in v4: - Align dt-bindings filename and compatible - Remove redundant word in [1/6] subject - Fix example on typo - Some minor fixes on YAML syntax - Explicitly include linux/platform_device.h - Drop device-tree related patch after internal discussions - Rebase on latest drm-misc-next Changes in v3: - Changed the compatible to show SoC specificity - Fixed includes in dt-binding example - Added "#clock-cells" description in dt-binding example - Some minor fixes on typo Changes in v2: - Dropped [1/8] because already merged - Dropped [4/8] since not mandatory for this serie - [1/6]: Switch compatible and clock-cells related areas - [1/6]: Remove faulty #include in the example. - [1/6]: Add missing entry in MAINTAINERS - [2/6]: Removed CamelCase macros - [2/6]: Removed hard to read debug log - [3/6]: Fixed my address - [3/6]: Fixed smatch warning - [5/6]: Move changes to stm32mp255.dtsi Signed-off-by: Raphael Gallais-Pou --- Raphael Gallais-Pou (3): dt-bindings: display: add STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock .../bindings/display/st,stm32mp25-lvds.yaml| 119 ++ MAINTAINERS|1 + drivers/gpu/drm/stm/Kconfig| 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c | 19 + drivers/gpu/drm/stm/ltdc.h |1 + drivers/gpu/drm/stm/lvds.c | 1226 7 files changed, 1379 insertions(+) --- base-commit: de8de2c8acb931ce6197a04376a7078ccf50e821 change-id: 20240205-lvds-e084ec50e878 Best regards, -- Raphael Gallais-Pou
[PATCH v6 1/3] dt-bindings: display: add STM32 LVDS device
Add "st,stm32mp25-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
Reviewed-by: Conor Dooley
---
Depends on: "dt-bindings: stm32: add clocks and reset binding for
stm32mp25 platform" by Gabriel Fernandez
Changes in v6:
- Added Conor's Reviewed-by
Changes in v5:
- Fixed path in MAINTAINERS
Changes in v4:
- Align filename to compatible
- Fix compatible in the example
- Remove redundant word in the subject
Changes in v3:
- Clarify commit dependency
- Fix includes in the example
- Fix YAML
- Add "clock-cells" description
- s/regroups/is composed of/
- Changed compatible to show SoC specificity
Changes in v2:
- Switch compatible and clock-cells related areas
- Remove faulty #include in the example.
- Add entry in MAINTAINERS
---
.../bindings/display/st,stm32mp25-lvds.yaml| 119 +
MAINTAINERS| 1 +
2 files changed, 120 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
new file mode 100644
index ..6736f93256b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It is composed of three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ compatible:
+const: st,stm32mp25-lvds
+
+ "#clock-cells":
+const: 0
+description:
+ Provides the internal LVDS PHY clock to the framework.
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+lvds: lvds@4806 {
+compatible = "st,stm32mp25-lvds";
+reg = <0x4806 0x2000>;
+#clock-cells = <0>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3527a2ece6cd..ff5c945f206e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7240,6 +7240,7 @@ L:dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
+F: Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
F: drivers/gpu/drm/stm
DRM DRIVERS FOR TI KEYSTONE
--
2.25.1
[PATCH v3 2/4] ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
Adds LTDC pinctrl support and assigns dedicated GPIO pins.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 57 +
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
index 27e0c3826789..32c5d8a1e06a 100644
--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
@@ -47,6 +47,63 @@ pins {
};
};
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = , /* LCD_CLK */
+, /* LCD_HSYNC */
+, /* LCD_VSYNC */
+, /* LCD_DE */
+, /* LCD_R2 */
+, /* LCD_R3 */
+, /* LCD_R4 */
+, /* LCD_R5 */
+, /* LCD_R6 */
+, /* LCD_R7 */
+, /* LCD_G2 */
+, /* LCD_G3 */
+, /* LCD_G4 */
+, /* LCD_G5 */
+, /* LCD_G6 */
+, /* LCD_G7 */
+, /* LCD_B2 */
+, /* LCD_B3 */
+, /* LCD_B4 */
+, /* LCD_B5 */
+, /* LCD_B6 */
+; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = , /* LCD_CLK */
+, /* LCD_HSYNC
*/
+, /* LCD_VSYNC
*/
+, /* LCD_DE */
+, /* LCD_R2 */
+, /* LCD_R3 */
+, /* LCD_R4 */
+, /* LCD_R5 */
+, /* LCD_R6 */
+, /* LCD_R7 */
+, /* LCD_G2 */
+, /* LCD_G3 */
+, /* LCD_G4 */
+, /* LCD_G5 */
+, /* LCD_G6 */
+, /* LCD_G7 */
+, /* LCD_B2 */
+, /* LCD_B3 */
+, /* LCD_B4 */
+, /* LCD_B5 */
+, /* LCD_B6 */
+; /* LCD_B7 */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.25.1
[PATCH v3 4/4] dt-bindings: display: simple: allow panel-common properties
This device inherits properties from panel-common. Those should be allowed to use, instead of specifying properties to true for each specific use. Signed-off-by: Raphael Gallais-Pou --- Changes in v3: - Allow every properties instead of adding each properties to true as Rob suggested - Rewrite commit log to match changes Changes in v2: - Added this patch Fixes following warnings: arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: 'height-mm', 'panel-timing', 'width-mm' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/display/panel/panel-simple.yaml# --- .../devicetree/bindings/display/panel/panel-simple.yaml | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 634a10c6f2dd..01c9153da3d3 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -344,15 +344,6 @@ properties: # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel - yes-optoelectronics,ytc700tlag-05-201c - backlight: true - ddc-i2c-bus: true - enable-gpios: true - port: true - power-supply: true - no-hpd: true - hpd-gpios: true - data-mapping: true - if: not: properties: @@ -363,7 +354,7 @@ then: properties: data-mapping: false -additionalProperties: false +unevaluatedProperties: false required: - compatible -- 2.25.1
[PATCH v3 3/4] ARM: dts: stm32: enable display support on stm32mp135f-dk board
Link panel and display controller.
Enable panel, backlight and display controller.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v2:
- Fixed dtbs_check warnings :
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-backlight:
'default-brightness-level' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id:
http://devicetree.org/schemas/leds/backlight/gpio-backlight.yaml#
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: data-mapping:0: 'bgr666' is
not one of ['jeida-18', 'jeida-24', 'vesa-24']
from schema $id:
http://devicetree.org/schemas/display/panel/panel-simple.yaml#
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: compatible:
['rocktech,rk043fn48h', 'panel-dpi'] is too long
from schema $id:
http://devicetree.org/schemas/display/panel/panel-simple.yaml#
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: data-mapping: False schema
does not allow ['bgr666']
from schema $id:
http://devicetree.org/schemas/display/panel/panel-simple.yaml#
---
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 53 +
1 file changed, 53 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index eea740d097c7..c918f332cbfd 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -66,6 +66,46 @@ led-blue {
default-state = "off";
};
};
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+ default-on;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h";
+ enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_backlight>;
+ power-supply = <&scmi_v3v3_sw>;
+ status = "okay";
+
+ width-mm = <105>;
+ height-mm = <67>;
+
+ panel-timing {
+ clock-frequency = <1000>;
+ hactive = <480>;
+ hback-porch = <43>;
+ hfront-porch = <10>;
+ hsync-len = <1>;
+ hsync-active = <0>;
+ vactive = <272>;
+ vback-porch = <26>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
};
&adc_1 {
@@ -160,6 +200,19 @@ &iwdg2 {
status = "okay";
};
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
--
2.25.1
[PATCH v3 0/4] Add display support for stm32mp135f-dk board
This serie aims to enable display support for the stm32mp135f-dk board
Those are only patches of the device-tree since the driver support has
already been added [1].
It respectivelly:
- adds support for the display controller on stm32mp135
- adds pinctrl for the display controller
- enables panel, backlight and display controller on
stm32mp135f-dk
Finally it fixes the flags on the panel default mode in the
'panel-simple' driver, allowing to override the default mode by one
described in the device tree, and push further the blanking limit on the
panel.
[1] commit 1726cee3d053 ("drm/stm: ltdc: support of new hardware version")
Changes in v3:
- [4/4] Allow every properties from panel-common in panel-simple.yaml
- [4/4] Rewrite commit description to match changes
Changes in v2:
- Removed already merged patches
https://lore.kernel.org/lkml/17072972.1647630.4818786052103823648.b4...@linaro.org/
https://lore.kernel.org/lkml/170729755662.1647630.425379349649657352.b4...@linaro.org/
- Fixed CHECK_DTBS warnings
- Added missing properties in panel-simple.yaml
Signed-off-by: Raphael Gallais-Pou
---
Raphael Gallais-Pou (4):
ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
ARM: dts: stm32: enable display support on stm32mp135f-dk board
dt-bindings: display: simple: allow panel-common properties
.../bindings/display/panel/panel-simple.yaml | 11 +
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi| 57 ++
arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +
arch/arm/boot/dts/st/stm32mp135f-dk.dts| 53
4 files changed, 122 insertions(+), 10 deletions(-)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240124-ltdc_mp13-2f86a782424c
Best regards,
--
Raphael Gallais-Pou
[PATCH v3 1/4] ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal
display - Thin film transistor) Display Controller.
It provides a parallel digital RGB (red, green, blue) and signals for
horizontal, vertical synchronization, pixel clock and data enable as
output to interface directly to a variety of LCD-TFT panels.
Main features
* 2 input layers blended together to compose the display
* Cropping of layers from any input size and location
* Multiple input pixel formats:
– Predefined ARGB, with 7 formats: ARGB, ABGR, RGBA,
BGRA, RGB565, BGR565, RGB888packed.
– Flexible ARGB, allowing any width and location for A,R,G,B
components.
– Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV,
Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L
(FourCC: Yxx, full planar) with some flexibility on the sequence of
the component.
* Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer
* Color transparency keying
* Composition with flexible window position and size versus output
display
* Blending with flexible layer order and alpha value (per pixel or
constant)
* Background underlying color
* Gamma with non-linear configurable table
* Dithering for output with less bits per component (pseudo-random on
2 bits)
* Polarity inversion for HSync, VSync, and DataEnable outputs
* Output as RGB888 24 bpp or YUV422 16 bpp
* Secure layer (using Layer2) capability, with grouped regs and
additional interrupt set
* Interrupts based on 7 different events
* AXI master interface with long efficient bursts (64 or 128 bytes)
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135.dtsi
b/arch/arm/boot/dts/st/stm32mp135.dtsi
index 68d32f9f5314..834a4d545fe4 100644
--- a/arch/arm/boot/dts/st/stm32mp135.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp135.dtsi
@@ -19,5 +19,16 @@ dcmipp: dcmipp@5a00 {
port {
};
};
+
+ ltdc: display-controller@5a001000 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x5a001000 0x400>;
+ interrupts = ,
+;
+ clocks = <&rcc LTDC_PX>;
+ clock-names = "lcd";
+ resets = <&scmi_reset RST_SCMI_LTDC>;
+ status = "disabled";
+ };
};
};
--
2.25.1
Re: [PATCH v2 4/4] dt-bindings: display: simple: hardware can use several properties
On 2/23/24 01:09, Rob Herring wrote: > On Sat, Feb 17, 2024 at 12:02:58PM +0100, Raphael Gallais-Pou wrote: >> Setting a panel-timing in the device-tree overwrite the one specified in >> the driver and set it as preferred. In that case 'height-mm', >> 'width-mm' and 'panel-timing' are properties that can be use for simple >> panels, according to panel-common.yaml >> >> Fixes following warnings: >> arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: 'height-mm', >> 'panel-timing', 'width-mm' do not match any of the regexes: 'pinctrl-[0-9]+' >> from schema $id: >> http://devicetree.org/schemas/display/panel/panel-simple.yaml# >> >> Signed-off-by: Raphael Gallais-Pou >> --- >> Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git >> a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml >> b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml >> index 634a10c6f2dd..c02cbbc7a100 100644 >> --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml >> +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml >> @@ -352,6 +352,9 @@ properties: >>no-hpd: true >>hpd-gpios: true >>data-mapping: true >> + height-mm: true >> + width-mm: true >> + panel-timing: true Hi Rob, > Instead, just change 'additionalProperties' to 'unevaluateProperties' > and drop all these 'prop: true' lines. Pretty much anything from > panel-common.yaml should be allowed. Will do, thanks :) Best regards, Raphaël > > Rob
[PATCH v2 0/4] Add display support for stm32mp135f-dk board
This serie aims to enable display support for the stm32mp135f-dk board
Those are only patches of the device-tree since the driver support has
already been added [1].
It respectivelly:
- adds support for the display controller on stm32mp135
- adds pinctrl for the display controller
- enables panel, backlight and display controller on
stm32mp135f-dk
Finally it fixes the flags on the panel default mode in the
'panel-simple' driver, allowing to override the default mode by one
described in the device tree, and push further the blanking limit on the
panel.
[1] commit 1726cee3d053 ("drm/stm: ltdc: support of new hardware version")
Changes in v2:
- Removed already merged patches
https://lore.kernel.org/lkml/17072972.1647630.4818786052103823648.b4...@linaro.org/
https://lore.kernel.org/lkml/170729755662.1647630.425379349649657352.b4...@linaro.org/
- Fixed CHECK_DTBS warnings
- Added missing properties in panel-simple.yaml
Signed-off-by: Raphael Gallais-Pou
---
Raphael Gallais-Pou (4):
ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
ARM: dts: stm32: enable display support on stm32mp135f-dk board
dt-bindings: display: simple: hardware can use several properties
.../bindings/display/panel/panel-simple.yaml | 3 ++
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi| 57 ++
arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +
arch/arm/boot/dts/st/stm32mp135f-dk.dts| 53
4 files changed, 124 insertions(+)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240124-ltdc_mp13-2f86a782424c
Best regards,
--
Raphael Gallais-Pou
[PATCH v2 3/4] ARM: dts: stm32: enable display support on stm32mp135f-dk board
Link panel and display controller.
Enable panel, backlight and display controller.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v2:
- Fixed dtbs_check warnings :
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-backlight:
'default-brightness-level' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id:
http://devicetree.org/schemas/leds/backlight/gpio-backlight.yaml#
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: data-mapping:0: 'bgr666' is
not one of ['jeida-18', 'jeida-24', 'vesa-24']
from schema $id:
http://devicetree.org/schemas/display/panel/panel-simple.yaml#
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: compatible:
['rocktech,rk043fn48h', 'panel-dpi'] is too long
from schema $id:
http://devicetree.org/schemas/display/panel/panel-simple.yaml#
arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: data-mapping: False schema
does not allow ['bgr666']
from schema $id:
http://devicetree.org/schemas/display/panel/panel-simple.yaml#
---
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 53 +
1 file changed, 53 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index eea740d097c7..c918f332cbfd 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -66,6 +66,46 @@ led-blue {
default-state = "off";
};
};
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+ default-on;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h";
+ enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_backlight>;
+ power-supply = <&scmi_v3v3_sw>;
+ status = "okay";
+
+ width-mm = <105>;
+ height-mm = <67>;
+
+ panel-timing {
+ clock-frequency = <1000>;
+ hactive = <480>;
+ hback-porch = <43>;
+ hfront-porch = <10>;
+ hsync-len = <1>;
+ hsync-active = <0>;
+ vactive = <272>;
+ vback-porch = <26>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
};
&adc_1 {
@@ -160,6 +200,19 @@ &iwdg2 {
status = "okay";
};
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
--
2.25.1
[PATCH v2 2/4] ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
Adds LTDC pinctrl support and assigns dedicated GPIO pins.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 57 +
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
index 27e0c3826789..32c5d8a1e06a 100644
--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
@@ -47,6 +47,63 @@ pins {
};
};
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = , /* LCD_CLK */
+, /* LCD_HSYNC */
+, /* LCD_VSYNC */
+, /* LCD_DE */
+, /* LCD_R2 */
+, /* LCD_R3 */
+, /* LCD_R4 */
+, /* LCD_R5 */
+, /* LCD_R6 */
+, /* LCD_R7 */
+, /* LCD_G2 */
+, /* LCD_G3 */
+, /* LCD_G4 */
+, /* LCD_G5 */
+, /* LCD_G6 */
+, /* LCD_G7 */
+, /* LCD_B2 */
+, /* LCD_B3 */
+, /* LCD_B4 */
+, /* LCD_B5 */
+, /* LCD_B6 */
+; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = , /* LCD_CLK */
+, /* LCD_HSYNC
*/
+, /* LCD_VSYNC
*/
+, /* LCD_DE */
+, /* LCD_R2 */
+, /* LCD_R3 */
+, /* LCD_R4 */
+, /* LCD_R5 */
+, /* LCD_R6 */
+, /* LCD_R7 */
+, /* LCD_G2 */
+, /* LCD_G3 */
+, /* LCD_G4 */
+, /* LCD_G5 */
+, /* LCD_G6 */
+, /* LCD_G7 */
+, /* LCD_B2 */
+, /* LCD_B3 */
+, /* LCD_B4 */
+, /* LCD_B5 */
+, /* LCD_B6 */
+; /* LCD_B7 */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.25.1
[PATCH v2 1/4] ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal
display - Thin film transistor) Display Controller.
It provides a parallel digital RGB (red, green, blue) and signals for
horizontal, vertical synchronization, pixel clock and data enable as
output to interface directly to a variety of LCD-TFT panels.
Main features
* 2 input layers blended together to compose the display
* Cropping of layers from any input size and location
* Multiple input pixel formats:
– Predefined ARGB, with 7 formats: ARGB, ABGR, RGBA,
BGRA, RGB565, BGR565, RGB888packed.
– Flexible ARGB, allowing any width and location for A,R,G,B
components.
– Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV,
Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L
(FourCC: Yxx, full planar) with some flexibility on the sequence of
the component.
* Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer
* Color transparency keying
* Composition with flexible window position and size versus output
display
* Blending with flexible layer order and alpha value (per pixel or
constant)
* Background underlying color
* Gamma with non-linear configurable table
* Dithering for output with less bits per component (pseudo-random on
2 bits)
* Polarity inversion for HSync, VSync, and DataEnable outputs
* Output as RGB888 24 bpp or YUV422 16 bpp
* Secure layer (using Layer2) capability, with grouped regs and
additional interrupt set
* Interrupts based on 7 different events
* AXI master interface with long efficient bursts (64 or 128 bytes)
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135.dtsi
b/arch/arm/boot/dts/st/stm32mp135.dtsi
index 68d32f9f5314..834a4d545fe4 100644
--- a/arch/arm/boot/dts/st/stm32mp135.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp135.dtsi
@@ -19,5 +19,16 @@ dcmipp: dcmipp@5a00 {
port {
};
};
+
+ ltdc: display-controller@5a001000 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x5a001000 0x400>;
+ interrupts = ,
+;
+ clocks = <&rcc LTDC_PX>;
+ clock-names = "lcd";
+ resets = <&scmi_reset RST_SCMI_LTDC>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH v2 4/4] dt-bindings: display: simple: hardware can use several properties
Setting a panel-timing in the device-tree overwrite the one specified in the driver and set it as preferred. In that case 'height-mm', 'width-mm' and 'panel-timing' are properties that can be use for simple panels, according to panel-common.yaml Fixes following warnings: arch/arm/boot/dts/st/stm32mp135f-dk.dtb: panel-rgb: 'height-mm', 'panel-timing', 'width-mm' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/display/panel/panel-simple.yaml# Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/panel/panel-simple.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 634a10c6f2dd..c02cbbc7a100 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -352,6 +352,9 @@ properties: no-hpd: true hpd-gpios: true data-mapping: true + height-mm: true + width-mm: true + panel-timing: true if: not: -- 2.25.1
Re: [PATCH 0/5] Add display support for stm32mp135f-dk board
Hi Alex
On 2/14/24 14:40, Alexandre TORGUE wrote:
> Hi Raphael
>
> On 2/5/24 10:06, Raphael Gallais-Pou wrote:
>> This serie aims to enable display support for the stm32mp135f-dk board
>>
>> Those are only patches of the device-tree since the driver support has
>> already been added [1].
>>
>> It respectivelly:
>> - adds support for the display controller on stm32mp135
>> - adds pinctrl for the display controller
>> - enables panel, backlight and display controller on
>> stm32mp135f-dk
>>
>> Finally it fixes the flags on the panel default mode in the
>> 'panel-simple' driver, allowing to override the default mode by one
>> described in the device tree, and push further the blanking limit on the
>> panel.
>>
>> [1] commit 1726cee3d053 ("drm/stm: ltdc: support of new hardware version")
>>
>> Signed-off-by: Raphael Gallais-Pou
>> ---
>> Raphael Gallais-Pou (5):
>> ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
>> ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
>> ARM: dts: stm32: enable display support on stm32mp135f-dk board
>> drm/panel: simple: fix flags on RK043FN48H
>> drm/panel: simple: push blanking limit on RK32FN48H
>>
>> arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 57
>> +
>> arch/arm/boot/dts/st/stm32mp135.dtsi | 11 ++
>> arch/arm/boot/dts/st/stm32mp135f-dk.dts | 55
>>
>> drivers/gpu/drm/panel/panel-simple.c | 7 ++--
>> 4 files changed, 127 insertions(+), 3 deletions(-)
>> ---
>> base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
>> change-id: 20240124-ltdc_mp13-2f86a782424c
>>
>> Best regards,
>
> I got the following errors during YAML verification:
>
> arch/arm/boot/dts/st/stm32mp135f-dk.dtb: /soc/i2c@40012000/pinctrl@21: failed
> to match any schema with compatible: ['microchip,mcp23017']
> /local/home/frq08678/STLINUX/kernel/my-kernel/stm32/arch/arm/boot/dts/st/stm32mp135f-dk.dtb:
> panel-backlight: 'default-brightness-level' does not match any of the regexes:
> 'pinctrl-[0-9]+'
> from schema $id:
> http://devicetree.org/schemas/leds/backlight/gpio-backlight.yaml#
> /local/home/frq08678/STLINUX/kernel/my-kernel/stm32/arch/arm/boot/dts/st/stm32mp135f-dk.dtb:
> panel-rgb: data-mapping:0: 'bgr666' is not one of ['jeida-18', 'jeida-24',
> 'vesa-24']
> from schema $id:
> http://devicetree.org/schemas/display/panel/panel-simple.yaml#
> /local/home/frq08678/STLINUX/kernel/my-kernel/stm32/arch/arm/boot/dts/st/stm32mp135f-dk.dtb:
> panel-rgb: compatible: ['rocktech,rk043fn48h', 'panel-dpi'] is too long
> from schema $id:
> http://devicetree.org/schemas/display/panel/panel-simple.yaml#
> /local/home/frq08678/STLINUX/kernel/my-kernel/stm32/arch/arm/boot/dts/st/stm32mp135f-dk.dtb:
> panel-rgb: data-mapping: False schema does not allow ['bgr666']
> from schema $id:
> http://devicetree.org/schemas/display/panel/panel-simple.yaml#
> /local/home/frq08678/STLINUX/kernel/my-kernel/stm32/arch/arm/boot/dts/st/stm32mp135f-dk.dtb:
> panel-rgb: 'height-mm', 'panel-timing', 'width-mm' do not match any of the
> regexes: 'pinctrl-[0-9]+'
> from schema $id:
> http://devicetree.org/schemas/display/panel/panel-simple.yaml#
> /local/home/frq08678/STLINUX/kernel/my-kernel/stm32/arch/arm/boot/dts/st/stm32mp135f-dk.dtb:
> panel-rgb: 'data-mapping' does not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id:
> http://devicetree.org/schemas/display/panel/panel-dpi.yaml#
>
> Do I miss something ?
I think I messed using a wrong make option :
make DTBS_CHECK=y W=1 -j$(nproc) st/stm32mp135f-dk.dtb
instead of
make CHECK_DTBS=y W=1 -j$(nproc) st/stm32mp135f-dk.dtb
I'll send a fix promptly.
Thanks,
Raphaël
>
> Alex
>
>
[PATCH v5 2/3] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It is composed of three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- Changes in v5: - Align compatible Changes in v4: - Explicitly include linux/platform_device.h, dependency introduced by ef175b29a242 of: Stop circularly including of_device.h and of_platform.h Changes in v3: - s/regroups/is composed of/ in commit log - Change the compatible to show SoC specificity Changes in v2: - Fixed Camel Case macros - Removed debug log --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1226 ++ 3 files changed, 1239 insertions(+) diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..4616544cb886 --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Raphaël GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identification register */ + +/* Bitfield description */ +#define CR_LVDSEN BIT(0) /* LVDS
[PATCH v5 1/3] dt-bindings: display: add STM32 LVDS device
Add "st,stm32mp25-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
Depends on: "dt-bindings: stm32: add clocks and reset binding for
stm32mp25 platform" by Gabriel Fernandez
Changes in v5:
- Fixed path in MAINTAINERS
Changes in v4:
- Align filename to compatible
- Fix compatible in the example
- Remove redundant word in the subject
Changes in v3:
- Clarify commit dependency
- Fix includes in the example
- Fix YAML
- Add "clock-cells" description
- s/regroups/is composed of/
- Changed compatible to show SoC specificity
Changes in v2:
- Switch compatible and clock-cells related areas
- Remove faulty #include in the example.
- Add entry in MAINTAINERS
---
.../bindings/display/st,stm32mp25-lvds.yaml| 119 +
MAINTAINERS| 1 +
2 files changed, 120 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
new file mode 100644
index ..6736f93256b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It is composed of three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ compatible:
+const: st,stm32mp25-lvds
+
+ "#clock-cells":
+const: 0
+description:
+ Provides the internal LVDS PHY clock to the framework.
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+lvds: lvds@4806 {
+compatible = "st,stm32mp25-lvds";
+reg = <0x4806 0x2000>;
+#clock-cells = <0>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 59b3da17debc..225e8ae75eee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7231,6 +7231,7 @@ L:dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
+F: Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
F: drivers/gpu/drm/stm
DRM DRIVERS FOR TI KEYSTONE
--
2.25.1
[PATCH v5 3/3] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
Changes in v2:
- Fixed my address
- Fixed smatch warning
---
drivers/gpu/drm/stm/ltdc.c | 19 +++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..23011a8913bd 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1896,6 +1902,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1918,13 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ clk_disable_unprepare(ldev->pixel_clk);
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1981,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..4a60ce5b610c 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH v5 0/3] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Changes in v5: - Fixed path in MAINTAINERS - Fixed compatible in driver Changes in v4: - Align dt-bindings filename and compatible - Remove redundant word in [1/6] subject - Fix example on typo - Some minor fixes on YAML syntax - Explicitly include linux/platform_device.h - Drop device-tree related patch after internal discussions - Rebase on latest drm-misc-next Changes in v3: - Changed the compatible to show SoC specificity - Fixed includes in dt-binding example - Added "#clock-cells" description in dt-binding example - Some minor fixes on typo Changes in v2: - Dropped [1/8] because already merged - Dropped [4/8] since not mandatory for this serie - [1/6]: Switch compatible and clock-cells related areas - [1/6]: Remove faulty #include in the example. - [1/6]: Add missing entry in MAINTAINERS - [2/6]: Removed CamelCase macros - [2/6]: Removed hard to read debug log - [3/6]: Fixed my address - [3/6]: Fixed smatch warning - [5/6]: Move changes to stm32mp255.dtsi Signed-off-by: Raphael Gallais-Pou --- Raphael Gallais-Pou (3): dt-bindings: display: add STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock .../bindings/display/st,stm32mp25-lvds.yaml| 119 ++ MAINTAINERS|1 + drivers/gpu/drm/stm/Kconfig| 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c | 19 + drivers/gpu/drm/stm/ltdc.h |1 + drivers/gpu/drm/stm/lvds.c | 1226 7 files changed, 1379 insertions(+) --- base-commit: bb3bc3eac316b7c388733e625cc2343131b69dee change-id: 20240205-lvds-e084ec50e878 Best regards, -- Raphael Gallais-Pou
[PATCH v4 2/3] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It is composed of three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- Changes in v4: - Explicitly include linux/platform_device.h, dependency introduced by ef175b29a242 of: Stop circularly including of_device.h and of_platform.h Changes in v3: - s/regroups/is composed of/ in commit log - Change the compatible to show SoC specificity Changes in v2: - Fixed Camel Case macros - Removed debug log --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1226 ++ 3 files changed, 1239 insertions(+) diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..ff872788943d --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Raphaël GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identification register */ + +/* Bitfield description */ +#define CR_LVDSEN BIT(0) /* LVDS PHY Enable */ +#define CR_HSPOL BIT(1) /*
[PATCH v4 1/3] dt-bindings: display: add STM32 LVDS device
Add "st,stm32mp25-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
Depends on: "dt-bindings: stm32: add clocks and reset binding for
stm32mp25 platform" by Gabriel Fernandez
Changes in v4:
- Align filename to compatible
- Fix compatible in the example
- Remove redundant word in the subject
Changes in v3:
- Clarify commit dependency
- Fix includes in the example
- Fix YAML
- Add "clock-cells" description
- s/regroups/is composed of/
- Changed compatible to show SoC specificity
Changes in v2:
- Switch compatible and clock-cells related areas
- Remove faulty #include in the example.
- Add entry in MAINTAINERS
---
.../bindings/display/st,stm32mp25-lvds.yaml| 119 +
MAINTAINERS| 1 +
2 files changed, 120 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
new file mode 100644
index ..6736f93256b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It is composed of three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ compatible:
+const: st,stm32mp25-lvds
+
+ "#clock-cells":
+const: 0
+description:
+ Provides the internal LVDS PHY clock to the framework.
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+lvds: lvds@4806 {
+compatible = "st,stm32mp25-lvds";
+reg = <0x4806 0x2000>;
+#clock-cells = <0>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 59b3da17debc..1736b243d7d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7231,6 +7231,7 @@ L:dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
+F: Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
F: drivers/gpu/drm/stm
DRM DRIVERS FOR TI KEYSTONE
--
2.25.1
[PATCH v4 0/3] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Changes in v4: - Align dt-bindings filename and compatible - Remove redundant word in [1/6] subject - Fix example on typo - Some minor fixes on YAML syntax - Explicitly include linux/platform_device.h - Drop device-tree related patch after internal discussions - Rebase on latest drm-misc-next Changes in v3: - Changed the compatible to show SoC specificity - Fixed includes in dt-binding example - Added "#clock-cells" description in dt-binding example - Some minor fixes on typo Changes in v2: - Dropped [1/8] because already merged - Dropped [4/8] since not mandatory for this serie - [1/6]: Switch compatible and clock-cells related areas - [1/6]: Remove faulty #include in the example. - [1/6]: Add missing entry in MAINTAINERS - [2/6]: Removed CamelCase macros - [2/6]: Removed hard to read debug log - [3/6]: Fixed my address - [3/6]: Fixed smatch warning - [5/6]: Move changes to stm32mp255.dtsi Signed-off-by: Raphael Gallais-Pou --- Raphael Gallais-Pou (3): dt-bindings: display: add STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock .../bindings/display/st,stm32mp25-lvds.yaml| 119 ++ MAINTAINERS|1 + drivers/gpu/drm/stm/Kconfig| 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c | 19 + drivers/gpu/drm/stm/ltdc.h |1 + drivers/gpu/drm/stm/lvds.c | 1226 7 files changed, 1379 insertions(+) --- base-commit: bb3bc3eac316b7c388733e625cc2343131b69dee change-id: 20240205-lvds-e084ec50e878 Best regards, -- Raphael Gallais-Pou
[PATCH v4 3/3] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
Changes in v2:
- Fixed my address
- Fixed smatch warning
---
drivers/gpu/drm/stm/ltdc.c | 19 +++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..23011a8913bd 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1896,6 +1902,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1918,13 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ clk_disable_unprepare(ldev->pixel_clk);
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1981,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..4a60ce5b610c 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH 5/5] drm/panel: simple: push blanking limit on RK32FN48H
Push horizontal front porch and vertical back porch blanking limit.
This allows to get a 60 fps sharp.
Signed-off-by: Raphael Gallais-Pou
---
drivers/gpu/drm/panel/panel-simple.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 7b286382ffb4..10b361d603be 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3516,10 +3516,10 @@ static const struct display_timing
rocktech_rk043fn48h_timing = {
.pixelclock = { 600, 900, 1200 },
.hactive = { 480, 480, 480 },
.hback_porch = { 8, 43, 43 },
- .hfront_porch = { 2, 8, 8 },
+ .hfront_porch = { 2, 8, 10 },
.hsync_len = { 1, 1, 1 },
.vactive = { 272, 272, 272 },
- .vback_porch = { 2, 12, 12 },
+ .vback_porch = { 2, 12, 26 },
.vfront_porch = { 1, 4, 4 },
.vsync_len = { 1, 10, 10 },
.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
--
2.25.1
[PATCH 2/5] ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
Adds LTDC pinctrl support and assigns dedicated GPIO pins.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 57 +
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
index 27e0c3826789..32c5d8a1e06a 100644
--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi
@@ -47,6 +47,63 @@ pins {
};
};
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = , /* LCD_CLK */
+, /* LCD_HSYNC */
+, /* LCD_VSYNC */
+, /* LCD_DE */
+, /* LCD_R2 */
+, /* LCD_R3 */
+, /* LCD_R4 */
+, /* LCD_R5 */
+, /* LCD_R6 */
+, /* LCD_R7 */
+, /* LCD_G2 */
+, /* LCD_G3 */
+, /* LCD_G4 */
+, /* LCD_G5 */
+, /* LCD_G6 */
+, /* LCD_G7 */
+, /* LCD_B2 */
+, /* LCD_B3 */
+, /* LCD_B4 */
+, /* LCD_B5 */
+, /* LCD_B6 */
+; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = , /* LCD_CLK */
+, /* LCD_HSYNC
*/
+, /* LCD_VSYNC
*/
+, /* LCD_DE */
+, /* LCD_R2 */
+, /* LCD_R3 */
+, /* LCD_R4 */
+, /* LCD_R5 */
+, /* LCD_R6 */
+, /* LCD_R7 */
+, /* LCD_G2 */
+, /* LCD_G3 */
+, /* LCD_G4 */
+, /* LCD_G5 */
+, /* LCD_G6 */
+, /* LCD_G7 */
+, /* LCD_B2 */
+, /* LCD_B3 */
+, /* LCD_B4 */
+, /* LCD_B5 */
+, /* LCD_B6 */
+; /* LCD_B7 */
+ };
+ };
+
mcp23017_pins_a: mcp23017-0 {
pins {
pinmux = ;
--
2.25.1
[PATCH 0/5] Add display support for stm32mp135f-dk board
This serie aims to enable display support for the stm32mp135f-dk board
Those are only patches of the device-tree since the driver support has
already been added [1].
It respectivelly:
- adds support for the display controller on stm32mp135
- adds pinctrl for the display controller
- enables panel, backlight and display controller on
stm32mp135f-dk
Finally it fixes the flags on the panel default mode in the
'panel-simple' driver, allowing to override the default mode by one
described in the device tree, and push further the blanking limit on the
panel.
[1] commit 1726cee3d053 ("drm/stm: ltdc: support of new hardware version")
Signed-off-by: Raphael Gallais-Pou
---
Raphael Gallais-Pou (5):
ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
ARM: dts: stm32: enable display support on stm32mp135f-dk board
drm/panel: simple: fix flags on RK043FN48H
drm/panel: simple: push blanking limit on RK32FN48H
arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 57 +
arch/arm/boot/dts/st/stm32mp135.dtsi| 11 ++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 55
drivers/gpu/drm/panel/panel-simple.c| 7 ++--
4 files changed, 127 insertions(+), 3 deletions(-)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240124-ltdc_mp13-2f86a782424c
Best regards,
--
Raphael Gallais-Pou
[PATCH 4/5] drm/panel: simple: fix flags on RK043FN48H
DISPLAY_FLAGS_SYNC_POSEDGE is missing in the flags on the default
timings. When overriding the default mode with one described in the
device tree, the mode does not get acked because of this missing flag.
Moreover since the panel is driven by the positive edge it makes sense
to add it here.
Signed-off-by: Raphael Gallais-Pou
---
drivers/gpu/drm/panel/panel-simple.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 2214cb09678c..7b286382ffb4 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3523,7 +3523,8 @@ static const struct display_timing
rocktech_rk043fn48h_timing = {
.vfront_porch = { 1, 4, 4 },
.vsync_len = { 1, 10, 10 },
.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
-DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
+DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
+DISPLAY_FLAGS_SYNC_POSEDGE,
};
static const struct panel_desc rocktech_rk043fn48h = {
--
2.25.1
[PATCH 3/5] ARM: dts: stm32: enable display support on stm32mp135f-dk board
Link panel and display controller.
Enable panel, backlight and display controller.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index eea740d097c7..4a52d314c46d 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -66,6 +66,48 @@ led-blue {
default-state = "off";
};
};
+
+ panel_backlight: panel-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
+ panel_rgb: panel-rgb {
+ compatible = "rocktech,rk043fn48h", "panel-dpi";
+ enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_backlight>;
+ power-supply = <&scmi_v3v3_sw>;
+ data-mapping = "bgr666";
+ status = "okay";
+
+ width-mm = <105>;
+ height-mm = <67>;
+
+ panel-timing {
+ clock-frequency = <1000>;
+ hactive = <480>;
+ hback-porch = <43>;
+ hfront-porch = <10>;
+ hsync-len = <1>;
+ hsync-active = <0>;
+ vactive = <272>;
+ vback-porch = <26>;
+ vfront-porch = <4>;
+ vsync-len = <10>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
};
&adc_1 {
@@ -160,6 +202,19 @@ &iwdg2 {
status = "okay";
};
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
--
2.25.1
[PATCH 1/5] ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal
display - Thin film transistor) Display Controller.
It provides a parallel digital RGB (red, green, blue) and signals for
horizontal, vertical synchronization, pixel clock and data enable as
output to interface directly to a variety of LCD-TFT panels.
Main features
* 2 input layers blended together to compose the display
* Cropping of layers from any input size and location
* Multiple input pixel formats:
– Predefined ARGB, with 7 formats: ARGB, ABGR, RGBA,
BGRA, RGB565, BGR565, RGB888packed.
– Flexible ARGB, allowing any width and location for A,R,G,B
components.
– Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV,
Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L
(FourCC: Yxx, full planar) with some flexibility on the sequence of
the component.
* Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer
* Color transparency keying
* Composition with flexible window position and size versus output
display
* Blending with flexible layer order and alpha value (per pixel or
constant)
* Background underlying color
* Gamma with non-linear configurable table
* Dithering for output with less bits per component (pseudo-random on
2 bits)
* Polarity inversion for HSync, VSync, and DataEnable outputs
* Output as RGB888 24 bpp or YUV422 16 bpp
* Secure layer (using Layer2) capability, with grouped regs and
additional interrupt set
* Interrupts based on 7 different events
* AXI master interface with long efficient bursts (64 or 128 bytes)
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp135.dtsi
b/arch/arm/boot/dts/st/stm32mp135.dtsi
index 68d32f9f5314..834a4d545fe4 100644
--- a/arch/arm/boot/dts/st/stm32mp135.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp135.dtsi
@@ -19,5 +19,16 @@ dcmipp: dcmipp@5a00 {
port {
};
};
+
+ ltdc: display-controller@5a001000 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x5a001000 0x400>;
+ interrupts = ,
+;
+ clocks = <&rcc LTDC_PX>;
+ clock-names = "lcd";
+ resets = <&scmi_reset RST_SCMI_LTDC>;
+ status = "disabled";
+ };
};
};
--
2.25.1
[PATCH RESEND v3 0/3] Update STM DSI PHY driver
This patch series aims to add several features of the dw-mipi-dsi phy driver that are missing or need to be updated. First patch update a PM macro. Second patch adds runtime PM functionality to the driver. Third patch adds a clock provider generated by the PHY itself. As explained in the commit log of the second patch, a clock declaration is missing. Since this clock is parent of 'dsi_k', it leads to an orphan clock. Most importantly this patch is an anticipation for future versions of the DSI PHY, and its inclusion within the display subsystem and the DRM framework. Last patch fixes a corner effect introduced previously. Since 'dsi' and 'dsi_k' are gated by the same bit on the same register, both reference work as peripheral clock in the device-tree. --- Changes in v3-resend: - Removed last patch as it has been merged https://lore.kernel.org/lkml/bf49f4c9-9e81-4c91-972d-13782d996...@foss.st.com/ Changes in v3: - Fix smatch warning (disable dsi->pclk when clk_register fails) Changes in v2: - Added patch 1/4 to use SYSTEM_SLEEP_PM_OPS instead of old macro and removed __maybe_used for accordingly - Changed SET_RUNTIME_PM_OPS to RUNTIME_PM_OPS Raphael Gallais-Pou (3): drm/stm: dsi: use new SYSTEM_SLEEP_PM_OPS() macro drm/stm: dsi: expose DSI PHY internal clock Yannick Fertre (1): drm/stm: dsi: add pm runtime ops drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 279 ++ 1 file changed, 238 insertions(+), 41 deletions(-) -- 2.25.1
[PATCH RESEND v3 3/3] drm/stm: dsi: expose DSI PHY internal clock
DSISRC __
__\_
|\
pll4_p_ck ->| 1 |dsi_k
ck_dsi_phy ->| 0 |
|/
A DSI clock is missing in the clock framework. Looking at the
clk_summary, it appears that 'ck_dsi_phy' is not implemented. Since the
DSI kernel clock is based on the internal DSI pll. The common clock
driver can not directly expose this 'ck_dsi_phy' clock because it does
not contain any common registers with the DSI. Thus it needs to be done
directly within the DSI phy driver.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v3:
- Fix smatch warning:
.../dw_mipi_dsi-stm.c:719 dw_mipi_dsi_stm_probe() warn: 'dsi->pclk'
from clk_prepare_enable() not released on lines: 719.
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 247 ++
1 file changed, 216 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 82fff9e84345..b20123854c4a 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -7,7 +7,9 @@
*/
#include
+#include
#include
+#include
#include
#include
#include
@@ -77,9 +79,12 @@ enum dsi_color {
struct dw_mipi_dsi_stm {
void __iomem *base;
+ struct device *dev;
struct clk *pllref_clk;
struct clk *pclk;
+ struct clk_hw txbyte_clk;
struct dw_mipi_dsi *dsi;
+ struct dw_mipi_dsi_plat_data pdata;
u32 hw_version;
int lane_min_kbps;
int lane_max_kbps;
@@ -196,29 +201,198 @@ static int dsi_pll_get_params(struct dw_mipi_dsi_stm
*dsi,
return 0;
}
-static int dw_mipi_dsi_phy_init(void *priv_data)
+#define clk_to_dw_mipi_dsi_stm(clk) \
+ container_of(clk, struct dw_mipi_dsi_stm, txbyte_clk)
+
+static void dw_mipi_dsi_clk_disable(struct clk_hw *clk)
{
- struct dw_mipi_dsi_stm *dsi = priv_data;
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /* Disable the DSI PLL */
+ dsi_clear(dsi, DSI_WRPCR, WRPCR_PLLEN);
+
+ /* Disable the regulator */
+ dsi_clear(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
+}
+
+static int dw_mipi_dsi_clk_enable(struct clk_hw *clk)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
u32 val;
int ret;
+ DRM_DEBUG_DRIVER("\n");
+
/* Enable the regulator */
dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
- ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
-SLEEP_US, TIMEOUT_US);
+ ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val &
WISR_RRS,
+ SLEEP_US, TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
/* Enable the DSI PLL & wait for its lock */
dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
- ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
-SLEEP_US, TIMEOUT_US);
+ ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val &
WISR_PLLLS,
+ SLEEP_US, TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
return 0;
}
+static int dw_mipi_dsi_clk_is_enabled(struct clk_hw *hw)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
+
+ return dsi_read(dsi, DSI_WRPCR) & WRPCR_PLLEN;
+}
+
+static unsigned long dw_mipi_dsi_clk_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
+ unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+ u32 val;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ pll_in_khz = (unsigned int)(parent_rate / 1000);
+
+ val = dsi_read(dsi, DSI_WRPCR);
+
+ idf = (val & WRPCR_IDF) >> 11;
+ if (!idf)
+ idf = 1;
+ ndiv = (val & WRPCR_NDIV) >> 2;
+ odf = int_pow(2, (val & WRPCR_ODF) >> 16);
+
+ /* Get the adjusted pll out value */
+ pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
+
+ return (unsigned long)pll_out_khz * 1000;
+}
+
+static long dw_mipi_dsi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
+ unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+ int ret;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ pll_in_khz = (unsigned int)(*parent_rate / 1000);
+
+ /* Compute best pll parame
[PATCH RESEND v3 2/3] drm/stm: dsi: add pm runtime ops
From: Yannick Fertre
Update control of clocks and supply thanks to the PM runtime
mechanism to avoid kernel crash during a system suspend.
Signed-off-by: Yannick Fertre
Signed-off-by: Raphael Gallais-Pou
---
Changes in v2:
- Changed SET_RUNTIME_PM_OPS to RUNTIME_PM_OPS and removed
__maybe_unused
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index b1aee43d51e9..82fff9e84345 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
@@ -77,6 +78,7 @@ enum dsi_color {
struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+ struct clk *pclk;
struct dw_mipi_dsi *dsi;
u32 hw_version;
int lane_min_kbps;
@@ -443,7 +445,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
*pdev)
{
struct device *dev = &pdev->dev;
struct dw_mipi_dsi_stm *dsi;
- struct clk *pclk;
int ret;
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
@@ -483,21 +484,21 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
*pdev)
goto err_clk_get;
}
- pclk = devm_clk_get(dev, "pclk");
- if (IS_ERR(pclk)) {
- ret = PTR_ERR(pclk);
+ dsi->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(dsi->pclk)) {
+ ret = PTR_ERR(dsi->pclk);
DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
goto err_dsi_probe;
}
- ret = clk_prepare_enable(pclk);
+ ret = clk_prepare_enable(dsi->pclk);
if (ret) {
DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
goto err_dsi_probe;
}
dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
- clk_disable_unprepare(pclk);
+ clk_disable_unprepare(dsi->pclk);
if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
ret = -ENODEV;
@@ -551,6 +552,7 @@ static int dw_mipi_dsi_stm_suspend(struct device *dev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(dsi->pllref_clk);
+ clk_disable_unprepare(dsi->pclk);
regulator_disable(dsi->vdd_supply);
return 0;
@@ -569,8 +571,16 @@ static int dw_mipi_dsi_stm_resume(struct device *dev)
return ret;
}
+ ret = clk_prepare_enable(dsi->pclk);
+ if (ret) {
+ regulator_disable(dsi->vdd_supply);
+ DRM_ERROR("Failed to enable pclk: %d\n", ret);
+ return ret;
+ }
+
ret = clk_prepare_enable(dsi->pllref_clk);
if (ret) {
+ clk_disable_unprepare(dsi->pclk);
regulator_disable(dsi->vdd_supply);
DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
return ret;
@@ -582,6 +592,8 @@ static int dw_mipi_dsi_stm_resume(struct device *dev)
static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
dw_mipi_dsi_stm_resume)
+ RUNTIME_PM_OPS(dw_mipi_dsi_stm_suspend,
+ dw_mipi_dsi_stm_resume, NULL)
};
static struct platform_driver dw_mipi_dsi_stm_driver = {
--
2.25.1
[PATCH RESEND v3 1/3] drm/stm: dsi: use new SYSTEM_SLEEP_PM_OPS() macro
Use RUNTIME_PM_OPS() instead of the old SET_SYSTEM_SLEEP_PM_OPS().
This means we don't need __maybe_unused on the functions.
Signed-off-by: Raphael Gallais-Pou
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index d5f8c923d7bc..b1aee43d51e9 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -544,7 +544,7 @@ static void dw_mipi_dsi_stm_remove(struct platform_device
*pdev)
regulator_disable(dsi->vdd_supply);
}
-static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev)
+static int dw_mipi_dsi_stm_suspend(struct device *dev)
{
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
@@ -556,7 +556,7 @@ static int __maybe_unused dw_mipi_dsi_stm_suspend(struct
device *dev)
return 0;
}
-static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev)
+static int dw_mipi_dsi_stm_resume(struct device *dev)
{
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
int ret;
@@ -580,8 +580,8 @@ static int __maybe_unused dw_mipi_dsi_stm_resume(struct
device *dev)
}
static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
- dw_mipi_dsi_stm_resume)
+ SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
+ dw_mipi_dsi_stm_resume)
};
static struct platform_driver dw_mipi_dsi_stm_driver = {
--
2.25.1
Re: [PATCH v3 1/6] dt-bindings: display: add dt-bindings for STM32 LVDS device
On 1/16/24 08:42, Krzysztof Kozlowski wrote: > On 15/01/2024 17:51, Raphael Gallais-Pou wrote: >> On 1/15/24 16:46, Rob Herring wrote: >>> On Mon, Jan 15, 2024 at 02:20:04PM +0100, Raphael Gallais-Pou wrote: >>>> Add "st,stm32mp25-lvds" compatible. >>>> > A nit, subject: drop second/last, redundant "dt-bindings for". The > "dt-bindings" prefix is already stating that these are bindings. > See also: > https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > >>>> Signed-off-by: Raphael Gallais-Pou >>>> --- >>>> Depends on: "dt-bindings: stm32: add clocks and reset binding for >>>>stm32mp25 platform" by Gabriel Fernandez >>>> >>>> Changes in v3: >>>>- Clarify commit dependency >>>>- Fix includes in the example >>>>- Fix YAML >>>>- Add "clock-cells" description >>>>- s/regroups/is composed of/ >>>>- Changed compatible to show SoC specificity >>>> >>>> Changes in v2: >>>>- Switch compatible and clock-cells related areas >>>>- Remove faulty #include in the example. >>>>- Add entry in MAINTAINERS >>>> --- >>>> .../bindings/display/st,stm32-lvds.yaml | 119 ++ >>> Filename matching compatible. >> Hi Rob, >> >> >> I was unsure about this. >> >> The driver will eventually support several SoCs with different compatibles, >> wouldn't this be more confusing ? > No. "Eventually" might never happen. > >> I also wanted to keep the similarity with the "st,stm32-.yaml" name for >> the >> DRM STM drivers. Would that be possible ? > But why? The consistency we want is the filename matching compatible, > not matching other filenames. If you have here multiple devices, > document them *now*. Hi Krzysztof, |There is no multiple devices, so I will stick to the "st,stm32mp25-lvds" pattern for now.| > >> >> Regards, >> >> Raphaël > I hope you did not ignore rest of the comments... We expect some sort of > "ack/ok/I'll fix/whatever" message and you wrote nothing further. Although I did not acknowledged what has been said previously, I always take into account every comment on my patches. I understand that it can lead to some confusion. So rest assured that I did not ignore Rob's and Dmitry's review. Regards, Raphaël > > Best regards, > Krzysztof >
Re: [PATCH v3 1/6] dt-bindings: display: add dt-bindings for STM32 LVDS device
On 1/15/24 16:46, Rob Herring wrote:
> On Mon, Jan 15, 2024 at 02:20:04PM +0100, Raphael Gallais-Pou wrote:
>> Add "st,stm32mp25-lvds" compatible.
>>
>> Signed-off-by: Raphael Gallais-Pou
>> ---
>> Depends on: "dt-bindings: stm32: add clocks and reset binding for
>> stm32mp25 platform" by Gabriel Fernandez
>>
>> Changes in v3:
>> - Clarify commit dependency
>> - Fix includes in the example
>> - Fix YAML
>> - Add "clock-cells" description
>> - s/regroups/is composed of/
>> - Changed compatible to show SoC specificity
>>
>> Changes in v2:
>> - Switch compatible and clock-cells related areas
>> - Remove faulty #include in the example.
>> - Add entry in MAINTAINERS
>> ---
>> .../bindings/display/st,stm32-lvds.yaml | 119 ++
> Filename matching compatible.
Hi Rob,
I was unsure about this.
The driver will eventually support several SoCs with different compatibles,
wouldn't this be more confusing ?
I also wanted to keep the similarity with the "st,stm32-.yaml" name for the
DRM STM drivers. Would that be possible ?
Regards,
Raphaël
>
>> +properties:
>> + compatible:
>> +const: st,stm32mp25-lvds
>
>> +examples:
>> + - |
>> +#include
>> +#include
>> +
>> +lvds: lvds@4806 {
>> +compatible = "st,stm32-lvds";
> Wrong compatible.
[PATCH v3 4/6] arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation. It provides a parallel digital RGB flow to be used
by display interfaces.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi
b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 5189d5a4f6a9..4446996c8f5d 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -218,6 +218,18 @@ i2c8: i2c@4604 {
status = "disabled";
};
+ ltdc: display-controller@4801 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x4801 0x400>;
+ st,syscon = <&syscfg>;
+ interrupts = ,
+ ;
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>;
+ clock-names = "bus", "lcd";
+ resets = <&rcc LTDC_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@4822 {
compatible = "st,stm32mp25-sdmmc2",
"arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
--
2.25.1
[PATCH v3 5/6] arm64: dts: st: add lvds support on stm32mp255
This patch adds LVDS support on stm32mp255. The LVDS is used on
STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC
input clock.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v3:
- Change the compatible to show SoC specificity
Changes in v2:
- Move patch to stm32mp255.dtsi after internal discussions
---
arch/arm64/boot/dts/st/stm32mp255.dtsi | 17 +
drivers/gpu/drm/stm/lvds.c | 2 +-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi
b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index e6fa596211f5..68f60da32126 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -7,3 +7,20 @@
/ {
};
+
+<dc {
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, <&lvds 0>;
+ clock-names = "bus", "lcd", "lvds";
+};
+
+&rifsc {
+ lvds: lvds@4806 {
+ #clock-cells = <0>;
+ compatible = "st,stm32mp25-lvds";
+ reg = <0x4806 0x2000>;
+ clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc LVDS_R>;
+ status = "disabled";
+ };
+};
diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c
index beb8b7e437a0..5808db1a5cdf 100644
--- a/drivers/gpu/drm/stm/lvds.c
+++ b/drivers/gpu/drm/stm/lvds.c
@@ -1198,7 +1198,7 @@ static int lvds_remove(struct platform_device *pdev)
static const struct of_device_id lvds_dt_ids[] = {
{
- .compatible = "st,stm32-lvds",
+ .compatible = "st,stm32mp25-lvds",
.data = NULL
},
{ /* sentinel */ }
--
2.25.1
[PATCH v3 6/6] arm64: dts: st: add display support on stm32mp257f-ev
This patch enables the following IPs on stm32mp257f-ev :
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel backlight
* Ilitek touchescreen
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 0ea8e69bfb3d..ca2da988d91c 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -29,6 +29,43 @@ memory@8000 {
reg = <0x0 0x8000 0x1 0x0>;
};
+ panel_lvds: panel-lvds {
+ compatible = "edt,etml0700z9ndha", "panel-lvds";
+ enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_lvds_backlight>;
+ status = "okay";
+
+ width-mm = <156>;
+ height-mm = <92>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ clock-frequency = <5400>;
+ hactive = <1024>;
+ vactive = <600>;
+ hfront-porch = <150>;
+ hback-porch = <150>;
+ hsync-len = <21>;
+ vfront-porch = <24>;
+ vback-porch = <24>;
+ vsync-len = <21>;
+ };
+
+ port {
+ lvds_panel_in: endpoint {
+ remote-endpoint = <&lvds_out0>;
+ };
+ };
+ };
+
+ panel_lvds_backlight: panel-lvds-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -63,6 +100,15 @@ &i2c2 {
i2c-scl-falling-time-ns = <13>;
clock-frequency = <40>;
status = "okay";
+
+ ili2511: ili2511@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
};
&i2c8 {
@@ -75,6 +121,39 @@ &i2c8 {
status = "disabled";
};
+<dc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+ };
+ };
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
--
2.25.1
[PATCH v3 2/6] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It is composed of three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- Changes in v3: - s/regroups/is composed of/ in commit log - Change the compatible to show SoC specificity Changes in v2: - Fixed Camel Case macros - Removed debug log --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1225 ++ 3 files changed, 1238 insertions(+) create mode 100644 drivers/gpu/drm/stm/lvds.c diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..beb8b7e437a0 --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Raphaël GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identification register */ + +/* Bitfield description */ +#define CR_LVDSEN BIT(0) /* LVDS PHY Enable */ +#define CR_HSPOL BIT(1) /* Horizontal Synchronization Polarity */ +#define CR_VSPOL BIT(2) /* Vertical Synchronization Polarity */ +#define CR_DEPOL BIT(3) /* D
[PATCH v3 1/6] dt-bindings: display: add dt-bindings for STM32 LVDS device
Add "st,stm32mp25-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
Depends on: "dt-bindings: stm32: add clocks and reset binding for
stm32mp25 platform" by Gabriel Fernandez
Changes in v3:
- Clarify commit dependency
- Fix includes in the example
- Fix YAML
- Add "clock-cells" description
- s/regroups/is composed of/
- Changed compatible to show SoC specificity
Changes in v2:
- Switch compatible and clock-cells related areas
- Remove faulty #include in the example.
- Add entry in MAINTAINERS
---
.../bindings/display/st,stm32-lvds.yaml | 119 ++
MAINTAINERS | 1 +
2 files changed, 120 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
diff --git a/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
new file mode 100644
index ..a6383858cd2c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It is composed of three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ compatible:
+const: st,stm32mp25-lvds
+
+ "#clock-cells":
+const: 0
+description:
+ Provides the internal LVDS PHY clock to the framework.
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+lvds: lvds@4806 {
+compatible = "st,stm32-lvds";
+reg = <0x4806 0x2000>;
+#clock-cells = <0>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d959a6881f7..0b6ec5347195 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7193,6 +7193,7 @@ L:dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
+F: Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
F: drivers/gpu/drm/stm
DRM DRIVERS FOR TI KEYSTONE
--
2.25.1
[PATCH v3 0/6] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Changes in v3: - Changed the compatible to show SoC specificity - Fixed includes in dt-binding example - Added "#clock-cells" description in dt-binding example - Some minor fixes on typo Changes in v2: - Dropped [1/8] because already merged - Dropped [4/8] since not mandatory for this serie - [1/6]: Switch compatible and clock-cells related areas - [1/6]: Remove faulty #include in the example. - [1/6]: Add missing entry in MAINTAINERS - [2/6]: Removed CamelCase macros - [2/6]: Removed hard to read debug log - [3/6]: Fixed my address - [3/6]: Fixed smatch warning - [5/6]: Move changes to stm32mp255.dtsi Raphael Gallais-Pou (6): dt-bindings: display: add dt-bindings for STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock arm64: dts: st: add ltdc support on stm32mp251 arm64: dts: st: add lvds support on stm32mp255 arm64: dts: st: add display support on stm32mp257f-ev .../bindings/display/st,stm32-lvds.yaml | 119 ++ MAINTAINERS |1 + arch/arm64/boot/dts/st/stm32mp251.dtsi| 12 + arch/arm64/boot/dts/st/stm32mp255.dtsi| 17 + arch/arm64/boot/dts/st/stm32mp257f-ev1.dts| 79 ++ drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c| 19 + drivers/gpu/drm/stm/ltdc.h|1 + drivers/gpu/drm/stm/lvds.c| 1225 + 10 files changed, 1486 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml create mode 100644 drivers/gpu/drm/stm/lvds.c -- 2.25.1
[PATCH v3 3/6] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
Changes in v2:
- Fixed my address
- Fixed smatch warning
---
drivers/gpu/drm/stm/ltdc.c | 19 +++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..23011a8913bd 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1896,6 +1902,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1918,13 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ clk_disable_unprepare(ldev->pixel_clk);
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1981,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..4a60ce5b610c 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH v2 4/6] arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation. It provides a parallel digital RGB flow to be used
by display interfaces.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi
b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 93bc8a8908ce..064077e98dfd 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -212,6 +212,18 @@ i2c8: i2c@4604 {
status = "disabled";
};
+ ltdc: display-controller@4801 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x4801 0x400>;
+ st,syscon = <&syscfg>;
+ interrupts = ,
+ ;
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>;
+ clock-names = "bus", "lcd";
+ resets = <&rcc LTDC_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@4822 {
compatible = "st,stm32mp25-sdmmc2",
"arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
--
2.25.1
[PATCH v2 6/6] arm64: dts: st: add display support on stm32mp257f-ev
This patch enables the following IPs on stm32mp257f-ev :
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel backlight
* Ilitek touchescreen
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 0ea8e69bfb3d..ca2da988d91c 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -29,6 +29,43 @@ memory@8000 {
reg = <0x0 0x8000 0x1 0x0>;
};
+ panel_lvds: panel-lvds {
+ compatible = "edt,etml0700z9ndha", "panel-lvds";
+ enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_lvds_backlight>;
+ status = "okay";
+
+ width-mm = <156>;
+ height-mm = <92>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ clock-frequency = <5400>;
+ hactive = <1024>;
+ vactive = <600>;
+ hfront-porch = <150>;
+ hback-porch = <150>;
+ hsync-len = <21>;
+ vfront-porch = <24>;
+ vback-porch = <24>;
+ vsync-len = <21>;
+ };
+
+ port {
+ lvds_panel_in: endpoint {
+ remote-endpoint = <&lvds_out0>;
+ };
+ };
+ };
+
+ panel_lvds_backlight: panel-lvds-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -63,6 +100,15 @@ &i2c2 {
i2c-scl-falling-time-ns = <13>;
clock-frequency = <40>;
status = "okay";
+
+ ili2511: ili2511@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
};
&i2c8 {
@@ -75,6 +121,39 @@ &i2c8 {
status = "disabled";
};
+<dc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+ };
+ };
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
--
2.25.1
[PATCH v2 5/6] arm64: dts: st: add lvds support on stm32mp255
This patch adds LVDS support on stm32mp255. The LVDS is used on
STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC
input clock.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v2:
- Move patch to stm32mp255.dtsi after internal discussions
---
arch/arm64/boot/dts/st/stm32mp255.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi
b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index e6fa596211f5..ac46a7dbed2d 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -7,3 +7,20 @@
/ {
};
+
+<dc {
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, <&lvds 0>;
+ clock-names = "bus", "lcd", "lvds";
+};
+
+&rifsc {
+ lvds: lvds@4806 {
+ #clock-cells = <0>;
+ compatible = "st,stm32-lvds";
+ reg = <0x4806 0x2000>;
+ clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc LVDS_R>;
+ status = "disabled";
+ };
+};
--
2.25.1
[PATCH v2 2/6] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It regroups three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- Changes in v2: - Fixed Camel Case macros - Removed debug log --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1225 ++ 3 files changed, 1238 insertions(+) create mode 100644 drivers/gpu/drm/stm/lvds.c diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..beb8b7e437a0 --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1225 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Raphaël GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identification register */ + +/* Bitfield description */ +#define CR_LVDSEN BIT(0) /* LVDS PHY Enable */ +#define CR_HSPOL BIT(1) /* Horizontal Synchronization Polarity */ +#define CR_VSPOL BIT(2) /* Vertical Synchronization Polarity */ +#define CR_DEPOL BIT(3) /* Data Enable Polarity */ +#define CR_CI BIT(4) /* Control Internal (software controlled bit) */ +#define CR_LKMOD
[PATCH v2 3/6] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
Changes in v2:
- Fixed my address
- Fixed smatch warning
---
drivers/gpu/drm/stm/ltdc.c | 19 +++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..23011a8913bd 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1896,6 +1902,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1918,13 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ clk_disable_unprepare(ldev->pixel_clk);
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1981,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..4a60ce5b610c 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH v2 1/6] dt-bindings: display: add dt-bindings for STM32 LVDS device
Add "st,stm32-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v2:
- Switch compatible and clock-cells related areas
- Remove faulty #include in the example.
- Add entry in MAINTAINERS
---
.../bindings/display/st,stm32-lvds.yaml | 117 ++
MAINTAINERS | 1 +
2 files changed, 118 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
diff --git a/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
new file mode 100644
index ..8dfc6e88f260
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It regroups three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ compatible:
+const: st,stm32-lvds
+
+ "#clock-cells":
+const: 0
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+
+lvds: lvds@4806 {
+compatible = "st,stm32-lvds";
+reg = <0x4806 0x2000>;
+#clock-cells = <0>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 9d959a6881f7..0b6ec5347195 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7193,6 +7193,7 @@ L:dri-devel@lists.freedesktop.org
S: Maintained
T: git git://anongit.freedesktop.org/drm/drm-misc
F: Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
+F: Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
F: drivers/gpu/drm/stm
DRM DRIVERS FOR TI KEYSTONE
--
2.25.1
[PATCH v2 0/6] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Changes in v2: - Dropped [1/8] because already merged - Dropped [4/8] since not mandatory for this serie - [1/6]: Switch compatible and clock-cells related areas - [1/6]: Remove faulty #include in the example. - [1/6]: Add missing entry in MAINTAINERS - [2/6]: Removed CamelCase macros - [2/6]: Removed hard to read debug log - [3/6]: Fixed my address - [3/6]: Fixed smatch warning - [5/6]: Move changes to stm32mp255.dtsi Raphael Gallais-Pou (6): dt-bindings: display: add dt-bindings for STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock arm64: dts: st: add ltdc support on stm32mp251 arm64: dts: st: add lvds support on stm32mp255 arm64: dts: st: add display support on stm32mp257f-ev .../bindings/display/st,stm32-lvds.yaml | 117 ++ MAINTAINERS |1 + arch/arm64/boot/dts/st/stm32mp251.dtsi| 12 + arch/arm64/boot/dts/st/stm32mp255.dtsi| 17 + arch/arm64/boot/dts/st/stm32mp257f-ev1.dts| 79 ++ drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c| 19 + drivers/gpu/drm/stm/ltdc.h|1 + drivers/gpu/drm/stm/lvds.c| 1225 + 10 files changed, 1484 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml create mode 100644 drivers/gpu/drm/stm/lvds.c -- 2.25.1
Re: [PATCH RESEND v1 4/8] drm/stm: ltdc: implement bus clock
On 12/21/23 14:17, Dmitry Baryshkov wrote:
> On Thu, 21 Dec 2023 at 14:45, Raphael Gallais-Pou
> wrote:
>> From: Yannick Fertre
>>
>> The latest hardware version of the LTDC presents the addition of a bus
>> clock, which contains the global configuration registers and the interrupt
>> register.
>>
>> Signed-off-by: Yannick Fertre
>> ---
>> drivers/gpu/drm/stm/ltdc.c | 8
>> drivers/gpu/drm/stm/ltdc.h | 1 +
>> 2 files changed, 9 insertions(+)
> I might be missing something, but I don't see this clock being set
> (compare this patch to the patch 5/8)
Hi Dmitry,
This patch needs rework. I'll drop it for now and send it back later when it is
more mature.
Regards,
Raphaël
>
>> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
>> index 5576fdae4962..67064f47a4cb 100644
>> --- a/drivers/gpu/drm/stm/ltdc.c
>> +++ b/drivers/gpu/drm/stm/ltdc.c
>> @@ -1896,6 +1896,8 @@ void ltdc_suspend(struct drm_device *ddev)
>>
>> DRM_DEBUG_DRIVER("\n");
>> clk_disable_unprepare(ldev->pixel_clk);
>> + if (ldev->bus_clk)
>> + clk_disable_unprepare(ldev->bus_clk);
>> }
>>
>> int ltdc_resume(struct drm_device *ddev)
>> @@ -1910,6 +1912,12 @@ int ltdc_resume(struct drm_device *ddev)
>> DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
>> return ret;
>> }
>> + if (ldev->bus_clk) {
>> + if (clk_prepare_enable(ldev->bus_clk)) {
>> + DRM_ERROR("Unable to prepare bus clock\n");
>> + return -ENODEV;
>> + }
>> + }
>>
>> return 0;
>> }
>> diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
>> index 9d488043ffdb..155d8e4a7c6b 100644
>> --- a/drivers/gpu/drm/stm/ltdc.h
>> +++ b/drivers/gpu/drm/stm/ltdc.h
>> @@ -44,6 +44,7 @@ struct ltdc_device {
>> void __iomem *regs;
>> struct regmap *regmap;
>> struct clk *pixel_clk; /* lcd pixel clock */
>> + struct clk *bus_clk;/* bus clock */
>> struct mutex err_lock; /* protecting error_status */
>> struct ltdc_caps caps;
>> u32 irq_status;
>> --
>> 2.25.1
>>
>
Re: [PATCH] drm/stm: Fix an error handling path in stm_drm_platform_probe()
Hi Christophe,
On 1/6/24 17:54, Christophe JAILLET wrote:
> If drm_dev_register() fails, a call to drv_load() must be undone, as
> already done in the remove function.
>
> Fixes: b759012c5fa7 ("drm/stm: Add STM32 LTDC driver")
> Signed-off-by: Christophe JAILLET
> ---
> This was already sent a few years ago in [1] but it got no response.
> Since, there has been some activity on this driver, so I send it again.
>
> Note that it is untested.
>
> [1]:
> https://lore.kernel.org/all/20200501125511.132029-1-christophe.jail...@wanadoo.fr/
> ---
> drivers/gpu/drm/stm/drv.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
I tested it against stm32mp157c-dk2.dts.
Thanks for your submission.
Acked-by: Raphael Gallais-Pou
Regards,
Raphaël Gallais-Pou
Re: [PATCH v2] drm/stm: Avoid use-after-free issues with crtc and plane
On 11/24/23 11:04, Katya Orlova wrote:
> ltdc_load() calls functions drm_crtc_init_with_planes(),
> drm_universal_plane_init() and drm_encoder_init(). These functions
> should not be called with parameters allocated with devm_kzalloc()
> to avoid use-after-free issues [1].
>
> Use allocations managed by the DRM framework.
>
> Found by Linux Verification Center (linuxtesting.org).
>
> [1]
> https://lore.kernel.org/lkml/u366i76e3qhh3ra5oxrtngjtm2u5lterkekcz6y2jkndhuxzli@diujon4h7qwb/
>
> Signed-off-by: Katya Orlova
> ---
> v2: use allocations managed by the DRM as
> Raphael Gallais-Pou suggested.
> Also add a fix for encoder.
> drivers/gpu/drm/stm/drv.c | 3 +-
> drivers/gpu/drm/stm/ltdc.c | 68 +-
> 2 files changed, 18 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
> index e8523abef27a..152bec2c0238 100644
> --- a/drivers/gpu/drm/stm/drv.c
> +++ b/drivers/gpu/drm/stm/drv.c
> @@ -25,6 +25,7 @@
> #include
> #include
> #include
> +#include
>
> #include "ltdc.h"
>
> @@ -75,7 +76,7 @@ static int drv_load(struct drm_device *ddev)
>
> DRM_DEBUG("%s\n", __func__);
>
> - ldev = devm_kzalloc(ddev->dev, sizeof(*ldev), GFP_KERNEL);
> + ldev = drmm_kzalloc(ddev, sizeof(*ldev), GFP_KERNEL);
> if (!ldev)
> return -ENOMEM;
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 5576fdae4962..02a7c8375f44 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -36,6 +36,7 @@
> #include
> #include
> #include
> +#include
>
> #include
>
> @@ -1199,7 +1200,6 @@ static void ltdc_crtc_atomic_print_state(struct
> drm_printer *p,
> }
>
> static const struct drm_crtc_funcs ltdc_crtc_funcs = {
> - .destroy = drm_crtc_cleanup,
> .set_config = drm_atomic_helper_set_config,
> .page_flip = drm_atomic_helper_page_flip,
> .reset = drm_atomic_helper_crtc_reset,
> @@ -1212,7 +1212,6 @@ static const struct drm_crtc_funcs ltdc_crtc_funcs = {
> };
>
> static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = {
> - .destroy = drm_crtc_cleanup,
> .set_config = drm_atomic_helper_set_config,
> .page_flip = drm_atomic_helper_page_flip,
> .reset = drm_atomic_helper_crtc_reset,
> @@ -1545,7 +1544,6 @@ static void ltdc_plane_atomic_print_state(struct
> drm_printer *p,
> static const struct drm_plane_funcs ltdc_plane_funcs = {
> .update_plane = drm_atomic_helper_update_plane,
> .disable_plane = drm_atomic_helper_disable_plane,
> - .destroy = drm_plane_cleanup,
> .reset = drm_atomic_helper_plane_reset,
> .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> @@ -1572,7 +1570,6 @@ static struct drm_plane *ltdc_plane_create(struct
> drm_device *ddev,
> const u64 *modifiers = ltdc_format_modifiers;
> u32 lofs = index * LAY_OFS;
> u32 val;
> - int ret;
>
> /* Allocate the biggest size according to supported color formats */
> formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
> @@ -1613,14 +1610,10 @@ static struct drm_plane *ltdc_plane_create(struct
> drm_device *ddev,
> }
> }
>
> - plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
> - if (!plane)
> - return NULL;
> -
> - ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
> -<dc_plane_funcs, formats, nb_fmt,
> -modifiers, type, NULL);
> - if (ret < 0)
> + plane = drmm_universal_plane_alloc(ddev, struct drm_plane, dev,
> +possible_crtcs, <dc_plane_funcs,
> formats, nb_fmt,
> +modifiers, type, NULL);
Hi Katya,
Thanks for your submission, and sorry for the delay.
There is several alignment style problems, such as the lines above.
You can use "--strict" option with checkpatch script to show you all the faulty
alignment before sending a patch.
Other than that this patch looks pretty good to me.
Regards,
Raphaël
> + if (IS_ERR(plane))
> return NULL;
>
> if (ldev->caps.ycbcr_input) {
> @@ -1643,15 +1636,6 @@ static struct drm_plane *ltdc_plane_create(struct
> drm_device *ddev,
> return plane;
> }
>
> -static void ltdc_plane_destroy_all(struct drm_device *ddev)
> -{
> - struct drm_plane *plane, *plane_temp;
> -
>
Re: [PATCH v2 3/4] drm/stm: dsi: expose DSI PHY internal clock
On 12/8/23 17:58, Simon Horman wrote:
> On Mon, Dec 04, 2023 at 11:11:12AM +0100, Raphael Gallais-Pou wrote:
>
> ...
>
>> @@ -514,18 +675,40 @@ static int dw_mipi_dsi_stm_probe(struct
>> platform_device *pdev)
>> dsi->lane_max_kbps *= 2;
>> }
>>
>> -dw_mipi_dsi_stm_plat_data.base = dsi->base;
>> -dw_mipi_dsi_stm_plat_data.priv_data = dsi;
>> +dsi->pdata = *pdata;
>> +dsi->pdata.base = dsi->base;
>> +dsi->pdata.priv_data = dsi;
>> +
>> +dsi->pdata.max_data_lanes = 2;
>> +dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops;
>>
>> platform_set_drvdata(pdev, dsi);
>>
>> -dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
>> +dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata);
>> if (IS_ERR(dsi->dsi)) {
>> ret = PTR_ERR(dsi->dsi);
>> dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n");
>> goto err_dsi_probe;
>> }
>>
>> +/*
>> + * We need to wait for the generic bridge to probe before enabling and
>> + * register the internal pixel clock.
>> + */
>> +ret = clk_prepare_enable(dsi->pclk);
>> +if (ret) {
>> +DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
>> +goto err_dsi_probe;
>> +}
>> +
>> +ret = dw_mipi_dsi_clk_register(dsi, dev);
>> +if (ret) {
>> +DRM_ERROR("Failed to register DSI pixel clock: %d\n", ret);
> Hi Raphael,
Hi Simon,
You are right, dsi->clk needs to be disabled in case the clock register fails
before exiting the probe.
I've sent a v3, which normally fixes it.
Regards,
Raphaël
>
> Does clk_disable_unprepare(dsi->pclk) need to be added to this unwind
> chain?
>
> Flagged by Smatch.
>
>> +goto err_dsi_probe;
>> +}
>> +
>> +clk_disable_unprepare(dsi->pclk);
>> +
>> return 0;
>>
>> err_dsi_probe:
> ...
[PATCH v3 4/4] arm: dts: st: fix DSI peripheral clock on stm32mp15 boards
In RCC driver, 'DSI_K' is a kernel clock while 'DSI' has pclk4 as parent
clock, which means that it is an APB peripheral clock. Swap the clocks
in the DSI peripheral clock reference.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/st/stm32mp157.dtsi | 2 +-
arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 2 +-
arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 2 +-
arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 2 +-
arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/st/stm32mp157.dtsi
b/arch/arm/boot/dts/st/stm32mp157.dtsi
index 6197d878894d..97cd24227cef 100644
--- a/arch/arm/boot/dts/st/stm32mp157.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp157.dtsi
@@ -20,7 +20,7 @@ gpu: gpu@5900 {
dsi: dsi@5a00 {
compatible = "st,stm32-dsi";
reg = <0x5a00 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
phy-dsi-supply = <®18>;
resets = <&rcc DSI_R>;
diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
index afcd6285890c..8634699cc65e 100644
--- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
@@ -30,7 +30,7 @@ &cpu1 {
};
&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
index 39358d902000..3a897fa7e167 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
@@ -36,7 +36,7 @@ &cryp1 {
&dsi {
phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
index 07ea765a4553..29d6465b1fe6 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
@@ -35,7 +35,7 @@ &cryp1 {
};
&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
index 813086ec2489..5acb78f0a084 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
@@ -37,7 +37,7 @@ &cryp1 {
&dsi {
phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
--
2.25.1
[PATCH v3 1/4] drm/stm: dsi: use new SYSTEM_SLEEP_PM_OPS() macro
Use RUNTIME_PM_OPS() instead of the old SET_SYSTEM_SLEEP_PM_OPS().
This means we don't need __maybe_unused on the functions.
Signed-off-by: Raphael Gallais-Pou
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index d5f8c923d7bc..b1aee43d51e9 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -544,7 +544,7 @@ static void dw_mipi_dsi_stm_remove(struct platform_device
*pdev)
regulator_disable(dsi->vdd_supply);
}
-static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev)
+static int dw_mipi_dsi_stm_suspend(struct device *dev)
{
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
@@ -556,7 +556,7 @@ static int __maybe_unused dw_mipi_dsi_stm_suspend(struct
device *dev)
return 0;
}
-static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev)
+static int dw_mipi_dsi_stm_resume(struct device *dev)
{
struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data;
int ret;
@@ -580,8 +580,8 @@ static int __maybe_unused dw_mipi_dsi_stm_resume(struct
device *dev)
}
static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
- dw_mipi_dsi_stm_resume)
+ SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
+ dw_mipi_dsi_stm_resume)
};
static struct platform_driver dw_mipi_dsi_stm_driver = {
--
2.25.1
[PATCH v3 2/4] drm/stm: dsi: add pm runtime ops
From: Yannick Fertre
Update control of clocks and supply thanks to the PM runtime
mechanism to avoid kernel crash during a system suspend.
Signed-off-by: Yannick Fertre
Signed-off-by: Raphael Gallais-Pou
---
Changes in v2:
- Changed SET_RUNTIME_PM_OPS to RUNTIME_PM_OPS and removed
__maybe_unused
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index b1aee43d51e9..82fff9e84345 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
@@ -77,6 +78,7 @@ enum dsi_color {
struct dw_mipi_dsi_stm {
void __iomem *base;
struct clk *pllref_clk;
+ struct clk *pclk;
struct dw_mipi_dsi *dsi;
u32 hw_version;
int lane_min_kbps;
@@ -443,7 +445,6 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
*pdev)
{
struct device *dev = &pdev->dev;
struct dw_mipi_dsi_stm *dsi;
- struct clk *pclk;
int ret;
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
@@ -483,21 +484,21 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
*pdev)
goto err_clk_get;
}
- pclk = devm_clk_get(dev, "pclk");
- if (IS_ERR(pclk)) {
- ret = PTR_ERR(pclk);
+ dsi->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(dsi->pclk)) {
+ ret = PTR_ERR(dsi->pclk);
DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
goto err_dsi_probe;
}
- ret = clk_prepare_enable(pclk);
+ ret = clk_prepare_enable(dsi->pclk);
if (ret) {
DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
goto err_dsi_probe;
}
dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
- clk_disable_unprepare(pclk);
+ clk_disable_unprepare(dsi->pclk);
if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
ret = -ENODEV;
@@ -551,6 +552,7 @@ static int dw_mipi_dsi_stm_suspend(struct device *dev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(dsi->pllref_clk);
+ clk_disable_unprepare(dsi->pclk);
regulator_disable(dsi->vdd_supply);
return 0;
@@ -569,8 +571,16 @@ static int dw_mipi_dsi_stm_resume(struct device *dev)
return ret;
}
+ ret = clk_prepare_enable(dsi->pclk);
+ if (ret) {
+ regulator_disable(dsi->vdd_supply);
+ DRM_ERROR("Failed to enable pclk: %d\n", ret);
+ return ret;
+ }
+
ret = clk_prepare_enable(dsi->pllref_clk);
if (ret) {
+ clk_disable_unprepare(dsi->pclk);
regulator_disable(dsi->vdd_supply);
DRM_ERROR("Failed to enable pllref_clk: %d\n", ret);
return ret;
@@ -582,6 +592,8 @@ static int dw_mipi_dsi_stm_resume(struct device *dev)
static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = {
SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend,
dw_mipi_dsi_stm_resume)
+ RUNTIME_PM_OPS(dw_mipi_dsi_stm_suspend,
+ dw_mipi_dsi_stm_resume, NULL)
};
static struct platform_driver dw_mipi_dsi_stm_driver = {
--
2.25.1
[PATCH v3 3/4] drm/stm: dsi: expose DSI PHY internal clock
DSISRC __
__\_
|\
pll4_p_ck ->| 1 |dsi_k
ck_dsi_phy ->| 0 |
|/
A DSI clock is missing in the clock framework. Looking at the
clk_summary, it appears that 'ck_dsi_phy' is not implemented. Since the
DSI kernel clock is based on the internal DSI pll. The common clock
driver can not directly expose this 'ck_dsi_phy' clock because it does
not contain any common registers with the DSI. Thus it needs to be done
directly within the DSI phy driver.
Signed-off-by: Raphael Gallais-Pou
---
Changes in v3:
- Fix smatch warning:
.../dw_mipi_dsi-stm.c:719 dw_mipi_dsi_stm_probe() warn: 'dsi->pclk'
from clk_prepare_enable() not released on lines: 719.
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 247 ++
1 file changed, 216 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 82fff9e84345..b20123854c4a 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -7,7 +7,9 @@
*/
#include
+#include
#include
+#include
#include
#include
#include
@@ -77,9 +79,12 @@ enum dsi_color {
struct dw_mipi_dsi_stm {
void __iomem *base;
+ struct device *dev;
struct clk *pllref_clk;
struct clk *pclk;
+ struct clk_hw txbyte_clk;
struct dw_mipi_dsi *dsi;
+ struct dw_mipi_dsi_plat_data pdata;
u32 hw_version;
int lane_min_kbps;
int lane_max_kbps;
@@ -196,29 +201,198 @@ static int dsi_pll_get_params(struct dw_mipi_dsi_stm
*dsi,
return 0;
}
-static int dw_mipi_dsi_phy_init(void *priv_data)
+#define clk_to_dw_mipi_dsi_stm(clk) \
+ container_of(clk, struct dw_mipi_dsi_stm, txbyte_clk)
+
+static void dw_mipi_dsi_clk_disable(struct clk_hw *clk)
{
- struct dw_mipi_dsi_stm *dsi = priv_data;
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /* Disable the DSI PLL */
+ dsi_clear(dsi, DSI_WRPCR, WRPCR_PLLEN);
+
+ /* Disable the regulator */
+ dsi_clear(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
+}
+
+static int dw_mipi_dsi_clk_enable(struct clk_hw *clk)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(clk);
u32 val;
int ret;
+ DRM_DEBUG_DRIVER("\n");
+
/* Enable the regulator */
dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
- ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
-SLEEP_US, TIMEOUT_US);
+ ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val &
WISR_RRS,
+ SLEEP_US, TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
/* Enable the DSI PLL & wait for its lock */
dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
- ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
-SLEEP_US, TIMEOUT_US);
+ ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val &
WISR_PLLLS,
+ SLEEP_US, TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
return 0;
}
+static int dw_mipi_dsi_clk_is_enabled(struct clk_hw *hw)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
+
+ return dsi_read(dsi, DSI_WRPCR) & WRPCR_PLLEN;
+}
+
+static unsigned long dw_mipi_dsi_clk_recalc_rate(struct clk_hw *hw,
+unsigned long parent_rate)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
+ unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+ u32 val;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ pll_in_khz = (unsigned int)(parent_rate / 1000);
+
+ val = dsi_read(dsi, DSI_WRPCR);
+
+ idf = (val & WRPCR_IDF) >> 11;
+ if (!idf)
+ idf = 1;
+ ndiv = (val & WRPCR_NDIV) >> 2;
+ odf = int_pow(2, (val & WRPCR_ODF) >> 16);
+
+ /* Get the adjusted pll out value */
+ pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
+
+ return (unsigned long)pll_out_khz * 1000;
+}
+
+static long dw_mipi_dsi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct dw_mipi_dsi_stm *dsi = clk_to_dw_mipi_dsi_stm(hw);
+ unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+ int ret;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ pll_in_khz = (unsigned int)(*parent_rate / 1000);
+
+ /* Compute best pll parame
[PATCH v3 0/4] Update STM DSI PHY driver
This patch series aims to add several features of the dw-mipi-dsi phy driver that are missing or need to be updated. First patch update a PM macro. Second patch adds runtime PM functionality to the driver. Third patch adds a clock provider generated by the PHY itself. As explained in the commit log of the second patch, a clock declaration is missing. Since this clock is parent of 'dsi_k', it leads to an orphan clock. Most importantly this patch is an anticipation for future versions of the DSI PHY, and its inclusion within the display subsystem and the DRM framework. Last patch fixes a corner effect introduced previously. Since 'dsi' and 'dsi_k' are gated by the same bit on the same register, both reference work as peripheral clock in the device-tree. --- Changes in v3: - Fix smatch warning (disable dsi->pclk when clk_register fails) Changes in v2: - Added patch 1/4 to use SYSTEM_SLEEP_PM_OPS instead of old macro and removed __maybe_used for accordingly - Changed SET_RUNTIME_PM_OPS to RUNTIME_PM_OPS Raphael Gallais-Pou (3): drm/stm: dsi: use new SYSTEM_SLEEP_PM_OPS() macro drm/stm: dsi: expose DSI PHY internal clock arm: dts: st: fix DSI peripheral clock on stm32mp15 boards Yannick Fertre (1): drm/stm: dsi: add pm runtime ops arch/arm/boot/dts/st/stm32mp157.dtsi | 2 +- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 2 +- arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 2 +- arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 2 +- arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 2 +- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 279 +++--- 6 files changed, 243 insertions(+), 46 deletions(-) -- 2.25.1
Re: [PATCH RESEND v1 2/8] dt-bindings: display: add dt-bindings for STM32 LVDS device
On 12/21/23 21:36, Krzysztof Kozlowski wrote: > On 21/12/2023 13:43, Raphael Gallais-Pou wrote: >> Add dt-binding file for "st,stm32-lvds" compatible. >> >> Signed-off-by: Raphael Gallais-Pou >> --- > I don't know why this was resend, nothing explains it, but I already > commented on other version. > > Please respond to comments there. > > In the future, unless it is obvious resend over 2 weeks, say why you are > doing it and what changed. My proxy tends to block every patch after a batch of 4 or 5 patches. Since it splitted the serie in half I resent it so that the serie could be entirely read without problems. This explains the resend. I was not sure about putting a short explanation in the cover letter since it was not related any change in the serie, but next time I will do so. Best Regards, Raphaël > > Best regards, > Krzysztof >
Re: [PATCH v1 2/8] dt-bindings: display: add dt-bindings for STM32 LVDS device
Hi Krzysztof,
Thanks for your review. I wall send another serie later with those
modifications.
Best regards,
Raphaël
On 12/21/23 18:27, Krzysztof Kozlowski wrote:
> On 21/12/2023 13:28, Raphael Gallais-Pou wrote:
>> Add dt-binding file for "st,stm32-lvds" compatible.
>>
> A nit, subject: drop second/last, redundant "dt-bindings for". The
> "dt-bindings" prefix is already stating that these are bindings.
>
>> Signed-off-by: Raphael Gallais-Pou
>> ---
>> .../bindings/display/st,stm32-lvds.yaml | 114 ++
>> 1 file changed, 114 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
>>
> ...
>
>> +properties:
>> + "#clock-cells":
>> +const: 0
>> +
>> + compatible:
>> +const: st,stm32-lvds
> Please put compatible as first.
>
>> +
>> + reg:
>> +maxItems: 1
>> +
>> + clocks:
>> +items:
>> + - description: APB peripheral clock
>> + - description: Reference clock for the internal PLL
>> +
>> + clock-names:
>> +items:
>> + - const: pclk
>> + - const: ref
>> +
>> + resets:
>> +maxItems: 1
>> +
>> + ports:
>> +$ref: /schemas/graph.yaml#/properties/ports
>> +
>> +properties:
>> + port@0:
>> +$ref: /schemas/graph.yaml#/properties/port
>> +description: |
>> + LVDS input port node, connected to the LTDC RGB output port.
>> +
>> + port@1:
>> +$ref: /schemas/graph.yaml#/properties/port
>> +description: |
>> + LVDS output port node, connected to a panel or bridge input port.
> Ports are not required? I would assume it won't work without input and
> output.
>
>> +
>> +required:
>> + - "#clock-cells"
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - ports
>> +
>> +unevaluatedProperties: false
> additionalProperties instead... or did I miss some $ref anywhere?
>
>> +
>> +examples:
>> + - |
>> +#include
>> +#include
>> +#include
>> +
>> +lvds: lvds@4806 {
>> +#clock-cells = <0>;
>> +compatible = "st,stm32-lvds";
> compatible is always the first property.
>
>> +reg = <0x4806 0x2000>;
> put clock-cells here
>
>> +clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
>> +clock-names = "pclk", "ref";
>> +resets = <&rcc LVDS_R>;
> Best regards,
> Krzysztof
>
Re: [PATCH RESEND v1 2/8] dt-bindings: display: add dt-bindings for STM32 LVDS device
Hi Rob On 12/21/23 15:45, Rob Herring wrote: > On Thu, 21 Dec 2023 13:43:33 +0100, Raphael Gallais-Pou wrote: >> Add dt-binding file for "st,stm32-lvds" compatible. >> >> Signed-off-by: Raphael Gallais-Pou >> --- >> .../bindings/display/st,stm32-lvds.yaml | 114 ++ >> 1 file changed, 114 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/display/st,stm32-lvds.yaml >> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/display/st,stm32-lvds.example.dts:18:18: > fatal error: dt-bindings/bus/stm32mp25_sys_bus.h: No such file or directory >18 | #include > | ^ > compilation terminated. > make[2]: *** [scripts/Makefile.lib:419: > Documentation/devicetree/bindings/display/st,stm32-lvds.example.dtb] Error 1 > make[2]: *** Waiting for unfinished jobs > make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1424: > dt_binding_check] Error 2 > make: *** [Makefile:234: __sub-make] Error 2 This is because I forgot to remove this line from the example. I'll remove it in V2. Thanks, Raphaël > doc reference errors (make refcheckdocs): > > See > https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20231221124339.420119-3-raphael.gallais-...@foss.st.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. >
[PATCH RESEND v1 8/8] arm64: dts: st: add display support on stm32mp257f-ev
This patch enables the following IPs on stm32mp257f-ev :
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel backlight
* Ilitek touchescreen
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 0ea8e69bfb3d..ca2da988d91c 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -29,6 +29,43 @@ memory@8000 {
reg = <0x0 0x8000 0x1 0x0>;
};
+ panel_lvds: panel-lvds {
+ compatible = "edt,etml0700z9ndha", "panel-lvds";
+ enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_lvds_backlight>;
+ status = "okay";
+
+ width-mm = <156>;
+ height-mm = <92>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ clock-frequency = <5400>;
+ hactive = <1024>;
+ vactive = <600>;
+ hfront-porch = <150>;
+ hback-porch = <150>;
+ hsync-len = <21>;
+ vfront-porch = <24>;
+ vback-porch = <24>;
+ vsync-len = <21>;
+ };
+
+ port {
+ lvds_panel_in: endpoint {
+ remote-endpoint = <&lvds_out0>;
+ };
+ };
+ };
+
+ panel_lvds_backlight: panel-lvds-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -63,6 +100,15 @@ &i2c2 {
i2c-scl-falling-time-ns = <13>;
clock-frequency = <40>;
status = "okay";
+
+ ili2511: ili2511@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
};
&i2c8 {
@@ -75,6 +121,39 @@ &i2c8 {
status = "disabled";
};
+<dc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+ };
+ };
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
--
2.25.1
[PATCH RESEND v1 5/8] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 18 ++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 67064f47a4cb..1cf9f16e56cc 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1898,6 +1904,8 @@ void ltdc_suspend(struct drm_device *ddev)
clk_disable_unprepare(ldev->pixel_clk);
if (ldev->bus_clk)
clk_disable_unprepare(ldev->bus_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1918,6 +1926,12 @@ int ltdc_resume(struct drm_device *ddev)
return -ENODEV;
}
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1989,6 +2003,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 155d8e4a7c6b..662650a0fae2 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct clk *bus_clk;/* bus clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
--
2.25.1
[PATCH RESEND v1 6/8] arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation. It provides a parallel digital RGB flow to be used
by display interfaces.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi
b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 93bc8a8908ce..064077e98dfd 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -212,6 +212,18 @@ i2c8: i2c@4604 {
status = "disabled";
};
+ ltdc: display-controller@4801 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x4801 0x400>;
+ st,syscon = <&syscfg>;
+ interrupts = ,
+ ;
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>;
+ clock-names = "bus", "lcd";
+ resets = <&rcc LTDC_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@4822 {
compatible = "st,stm32mp25-sdmmc2",
"arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
--
2.25.1
[PATCH RESEND v1 7/8] arm64: dts: st: add lvds support on stm32mp253
This patch adds LVDS support on stm32mp253. The LVDS is used on
STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC
input clock.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp253.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi
b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index af48e82efe8a..bcc605e502de 100644
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -21,3 +21,20 @@ arm-pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};
};
+
+<dc {
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, <&lvds 0>;
+ clock-names = "bus", "lcd", "lvds";
+};
+
+&rifsc {
+ lvds: lvds@4806 {
+ #clock-cells = <0>;
+ compatible = "st,stm32-lvds";
+ reg = <0x4806 0x2000>;
+ clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc LVDS_R>;
+ status = "disabled";
+ };
+};
--
2.25.1
[PATCH RESEND v1 4/8] drm/stm: ltdc: implement bus clock
From: Yannick Fertre
The latest hardware version of the LTDC presents the addition of a bus
clock, which contains the global configuration registers and the interrupt
register.
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 8
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..67064f47a4cb 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -1896,6 +1896,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->bus_clk)
+ clk_disable_unprepare(ldev->bus_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1912,12 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->bus_clk) {
+ if (clk_prepare_enable(ldev->bus_clk)) {
+ DRM_ERROR("Unable to prepare bus clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..155d8e4a7c6b 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *bus_clk;/* bus clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH RESEND v1 3/8] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It regroups three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1226 ++ 3 files changed, 1239 insertions(+) create mode 100644 drivers/gpu/drm/stm/lvds.c diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..f01490939ab5 --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Rapha??l GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identification register */ + +/* Bitfield description */ +#define CR_LVDSEN BIT(0) /* LVDS PHY Enable */ +#define CR_HSPOL BIT(1) /* Horizontal Synchronization Polarity */ +#define CR_VSPOL BIT(2) /* Vertical Synchronization Polarity */ +#define CR_DEPOL BIT(3) /* Data Enable Polarity */ +#define CR_CI BIT(4) /* Control Internal (software controlled bit) */ +#define CR_LKMOD BIT(5) /* Link Mode, for both Links */ +#define CR_LKPHA BIT(6) /* Link
[PATCH RESEND v1 0/8] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Raphael Gallais-Pou (7): dt-bindings: panel: lvds: Append edt,etml0700z9ndha in panel-lvds dt-bindings: display: add dt-bindings for STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock arm64: dts: st: add ltdc support on stm32mp251 arm64: dts: st: add lvds support on stm32mp253 arm64: dts: st: add display support on stm32mp257f-ev Yannick Fertre (1): drm/stm: ltdc: implement bus clock .../bindings/display/panel/panel-lvds.yaml|2 + .../bindings/display/st,stm32-lvds.yaml | 114 ++ arch/arm64/boot/dts/st/stm32mp251.dtsi| 12 + arch/arm64/boot/dts/st/stm32mp253.dtsi| 17 + arch/arm64/boot/dts/st/stm32mp257f-ev1.dts| 79 ++ drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c| 26 + drivers/gpu/drm/stm/ltdc.h|2 + drivers/gpu/drm/stm/lvds.c| 1226 + 10 files changed, 1491 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml create mode 100644 drivers/gpu/drm/stm/lvds.c -- 2.25.1
[PATCH RESEND v1 2/8] dt-bindings: display: add dt-bindings for STM32 LVDS device
Add dt-binding file for "st,stm32-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
.../bindings/display/st,stm32-lvds.yaml | 114 ++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
diff --git a/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
new file mode 100644
index ..d72c9088133c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It regroups three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ "#clock-cells":
+const: 0
+
+ compatible:
+const: st,stm32-lvds
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+lvds: lvds@4806 {
+#clock-cells = <0>;
+compatible = "st,stm32-lvds";
+reg = <0x4806 0x2000>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH RESEND v1 1/8] dt-bindings: panel: lvds: Append edt, etml0700z9ndha in panel-lvds
List EDT ETML0700Z9NDHA in the LVDS panel enumeration. Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index 9f1016551e0b..3fb24393529c 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -42,6 +42,8 @@ properties: - auo,b101ew05 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel - chunghwa,claa070wp03xg + # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel + - edt,etml0700z9ndha # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel - hannstar,hsd101pww2 # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel -- 2.25.1
[PATCH v1 8/8] arm64: dts: st: add display support on stm32mp257f-ev
This patch enables the following IPs on stm32mp257f-ev :
* LTDC
* LVDS
* WSVGA LVDS panel (1024x600)
* Panel backlight
* Ilitek touchescreen
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 0ea8e69bfb3d..ca2da988d91c 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -29,6 +29,43 @@ memory@8000 {
reg = <0x0 0x8000 0x1 0x0>;
};
+ panel_lvds: panel-lvds {
+ compatible = "edt,etml0700z9ndha", "panel-lvds";
+ enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
+ backlight = <&panel_lvds_backlight>;
+ status = "okay";
+
+ width-mm = <156>;
+ height-mm = <92>;
+ data-mapping = "vesa-24";
+
+ panel-timing {
+ clock-frequency = <5400>;
+ hactive = <1024>;
+ vactive = <600>;
+ hfront-porch = <150>;
+ hback-porch = <150>;
+ hsync-len = <21>;
+ vfront-porch = <24>;
+ vback-porch = <24>;
+ vsync-len = <21>;
+ };
+
+ port {
+ lvds_panel_in: endpoint {
+ remote-endpoint = <&lvds_out0>;
+ };
+ };
+ };
+
+ panel_lvds_backlight: panel-lvds-backlight {
+ compatible = "gpio-backlight";
+ gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
+ default-on;
+ default-brightness-level = <0>;
+ status = "okay";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -63,6 +100,15 @@ &i2c2 {
i2c-scl-falling-time-ns = <13>;
clock-frequency = <40>;
status = "okay";
+
+ ili2511: ili2511@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ interrupt-parent = <&gpioi>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
};
&i2c8 {
@@ -75,6 +121,39 @@ &i2c8 {
status = "disabled";
};
+<dc {
+ status = "okay";
+
+ port {
+ ltdc_ep0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+};
+
+&lvds {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+ };
+ };
+ };
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
--
2.25.1
[PATCH v1 7/8] arm64: dts: st: add lvds support on stm32mp253
This patch adds LVDS support on stm32mp253. The LVDS is used on
STM32MP2 as a display interface. LVDS PLL clock is binded to the LTDC
input clock.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp253.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi
b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index af48e82efe8a..bcc605e502de 100644
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -21,3 +21,20 @@ arm-pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};
};
+
+<dc {
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>, <&lvds 0>;
+ clock-names = "bus", "lcd", "lvds";
+};
+
+&rifsc {
+ lvds: lvds@4806 {
+ #clock-cells = <0>;
+ compatible = "st,stm32-lvds";
+ reg = <0x4806 0x2000>;
+ clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc LVDS_R>;
+ status = "disabled";
+ };
+};
--
2.25.1
[PATCH v1 6/8] arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation. It provides a parallel digital RGB flow to be used
by display interfaces.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi
b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 93bc8a8908ce..064077e98dfd 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -212,6 +212,18 @@ i2c8: i2c@4604 {
status = "disabled";
};
+ ltdc: display-controller@4801 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x4801 0x400>;
+ st,syscon = <&syscfg>;
+ interrupts = ,
+ ;
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>;
+ clock-names = "bus", "lcd";
+ resets = <&rcc LTDC_R>;
+ status = "disabled";
+ };
+
sdmmc1: mmc@4822 {
compatible = "st,stm32mp25-sdmmc2",
"arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00353180>;
--
2.25.1
[PATCH v1 5/8] drm/stm: ltdc: add lvds pixel clock
The STM32MP25x display subsystem presents a mux which feeds the loopback
pixel clock of the current bridge in use into the LTDC. This mux is only
accessible through sysconfig registers which is not yet available in the
STM32MP25x common clock framework.
While waiting for a complete update of the clock framework, this would
allow to use the LVDS.
Signed-off-by: Raphael Gallais-Pou
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 18 ++
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 67064f47a4cb..1cf9f16e56cc 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -838,6 +838,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc,
int target_max = target + CLK_TOLERANCE_HZ;
int result;
+ if (ldev->lvds_clk) {
+ result = clk_round_rate(ldev->lvds_clk, target);
+ DRM_DEBUG_DRIVER("lvds pixclk rate target %d, available %d\n",
+target, result);
+ }
+
result = clk_round_rate(ldev->pixel_clk, target);
DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
@@ -1898,6 +1904,8 @@ void ltdc_suspend(struct drm_device *ddev)
clk_disable_unprepare(ldev->pixel_clk);
if (ldev->bus_clk)
clk_disable_unprepare(ldev->bus_clk);
+ if (ldev->lvds_clk)
+ clk_disable_unprepare(ldev->lvds_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1918,6 +1926,12 @@ int ltdc_resume(struct drm_device *ddev)
return -ENODEV;
}
}
+ if (ldev->lvds_clk) {
+ if (clk_prepare_enable(ldev->lvds_clk)) {
+ DRM_ERROR("Unable to prepare lvds clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
@@ -1989,6 +2003,10 @@ int ltdc_load(struct drm_device *ddev)
}
}
+ ldev->lvds_clk = devm_clk_get(dev, "lvds");
+ if (IS_ERR(ldev->lvds_clk))
+ ldev->lvds_clk = NULL;
+
rstc = devm_reset_control_get_exclusive(dev, NULL);
mutex_init(&ldev->err_lock);
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 155d8e4a7c6b..662650a0fae2 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *lvds_clk; /* lvds pixel clock */
struct clk *bus_clk;/* bus clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
--
2.25.1
[PATCH v1 3/8] drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver
The Low-Voltage Differential Signaling (LVDS) Display Interface Transmitter handles the LVDS protocol: it maps the pixels received from the upstream Pixel-DMA LCD-TFT Display Controller (LTDC) onto the LVDS PHY. It regroups three sub blocks: * LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input pixels onto the data lanes of the PHY * LVDS PHY: parallelize the data and drives the LVDS data lanes * LVDS wrapper: handles top-level settings The LVDS controller driver supports the following high-level features: * FDP-Link-I and OpenLDI (v0.95) protocols * Single-Link or Dual-Link operation * Single-Display or Double-Display (with the same content duplicated on both) * Flexible Bit-Mapping, including JEIDA and VESA * RGB888 or RGB666 output * Synchronous design, with one input pixel per clock cycle Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/lvds.c | 1226 ++ 3 files changed, 1239 insertions(+) create mode 100644 drivers/gpu/drm/stm/lvds.c diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig index fa49cde43bb2..9627814d027c 100644 --- a/drivers/gpu/drm/stm/Kconfig +++ b/drivers/gpu/drm/stm/Kconfig @@ -20,3 +20,14 @@ config DRM_STM_DSI select DRM_DW_MIPI_DSI help Choose this option for MIPI DSI support on STMicroelectronics SoC. + +config DRM_STM_LVDS + tristate "STMicroelectronics LVDS Display Interface Transmitter DRM driver" + depends on DRM_STM + help + Enable support for LVDS encoders on STMicroelectronics SoC. + The STM LVDS is a bridge which serialize pixel stream onto + a LVDS protocol. + + To compile this driver as a module, choose M here: the module will be + called lvds. diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile index 4df5caf01f35..ad740d6175a6 100644 --- a/drivers/gpu/drm/stm/Makefile +++ b/drivers/gpu/drm/stm/Makefile @@ -5,4 +5,6 @@ stm-drm-y := \ obj-$(CONFIG_DRM_STM_DSI) += dw_mipi_dsi-stm.o +obj-$(CONFIG_DRM_STM_LVDS) += lvds.o + obj-$(CONFIG_DRM_STM) += stm-drm.o diff --git a/drivers/gpu/drm/stm/lvds.c b/drivers/gpu/drm/stm/lvds.c new file mode 100644 index ..f01490939ab5 --- /dev/null +++ b/drivers/gpu/drm/stm/lvds.c @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Rapha??l GALLAIS-POU for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* LVDS Host registers */ +#define LVDS_CR0x /* configuration register */ +#define LVDS_DMLCR00x0004 /* data mapping lsb configuration register 0 */ +#define LVDS_DMMCR00x0008 /* data mapping msb configuration register 0 */ +#define LVDS_DMLCR10x000C /* data mapping lsb configuration register 1 */ +#define LVDS_DMMCR10x0010 /* data mapping msb configuration register 1 */ +#define LVDS_DMLCR20x0014 /* data mapping lsb configuration register 2 */ +#define LVDS_DMMCR20x0018 /* data mapping msb configuration register 2 */ +#define LVDS_DMLCR30x001C /* data mapping lsb configuration register 3 */ +#define LVDS_DMMCR30x0020 /* data mapping msb configuration register 3 */ +#define LVDS_DMLCR40x0024 /* data mapping lsb configuration register 4 */ +#define LVDS_DMMCR40x0028 /* data mapping msb configuration register 4 */ +#define LVDS_CDL1CR0x002C /* channel distrib link 1 configuration register */ +#define LVDS_CDL2CR0x0030 /* channel distrib link 2 configuration register */ + +#define CDL1CR_DEFAULT 0x04321 /* Default value for CDL1CR */ +#define CDL2CR_DEFAULT 0x59876 /* Default value for CDL2CR */ + +#define LVDS_DMLCR(bit)(LVDS_DMLCR0 + 0x8 * (bit)) +#define LVDS_DMMCR(bit)(LVDS_DMMCR0 + 0x8 * (bit)) + +/* LVDS Wrapper registers */ +#define LVDS_WCLKCR0x11B0 /* Wrapper clock control register */ + +#define LVDS_HWCFGR0x1FF0 /* HW configuration register*/ +#define LVDS_VERR 0x1FF4 /* Version register */ +#define LVDS_IPIDR 0x1FF8 /* Identification register */ +#define LVDS_SIDR 0x1FFC /* Size Identification register */ + +/* Bitfield description */ +#define CR_LVDSEN BIT(0) /* LVDS PHY Enable */ +#define CR_HSPOL BIT(1) /* Horizontal Synchronization Polarity */ +#define CR_VSPOL BIT(2) /* Vertical Synchronization Polarity */ +#define CR_DEPOL BIT(3) /* Data Enable Polarity */ +#define CR_CI BIT(4) /* Control Internal (software controlled bit) */ +#define CR_LKMOD BIT(5) /* Link Mode, for both Links */ +#define CR_LKPHA BIT(6) /* Link
[PATCH v1 2/8] dt-bindings: display: add dt-bindings for STM32 LVDS device
Add dt-binding file for "st,stm32-lvds" compatible.
Signed-off-by: Raphael Gallais-Pou
---
.../bindings/display/st,stm32-lvds.yaml | 114 ++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
diff --git a/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
new file mode 100644
index ..d72c9088133c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32-lvds.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/st,stm32-lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 LVDS Display Interface Transmitter
+
+maintainers:
+ - Raphael Gallais-Pou
+ - Yannick Fertre
+
+description: |
+ The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
+ LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
+ onto the LVDS PHY.
+
+ It regroups three sub blocks:
+- LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
+ pixels onto the data lanes of the PHY
+- LVDS PHY: parallelize the data and drives the LVDS data lanes
+- LVDS wrapper: handles top-level settings
+
+ The LVDS controller driver supports the following high-level features:
+- FDP-Link-I and OpenLDI (v0.95) protocols
+- Single-Link or Dual-Link operation
+- Single-Display or Double-Display (with the same content duplicated on
both)
+- Flexible Bit-Mapping, including JEIDA and VESA
+- RGB888 or RGB666 output
+- Synchronous design, with one input pixel per clock cycle
+
+properties:
+ "#clock-cells":
+const: 0
+
+ compatible:
+const: st,stm32-lvds
+
+ reg:
+maxItems: 1
+
+ clocks:
+items:
+ - description: APB peripheral clock
+ - description: Reference clock for the internal PLL
+
+ clock-names:
+items:
+ - const: pclk
+ - const: ref
+
+ resets:
+maxItems: 1
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+ LVDS input port node, connected to the LTDC RGB output port.
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description: |
+ LVDS output port node, connected to a panel or bridge input port.
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+lvds: lvds@4806 {
+#clock-cells = <0>;
+compatible = "st,stm32-lvds";
+reg = <0x4806 0x2000>;
+clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>;
+clock-names = "pclk", "ref";
+resets = <&rcc LVDS_R>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+lvds_in: endpoint {
+ remote-endpoint = <<dc_ep1_out>;
+};
+};
+
+port@1 {
+reg = <1>;
+lvds_out0: endpoint {
+ remote-endpoint = <&lvds_panel_in>;
+};
+};
+};
+};
+
+...
--
2.25.1
[PATCH v1 4/8] drm/stm: ltdc: implement bus clock
From: Yannick Fertre
The latest hardware version of the LTDC presents the addition of a bus
clock, which contains the global configuration registers and the interrupt
register.
Signed-off-by: Yannick Fertre
---
drivers/gpu/drm/stm/ltdc.c | 8
drivers/gpu/drm/stm/ltdc.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 5576fdae4962..67064f47a4cb 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -1896,6 +1896,8 @@ void ltdc_suspend(struct drm_device *ddev)
DRM_DEBUG_DRIVER("\n");
clk_disable_unprepare(ldev->pixel_clk);
+ if (ldev->bus_clk)
+ clk_disable_unprepare(ldev->bus_clk);
}
int ltdc_resume(struct drm_device *ddev)
@@ -1910,6 +1912,12 @@ int ltdc_resume(struct drm_device *ddev)
DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
return ret;
}
+ if (ldev->bus_clk) {
+ if (clk_prepare_enable(ldev->bus_clk)) {
+ DRM_ERROR("Unable to prepare bus clock\n");
+ return -ENODEV;
+ }
+ }
return 0;
}
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
index 9d488043ffdb..155d8e4a7c6b 100644
--- a/drivers/gpu/drm/stm/ltdc.h
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -44,6 +44,7 @@ struct ltdc_device {
void __iomem *regs;
struct regmap *regmap;
struct clk *pixel_clk; /* lcd pixel clock */
+ struct clk *bus_clk;/* bus clock */
struct mutex err_lock; /* protecting error_status */
struct ltdc_caps caps;
u32 irq_status;
--
2.25.1
[PATCH v1 1/8] dt-bindings: panel: lvds: Append edt, etml0700z9ndha in panel-lvds
List EDT ETML0700Z9NDHA in the LVDS panel enumeration. Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/panel/panel-lvds.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index 9f1016551e0b..3fb24393529c 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -42,6 +42,8 @@ properties: - auo,b101ew05 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel - chunghwa,claa070wp03xg + # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel + - edt,etml0700z9ndha # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel - hannstar,hsd101pww2 # Hydis Technologies 7" WXGA (800x1280) TFT LCD LVDS panel -- 2.25.1
[PATCH v1 0/8] Introduce STM32 LVDS driver
This serie introduces a new DRM bridge driver for STM32MP257 platforms based on Arm Cortex-35. It also adds an instance in the device-tree and handle the inclusion of the driver within the DRM framework. First patch adds a new panel compatible in the panel-lvds driver, which is used by default on the STM32MP257. Raphael Gallais-Pou (7): dt-bindings: panel: lvds: Append edt,etml0700z9ndha in panel-lvds dt-bindings: display: add dt-bindings for STM32 LVDS device drm/stm: lvds: add new STM32 LVDS Display Interface Transmitter driver drm/stm: ltdc: add lvds pixel clock arm64: dts: st: add ltdc support on stm32mp251 arm64: dts: st: add lvds support on stm32mp253 arm64: dts: st: add display support on stm32mp257f-ev Yannick Fertre (1): drm/stm: ltdc: implement bus clock .../bindings/display/panel/panel-lvds.yaml|2 + .../bindings/display/st,stm32-lvds.yaml | 114 ++ arch/arm64/boot/dts/st/stm32mp251.dtsi| 12 + arch/arm64/boot/dts/st/stm32mp253.dtsi| 17 + arch/arm64/boot/dts/st/stm32mp257f-ev1.dts| 79 ++ drivers/gpu/drm/stm/Kconfig | 11 + drivers/gpu/drm/stm/Makefile |2 + drivers/gpu/drm/stm/ltdc.c| 26 + drivers/gpu/drm/stm/ltdc.h|2 + drivers/gpu/drm/stm/lvds.c| 1226 + 10 files changed, 1491 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/st,stm32-lvds.yaml create mode 100644 drivers/gpu/drm/stm/lvds.c -- 2.25.1
[PATCH v2 4/4] arm: dts: st: fix DSI peripheral clock on stm32mp15 boards
In RCC driver, 'DSI_K' is a kernel clock while 'DSI' has pclk4 as parent
clock, which means that it is an APB peripheral clock. Swap the clocks
in the DSI peripheral clock reference.
Signed-off-by: Raphael Gallais-Pou
---
arch/arm/boot/dts/st/stm32mp157.dtsi | 2 +-
arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 2 +-
arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 2 +-
arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 2 +-
arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/st/stm32mp157.dtsi
b/arch/arm/boot/dts/st/stm32mp157.dtsi
index 6197d878894d..97cd24227cef 100644
--- a/arch/arm/boot/dts/st/stm32mp157.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp157.dtsi
@@ -20,7 +20,7 @@ gpu: gpu@5900 {
dsi: dsi@5a00 {
compatible = "st,stm32-dsi";
reg = <0x5a00 0x800>;
- clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
phy-dsi-supply = <®18>;
resets = <&rcc DSI_R>;
diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
index afcd6285890c..8634699cc65e 100644
--- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
@@ -30,7 +30,7 @@ &cpu1 {
};
&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
index 39358d902000..3a897fa7e167 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
@@ -36,7 +36,7 @@ &cryp1 {
&dsi {
phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
index 07ea765a4553..29d6465b1fe6 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
@@ -35,7 +35,7 @@ &cryp1 {
};
&dsi {
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
index 813086ec2489..5acb78f0a084 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
@@ -37,7 +37,7 @@ &cryp1 {
&dsi {
phy-dsi-supply = <&scmi_reg18>;
- clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
+ clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
--
2.25.1
