RE: [PATCH v2 6/6] drm/bridge: cdns-mhdp8546: Fix the interrupt enable/disable
Hi Nikhil,
> -Original Message-
> From: Nikhil Devshatwar
> Sent: Monday, November 9, 2020 10:36 PM
> To: dri-devel@lists.freedesktop.org; Tomi Valkeinen
>
> Cc: Sekhar Nori ; Laurent Pinchart
> ; Swapnil Kashinath Jakhade
> ; Yuti Suresh Amonkar
> Subject: [PATCH v2 6/6] drm/bridge: cdns-mhdp8546: Fix the interrupt
> enable/disable
>
> EXTERNAL MAIL
>
>
> When removing the tidss driver, there is a warning reported by kernel about
> an unhandled interrupt for mhdp driver.
>
> [ 43.238895] irq 31: nobody cared (try booting with the "irqpoll" option)
> ... [snipped backtrace]
> [ 43.330735] handlers:
> [ 43.333020] [<5367c4f9>] irq_default_primary_handler threaded
> [<7e02b601>]
> cdns_mhdp_irq_handler [cdns_mhdp8546]
> [ 43.344607] Disabling IRQ #31
>
> This happens because as part of cdns_mhdp_bridge_hpd_disable, driver
> tries to disable the interrupts. While disabling the SW_EVENT interrupts, it
> accidentally enables the MBOX interrupts, which are not handled by the
> driver.
>
> Fix this with a read-modify-write to update only required bits.
> Do the same for enabling interrupts as well.
>
> Signed-off-by: Nikhil Devshatwar
> ---
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> index 2cd809eed827..6beccd2a408e 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> @@ -2146,7 +2146,8 @@ static void cdns_mhdp_bridge_hpd_enable(struct
> drm_bridge *bridge)
>
> /* Enable SW event interrupts */
> if (mhdp->bridge_attached)
> - writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(readl(mhdp->regs + CDNS_APB_INT_MASK) &
> +~CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK); }
>
> @@ -2154,7 +2155,9 @@ static void cdns_mhdp_bridge_hpd_disable(struct
> drm_bridge *bridge) {
> struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
>
> - writel(CDNS_APB_INT_MASK_SW_EVENT_INT, mhdp->regs +
> CDNS_APB_INT_MASK);
> + writel(readl(mhdp->regs + CDNS_APB_INT_MASK) |
> +CDNS_APB_INT_MASK_SW_EVENT_INT,
> +mhdp->regs + CDNS_APB_INT_MASK);
> }
>
Can we do similar change at other places in driver too?
Other than that:
Reviewed-by: Swapnil Jakhade
Thanks & regards,
Swapnil
> static const struct drm_bridge_funcs cdns_mhdp_bridge_funcs = {
> --
> 2.17.1
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RE: [PATCH v2 6/6] drm/bridge: cdns-mhdp8546: Fix the interrupt enable/disable
> -Original Message-
> From: Nikhil Devshatwar
> Sent: Tuesday, November 10, 2020 7:23 PM
> To: Tomi Valkeinen ; Swapnil Kashinath Jakhade
> ; Yuti Suresh Amonkar
> Cc: dri-devel@lists.freedesktop.org; Swapnil Kashinath Jakhade
> ; Sekhar Nori ; Laurent Pinchart
> ; Yuti Suresh Amonkar
>
> Subject: Re: [PATCH v2 6/6] drm/bridge: cdns-mhdp8546: Fix the interrupt
> enable/disable
>
> EXTERNAL MAIL
>
>
> On 14:27-20201110, Tomi Valkeinen wrote:
> > On 10/11/2020 12:27, Nikhil Devshatwar wrote:
> > > On 11:21-20201110, Tomi Valkeinen wrote:
> > >> On 09/11/2020 19:06, Nikhil Devshatwar wrote:
> > >>> When removing the tidss driver, there is a warning reported by
> > >>> kernel about an unhandled interrupt for mhdp driver.
> > >>>
> > >>> [ 43.238895] irq 31: nobody cared (try booting with the "irqpoll"
> option)
> > >>> ... [snipped backtrace]
> > >>> [ 43.330735] handlers:
> > >>> [ 43.333020] [<5367c4f9>] irq_default_primary_handler
> threaded [<7e02b601>]
> > >>> cdns_mhdp_irq_handler [cdns_mhdp8546]
> > >>> [ 43.344607] Disabling IRQ #31
> > >>>
> > >>> This happens because as part of cdns_mhdp_bridge_hpd_disable,
> > >>> driver tries to disable the interrupts. While disabling the
> > >>> SW_EVENT interrupts, it accidentally enables the MBOX interrupts,
> > >>> which are not handled by the driver.
> > >>>
> > >>> Fix this with a read-modify-write to update only required bits.
> > >>> Do the same for enabling interrupts as well.
> > >>>
> > >>> Signed-off-by: Nikhil Devshatwar
> > >>> ---
> > >>> drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 7 +--
> > >>> 1 file changed, 5 insertions(+), 2 deletions(-)
> > >>>
> > >>> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > >>> b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > >>> index 2cd809eed827..6beccd2a408e 100644
> > >>> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > >>> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > >>> @@ -2146,7 +2146,8 @@ static void
> > >>> cdns_mhdp_bridge_hpd_enable(struct drm_bridge *bridge)
> > >>>
> > >>> /* Enable SW event interrupts */
> > >>> if (mhdp->bridge_attached)
> > >>> - writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> > >>> + writel(readl(mhdp->regs + CDNS_APB_INT_MASK) &
> > >>> + ~CDNS_APB_INT_MASK_SW_EVENT_INT,
> > >>>mhdp->regs + CDNS_APB_INT_MASK); }
> > >>>
> > >>> @@ -2154,7 +2155,9 @@ static void
> > >>> cdns_mhdp_bridge_hpd_disable(struct drm_bridge *bridge) {
> > >>> struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
> > >>>
> > >>> - writel(CDNS_APB_INT_MASK_SW_EVENT_INT, mhdp->regs +
> CDNS_APB_INT_MASK);
> > >>> + writel(readl(mhdp->regs + CDNS_APB_INT_MASK) |
> > >>> + CDNS_APB_INT_MASK_SW_EVENT_INT,
> > >>> + mhdp->regs + CDNS_APB_INT_MASK);
> > >>> }
> > >>>
> > >>> static const struct drm_bridge_funcs cdns_mhdp_bridge_funcs = {
> > >>
> > >> Good catch. I wonder why we need the above functions... We already
> > >> enable and disable the interrupts when attaching/detaching the
> > >> driver. And I think we want to get the interrupt even if we won't report
> HPD (but I think we always do report it), as we need the interrupts to track
> the link status.
> > >>
> > >
> > > I read from the code that there is TODO for handling the mailbox
> > > interrupts in the driver. Once that is supported, you will be able
> > > to explictily enable/disable interrupts for SW_EVENTS (like hotplug)
> > > as well as mailbox events. This enabling specific bits in the
> > > interrupt status.
> >
> > But SW_EVENTS is not the same as HPD, at least in theory. If we
> > disable SW_EVENT_INT in hpd_disable(), we lose all SW_EVENT interrupts.
>
> I am not sure, what exactly is covered in the SW events apart from the
> hotplug.
>
> Swapnil, Yuti, Please fill in..
hpd_enable/hpd_disable callbacks were implemented as a part of supporting
DRM_BRIDGE_OP_HPD bridge operation. The existing implementation could
work with current features set supported by MHDP driver. But Tomi's point is
valid, as there are some HDCP interrupts which are part of SW_EVENT interrupts
and this might not be the control to just enable/disable HPD.
Swapnil
>
> Nikhil D
> >
> > Tomi
> >
> > --
> > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> > Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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RE: [PATCH 5/5] drm/bridge: mhdp8564: Support format negotiation
Hi,
> -Original Message-
> From: Nikhil Devshatwar
> Sent: Friday, October 16, 2020 4:09 PM
> To: dri-devel@lists.freedesktop.org; Tomi Valkeinen
>
> Cc: Sekhar Nori ; Laurent Pinchart
> ; Swapnil Kashinath Jakhade
>
> Subject: [PATCH 5/5] drm/bridge: mhdp8564: Support format negotiation
>
s/mhdp8564/mhdp8546
> EXTERNAL MAIL
>
>
> With new connector model, mhdp bridge will not create the connector and
> SoC driver will rely on format negotiation to setup the encoder format.
>
> Support format negotiations hooks in the drm_bridge_funcs.
> Support a single format for input.
>
> Signed-off-by: Nikhil Devshatwar
> ---
> .../drm/bridge/cadence/cdns-mhdp8546-core.c | 29 +++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> index d0c65610ebb5..230f6e28f82f 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> @@ -2078,6 +2078,34 @@ cdns_mhdp_bridge_atomic_reset(struct
> drm_bridge *bridge)
> return _mhdp_state->base;
> }
>
> +static u32 *cdns_mhdp_get_input_bus_fmts(struct drm_bridge *bridge,
> + struct drm_bridge_state *bridge_state,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state,
> + u32 output_fmt,
> + unsigned int *num_input_fmts) {
> + u32 *input_fmts;
> + u32 default_bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
> +
> + *num_input_fmts = 0;
> +
> + /*
> + * This bridge does not support media_bus_format conversion
> + * Propagate only if supported
> + */
> + if (output_fmt != default_bus_format && output_fmt !=
> MEDIA_BUS_FMT_FIXED)
> + return NULL;
> +
> + input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL);
> + if (!input_fmts)
> + return NULL;
> +
> + *num_input_fmts = 1;
> + input_fmts[0] = default_bus_format;
> + return input_fmts;
> +}
> +
> static int cdns_mhdp_atomic_check(struct drm_bridge *bridge,
> struct drm_bridge_state *bridge_state,
> struct drm_crtc_state *crtc_state, @@ -
> 2142,6 +2170,7 @@ static const struct drm_bridge_funcs
> cdns_mhdp_bridge_funcs = {
> .atomic_duplicate_state =
> cdns_mhdp_bridge_atomic_duplicate_state,
> .atomic_destroy_state = cdns_mhdp_bridge_atomic_destroy_state,
> .atomic_reset = cdns_mhdp_bridge_atomic_reset,
> + .atomic_get_input_bus_fmts = cdns_mhdp_get_input_bus_fmts,
> .detect = cdns_mhdp_bridge_detect,
> .get_edid = cdns_mhdp_bridge_get_edid,
> .hpd_enable = cdns_mhdp_bridge_hpd_enable,
> --
> 2.17.1
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RE: [PATCH] drm: bridge: cdns-mhdp8546: fix compile warning
Hi Tomi,
Thank you for the patch.
> -Original Message-
> From: Tomi Valkeinen
> Sent: Wednesday, September 23, 2020 2:01 PM
> To: dri-devel@lists.freedesktop.org; Swapnil Kashinath Jakhade
> ; Yuti Suresh Amonkar
> Cc: Stephen Rothwell ; Dave Airlie
> ; Laurent Pinchart ;
> Tomi Valkeinen
> Subject: [PATCH] drm: bridge: cdns-mhdp8546: fix compile warning
>
> EXTERNAL MAIL
>
>
> On x64 we get:
>
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:751:10: warning:
> conversion from 'long unsigned int' to 'unsigned int' changes value from
> '18446744073709551613' to '4294967293' [-Woverflow]
>
> The registers are 32 bit, so fix by casting to u32.
>
> Fixes: fb43aa0acdfd ("drm: bridge: Add support for Cadence MHDP8546
> DPI/DP bridge")
> Signed-off-by: Tomi Valkeinen
> ---
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> index 621ebdbff8a3..d0c65610ebb5 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> @@ -748,7 +748,7 @@ static int cdns_mhdp_fw_activate(const struct
> firmware *fw,
>* bridge should already be detached.
>*/
> if (mhdp->bridge_attached)
> - writel(~CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK);
>
> spin_unlock(>start_lock);
> @@ -1689,7 +1689,7 @@ static int cdns_mhdp_attach(struct drm_bridge
> *bridge,
>
> /* Enable SW event interrupts */
> if (hw_ready)
> - writel(~CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK);
>
> return 0;
> @@ -2122,7 +2122,7 @@ static void cdns_mhdp_bridge_hpd_enable(struct
> drm_bridge *bridge)
>
> /* Enable SW event interrupts */
> if (mhdp->bridge_attached)
> - writel(~CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK); }
>
Reviewed-by: Swapnil Jakhade
Thanks,
Swapnil
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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RE: [PATCH v10 1/3] dt-bindings: drm/bridge: Document Cadence MHDP8546 bridge bindings
Hi Tomi, > -Original Message- > From: Tomi Valkeinen > Sent: Wednesday, September 16, 2020 5:48 PM > To: Swapnil Kashinath Jakhade ; airl...@linux.ie; > dan...@ffwll.ch; laurent.pinch...@ideasonboard.com; robh...@kernel.org; > a.ha...@samsung.com; narmstr...@baylibre.com; jo...@kwiboo.se; > jernej.skra...@siol.net; dri-devel@lists.freedesktop.org; > devicet...@vger.kernel.org; linux-ker...@vger.kernel.org > Cc: Milind Parab ; Yuti Suresh Amonkar > ; jsa...@ti.com; nsek...@ti.com; > prane...@ti.com; nikhil...@ti.com > Subject: Re: [PATCH v10 1/3] dt-bindings: drm/bridge: Document Cadence > MHDP8546 bridge bindings > > EXTERNAL MAIL > > > Hi Swapnil, Yuti, > > On 14/09/2020 15:48, Swapnil Jakhade wrote: > > From: Yuti Amonkar > > > > Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in > > yaml format. > > > > Signed-off-by: Yuti Amonkar > > Signed-off-by: Swapnil Jakhade > > Reviewed-by: Rob Herring > > Reviewed-by: Laurent Pinchart > > --- > > .../display/bridge/cdns,mhdp8546.yaml | 154 ++ > > 1 file changed, 154 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml > I was testing this on J7 EVM, and looking at the dts files and DT bindings. To > get rid of the warnings from dtbs_check, I made the following changes. > > I think the interrupt one is clear. The driver needs the interrupt, but it was > not defined in the yaml file. > > For phy-names, we had that in the out-of-tree dts file, so I added it here. > The > driver just looks for the PHY via index, but I guess we should require it. > > The power-domain is not needed by the driver, but if I'm not mistaken, has > to be defined here. > > > diff --git > a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml > b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml > index a21a4bfe15cf..c5f5781c1ed6 100644 > --- > a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml > +++ > b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yam > +++ l > @@ -46,6 +46,16 @@ properties: > description: >phandle to the DisplayPort PHY. > > + phy-names: > +items: > + - const: dpphy > + > + power-domains: > +maxItems: 1 > + > + interrupts: > +maxItems: 1 > + >ports: > type: object > description: > @@ -114,6 +124,8 @@ required: >- reg >- reg-names >- phys > + - phy-names > + - interrupts >- ports > Okay. We will update the bindings as per above suggestions. Thanks for your inputs. Thanks & regards, Swapnil > additionalProperties: false > > Tomi > > -- > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. > Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
RE: [PATCH v8 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
Hi Guido,
> -Original Message-
> From: Guido Günther
> Sent: Wednesday, August 12, 2020 7:27 PM
> To: Tomi Valkeinen
> Cc: Swapnil Kashinath Jakhade ; airl...@linux.ie;
> dan...@ffwll.ch; laurent.pinch...@ideasonboard.com; robh...@kernel.org;
> a.ha...@samsung.com; narmstr...@baylibre.com; jo...@kwiboo.se;
> jernej.skra...@siol.net; dri-devel@lists.freedesktop.org;
> devicet...@vger.kernel.org; linux-ker...@vger.kernel.org; Milind Parab
> ; Yuti Suresh Amonkar ;
> prane...@ti.com; nsek...@ti.com; jsa...@ti.com; sandor...@nxp.com
> Subject: Re: [PATCH v8 0/3] drm: Add support for Cadence MHDP DPI/DP
> bridge and J721E wrapper.
>
> EXTERNAL MAIL
>
>
> Hi,
> On Wed, Aug 12, 2020 at 01:47:42PM +0300, Tomi Valkeinen wrote:
> > Hi Guido,
> >
> > On 12/08/2020 11:39, Guido Günther wrote:
> > > Hi,
> > > On Thu, Aug 06, 2020 at 01:34:29PM +0200, Swapnil Jakhade wrote:
> > >> This patch series adds new DRM bridge driver for Cadence MHDP
> > >> DPI/DP bridge. The Cadence Display Port IP is also referred as MHDP
> > >> (Mobile High Definition Link, High-Definition Multimedia Interface,
> Display Port).
> > >> Cadence Display Port complies with VESA DisplayPort (DP) and
> > >> embedded Display Port (eDP) standards.
> > >
> > > Is there any relation to the cadence mhdp ip core used inthe imx8mq:
> > >
> > >
> > > https://urldefense.com/v3/__https://lore.kernel.org/dri-devel/cover.
> > >
> 1590982881.git.sandor...@nxp.com/__;!!EHscmS1ygiU1lA!QIVUQ0JEY1Wz4
> gM
> > > qV3HYGyyp5m4r_Fje6dL5ptUdhSzeqzzqBBR0Jo-BC9arK-g$
> > >
> > > It looks very similar in several places so should that use the same
> > > driver?
> > > Cheers,
> > > -- Guido
> >
> > Interesting.
> >
> > So the original Cadence DP patches for TI SoCs did create a common
> > driver with Rockchip's older mhdp driver. And looks like the IMX series
> points to an early version of that patch ("drm/rockchip:
> > prepare common code for cdns and rk dpi/dp driver").
> >
> > We gave up on that as the IPs did have differences and the firmwares
> > used were apparently quite different. The end result was very
> > difficult to maintain, especially as (afaik) none of the people involved had
> relevant Rockchip HW.
>
> Is the `struct mhdp_platform_ops` a leftover from that? Can that be
> dropped?
>
> > The idea was to get a stable DP driver for TI SoCs ready and upstream,
> > and then carefully try to create common parts with Rockchip's driver in
> small pieces.
>
> I wonder how imx8 would best blend into this? First thing will likely be to
> upstream the phy code in driveres/phy/ so a modified version of this bridge
> driver could call into that, then go and look for common patterns.
>
> > If the Rockchip and IMX mhdp have the same IP and same firmware, then
> > they obviously should share code as done in the series you point to.
>
> I'm pretty sure they use different firmware though - the imx8mq additionally
> supports HDMI with a different firmware on the same IP core
> (13.4 and 13.5 in the imx8mq ref manual).
>
> > Perhaps Cadence can clarify the differences between IMX, TI and
> > Rockchip IPs and FWs?
>
> That would be great!
> -- Guido
>
Following are the differences between MHDP IPs from Cadence for Rockchip, TI
and NxP:
The Rockchip and NXP MHDP Core shares the same part (IP8501) which is DP v1.3
SST
Controller with HDCP 2.2/1.x. NXP's version additionally supports HDMI.
TI uses a different part (IP8546A), which is DP v1.4 with HDCP 2.2/1.x.
TI DP Controller adds support for additional features such as Multi Stream
Support (MST),
Forward Error Correction (FEC) and Compression (DSC).
Also, FW used for TI has significant differences than FW used for Rockchip or
NXP.
NxP and TI firmware are developed and maintained separately by Cadence and are
in
active support.
>From the Linux driver perspective, given the differences, it would make sense
>to have
TI driver maintained separately.
Thanks,
Swapnil
>
> > I'm worried that if there are IP differences, even if not great ones,
> > and if the FWs are different and developed separately, it'll be a
> > constant "fix X for SoC A, and accidentally break Y for SoC B and C",
> especially if too much code is shared.
> >
> > In the long run I'm all for a single driver (or large shared parts),
> > but I'm not sure if we should start with that approach.
>
>
>
>
> >
> > Tomi
> >
> > --
> > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> > Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> >
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