Re: [bug report] drm/prime: replace NULL with error value in drm_prime_pages_to_sg

[YoungJun Cho]

Dear Dan,

Your mail flashes back to my memory 5 years ago.
Back then, I had cleaned up the exynos driver.

And the replacement IS_ERR was one of items.

IMHO it is still better to modify those two functions,
drm_gem_cma_prime_get_sg_table and xen_drm_front_gem_get_sg_table.

Thank you.
Best regards YJ


On Thu, 14 Jun 2018, 23:42 Dan Carpenter,  wrote:

> Hello YoungJun Cho,
>
> The patch 7e3d88f9cce3: "drm/prime: replace NULL with error value in
> drm_prime_pages_to_sg" from Jun 24, 2013, leads to the following
> static checker warning:
>
> drivers/gpu/drm/drm_prime.c:317 drm_gem_map_dma_buf()
> warn: 'sgt' can also be NULL
>
> drivers/gpu/drm/drm_prime.c
>307  /*
>308   * two mappings with different directions for the same
> attachment are
>309   * not allowed
>310   */
>311  if (WARN_ON(prime_attach->dir != DMA_NONE))
>312  return ERR_PTR(-EBUSY);
>313
>314  sgt = obj->dev->driver->gem_prime_get_sg_table(obj);
>
> The problematic functions here are drm_gem_cma_prime_get_sg_table() and
> xen_drm_front_gem_get_sg_table().  My preference would be to update
> those functions to return error pointers, but I'm not familiar with the
> code or able to test it.
>
> But this static checker test seems pretty good so I'm likely to publish
> it soon and then this sort of bug will normally be caught quickly.
>
>315
>316  if (!IS_ERR(sgt)) {
>317  if (!dma_map_sg_attrs(attach->dev, sgt->sgl,
> sgt->nents, dir,
>318DMA_ATTR_SKIP_CPU_SYNC)) {
>319  sg_free_table(sgt);
>320  kfree(sgt);
>321  sgt = ERR_PTR(-ENOMEM);
>322  } else {
>323  prime_attach->sgt = sgt;
>324  prime_attach->dir = dir;
>325  }
>326  }
>327
>328  return sgt;
>
> regards,
> dan carpenter
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[RFC PATCH v2] drm/exynos: make non kms drivers to be indenpendent modules

[YoungJun Cho]

Hi Inki,

There are 3 comments below.

On 11/19/2014 12:19 PM, Inki Dae wrote:
> This patch makes non kms drivers to be independent modules.
> For this, it removes all register codes to non kms drivers
> from exynos_drm_drv module and adds module_init/exit
> for each non kms driver so that each non kms driver can be
> called independently.
>
> In addition, this patch adds non kms register/unregister functions
> to exynos_drm_core module and also modifies existing codes relevant
> to sub driver.
>
> The idea is that non kms driver is registered by entry point,
> module_init, of each non kms driver and sets its own sub driver
> to registered non kms driver object when the sub driver is probed.
> For this, this patch adds a new structure, exynos_drm_non_kms_dev,
> to exynos_drm_core module.
>
> Changelog v2:
> - check if available g2d device node.
> - return 0 instead of -EPROBE_DEFER in case of no non kms device
>registered. This case is not error.
>
> Signed-off-by: Inki Dae 
> ---
>   drivers/gpu/drm/exynos/exynos_drm_core.c|  164 
> +++
>   drivers/gpu/drm/exynos/exynos_drm_drv.c |   50 +---
>   drivers/gpu/drm/exynos/exynos_drm_drv.h |   28 ++---
>   drivers/gpu/drm/exynos/exynos_drm_fimc.c|   13 +++
>   drivers/gpu/drm/exynos/exynos_drm_g2d.c |   42 +++
>   drivers/gpu/drm/exynos/exynos_drm_gsc.c |   12 ++
>   drivers/gpu/drm/exynos/exynos_drm_ipp.c |   39 ++-
>   drivers/gpu/drm/exynos/exynos_drm_rotator.c |   13 +++
>   8 files changed, 271 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c 
> b/drivers/gpu/drm/exynos/exynos_drm_core.c
> index 4c9f972..715a0ad 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_core.c
> @@ -19,6 +19,13 @@
>   #include "exynos_drm_fbdev.h"
>
>   static LIST_HEAD(exynos_drm_subdrv_list);
> +DEFINE_MUTEX(list_lock);
> +
> +struct exynos_drm_non_kms_dev {
> + struct list_head list;
> + struct exynos_drm_subdrv *subdrv;
> + unsigned int device_type;
> +};
>
>   int exynos_drm_create_enc_conn(struct drm_device *dev,
>   struct exynos_drm_display *display)
> @@ -55,12 +62,66 @@ err_destroy_encoder:
>   return ret;
>   }
>
> +int exynos_drm_non_kms_register(unsigned int device_type)
> +{
> + struct exynos_drm_non_kms_dev *dev;
> +
> + dev = kzalloc(sizeof(*dev), GFP_KERNEL);
> + if (!dev)
> + return -ENOMEM;
> +
> + dev->device_type = device_type;
> +
> + mutex_lock(&list_lock);
> + list_add_tail(&dev->list, &exynos_drm_subdrv_list);
> + mutex_unlock(&list_lock);
> +
> + return 0;
> +}
> +
> +void exynos_drm_non_kms_unregister(unsigned int device_type)
> +{
> + struct exynos_drm_non_kms_dev *dev, *next;
> +
> + mutex_lock(&list_lock);
> + list_for_each_entry_safe(dev, next, &exynos_drm_subdrv_list, list) {
> + mutex_unlock(&list_lock);
> + if (dev->device_type == device_type) {
> + list_del_init(&dev->list);
> + kfree(dev);
> + mutex_lock(&list_lock);
> + break;
> + }
> + mutex_lock(&list_lock);
> + }
> + mutex_unlock(&list_lock);
> +}
> +
>   int exynos_drm_subdrv_register(struct exynos_drm_subdrv *subdrv)
>   {
> + struct exynos_drm_non_kms_dev *dev;
> +
>   if (!subdrv)
>   return -EINVAL;
>
> - list_add_tail(&subdrv->list, &exynos_drm_subdrv_list);
> + mutex_lock(&list_lock);
> + if (list_empty(&exynos_drm_subdrv_list)) {
> + mutex_unlock(&list_lock);
> + return -ENODEV;
> + }
> + mutex_unlock(&list_lock);

The list_for_each_entry() could handle empty list, so list_empty() could 
be removed.

> +
> + mutex_lock(&list_lock);
> + list_for_each_entry(dev, &exynos_drm_subdrv_list, list) {
> + mutex_unlock(&list_lock);
> + if (dev->device_type == subdrv->device_type) {
> + dev->subdrv = subdrv;
> + mutex_lock(&list_lock);
> + break;
> + }
> + mutex_lock(&list_lock);
> + }
> + mutex_unlock(&list_lock);
>
>   return 0;
>   }
> @@ -68,94 +129,149 @@ EXPORT_SYMBOL_GPL(exynos_drm_subdrv_register);
>
>   int exynos_drm_subdrv_unregister(struct exynos_drm_subdrv *subdrv)
>   {
> + struct exynos_drm_non_kms_dev *dev;
> +
>   if (!subdrv)
>   return -EINVAL;
>
> - list_del(&subdrv->list);
> + mutex_lock(&list_lock);
> + list_for_each_entry(dev, &exynos_drm_subdrv_list, list) {
> + mutex_unlock(&list_lock);
> + if (dev->device_type == subdrv->device_type) {
> + dev->subdrv = NULL;
> + break;
> + }
> + mutex_lock(&list_lock);
> + }
> + mutex_unlock(&list_lock);
>
>   return 0;
>   

[PATCH 9/9] drm/exynos: dsi: set TE GPIO IRQ status as IRQ_NOAUTOEN

[YoungJun Cho]

The exynos_dsi_te_irq_handler() works only dsi(DPMS) is on.
So it is enough to enable and disable TE GPIO IRQ in
exynos_dsi_enable(disable)_irq() like DSI IRQ.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae a
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6fe6486..717c719 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1155,6 +1155,7 @@ static int exynos_dsi_init(struct exynos_dsi *dsi)
 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
 {
int ret;
+   int te_gpio_irq;

dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
if (!gpio_is_valid(dsi->te_gpio)) {
@@ -1169,14 +1170,10 @@ static int exynos_dsi_register_te_irq(struct exynos_dsi 
*dsi)
goto out;
}

-   /*
-* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
-* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
-* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
-* called by drm_panel_init() before panel is attached.
-*/
-   ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
-   exynos_dsi_te_irq_handler, NULL,
+   te_gpio_irq = gpio_to_irq(dsi->te_gpio);
+
+   irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
+   ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
IRQF_TRIGGER_RISING, "TE", dsi);
if (ret) {
dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
-- 
1.9.0

[PATCH 8/9] drm/exynos: dsi: move TE irq handler registration position

[YoungJun Cho]

The drm_helper_hpd_irq_event() does dpms control and
the panel is initialized and displayed on by it.
So the exynos_dsi_te_irq_handler() should be registered
beforehand.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 66d427e..6fe6486 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1207,9 +1207,6 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
dsi->mode_flags = device->mode_flags;
dsi->panel_node = device->dev.of_node;

-   if (dsi->connector.dev)
-   drm_helper_hpd_irq_event(dsi->connector.dev);
-
/*
 * This is a temporary solution and should be made by more generic way.
 *
@@ -1223,6 +1220,9 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
return ret;
}

+   if (dsi->connector.dev)
+   drm_helper_hpd_irq_event(dsi->connector.dev);
+
return 0;
 }

-- 
1.9.0

[PATCH 7/9] drm/exynos: use irq_flags instead of triggering

[YoungJun Cho]

From: Joonyoung Shim 

The drm_handle_vblank should be called whenever be vsync, te interrupt
means vsync on i80 interface.

Signed-off-by: Joonyoung Shim 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index e488b80..a8ab3ec 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -1014,7 +1014,7 @@ static void fimd_te_handler(struct exynos_drm_manager 
*mgr)
wake_up(&ctx->wait_vsync_queue);
}

-   if (!atomic_read(&ctx->triggering))
+   if (test_bit(0, &ctx->irq_flags))
drm_handle_vblank(ctx->drm_dev, ctx->pipe);
 }

@@ -1052,13 +1052,15 @@ static irqreturn_t fimd_irq_handler(int irq, void 
*dev_id)
if (ctx->pipe < 0 || !ctx->drm_dev)
goto out;

-   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
-   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
-
if (ctx->i80_if) {
+   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
+
/* Exits triggering mode */
atomic_set(&ctx->triggering, 0);
} else {
+   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
+   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
+
/* set wait vsync event to zero and wake up queue. */
if (atomic_read(&ctx->wait_vsync_event)) {
atomic_set(&ctx->wait_vsync_event, 0);
-- 
1.9.0

[PATCH 6/9] drm/exynos: fimd: add triggering unset routine in fimd_trigger()

[YoungJun Cho]

There is a case like set config which requires triggering
but vblank is not enabled yet.
So triggering unset routine is required to exit from
triggering mode.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 3c63237..e488b80 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -984,6 +984,13 @@ static void fimd_trigger(struct device *dev)
reg = readl(timing_base + TRIGCON);
reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
writel(reg, timing_base + TRIGCON);
+
+   /*
+* Exits triggering mode if vblank is not enabled yet, because when the
+* VIDINTCON0 register is not set, it can not exit from triggering mode.
+*/
+   if (!test_bit(0, &ctx->irq_flags))
+   atomic_set(&ctx->triggering, 0);
 }

 static void fimd_te_handler(struct exynos_drm_manager *mgr)
-- 
1.9.0

[PATCH 5/9] drm/exynos: fimd: modify I80 i/f irq relevant routine

[YoungJun Cho]

For the I80 interface, the video interrupt pending register(VIDINTCON1)
should be handled in fimd_irq_handler() and the video interrupt control
register(VIDINTCON0) should be handled in fimd_enable_vblank() and
fimd_disable_vblank() like RGB interface.
So this patch moves each set / unset routines into proper positions.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 53 
 1 file changed, 27 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index fd7b469..3c63237 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -469,12 +469,19 @@ static int fimd_enable_vblank(struct exynos_drm_manager 
*mgr)
val = readl(ctx->regs + VIDINTCON0);

val |= VIDINTCON0_INT_ENABLE;
-   val |= VIDINTCON0_INT_FRAME;

-   val &= ~VIDINTCON0_FRAMESEL0_MASK;
-   val |= VIDINTCON0_FRAMESEL0_VSYNC;
-   val &= ~VIDINTCON0_FRAMESEL1_MASK;
-   val |= VIDINTCON0_FRAMESEL1_NONE;
+   if (ctx->i80_if) {
+   val |= VIDINTCON0_INT_I80IFDONE;
+   val |= VIDINTCON0_INT_SYSMAINCON;
+   val &= ~VIDINTCON0_INT_SYSSUBCON;
+   } else {
+   val |= VIDINTCON0_INT_FRAME;
+
+   val &= ~VIDINTCON0_FRAMESEL0_MASK;
+   val |= VIDINTCON0_FRAMESEL0_VSYNC;
+   val &= ~VIDINTCON0_FRAMESEL1_MASK;
+   val |= VIDINTCON0_FRAMESEL1_NONE;
+   }

writel(val, ctx->regs + VIDINTCON0);
}
@@ -493,9 +500,15 @@ static void fimd_disable_vblank(struct exynos_drm_manager 
*mgr)
if (test_and_clear_bit(0, &ctx->irq_flags)) {
val = readl(ctx->regs + VIDINTCON0);

-   val &= ~VIDINTCON0_INT_FRAME;
val &= ~VIDINTCON0_INT_ENABLE;

+   if (ctx->i80_if) {
+   val &= ~VIDINTCON0_INT_I80IFDONE;
+   val &= ~VIDINTCON0_INT_SYSMAINCON;
+   val &= ~VIDINTCON0_INT_SYSSUBCON;
+   } else
+   val &= ~VIDINTCON0_INT_FRAME;
+
writel(val, ctx->regs + VIDINTCON0);
}
 }
@@ -959,19 +972,15 @@ static void fimd_trigger(struct device *dev)
u32 reg;

 /*
-* Skips to trigger if in triggering state, because multiple triggering
-* requests can cause panel reset.
-*/
+ * Skips triggering if in triggering state, because multiple triggering
+ * requests can cause panel reset.
+ */
if (atomic_read(&ctx->triggering))
return;

+   /* Enters triggering mode */
atomic_set(&ctx->triggering, 1);

-   reg = readl(ctx->regs + VIDINTCON0);
-   reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
-   VIDINTCON0_INT_SYSMAINCON);
-   writel(reg, ctx->regs + VIDINTCON0);
-
reg = readl(timing_base + TRIGCON);
reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
writel(reg, timing_base + TRIGCON);
@@ -1036,21 +1045,13 @@ static irqreturn_t fimd_irq_handler(int irq, void 
*dev_id)
if (ctx->pipe < 0 || !ctx->drm_dev)
goto out;

-   if (ctx->i80_if) {
-   /* unset I80 frame done interrupt */
-   val = readl(ctx->regs + VIDINTCON0);
-   val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
-   writel(val, ctx->regs + VIDINTCON0);
+   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
+   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);

-   /* exit triggering mode */
+   if (ctx->i80_if) {
+   /* Exits triggering mode */
atomic_set(&ctx->triggering, 0);
-
-   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
-   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
} else {
-   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
-   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
-
/* set wait vsync event to zero and wake up queue. */
if (atomic_read(&ctx->wait_vsync_event)) {
atomic_set(&ctx->wait_vsync_event, 0);
-- 
1.9.0

[PATCH 4/9] drm/exynos: fimd: add fimd_enable_shadow_channel_path() to cleanup

[YoungJun Cho]

This function is valid only the SoC has SHADOWCON register
and it should be used together with fimd_enable_video_output()
to match the ENWIN_F bit in WINCON# and C#_EN_F bit in SHADOWCON.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 40 ++--
 1 file changed, 22 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 5cfd251..fd7b469 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -242,6 +242,19 @@ static void fimd_enable_video_output(struct fimd_context 
*ctx, int win,
writel(val, ctx->regs + WINCON(win));
 }

+static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
+   bool enable)
+{
+   u32 val = readl(ctx->regs + SHADOWCON);
+
+   if (enable)
+   val |= SHADOWCON_CHx_ENABLE(win);
+   else
+   val &= ~SHADOWCON_CHx_ENABLE(win);
+
+   writel(val, ctx->regs + SHADOWCON);
+}
+
 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
 {
struct fimd_context *ctx = mgr->ctx;
@@ -256,12 +269,10 @@ static void fimd_clear_channel(struct exynos_drm_manager 
*mgr)
if (val & WINCONx_ENWIN) {
fimd_enable_video_output(ctx, win, false);

-   /* unprotect windows */
-   if (ctx->driver_data->has_shadowcon) {
-   val = readl(ctx->regs + SHADOWCON);
-   val &= ~SHADOWCON_CHx_ENABLE(win);
-   writel(val, ctx->regs + SHADOWCON);
-   }
+   if (ctx->driver_data->has_shadowcon)
+   fimd_enable_shadow_channel_path(ctx, win,
+   false);
+
ch_enabled = 1;
}
}
@@ -759,11 +770,8 @@ static void fimd_win_commit(struct exynos_drm_manager 
*mgr, int zpos)

fimd_enable_video_output(ctx, win, true);

-   if (ctx->driver_data->has_shadowcon) {
-   val = readl(ctx->regs + SHADOWCON);
-   val |= SHADOWCON_CHx_ENABLE(win);
-   writel(val, ctx->regs + SHADOWCON);
-   }
+   if (ctx->driver_data->has_shadowcon)
+   fimd_enable_shadow_channel_path(ctx, win, true);

/* Enable DMA channel and unprotect windows */
fimd_shadow_protect_win(ctx, win, false);
@@ -779,7 +787,6 @@ static void fimd_win_disable(struct exynos_drm_manager 
*mgr, int zpos)
struct fimd_context *ctx = mgr->ctx;
struct fimd_win_data *win_data;
int win = zpos;
-   u32 val;

if (win == DEFAULT_ZPOS)
win = ctx->default_win;
@@ -800,13 +807,10 @@ static void fimd_win_disable(struct exynos_drm_manager 
*mgr, int zpos)

fimd_enable_video_output(ctx, win, false);

-   /* unprotect windows */
-   if (ctx->driver_data->has_shadowcon) {
-   val = readl(ctx->regs + SHADOWCON);
-   val &= ~SHADOWCON_CHx_ENABLE(win);
-   writel(val, ctx->regs + SHADOWCON);
-   }
+   if (ctx->driver_data->has_shadowcon)
+   fimd_enable_shadow_channel_path(ctx, win, false);

+   /* unprotect windows */
fimd_shadow_protect_win(ctx, win, false);

win_data->enabled = false;
-- 
1.9.0

[PATCH 3/9] drm/exynos: fimd: add fimd_enable_video_output() to cleanup

[YoungJun Cho]

This bit is used for video output and logic signal control.
So it is better for readability.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 27 ---
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 77ba961..5cfd251 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -229,6 +229,19 @@ static void fimd_wait_for_vblank(struct exynos_drm_manager 
*mgr)
DRM_DEBUG_KMS("vblank wait timed out.\n");
 }

+static void fimd_enable_video_output(struct fimd_context *ctx, int win,
+   bool enable)
+{
+   u32 val = readl(ctx->regs + WINCON(win));
+
+   if (enable)
+   val |= WINCONx_ENWIN;
+   else
+   val &= ~WINCONx_ENWIN;
+
+   writel(val, ctx->regs + WINCON(win));
+}
+
 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
 {
struct fimd_context *ctx = mgr->ctx;
@@ -241,9 +254,7 @@ static void fimd_clear_channel(struct exynos_drm_manager 
*mgr)
u32 val = readl(ctx->regs + WINCON(win));

if (val & WINCONx_ENWIN) {
-   /* wincon */
-   val &= ~WINCONx_ENWIN;
-   writel(val, ctx->regs + WINCON(win));
+   fimd_enable_video_output(ctx, win, false);

/* unprotect windows */
if (ctx->driver_data->has_shadowcon) {
@@ -746,10 +757,7 @@ static void fimd_win_commit(struct exynos_drm_manager 
*mgr, int zpos)
if (win != 0)
fimd_win_set_colkey(ctx, win);

-   /* wincon */
-   val = readl(ctx->regs + WINCON(win));
-   val |= WINCONx_ENWIN;
-   writel(val, ctx->regs + WINCON(win));
+   fimd_enable_video_output(ctx, win, true);

if (ctx->driver_data->has_shadowcon) {
val = readl(ctx->regs + SHADOWCON);
@@ -790,10 +798,7 @@ static void fimd_win_disable(struct exynos_drm_manager 
*mgr, int zpos)
/* protect windows */
fimd_shadow_protect_win(ctx, win, true);

-   /* wincon */
-   val = readl(ctx->regs + WINCON(win));
-   val &= ~WINCONx_ENWIN;
-   writel(val, ctx->regs + WINCON(win));
+   fimd_enable_video_output(ctx, win, false);

/* unprotect windows */
if (ctx->driver_data->has_shadowcon) {
-- 
1.9.0

[PATCH 2/9] drm/exynos: fimd: move shadow unprotection position

[YoungJun Cho]

The C#_EN_F in SHADOWCON register is updated per frame.
So it should be protected by fimd_shadow_protect_win().

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index ec2d170..77ba961 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -751,15 +751,15 @@ static void fimd_win_commit(struct exynos_drm_manager 
*mgr, int zpos)
val |= WINCONx_ENWIN;
writel(val, ctx->regs + WINCON(win));

-   /* Enable DMA channel and unprotect windows */
-   fimd_shadow_protect_win(ctx, win, false);
-
if (ctx->driver_data->has_shadowcon) {
val = readl(ctx->regs + SHADOWCON);
val |= SHADOWCON_CHx_ENABLE(win);
writel(val, ctx->regs + SHADOWCON);
}

+   /* Enable DMA channel and unprotect windows */
+   fimd_shadow_protect_win(ctx, win, false);
+
win_data->enabled = true;

if (ctx->i80_if)
-- 
1.9.0

[PATCH 1/9] drm/exynos: move triggering checking

[YoungJun Cho]

From: Joonyoung Shim 

It's better to be checking whether triggerring in fimd_trigger function.
Also it will return if in triggerring on fimd_te_handler, then it can't
execute remain codes.

Signed-off-by: Joonyoung Shim 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 0673a39..ec2d170 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -949,6 +949,13 @@ static void fimd_trigger(struct device *dev)
void *timing_base = ctx->regs + driver_data->timing_base;
u32 reg;

+/*
+* Skips to trigger if in triggering state, because multiple triggering
+* requests can cause panel reset.
+*/
+   if (atomic_read(&ctx->triggering))
+   return;
+
atomic_set(&ctx->triggering, 1);

reg = readl(ctx->regs + VIDINTCON0);
@@ -969,13 +976,6 @@ static void fimd_te_handler(struct exynos_drm_manager *mgr)
if (ctx->pipe < 0 || !ctx->drm_dev)
return;

-/*
-* Skips to trigger if in triggering state, because multiple triggering
-* requests can cause panel reset.
-*/
-   if (atomic_read(&ctx->triggering))
-   return;
-
/*
 * If there is a page flip request, triggers and handles the page flip
 * event so that current fb can be updated into panel GRAM.
-- 
1.9.0

[PATCH v2 0/9] drm/exynos: modify LCD I80 interface display

[YoungJun Cho]

Hi,

This series modifies LCD I80 interface display for Exynos DRM driver
to make it similar with Video(RGB) interface.
Some patches in v1 are applied already and these are modified as Inki's
comments.
And Joonyoung's patches are also included for merge convenience.

This is based on exynos-drm-next branch.

The previous patches,
v1: http://www.spinics.net/lists/dri-devel/msg69159.html

Changelog v2:
- Splits patches into single feature. (commented by Inki)

I welcome any comments.

Thank you.
Best regards YJ

Joonyoung Shim (2):
  drm/exynos: move triggering checking
  drm/exynos: use irq_flags instead of triggering

YoungJun Cho (7):
  drm/exynos: fimd: move shadow unprotection position
  drm/exynos: fimd: add fimd_enable_video_output() to cleanup
  drm/exynos: fimd: add fimd_enable_shadow_channel_path() to cleanup
  drm/exynos: fimd: modify I80 i/f irq relevant routine
  drm/exynos: fimd: add triggering unset routine in fimd_trigger()
  drm/exynos: dsi: move TE irq handler registration position
  drm/exynos: dsi: set TE GPIO IRQ status as IRQ_NOAUTOEN

 drivers/gpu/drm/exynos/exynos_drm_dsi.c  |  19 ++---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 135 ++-
 2 files changed, 85 insertions(+), 69 deletions(-)

-- 
1.9.0

[PATCH 5/7] drm/exynos: fimd: modify I80 i/f interrupt relevant routine

[YoungJun Cho]

Hi Inki,

On 11/14/2014 10:36 AM, Inki Dae wrote:
> On 2014년 10월 01일 15:19, YoungJun Cho wrote:
>> For the I80 interface, the video interrupt pending register(VIDINTCON1)
>> should be handled in fimd_irq_handler() and the video interrupt control
>> register(VIDINTCON0) should be handled in fimd_enable_vblank() and
>> fimd_disable_vblank() like RGB interface.
>> So this patch moves each set / unset routines into proper positions.
>> And adds triggering unset routine in fimd_trigger() to exit from it
>> because there is a case like set config which requires triggering
>> but vblank is not enabled.
>
> Reasonable but how about separating this patch into two patches. One is
> set/unset properly the registers relevant to interrupt, and other?
>
> It seems that your patch includes some codes not relevant to above
> description. And below is my comment.
>
> Thanks,
> Inki Dae
>
>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   drivers/gpu/drm/exynos/exynos_drm_fimd.c | 60 
>> ++--
>>   1 file changed, 34 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> index f062335..c949099 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> @@ -463,12 +463,19 @@ static int fimd_enable_vblank(struct 
>> exynos_drm_manager *mgr)
>>  val = readl(ctx->regs + VIDINTCON0);
>>
>>  val |= VIDINTCON0_INT_ENABLE;
>> -val |= VIDINTCON0_INT_FRAME;
>>
>> -val &= ~VIDINTCON0_FRAMESEL0_MASK;
>> -val |= VIDINTCON0_FRAMESEL0_VSYNC;
>> -val &= ~VIDINTCON0_FRAMESEL1_MASK;
>> -val |= VIDINTCON0_FRAMESEL1_NONE;
>> +if (ctx->i80_if) {
>> +val |= VIDINTCON0_INT_I80IFDONE;
>> +val |= VIDINTCON0_INT_SYSMAINCON;
>> +val &= ~VIDINTCON0_INT_SYSSUBCON;
>> +} else {
>> +val |= VIDINTCON0_INT_FRAME;
>> +
>> +val &= ~VIDINTCON0_FRAMESEL0_MASK;
>> +val |= VIDINTCON0_FRAMESEL0_VSYNC;
>> +val &= ~VIDINTCON0_FRAMESEL1_MASK;
>> +val |= VIDINTCON0_FRAMESEL1_NONE;
>> +}
>>
>>  writel(val, ctx->regs + VIDINTCON0);
>>  }
>> @@ -487,9 +494,15 @@ static void fimd_disable_vblank(struct 
>> exynos_drm_manager *mgr)
>>  if (test_and_clear_bit(0, &ctx->irq_flags)) {
>>  val = readl(ctx->regs + VIDINTCON0);
>>
>> -val &= ~VIDINTCON0_INT_FRAME;
>>  val &= ~VIDINTCON0_INT_ENABLE;
>>
>> +if (ctx->i80_if) {
>> +val &= ~VIDINTCON0_INT_I80IFDONE;
>> +val &= ~VIDINTCON0_INT_SYSMAINCON;
>> +val &= ~VIDINTCON0_INT_SYSSUBCON;
>> +} else
>> +val &= ~VIDINTCON0_INT_FRAME;
>> +
>>  writel(val, ctx->regs + VIDINTCON0);
>>  }
>>   }
>> @@ -945,16 +958,19 @@ static void fimd_trigger(struct device *dev)
>>  void *timing_base = ctx->regs + driver_data->timing_base;
>>  u32 reg;
>>
>> +/* Enters triggering mode */
>>  atomic_set(&ctx->triggering, 1);
>>
>> -reg = readl(ctx->regs + VIDINTCON0);
>> -reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
>> -VIDINTCON0_INT_SYSMAINCON);
>> -writel(reg, ctx->regs + VIDINTCON0);
>> -
>>  reg = readl(timing_base + TRIGCON);
>>  reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
>>  writel(reg, timing_base + TRIGCON);
>> +
>> +/*
>> + * Exits triggering mode if vblank is not enabled yet, because when the
>> + * VIDINTCON0 register is not set, it can not exit from triggering mode.
>> + */
>> +if (!test_bit(0, &ctx->irq_flags))
>> +atomic_set(&ctx->triggering, 0);
>
> I think this code would make for other trigger requested while triggering.
>

I missed this comment.

After modifying this patch, the I80 interface works with vblank enable / 
disable.
And there is a case like set config which requires triggering to update 
frame buffer but vblank is not enabled yet. So this ex

[PATCH 2/2] drm/exynos: use irq_flags instead of triggering

[YoungJun Cho]

Hi JoonYoung,

On 11/14/2014 02:12 PM, Joonyoung Shim wrote:
> Hi,
>
> On 11/14/2014 02:01 PM, YoungJun Cho wrote:
>> Hi JoonYoung,
>>
>> On 11/14/2014 11:36 AM, Joonyoung Shim wrote:
>>> The drm_handle_vblank should be called whenever be vsync, te interrupt
>>> means vsync on i80 interface.
>>
>> That's right.
>>
>>>
>>> Signed-off-by: Joonyoung Shim 
>>> ---
>>> Based on lastest exynos-drm-next branch and patch of Youngjun Cho
>>> ("drm/exynos: fimd: move handle vblank position in TE handler").
>>>
>>>drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
>>>1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
>>> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> index 033b18b..5cc57f7 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>>> @@ -984,7 +984,7 @@ static void fimd_te_handler(struct exynos_drm_manager 
>>> *mgr)
>>>wake_up(&ctx->wait_vsync_queue);
>>>}
>>>
>>> -if (!atomic_read(&ctx->triggering))
>>> +if (test_bit(0, &ctx->irq_flags))
>>>drm_handle_vblank(ctx->drm_dev, ctx->pipe);
>>
>> But after triggering, "fimd_irq_handler()" is called by "lcd_sys" interrupt 
>> and that calls "drm_handle_vblank()".
>>
>
> I missed the routine but i think drm_handle_vblank should be called by
> vsync interrupt handler. As you know, fimd_irq_handler is not vsync
> interrupt handler on i80 interface.

That sounds reasonable.
For that, we should modify "fimd_irq_handler()" not to call 
"drm_handle_vblank()" in I80 interface.

Thank you.
Best regards YJ

>
>> So I think "fimd_te_handler()" calls "drm_handle_vblank()" only 
>> non-triggering condition.
>>
>> Thank you.
>> Best regards YJ
>>
>>>}
>>>
>>>
>>
>>
>
>

[PATCH 2/2] drm/exynos: use irq_flags instead of triggering

[YoungJun Cho]

Hi JoonYoung,

On 11/14/2014 11:36 AM, Joonyoung Shim wrote:
> The drm_handle_vblank should be called whenever be vsync, te interrupt
> means vsync on i80 interface.

That's right.

>
> Signed-off-by: Joonyoung Shim 
> ---
> Based on lastest exynos-drm-next branch and patch of Youngjun Cho
> ("drm/exynos: fimd: move handle vblank position in TE handler").
>
>   drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> index 033b18b..5cc57f7 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
> @@ -984,7 +984,7 @@ static void fimd_te_handler(struct exynos_drm_manager 
> *mgr)
>   wake_up(&ctx->wait_vsync_queue);
>   }
>
> - if (!atomic_read(&ctx->triggering))
> + if (test_bit(0, &ctx->irq_flags))
>   drm_handle_vblank(ctx->drm_dev, ctx->pipe);

But after triggering, "fimd_irq_handler()" is called by "lcd_sys" 
interrupt and that calls "drm_handle_vblank()".

So I think "fimd_te_handler()" calls "drm_handle_vblank()" only 
non-triggering condition.

Thank you.
Best regards YJ

>   }
>
>

[PATCH 6/7] drm/exynos: dsi: move TE irq handler registration position

[YoungJun Cho]

Hi Inki,

On 11/14/2014 10:49 AM, Inki Dae wrote:
> On 2014년 10월 01일 15:19, YoungJun Cho wrote:
>> The drm_helper_hpd_irq_event() does dpms control and panel is
>> initialized and displayed on by it.
>> So should register TE irq handler(exynos_dsi_te_irq_handler())
>> beforehand.
>
> This patch also includes some codes not relevant to register TE irq
> handler before drm_helper_hpd_irq_event call. How about separating this
> patch into two patches?
>
> And below is my comment.
>
> Thanks,
> Inki Dae
>
>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 ---
>>   1 file changed, 8 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> index 24741d8..ded69df 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> @@ -1143,6 +1143,7 @@ static int exynos_dsi_init(struct exynos_dsi *dsi)
>>   static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
>>   {
>>  int ret;
>> +int te_gpio_irq;
>>
>>  dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
>>  if (!gpio_is_valid(dsi->te_gpio)) {
>> @@ -1157,14 +1158,10 @@ static int exynos_dsi_register_te_irq(struct 
>> exynos_dsi *dsi)
>>  goto out;
>>  }
>>
>> -/*
>> - * This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
>> - * calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
>> - * It means that te_gpio is invalid when exynos_dsi_enable_irq() is
>> - * called by drm_panel_init() before panel is attached.
>> - */
>> -ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
>> -exynos_dsi_te_irq_handler, NULL,
>> +te_gpio_irq = gpio_to_irq(dsi->te_gpio);
>> +
>> +irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
>
> I think with IRQ_NOAUTOEN, te irq wouldn't be enabled automatically. So
> shouldn't we call enable_irq() and disable_irq() somewhere?

The te_gpio irq triggering is done by exynos_dsi_enable_irq() and 
exynos_dsi_disable_irq() like dsi irq.

And I'll separate patch with others also.

Thank you.
Best regards YJ

>
>> +ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
>>  IRQF_TRIGGER_RISING, "TE", dsi);
>>  if (ret) {
>>  dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
>> @@ -1195,9 +1192,6 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
>> *host,
>>  dsi->mode_flags = device->mode_flags;
>>  dsi->panel_node = device->dev.of_node;
>>
>> -if (dsi->connector.dev)
>> -drm_helper_hpd_irq_event(dsi->connector.dev);
>> -
>>  /*
>>   * This is a temporary solution and should be made by more generic way.
>>   *
>> @@ -1211,6 +1205,9 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
>> *host,
>>  return ret;
>>  }
>>
>> +if (dsi->connector.dev)
>> +drm_helper_hpd_irq_event(dsi->connector.dev);
>> +
>>  return 0;
>>   }
>>
>>
>
>

[PATCH 3/7] drm/exynos: fimd: modify vclk calculation for I80 i/f

[YoungJun Cho]

Hi Inki,

On 11/13/2014 06:12 PM, Inki Dae wrote:
> On 2014년 10월 01일 15:19, YoungJun Cho wrote:
>> The I80 interface uses SYS_WE and SYS_CS to process
>> 1 pixel data, so it requires the twice faster clock
>> than the pixel clock.
>> And the frame done interrupt should occurr prior to
>> the next TE signal, H/W guy recommends to use as 1.73
>> times faster clock frequency.
>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   drivers/gpu/drm/exynos/exynos_drm_fimd.c | 26 --
>>   1 file changed, 20 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> index b2f6007..05c2a97a 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
>> @@ -81,6 +81,11 @@
>>   #define LCD_WR_HOLD(x) ((x) << 4)
>>   #define I80IFEN_ENABLE (1 << 0)
>>
>> +/* I80 interface clock */
>> +#define I80_DATA_SAMPLING_CYCLE 2
>> +#define I80_TE_PERIOD_US1667
>> +#define I80_DATA_TRANSACTION_TIME_US964
>> +
>>   /* FIMD has totally five hardware windows. */
>>   #define WINDOWS_NR 5
>>
>> @@ -303,16 +308,25 @@ static void fimd_mgr_remove(struct exynos_drm_manager 
>> *mgr)
>>   static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
>>  const struct drm_display_mode *mode)
>>   {
>> -unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
>> +unsigned long ideal_clk;
>>  u32 clkdiv;
>>
>>  if (ctx->i80_if) {
>>  /*
>> - * The frame done interrupt should be occurred prior to the
>> - * next TE signal.
>> + * The I80 interface uses SYS_WE and SYS_CS to process 1 pixel
>> + * data, so it requires the twice faster clock than the pixel
>> + * clock[I80_DATA_SAMPLING_CYCLE].
>> + * And the frame done interrupt should occurr prior to the next
>> + * TE signal, H/W guy recommends to use as 1.73 times faster
>> + * frequency[I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US].
>>   */
>> -ideal_clk *= 2;
>> -}
>> +ideal_clk = mode->hdisplay * mode->vdisplay *
>> +I80_DATA_SAMPLING_CYCLE *
>> +I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US;
>
> How about using one constant directly?
>
> I.e.,
> #define RECOMMENDED_VAR   1.73
>
>   ... I80_DATA_SAMPLING_CYCLE * RECOMMENDED_VAR
>
> Is there any case that the te period and data transaction time should be
> changed?
>

At first time, I did.

But it made following build break :
   drivers/built-in.o: In function `fimd_commit':
   exynos_adc.c:(.text+0x878bc): undefined reference to `__aeabi_ui2d'
   exynos_adc.c:(.text+0x878d0): undefined reference to `__aeabi_dmul'
   exynos_adc.c:(.text+0x878d4): undefined reference to `__aeabi_d2uiz'
   make: *** [vmlinux] Error 1

It came from using floating point value.
So I changed it.

Do you have any good idea ?

Thank you.
Best regards YJ

>
> Thanks,
> Inki Dae
>
>
>> +} else
>> +ideal_clk = mode->htotal * mode->vtotal;
>> +
>> +ideal_clk *= mode->vrefresh;
>>
>>  /* Find the clock divider value that gets us closest to ideal_clk */
>>  clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
>> @@ -431,7 +445,7 @@ static void fimd_commit(struct exynos_drm_manager *mgr)
>>  val |= VIDCON0_CLKSEL_LCD;
>>
>>  clkdiv = fimd_calc_clkdiv(ctx, mode);
>> -if (clkdiv > 1)
>> +if (clkdiv >= 1)
>>  val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
>>
>>  writel(val, ctx->regs + VIDCON0);
>>
>
>

[PATCH 4/4] ARM: dts: add mipi dsi device node to exynos4415.dtsi

[YoungJun Cho]

This patch adds mipi dsi device node to exynos4415.dtsi.

Signed-off-by: YoungJun Cho 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos4415.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4415.dtsi 
b/arch/arm/boot/dts/exynos4415.dtsi
index 30acb3a..6105236 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -246,6 +246,21 @@
status = "disabled";
};

+   dsi_0: dsi at 11C8 {
+   compatible = "samsung,exynos4415-mipi-dsi";
+   reg = <0x11C8 0x1>;
+   interrupts = <0 83 0>;
+   samsung,phy-type = <0>;
+   samsung,power-domain = <&pd_lcd0>;
+   phys = <&mipi_phy 1>;
+   phy-names = "dsim";
+   clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
+   clock-names = "bus_clk", "pll_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
hsotg: hsotg at 1248 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x1248 0x2>;
-- 
1.9.0

[PATCH 3/4] ARM: dts: add fimd device node to exynos4415.dtsi

[YoungJun Cho]

This patch adds fimd device node to exynos4415.dtsi.

Signed-off-by: YoungJun Cho 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos4415.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4415.dtsi 
b/arch/arm/boot/dts/exynos4415.dtsi
index c1c9b37..30acb3a 100644
--- a/arch/arm/boot/dts/exynos4415.dtsi
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -234,6 +234,18 @@
interrupts = <0 240 0>;
};

+   fimd: fimd at 11C0 {
+   compatible = "samsung,exynos4415-fimd";
+   reg = <0x11C0 0x3>;
+   interrupt-names = "fifo", "vsync", "lcd_sys";
+   interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
+   clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
+   clock-names = "sclk_fimd", "fimd";
+   samsung,power-domain = <&pd_lcd0>;
+   samsung,sysreg = <&sysreg_system_controller>;
+   status = "disabled";
+   };
+
hsotg: hsotg at 1248 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x1248 0x2>;
-- 
1.9.0

[PATCH 2/4] drm/exynos: fimd: support Exynos4415 SoC

[YoungJun Cho]

This patch supports Exynos4415 SoC.

Signed-off-by: YoungJun Cho 
Acked-by: Kyungmin Park 
---
 Documentation/devicetree/bindings/video/samsung-fimd.txt |  1 +
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt 
b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 4e6c77c..cf1af63 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -11,6 +11,7 @@ Required properties:
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
+   "samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */

 - reg: physical base address and length of the FIMD registers set.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 085b066..5dfbbdb 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -120,6 +120,15 @@ static struct fimd_driver_data exynos4_fimd_driver_data = {
.has_shadowcon = 1,
 };

+static struct fimd_driver_data exynos4415_fimd_driver_data = {
+   .timing_base = 0x2,
+   .lcdblk_offset = 0x210,
+   .lcdblk_vt_shift = 10,
+   .lcdblk_bypass_shift = 1,
+   .has_shadowcon = 1,
+   .has_vidoutcon = 1,
+};
+
 static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
.lcdblk_offset = 0x214,
@@ -180,6 +189,8 @@ static const struct of_device_id fimd_driver_dt_match[] = {
  .data = &exynos3_fimd_driver_data },
{ .compatible = "samsung,exynos4210-fimd",
  .data = &exynos4_fimd_driver_data },
+   { .compatible = "samsung,exynos4415-fimd",
+ .data = &exynos4415_fimd_driver_data },
{ .compatible = "samsung,exynos5250-fimd",
  .data = &exynos5_fimd_driver_data },
{},
-- 
1.9.0

[PATCH 1/4] drm/exynos: dsi: support Exynos4415 SoC

[YoungJun Cho]

This patch supports Exynos4415 SoC.

Signed-off-by: YoungJun Cho 
Acked-by: Kyungmin Park 
---
 Documentation/devicetree/bindings/video/exynos_dsim.txt | 1 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt 
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index e74243b..ca2b4aa 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -4,6 +4,7 @@ Required properties:
   - compatible: value should be one of the following
"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
+   "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs 
*/
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index acf7e9e..ff17c6e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -316,6 +316,11 @@ static struct exynos_dsi_driver_data 
exynos4_dsi_driver_data = {
.has_clklane_stop = 1,
 };

+static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
+   .plltmr_reg = 0x58,
+   .has_clklane_stop = 1,
+};
+
 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
.plltmr_reg = 0x58,
 };
@@ -325,6 +330,8 @@ static struct of_device_id exynos_dsi_of_match[] = {
  .data = &exynos3_dsi_driver_data },
{ .compatible = "samsung,exynos4210-mipi-dsi",
  .data = &exynos4_dsi_driver_data },
+   { .compatible = "samsung,exynos4415-mipi-dsi",
+ .data = &exynos4415_dsi_driver_data },
{ .compatible = "samsung,exynos5410-mipi-dsi",
  .data = &exynos5_dsi_driver_data },
{ }
-- 
1.9.0

[PATCH 0/4] drm/exynos: support Exynos4415 SoC

[YoungJun Cho]

This patch series adds of_device_id and relevant device nodes
for Exynos4415 SoC support.

This is based on exynos-drm-next branch for drm/exynos,
and is based on for-next branch in linux-samsung git for dts.

I think this requires rebase for the patch "drm/exynos: add has_vtsel flag"[1].

[1] http://www.spinics.net/lists/dri-devel/msg71092.html

YoungJun Cho (4):
  drm/exynos: dsi: support Exynos4415 SoC
  drm/exynos: fimd: support Exynos4415 SoC
  ARM: dts: add fimd device node to exynos4415.dtsi
  ARM: dts: add mipi dsi device node to exynos4415.dtsi

 .../devicetree/bindings/video/exynos_dsim.txt  |  1 +
 .../devicetree/bindings/video/samsung-fimd.txt |  1 +
 arch/arm/boot/dts/exynos4415.dtsi  | 27 ++
 drivers/gpu/drm/exynos/exynos_drm_dsi.c|  7 ++
 drivers/gpu/drm/exynos/exynos_drm_fimd.c   | 11 +
 5 files changed, 47 insertions(+)

-- 
1.9.0

[PATCH 7/7] drm/exynos: dsi: move DSIM_STATE_ENABLED set position

[YoungJun Cho]

The command mode panel should draw image earlier than the display
on command execution to prevent showing garbage GRAM screen data.
So should set dsi->state as DSIM_STATE_ENABLED between calling
exynos_dsi_set_display_enable() and drm_panel_enable() to transmit
image data before executing display on command.
And moves the display on command execution routine from prepare()
to enable() in drm_panel_funcs also.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index ded69df..f304a20 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1366,16 +1366,17 @@ static int exynos_dsi_enable(struct exynos_dsi *dsi)
exynos_dsi_set_display_mode(dsi);
exynos_dsi_set_display_enable(dsi, true);

+   dsi->state |= DSIM_STATE_ENABLED;
+
ret = drm_panel_enable(dsi->panel);
if (ret < 0) {
+   dsi->state &= ~DSIM_STATE_ENABLED;
exynos_dsi_set_display_enable(dsi, false);
drm_panel_unprepare(dsi->panel);
exynos_dsi_poweroff(dsi);
return ret;
}

-   dsi->state |= DSIM_STATE_ENABLED;
-
return 0;
 }

-- 
1.9.0

[PATCH 6/7] drm/exynos: dsi: move TE irq handler registration position

[YoungJun Cho]

The drm_helper_hpd_irq_event() does dpms control and panel is
initialized and displayed on by it.
So should register TE irq handler(exynos_dsi_te_irq_handler())
beforehand.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 19 ---
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 24741d8..ded69df 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -1143,6 +1143,7 @@ static int exynos_dsi_init(struct exynos_dsi *dsi)
 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
 {
int ret;
+   int te_gpio_irq;

dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
if (!gpio_is_valid(dsi->te_gpio)) {
@@ -1157,14 +1158,10 @@ static int exynos_dsi_register_te_irq(struct exynos_dsi 
*dsi)
goto out;
}

-   /*
-* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
-* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
-* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
-* called by drm_panel_init() before panel is attached.
-*/
-   ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
-   exynos_dsi_te_irq_handler, NULL,
+   te_gpio_irq = gpio_to_irq(dsi->te_gpio);
+
+   irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
+   ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
IRQF_TRIGGER_RISING, "TE", dsi);
if (ret) {
dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
@@ -1195,9 +1192,6 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
dsi->mode_flags = device->mode_flags;
dsi->panel_node = device->dev.of_node;

-   if (dsi->connector.dev)
-   drm_helper_hpd_irq_event(dsi->connector.dev);
-
/*
 * This is a temporary solution and should be made by more generic way.
 *
@@ -1211,6 +1205,9 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
return ret;
}

+   if (dsi->connector.dev)
+   drm_helper_hpd_irq_event(dsi->connector.dev);
+
return 0;
 }

-- 
1.9.0

[PATCH 5/7] drm/exynos: fimd: modify I80 i/f interrupt relevant routine

[YoungJun Cho]

For the I80 interface, the video interrupt pending register(VIDINTCON1)
should be handled in fimd_irq_handler() and the video interrupt control
register(VIDINTCON0) should be handled in fimd_enable_vblank() and
fimd_disable_vblank() like RGB interface.
So this patch moves each set / unset routines into proper positions.
And adds triggering unset routine in fimd_trigger() to exit from it
because there is a case like set config which requires triggering
but vblank is not enabled.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 60 ++--
 1 file changed, 34 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index f062335..c949099 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -463,12 +463,19 @@ static int fimd_enable_vblank(struct exynos_drm_manager 
*mgr)
val = readl(ctx->regs + VIDINTCON0);

val |= VIDINTCON0_INT_ENABLE;
-   val |= VIDINTCON0_INT_FRAME;

-   val &= ~VIDINTCON0_FRAMESEL0_MASK;
-   val |= VIDINTCON0_FRAMESEL0_VSYNC;
-   val &= ~VIDINTCON0_FRAMESEL1_MASK;
-   val |= VIDINTCON0_FRAMESEL1_NONE;
+   if (ctx->i80_if) {
+   val |= VIDINTCON0_INT_I80IFDONE;
+   val |= VIDINTCON0_INT_SYSMAINCON;
+   val &= ~VIDINTCON0_INT_SYSSUBCON;
+   } else {
+   val |= VIDINTCON0_INT_FRAME;
+
+   val &= ~VIDINTCON0_FRAMESEL0_MASK;
+   val |= VIDINTCON0_FRAMESEL0_VSYNC;
+   val &= ~VIDINTCON0_FRAMESEL1_MASK;
+   val |= VIDINTCON0_FRAMESEL1_NONE;
+   }

writel(val, ctx->regs + VIDINTCON0);
}
@@ -487,9 +494,15 @@ static void fimd_disable_vblank(struct exynos_drm_manager 
*mgr)
if (test_and_clear_bit(0, &ctx->irq_flags)) {
val = readl(ctx->regs + VIDINTCON0);

-   val &= ~VIDINTCON0_INT_FRAME;
val &= ~VIDINTCON0_INT_ENABLE;

+   if (ctx->i80_if) {
+   val &= ~VIDINTCON0_INT_I80IFDONE;
+   val &= ~VIDINTCON0_INT_SYSMAINCON;
+   val &= ~VIDINTCON0_INT_SYSSUBCON;
+   } else
+   val &= ~VIDINTCON0_INT_FRAME;
+
writel(val, ctx->regs + VIDINTCON0);
}
 }
@@ -945,16 +958,19 @@ static void fimd_trigger(struct device *dev)
void *timing_base = ctx->regs + driver_data->timing_base;
u32 reg;

+   /* Enters triggering mode */
atomic_set(&ctx->triggering, 1);

-   reg = readl(ctx->regs + VIDINTCON0);
-   reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
-   VIDINTCON0_INT_SYSMAINCON);
-   writel(reg, ctx->regs + VIDINTCON0);
-
reg = readl(timing_base + TRIGCON);
reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
writel(reg, timing_base + TRIGCON);
+
+   /*
+* Exits triggering mode if vblank is not enabled yet, because when the
+* VIDINTCON0 register is not set, it can not exit from triggering mode.
+*/
+   if (!test_bit(0, &ctx->irq_flags))
+   atomic_set(&ctx->triggering, 0);
 }

 static void fimd_te_handler(struct exynos_drm_manager *mgr)
@@ -966,9 +982,9 @@ static void fimd_te_handler(struct exynos_drm_manager *mgr)
return;

 /*
-* Skips to trigger if in triggering state, because multiple triggering
-* requests can cause panel reset.
-*/
+ * Skips triggering if in triggering mode, because multiple triggering
+ * requests can cause panel reset.
+ */
if (atomic_read(&ctx->triggering))
return;

@@ -1023,21 +1039,13 @@ static irqreturn_t fimd_irq_handler(int irq, void 
*dev_id)
if (ctx->pipe < 0 || !ctx->drm_dev)
goto out;

-   if (ctx->i80_if) {
-   /* unset I80 frame done interrupt */
-   val = readl(ctx->regs + VIDINTCON0);
-   val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
-   writel(val, ctx->regs + VIDINTCON0);
+   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
+   exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);

-   /* exit triggering mode */
+   if (ctx->i80_if) {
+   /* Exits triggering mode */
atomic_set(&ctx->triggering, 0);
-
-   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
-   exynos_drm_crtc_finish_pageflip(ctx-

[PATCH 4/7] drm/exynos: fimd: move handle vblank position in TE handler

[YoungJun Cho]

For providing VBLANK information, drm_handle_vblank() should
be called properly, but it is blocked by wait_vsync_event
condition which is set by manager_ops->wait_for_vblank().
So moves it out from wait_vsync_event routine.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 05c2a97a..f062335 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -983,10 +983,10 @@ static void fimd_te_handler(struct exynos_drm_manager 
*mgr)
if (atomic_read(&ctx->wait_vsync_event)) {
atomic_set(&ctx->wait_vsync_event, 0);
wake_up(&ctx->wait_vsync_queue);
-
-   if (!atomic_read(&ctx->triggering))
-   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
}
+
+   if (!atomic_read(&ctx->triggering))
+   drm_handle_vblank(ctx->drm_dev, ctx->pipe);
 }

 static struct exynos_drm_manager_ops fimd_manager_ops = {
-- 
1.9.0

[PATCH 3/7] drm/exynos: fimd: modify vclk calculation for I80 i/f

[YoungJun Cho]

The I80 interface uses SYS_WE and SYS_CS to process
1 pixel data, so it requires the twice faster clock
than the pixel clock.
And the frame done interrupt should occurr prior to
the next TE signal, H/W guy recommends to use as 1.73
times faster clock frequency.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 26 --
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index b2f6007..05c2a97a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -81,6 +81,11 @@
 #define LCD_WR_HOLD(x) ((x) << 4)
 #define I80IFEN_ENABLE (1 << 0)

+/* I80 interface clock */
+#define I80_DATA_SAMPLING_CYCLE2
+#define I80_TE_PERIOD_US   1667
+#define I80_DATA_TRANSACTION_TIME_US   964
+
 /* FIMD has totally five hardware windows. */
 #define WINDOWS_NR 5

@@ -303,16 +308,25 @@ static void fimd_mgr_remove(struct exynos_drm_manager 
*mgr)
 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
const struct drm_display_mode *mode)
 {
-   unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
+   unsigned long ideal_clk;
u32 clkdiv;

if (ctx->i80_if) {
/*
-* The frame done interrupt should be occurred prior to the
-* next TE signal.
+* The I80 interface uses SYS_WE and SYS_CS to process 1 pixel
+* data, so it requires the twice faster clock than the pixel
+* clock[I80_DATA_SAMPLING_CYCLE].
+* And the frame done interrupt should occurr prior to the next
+* TE signal, H/W guy recommends to use as 1.73 times faster
+* frequency[I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US].
 */
-   ideal_clk *= 2;
-   }
+   ideal_clk = mode->hdisplay * mode->vdisplay *
+   I80_DATA_SAMPLING_CYCLE *
+   I80_TE_PERIOD_US / I80_DATA_TRANSACTION_TIME_US;
+   } else
+   ideal_clk = mode->htotal * mode->vtotal;
+
+   ideal_clk *= mode->vrefresh;

/* Find the clock divider value that gets us closest to ideal_clk */
clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
@@ -431,7 +445,7 @@ static void fimd_commit(struct exynos_drm_manager *mgr)
val |= VIDCON0_CLKSEL_LCD;

clkdiv = fimd_calc_clkdiv(ctx, mode);
-   if (clkdiv > 1)
+   if (clkdiv >= 1)
val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;

writel(val, ctx->regs + VIDCON0);
-- 
1.9.0

[PATCH 2/7] drm/exynos: fimd: add fimd_channel_win() to clean up code

[YoungJun Cho]

The ENWIN_F in WINCON# register and C#_EN_Fs in SHADOWCON register
should be always matched together, so adds fimd_channel_win()
to clean up code.
And this fimd_channel_win() should be called before unprotecting
window in fimd_win_commit().

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 62 
 1 file changed, 30 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 8b31b7e..b2f6007 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -214,6 +214,33 @@ static void fimd_wait_for_vblank(struct exynos_drm_manager 
*mgr)
DRM_DEBUG_KMS("vblank wait timed out.\n");
 }

+static void fimd_channel_win(struct fimd_context *ctx, int win, bool enable)
+{
+   u32 val;
+
+   /* for DMA output */
+   val = readl(ctx->regs + WINCON(win));
+
+   if (enable)
+   val |= WINCONx_ENWIN;
+   else
+   val &= ~WINCONx_ENWIN;
+
+   writel(val, ctx->regs + WINCON(win));
+
+   /* for shadow channel */
+   if (ctx->driver_data->has_shadowcon) {
+   val = readl(ctx->regs + SHADOWCON);
+
+   if (enable)
+   val |= SHADOWCON_CHx_ENABLE(win);
+   else
+   val &= ~SHADOWCON_CHx_ENABLE(win);
+
+   writel(val, ctx->regs + SHADOWCON);
+   }
+}
+
 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
 {
struct fimd_context *ctx = mgr->ctx;
@@ -226,16 +253,7 @@ static void fimd_clear_channel(struct exynos_drm_manager 
*mgr)
u32 val = readl(ctx->regs + WINCON(win));

if (val & WINCONx_ENWIN) {
-   /* wincon */
-   val &= ~WINCONx_ENWIN;
-   writel(val, ctx->regs + WINCON(win));
-
-   /* unprotect windows */
-   if (ctx->driver_data->has_shadowcon) {
-   val = readl(ctx->regs + SHADOWCON);
-   val &= ~SHADOWCON_CHx_ENABLE(win);
-   writel(val, ctx->regs + SHADOWCON);
-   }
+   fimd_channel_win(ctx, win, false);
ch_enabled = 1;
}
}
@@ -730,20 +748,11 @@ static void fimd_win_commit(struct exynos_drm_manager 
*mgr, int zpos)
if (win != 0)
fimd_win_set_colkey(ctx, win);

-   /* wincon */
-   val = readl(ctx->regs + WINCON(win));
-   val |= WINCONx_ENWIN;
-   writel(val, ctx->regs + WINCON(win));
+   fimd_channel_win(ctx, win, true);

/* Enable DMA channel and unprotect windows */
fimd_shadow_protect_win(ctx, win, false);

-   if (ctx->driver_data->has_shadowcon) {
-   val = readl(ctx->regs + SHADOWCON);
-   val |= SHADOWCON_CHx_ENABLE(win);
-   writel(val, ctx->regs + SHADOWCON);
-   }
-
win_data->enabled = true;

if (ctx->i80_if)
@@ -755,7 +764,6 @@ static void fimd_win_disable(struct exynos_drm_manager 
*mgr, int zpos)
struct fimd_context *ctx = mgr->ctx;
struct fimd_win_data *win_data;
int win = zpos;
-   u32 val;

if (win == DEFAULT_ZPOS)
win = ctx->default_win;
@@ -774,17 +782,7 @@ static void fimd_win_disable(struct exynos_drm_manager 
*mgr, int zpos)
/* protect windows */
fimd_shadow_protect_win(ctx, win, true);

-   /* wincon */
-   val = readl(ctx->regs + WINCON(win));
-   val &= ~WINCONx_ENWIN;
-   writel(val, ctx->regs + WINCON(win));
-
-   /* unprotect windows */
-   if (ctx->driver_data->has_shadowcon) {
-   val = readl(ctx->regs + SHADOWCON);
-   val &= ~SHADOWCON_CHx_ENABLE(win);
-   writel(val, ctx->regs + SHADOWCON);
-   }
+   fimd_channel_win(ctx, win, false);

fimd_shadow_protect_win(ctx, win, false);

-- 
1.9.0

[PATCH 1/7] drm/exynos: fimd: remove unnecessary waiting vblank routine

[YoungJun Cho]

The exynos_drm_crtc_dpms() waits until pended page flip
queue is empty, calls the drm_vblank_off() then calls
manager->ops->dpms() when mode is DRM_MODE_DPMS_OFF.
The fimd_dpms() is one of manager->ops->dpms()s and
finally calls fimd_window_suspend().
But there is no active window and vblank is already off
when it is called.
So addtional waiting vblank is not necessary any more.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 085b066..8b31b7e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -803,7 +803,6 @@ static void fimd_window_suspend(struct exynos_drm_manager 
*mgr)
if (win_data->enabled)
fimd_win_disable(mgr, i);
}
-   fimd_wait_for_vblank(mgr);
 }

 static void fimd_window_resume(struct exynos_drm_manager *mgr)
-- 
1.9.0

[PATCH 0/7] drm/exynos: modify LCD I80 interface display

[YoungJun Cho]

Hi,

This series modifies LCD I80 interface display for Exynos DRM driver.

This is based on exynos-drm-next branch.

Patches 1 and 2 modify trivial things.

Patch 3 changes ideal clock calculation standard as H/W guideline.

Patch 4 moves vblank handler in TE handler to privide proper VBLANK information.

Patch 5 arranges I80 interface interrupt configuration like RGB interface.

Patches 6 and 7 prevent showing the command mode panel garbage GRAM screen data.

I welcome any comments.

Thank you.
Best regards YJ

YoungJun Cho (7):
  drm/exynos: fimd: remove unnecessary waiting vblank routine
  drm/exynos: fimd: add fimd_channel_win() to clean up code
  drm/exynos: fimd: modify vclk calculation for I80 i/f
  drm/exynos: fimd: move handle vblank position in TE handler
  drm/exynos: fimd: modify I80 i/f interrupt relevant routine
  drm/exynos: dsi: move TE irq handler registration position
  drm/exynos: dsi: move DSIM_STATE_ENABLED set position

 drivers/gpu/drm/exynos/exynos_drm_dsi.c  |  24 +++--
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 155 +--
 2 files changed, 98 insertions(+), 81 deletions(-)

-- 
1.9.0

[PATCH] drm/exynos: dsi: fix exynos_dsi_set_pll() wrong return value

[YoungJun Cho]

The type of this function is unsigned long, and it is expected
to return proper fout value or zero if something is wrong.
So this patch fixes wrong return value for error cases.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 86aebd8..061017b 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -421,7 +421,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi 
*dsi,
if (!fout) {
dev_err(dsi->dev,
"failed to find PLL PMS for requested frequency\n");
-   return -EFAULT;
+   return 0;
}
dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);

@@ -453,7 +453,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi 
*dsi,
do {
if (timeout-- == 0) {
dev_err(dsi->dev, "PLL failed to stabilize\n");
-   return -EFAULT;
+   return 0;
}
reg = readl(dsi->reg_base + DSIM_STATUS_REG);
} while ((reg & DSIM_PLL_STABLE) == 0);
-- 
1.9.0

[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

[YoungJun Cho]

Hi Inki, Andrzej

On 08/11/2014 04:09 PM, Inki Dae wrote:
> On 2014? 08? 08? 18:40, Andrzej Hajda wrote:
>> On 08/08/2014 11:02 AM, Andrzej Hajda wrote:
>>> On 08/08/2014 09:37 AM, Inki Dae wrote:
 On 2014? 08? 08? 16:03, Thierry Reding wrote:
> On Fri, Aug 08, 2014 at 10:45:47AM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 22:55, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 10:39:29PM +0900, Inki Dae wrote:
 On 2014? 08? 07? 22:17, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 10:05:44PM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 20:09, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 07:49:03PM +0900, Inki Dae wrote:
 On 2014? 08? 07? 18:09, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 04:51:18PM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 15:58, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote:
 2014-08-06 16:43 GMT+09:00 Thierry Reding >>> gmail.com>:
> [...]
> As far as I can tell non-continuous mode simply means that 
> the host can
> turn off the HS clock after a high-speed transmission. I 
> think Andrzej
> mentioned this already in another subthread, but this is an 
> optional
> mode that peripherals can support if they have extra 
> circuitry that
> provides an internal clock. Peripherals that don't have such 
> circuitry
> may rely on the HS clock to perform in between transmissions 
> and
> therefore require the HS clock to be always on (continuous 
> mode). That's
> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises 
> that the
> peripheral supports non-continuous mode and therefore the 
> host can turn
> the HS clock off after high-speed transmissions.
 What I don't make sure is this sentence. With
 MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible 
 operations.
 One is,
 1. host controller will generates signals if a bit of a 
 register
 related to non-contiguous clock mode is set or unset.
 2. And then video data is transmitted to panel in HS mode.
 3. And then D-PHY detects LP-11 signal (positive and negative 
 lane all
 are high).
 4. And then D-PHY disables HS clock of host controller.
 5. At this time, operation mode of host controller becomes LPM.

 Other is,
 1. host controller will generates signals if a bit of a 
 register
 related to non-contiguous clock mode is set or unset.
 2. And then D-PHY detects LP-11 signal (positive and negative 
 lane all
 are high).
 3. And then video data is transmitted to panel in LPM.
 4. At this time, operation mode of host controller becomes LPM.

 It seems that you says latter case.
>>> No. High speed clock and low power mode are orthogonal. 
>>> Non-continuous
>>> mode simply means that the clock lane enters LP-11 between HS
>>> transmissions (see 5.6 "Clock Management" of the DSI 
>>> specification).
>>>
>> It seems that clock lane enters LP-11 regardless of HS clock 
>> enabled if
>> non-continous mode is used. Right?
> No, I think as long as HS clock is enabled the clock lane won't 
> enter
> LP-11. Non-continuous mode means that the controller can disable 
> the HS
> clock between HS transmissions. So in non-continuous mode the 
> clock lane
> can enter LP-11 because the controller disables the HS clock.
 It makes me a little bit confusing. You said "if HS clock is 
 enabled,
 the the clock lane won't enter LP-11" But you said again "the 
 clock lane
 can enter LP-11 because the controller disables the HS clock" What 
 is
 the meaning?
>>> It means that if the HS clock is enabled, then the clock lane is 
>>> not in
>>> LP-11. When the HS clock stops, then the clock lane enters LP-11.
>>>
> In continuous mode, then the clock will never be disabled, hence 
> the
> clock lane will never enter LP-11.
>
>> And also it seems that non-continous mode is different from LPM 
>> at all
>>

[RFC PATCH] drm/mipi-dsi: add some generic functions for DCS

[YoungJun Cho]

This patch adds some generic functions for DCS like below
to standize on common APIs rather than per-driver
implementations.

mipi_dcs_enter_sleep_mode() / mipi_dcs_exit_sleep_mode()
- These are required to disable / enable all blocks inside
  the display module.

mipi_dcs_set_display_off() / mipi_dcs_set_display_on()
- These are required to stop / start displaying the image
  data on the display device.

mipi_dcs_set_tear_off() / mipi_dcs_set_tear_on()
- These are required to turn off or on the display module's
  TE output signal on the TE signal line.

mipi_dsi_set_maximum_return_packet_size()
- Although it is not related with DCS, it is required before
  using mipi_dsi_dcs_read() to specify the maximum size of
  the payload in a long packet.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/drm_mipi_dsi.c | 113 +
 include/drm/drm_mipi_dsi.h |  14 +
 2 files changed, 127 insertions(+)

diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
index 6b2bbda..ba506d7 100644
--- a/drivers/gpu/drm/drm_mipi_dsi.c
+++ b/drivers/gpu/drm/drm_mipi_dsi.c
@@ -269,6 +269,119 @@ ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, 
unsigned int channel,
 }
 EXPORT_SYMBOL(mipi_dsi_dcs_read);

+/**
+ * mipi_dsi_set_maximum_return_packet_size
+ * - specify the maximum size of the payload in a Long packet transmitted from
+ *   peripheral back to the host processor
+ * @dsi: DSI peripheral device
+ * @size: the maximum size of the payload
+ */
+int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
+   u16 size)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+   struct mipi_dsi_msg msg;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   memset(&msg, 0, sizeof(msg));
+   msg.channel = dsi->channel;
+   msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE;
+   msg.tx_len = sizeof(size);
+   msg.tx_buf = (const void *)(&size);
+
+   return ops->transfer(dsi->host, &msg);
+}
+EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
+
+/**
+ * mipi_dcs_enter_sleep_mode - disable all unnecessary blocks inside the 
display
+ * module except interface communication
+ * @dsi: DSI peripheral device
+ */
+int mipi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi)
+{
+   u8 data = MIPI_DCS_ENTER_SLEEP_MODE;
+
+   return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
+   sizeof(data));
+}
+EXPORT_SYMBOL(mipi_dcs_enter_sleep_mode);
+
+/**
+ * mipi_dcs_exit_sleep_mode - enable all blocks inside the display module
+ * @dsi: DSI peripheral device
+ */
+int mipi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi)
+{
+   u8 data = MIPI_DCS_EXIT_SLEEP_MODE;
+
+   return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
+   sizeof(data));
+}
+EXPORT_SYMBOL(mipi_dcs_exit_sleep_mode);
+
+/**
+ * mipi_dcs_set_display_off - stop displaying the image data on the display 
device
+ * @dsi: DSI peripheral device
+ */
+int mipi_dcs_set_display_off(struct mipi_dsi_device *dsi)
+{
+   u8 data = MIPI_DCS_SET_DISPLAY_OFF;
+
+   return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
+   sizeof(data));
+}
+EXPORT_SYMBOL(mipi_dcs_set_display_off);
+
+/**
+ * mipi_dcs_set_display_on - start displaying the image data on the display 
device
+ * @dsi: DSI peripheral device
+ */
+int mipi_dcs_set_display_on(struct mipi_dsi_device *dsi)
+{
+   u8 data = MIPI_DCS_SET_DISPLAY_ON;
+
+   return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
+   sizeof(data));
+}
+EXPORT_SYMBOL(mipi_dcs_set_display_on);
+
+/**
+ * mipi_dcs_set_tear_off - turn off the display module's Tearing Effect output
+ * signal on the TE signal line
+ * @dsi: DSI peripheral device
+ */
+int mipi_dcs_set_tear_off(struct mipi_dsi_device *dsi)
+{
+   u8 data = MIPI_DCS_SET_TEAR_OFF;
+
+   return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
+   sizeof(data));
+}
+EXPORT_SYMBOL(mipi_dcs_set_tear_off);
+
+/**
+ * mipi_dcs_set_tear_on - turn on the display module's Tearing Effect output
+ *signal on the TE signal line.
+ * @dsi: DSI peripheral device
+ * @mode: the Tearing Effect output line mode
+ *  - MIPI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking
+ *   information only
+ *  - MIPI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both
+ * V-Blanking and H-Blanking information
+ */
+int mipi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
+ 

[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

Hi Thierry,

Sorry for late reply.

I implemented common DSI helper functions and tested in s6e3fa0 panel
(I should test with other panels).

The helper function prototypes are like below:

int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
u16 size);

int mipi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi);
int mipi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi);
int mipi_dcs_set_display_off(struct mipi_dsi_device *dsi);
int mipi_dcs_set_display_on(struct mipi_dsi_device *dsi);
int mipi_dcs_set_tear_off(struct mipi_dsi_device *dsi);

enum mipi_dcs_tear_mode {
MIPI_DCS_TEAR_MODE_VBLANK,
MIPI_DCS_TEAR_MODE_HVBLANK,
};

int mipi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
enum mipi_dcs_tear_mode mode);

Last time you recommended to implement mipi_dcs_set_tear_on() unrelated 
with mipi_dsi_dcs_write().
As you know, the only difference between mipi_dcs_xxx() except 
mipi_dcs_set_tear_on() is data(dcs command).
So I think it's better to use mipi_dsi_dcs_write() instead.
Do you agree?

And one more thing.
 From my point of view there is no initialization sequence in simple 
panel driver, so this and s6e8aa0 panel couldn't use that interface.
The s6e3fa0 and s6e8aa0 are very similar so I think it is possible to 
combine together like simple panel driver.
I want to ask you for advice on this.

Thank you.
Best regards YJ

On 07/22/2014 12:56 PM, YoungJun Cho wrote:
> Hi Thierry,
>
> Now I understand what you mean.
>
> I'll implement common DSI helper functions.
>
> Thank you.
> Best regards YJ
>
> On 07/21/2014 06:35 PM, Thierry Reding wrote:
>> On Fri, Jul 18, 2014 at 10:49:35AM +0900, YoungJun Cho wrote:
>>> Hi Thierry,
>>>
>>> Thank you a lot for kind comments.
>>>
>>> On 07/17/2014 07:36 PM, Thierry Reding wrote:
>>>> On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
>> [...]
>>>>> diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
>>>>> b/drivers/gpu/drm/panel/panel-s6e3fa0.c
>> [...]
>>>>> +static void s6e3fa0_set_maximum_return_packet_size(struct s6e3fa0
>>>>> *ctx,
>>>>> +unsigned int size)
>>>>> +{
>>>>> +struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
>>>>> +const struct mipi_dsi_host_ops *ops = dsi->host->ops;
>>>>> +
>>>>> +if (ops && ops->transfer) {
>>>>> +unsigned char buf[] = {size, 0};
>>>>> +struct mipi_dsi_msg msg = {
>>>>> +.channel = dsi->channel,
>>>>> +.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
>>>>> +.tx_len = sizeof(buf),
>>>>> +.tx_buf = buf
>>>>> +};
>>>>> +
>>>>> +ops->transfer(dsi->host, &msg);
>>>>> +}
>>>>> +}
>>>>
>>>> The Set Maximum Return Packet Size command is a standard command, so
>>>> please turn that into a generic function exposed by the DSI core.
>>>>
>>>
>>> For this and below standard DCS commands, you want to use generic
>>> functions,
>>> but I have no idea for that.
>>> Could you explain more detail?
>>
>> The goal should be to make these standard DCS commands available to all
>> DSI peripherals, so the implementation should look something like this:
>>
>> static int mipi_dsi_set_maximum_return_packet_size(struct
>> mipi_dsi_device *dsi,
>>u16 size)
>> {
>> struct mipi_dsi_msg msg;
>>
>> if (!dsi->ops || !dsi->ops->transfer)
>> return -ENOSYS;
>>
>> memset(&msg, 0, sizeof(msg));
>> msg.channel = dsi->channel;
>> msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE;
>> msg.tx_len = sizeof(size);
>> msg.tx_buf = &size;
>>
>> return dsi->ops->transfer(dsi->host, &msg);
>> }
>>
>> The above is somewhat special, since it isn't DCS. For DCS I'd suggest a
>> common prefix, like so:
>>
>> enum mipi_dcs_tear_mode {
>> MIPI_DCS_TEAR_VBLANK,
>> MIPI_DCS_TEAR_BLANK,
>> };
>>
>> static int mipi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
>> enum mipi_dcs_tear_mode mode)
>> {
>> u8 data[2] = { MIPI_DSI_DCS_SET_TEAR_ON, mode };
>> struct mipi_dsi_msg msg;
>>
>> if (!dsi->ops || !dsi->ops->transfer)
>> return -ENOSYS;
>>
>> memset(&msg, 0, sizeof(msg));
>> msg.channel = dsi->channel;
>> msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
>> msg.tx_len = sizeof(data);
>> msg.tx_buf = data;
>>
>> return dsi->ops->transfer(dsi->host, &msg);
>> }
>>
>> Thierry
>>
>
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> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>

[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

[YoungJun Cho]

Hi Andrzej,

On 07/29/2014 01:09 AM, Andrzej Hajda wrote:
> On 07/28/2014 04:00 AM, Inki Dae wrote:
>> This patch adds below two flags for LPM transfer, and it attaches LPM flags
>> to a msg in accordance with master's mode_flags set by LCD Panel driver.
>>
>> MIPI_DSI_MODE_CMD_LPM
>> - If this flag is set by Panel driver, MIPI-DSI controller will tranfer
>> command data to Panel device in Low Power Mode.
>
> What do you mean by command data? It could be:
> - all transfer in command mode of operations,
> - transfer initialized by the driver by writing to DSIM registers.

The 2nd one.

>
>>
>> MIPI_DSI_MODE_VIDEO_LPM
>> - If this flag is set by Panel driver, MIPI-DSI controller will tranfer
>> image data to Panel device in Low Power Mode.
>
> What is the meaning of this flag in case of command mode of operation?

I'm also not sure that there is a case to transfer image data in Low 
Power Mode, but this flag is not related with 'command mode' only.
Inki may consider generic condition.

>
> Maybe it would be better to create flags based on source of data/FIFOs:
> - commands send by SFR registers,
> - commands generated from data sent from Display Controller.
>
>
>>
>> And above two flags can be combined together to transfer command and video
>> data to Panel device.
>>
>> MIPI DSI spec says,
>>   "the host processor controls the desired mode of clock operation.
>>Host protocol and applications control Clock Lane operating mode
>>(High Speed or Low Power mode). System designers are responsible
>>for understanding the clock requirements for peripherals attached
>>to DSI and controlling clock behavior in accordance with those
>>requirements."
>>
>> Some LCD Panel devices, nt35502a, would need LPM transfer support
>> because they should receive some initial commands with LPM by default
>> hardware setting.
>
>
> Is this requirement for initial commands, or for all commands.
> Btw what is the mode of operation of nt35502a? What flags do you need
> for it?
>

The nt35502a panel is video(RGB) mode panel and it requires low power 
mode for initial commands, which means to initialize nt35502a panel, the 
initial commands are transferred by LP mode(Not HS mode).
And after initialization, its other features like gamma control or etc 
could be controlled in HS mode.

Thank you.
Best regards YJ

>
>
>>
>> Changelog v2: just add more descriptions.
>>
>> Signed-off-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   drivers/gpu/drm/drm_mipi_dsi.c |3 +++
>>   include/drm/drm_mipi_dsi.h |4 
>>   2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
>> index e633df2..6b2bbda 100644
>> --- a/drivers/gpu/drm/drm_mipi_dsi.c
>> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
>> @@ -232,6 +232,9 @@ int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, 
>> unsigned int channel,
>>  break;
>>  }
>>
>> +if (dsi->mode_flags & MIPI_DSI_MODE_CMD_LPM)
>> +msg.flags = MIPI_DSI_MSG_USE_LPM;
>> +
>>  return ops->transfer(dsi->host, &msg);
>>   }
>
> Shouldn't this be also the same for dcs read?
>
> Anyway I think check in the DSIM should be used instead, as panel driver
> can issue other dsi transfers without MIPI_DSI_MSG_USE_LPM flag set.
>
> Regards
> Andrzej
>
>
>>   EXPORT_SYMBOL(mipi_dsi_dcs_write);
>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>> index 944f33f..1c41e49 100644
>> --- a/include/drm/drm_mipi_dsi.h
>> +++ b/include/drm/drm_mipi_dsi.h
>> @@ -94,6 +94,10 @@ void mipi_dsi_host_unregister(struct mipi_dsi_host *host);
>>   #define MIPI_DSI_MODE_VSYNC_FLUSH  BIT(8)
>>   /* disable EoT packets in HS mode */
>>   #define MIPI_DSI_MODE_EOT_PACKET   BIT(9)
>> +/* command low power mode */
>> +#define MIPI_DSI_MODE_CMD_LPM   BIT(10)
>> +/* video low power mode */
>> +#define MIPI_DSI_MODE_VIDEO_LPM BIT(11)
>>
>>   enum mipi_dsi_pixel_format {
>>  MIPI_DSI_FMT_RGB888,
>>
>
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> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

Hi Varka,

On 07/22/2014 08:14 PM, Varka Bhadram wrote:
> On 07/22/2014 04:40 PM, YoungJun Cho wrote:
>> Hi Varka,
>>
>> This irq handler should be registered in attach() and unregistered in
>> detach().
>>
>> The devm_* APIs are released(freed) in remove(), right?
>>
>> Logically the panel could be attached and detached several times after
>> dsi is probed and not removed.
>> So I don't use devm_* APIs.
>
> You meant to say that in-case of GPIOs also you are following the same
> thing ..?
>
> Means requesting the GPIOs and Releasing several times ..?
>

Yes, this TE gpio is came from panel.
So it should be refresh whenever a (new) panel is attached.

Thank you.
Best regards YJ

>>
>>>
>>
>
>

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

Hi Varka,

This irq handler should be registered in attach() and unregistered in 
detach().

The devm_* APIs are released(freed) in remove(), right?

Logically the panel could be attached and detached several times after 
dsi is probed and not removed.
So I don't use devm_* APIs.

Thank you.
Best regards YJ

On 07/22/2014 07:57 PM, Varka Bhadram wrote:
> On 07/22/2014 04:19 PM, YoungJun Cho wrote:
>
> (...)
>
>> +ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
>
> devm_* APIs..?
>
>> +if (ret) {
>> +dev_err(dsi->dev, "gpio request failed with %d\n", ret);
>> +goto out;
>> +}
>> +
>> +/*
>> + * This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
>> + * calls drm_panel_init() first then calls mipi_dsi_attach() in
>> probe().
>> + * It means that te_gpio is invalid when exynos_dsi_enable_irq() is
>> + * called by drm_panel_init() before panel is attached.
>> + */
>> +ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
>> +exynos_dsi_te_irq_handler, NULL,
>> +IRQF_TRIGGER_RISING, "TE", dsi);
>
> why don't we use devm_request_threaded_irq()..?
>
>

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

This is a temporary solution and should be made by more
generic way.

To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 97 -
 1 file changed, 95 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..3adad44 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
 #include 

 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -24,6 +26,7 @@
 #include 
 #include 

+#include "exynos_drm_crtc.h"
 #include "exynos_drm_drv.h"

 /* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+   int te_gpio;

u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
 }

+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+   struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+   struct drm_encoder *encoder = dsi->encoder;
+
+   if (dsi->state & DSIM_STATE_ENABLED)
+   exynos_drm_crtc_te_handler(encoder->crtc);
+
+   return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+   enable_irq(dsi->irq);
+
+   if (gpio_is_valid(dsi->te_gpio))
+   enable_irq(gpio_to_irq(dsi->te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+   if (gpio_is_valid(dsi->te_gpio))
+   disable_irq(gpio_to_irq(dsi->te_gpio));
+
+   disable_irq(dsi->irq);
+}
+
 static int exynos_dsi_init(struct exynos_dsi *dsi)
 {
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
-   enable_irq(dsi->irq);
+   exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);

return 0;
 }

+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+   int ret;
+
+   dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
+   if (!gpio_is_valid(dsi->te_gpio)) {
+   dev_err(dsi->dev, "no te-gpios specified\n");
+   ret = dsi->te_gpio;
+   goto out;
+   }
+
+   ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
+   if (ret) {
+   dev_err(dsi->dev, "gpio request failed with %d\n", ret);
+   goto out;
+   }
+
+   /*
+* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
+* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
+* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
+* called by drm_panel_init() before panel is attached.
+*/
+   ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
+   exynos_dsi_te_irq_handler, NULL,
+   IRQF_TRIGGER_RISING, "TE", dsi);
+   if (ret) {
+   dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
+   gpio_free(dsi->te_gpio);
+   goto out;
+   }
+
+out:
+   return ret;
+}
+
+static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
+{
+   if (gpio_is_valid(dsi->te_gpio)) {
+   free_irq(gpio_to_irq(dsi->te_gpio), dsi);
+   gpio_free(dsi->te_gpio);
+   dsi->te_gpio = -ENOENT;
+   }
+}
+
 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
  struct mipi_dsi_device *device)
 {
@@ -978,6 +1054,18 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
if (dsi->connector.dev)
drm_helper_hpd_irq_event(dsi->connector.dev);

+   /*
+* This is a temporary solution and should be made by more generic way.
+*
+* If attached panel device is for command mode one, dsi should register
+* TE interrupt handler.
+*/
+   if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
+   int ret = exynos_dsi_register_te_irq(dsi);
+   if (ret)
+   return ret;
+   }
+
return 0;
 }

@@ -986,6 +1074,8 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host 
*host,
 {
struct exynos_dsi *dsi = host_to_dsi(host);

+   exynos_ds

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

Hi Andrzej,

On 07/22/2014 07:12 PM, Andrzej Hajda wrote:
> On 07/22/2014 03:23 AM, Inki Dae wrote:
>> On 2014? 07? 21? 23:01, Andrzej Hajda wrote:
>>> On 07/17/2014 11:01 AM, YoungJun Cho wrote:
>>>> To support LCD I80 interface, the DSI host should register
>>>> TE interrupt handler from the TE GPIO of attached panel.
>>>> So the panel generates a tearing effect synchronization signal
>>>> then the DSI host calls the CRTC device manager to trigger
>>>> to transfer video image.
>>>>
>>> This whole patch seems to be a hack.
>>>
>>> I think it is not a good idea to parse property of one device by another
>>> device's driver.
>>>
>>> Especially here TE GPIO belongs to the panel. The panel driver should
>>> know how to configure it and how to use it or not. The panel driver will
>>> generate TE signal based on this GPIO, DSI/BTA mechanism or any other
>>> mechanism provided by the panel.
>>> TE signal should be delivered to the display controller. The only role
>>> of DSIM here is that it is between the panel and the display controller
>>> so it should be used to route this signal to DC.
>>>
>>> According to specs TE signal should/can be generated by DBI and DSI
>>> command mode panels, so its handling should be more generic, not Exynos
>>> specific.
>>>
>> Right. However, it seems that there are no much users using command mode
>> panel so we would need more times to discuss the generic way. I think we
>> can have this feature in specific to Exynos drm - it doesn't affect
>> other SoC -.  Actually, I know OMAP people handle this feature in a way
>> specific to OMAP SoC. If other users need more generic way to this
>> feature then we could have a discussion about the generic way at that time.
>>
>> That is why Mr. Cho implemented TE feature like this. Do you have more
>> good idea? I wish the idea would be specific so that Mr. Cho can
>> implement it.
>>
>> P.s. Thierry already opposed the use of mipi_dsi_host_ops, I agree with
>> him. And also it seems not good to use crtc and encoder/connector
>> because these frameworks are common to all architecture including x86 so
>> other architectures wouldn't need TE feature.
>
> The good thing is that DT bindings in this case are OK, TE GPIO is in
> panel node.
> Maybe we can leave it this way for now, but at least lets add a comment to
> the code describing that it is temporary solution and should be make
> more generic in the future.
>

Okay, I'll leave this comment at exynos_dsi_host_attach() before current 
exynos_dsi_register_te_irq() relevant comment.

Thank you.
Best regards YJ

> Regards
> Andrzej
>>
>> Thanks,
>> Inki Dae
>>
>>> Regards
>>> Andrzej
>>>
>>>> Signed-off-by: YoungJun Cho 
>>>> Acked-by: Inki Dae 
>>>> Acked-by: Kyungmin Park 
>>>> ---
>>>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 
>>>> -
>>>>   1 file changed, 93 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>>>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>> index 58bfb2a..4997bfe 100644
>>>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>> @@ -16,7 +16,9 @@
>>>>   #include 
>>>>
>>>>   #include 
>>>> +#include 
>>>>   #include 
>>>> +#include 
>>>>   #include 
>>>>   #include 
>>>>   #include 
>>>> @@ -24,6 +26,7 @@
>>>>   #include 
>>>>   #include 
>>>>
>>>> +#include "exynos_drm_crtc.h"
>>>>   #include "exynos_drm_drv.h"
>>>>
>>>>   /* returns true iff both arguments logically differs */
>>>> @@ -247,6 +250,7 @@ struct exynos_dsi {
>>>>struct clk *bus_clk;
>>>>struct regulator_bulk_data supplies[2];
>>>>int irq;
>>>> +  int te_gpio;
>>>>
>>>>u32 pll_clk_rate;
>>>>u32 burst_clk_rate;
>>>> @@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void 
>>>> *dev_id)
>>>>return IRQ_HANDLED;
>>>>   }
>>>>
>>>> +static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
>>>> +{
>>>> +  struct exynos_dsi *dsi = 

[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

Hi Thierry,

On 07/22/2014 04:49 PM, Thierry Reding wrote:
> On Tue, Jul 22, 2014 at 12:41:21PM +0900, YoungJun Cho wrote:
>> On 07/21/2014 08:18 PM, Andrzej Hajda wrote:
>>> On 07/21/2014 11:19 AM, Thierry Reding wrote:
>>>> On Mon, Jul 21, 2014 at 10:56:08AM +0200, Andrzej Hajda wrote:
>>>>> On 07/18/2014 03:49 AM, YoungJun Cho wrote:
>>>>>> On 07/17/2014 07:36 PM, Thierry Reding wrote:
>>>>>>> On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
> [...]
>>>>>>>> +static void s6e3fa0_read_mtp_id(struct s6e3fa0 *ctx)
>>>>>>>> +{
>>>>>>>> +  unsigned char id[MTP_ID_LEN];
>>>>>>>> +  int ret;
>>>>>>>> +
>>>>>>>> +  s6e3fa0_set_maximum_return_packet_size(ctx, MTP_ID_LEN);
>>>>>>>> +  ret = s6e3fa0_dcs_read(ctx, MIPI_DCS_GET_DISPLAY_ID, id, 
>>>>>>>> MTP_ID_LEN);
>>>>>>> This also looks like a standard DCS command. I can't find it in either
>>>>>>> v1.01 nor v1.02 of the specification, though. Do you know where it's
>>>>>>> specified?
>>>>>>>
>>>>>> Yes, I also can't find it in DCS specification and there is no special
>>>>>> description in panel datasheet.
>>>>>> But as it is declared in "include/video/mipi_display.h", so I think it
>>>>>> is a standard one.
>>>>>
>>>>> On page 9 of the "Introduction of MIPI by Renesas" [2] there is info
>>>>> it is a part of "Nokia I/F command list", I guess it is kind of alpha
>>>>> version of MIPI DCS.
>>>>>
>>>>> [2]: http://wenku.baidu.com/view/658fab68af1ffc4ffe47acbe.html
>>>>
>>>> That link is the only one which contains "Nokia I/F command list" on the
>>>> internet (that is, according to Google). But since this is already part
>>>> of the mipi_display.h header file we may as well use it.
>>>>
>>>> I wonder if perhaps the READ_DDB_START and READ_DDB_CONTINUE commands
>>>> could be used as a replacement for this display ID.
>>>>
>>
>> There is a simple description for "Read DDB Start(A1H)" like below.
>> - This command returns supplier identification and display module model /
>> revision information.
>> - NOTE: This information is not the same what Read IDs(04H) command is
>> returning.
>>
>> For reference, Read IDs(04H) description is like below.
>> - This read command returns 24-bit display identification information.
>> - The first read byte identifies the OLED module's manufacturer.
>> - The Second read byte is used to track the OLED module/driver version.
>> - The third read byte identifies the OLED module/driver.
>
> Okay, that explains things a little better. Can you point me to the
> document that this is from?

Sorry, I forgot to write specification name.
This specification is s6e3fa0 data sheet and it is confidential.
So I quoted only that portion.

>
> But what I was trying to say is that if the Read IDs command isn't an
> official DCS command, maybe it would be a better idea to use the DDB
> instead. I assume that even if it isn't the same information it would
> at least be a superset and therefore a suitable replacement.

This panel has several versions and each should set specific tuning 
value especially for AID, ELVSS and etc.
(Current is suitable for id[2] == 0x23).

I'll check READ_DDB_START & READ_DDB_CONTINUE result and try to use them 
if it is possible.

Thank you.
Best regards YJ

>
> Thierry
>

[PATCH 1/4] drm/dsi: Make mipi_dsi_dcs_write() return ssize_t

[YoungJun Cho]

Hi,

On 07/22/2014 04:28 PM, Andrzej Hajda wrote:
> Hi Thierry,
>
> Thanks for the patch.
>
> On 07/22/2014 09:12 AM, Thierry Reding wrote:
>> From: Thierry Reding 
>>
>> This function returns the value of the struct mipi_dsi_host_ops'
>> .transfer() so make sure the return types are consistent.
>>
>> Signed-off-by: Thierry Reding 
>
> Acked-by: Andrzej Hajda 
> --
> Regards
> Andrzej
>> ---
>>   drivers/gpu/drm/drm_mipi_dsi.c| 4 ++--
>>   drivers/gpu/drm/panel/panel-s6e8aa0.c | 4 ++--
>>   include/drm/drm_mipi_dsi.h| 4 ++--
>>   3 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
>> index e633df2f68d8..6d2fd2077dae 100644
>> --- a/drivers/gpu/drm/drm_mipi_dsi.c
>> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
>> @@ -205,8 +205,8 @@ EXPORT_SYMBOL(mipi_dsi_detach);
>>* @data: pointer to the command followed by parameters
>>* @len: length of @data
>>*/
>> -int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int channel,
>> -   const void *data, size_t len)
>> +ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int 
>> channel,
>> +   const void *data, size_t len)
>>   {
>>  const struct mipi_dsi_host_ops *ops = dsi->host->ops;
>>  struct mipi_dsi_msg msg = {
>> diff --git a/drivers/gpu/drm/panel/panel-s6e8aa0.c 
>> b/drivers/gpu/drm/panel/panel-s6e8aa0.c
>> index 06e57a26db7a..beb43492b649 100644
>> --- a/drivers/gpu/drm/panel/panel-s6e8aa0.c
>> +++ b/drivers/gpu/drm/panel/panel-s6e8aa0.c
>> @@ -133,14 +133,14 @@ static int s6e8aa0_clear_error(struct s6e8aa0 *ctx)
>>   static void s6e8aa0_dcs_write(struct s6e8aa0 *ctx, const void *data, 
>> size_t len)
>>   {
>>  struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
>> -int ret;
>> +ssize_t ret;
>>
>>  if (ctx->error < 0)
>>  return;
>>
>>  ret = mipi_dsi_dcs_write(dsi, dsi->channel, data, len);
>>  if (ret < 0) {
>> -dev_err(ctx->dev, "error %d writing dcs seq: %*ph\n", ret, len,
>> +dev_err(ctx->dev, "error %zd writing dcs seq: %*ph\n", ret, len,
>>  data);
>>  ctx->error = ret;

One more thing!
This 'ctx->error' type is 'int'. So it should be changed from int to 
ssize_t in struct s6e8aa0.

Thank you.
Best regards YJ

>>  }
>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>> index efa1b552adc5..4b0112781910 100644
>> --- a/include/drm/drm_mipi_dsi.h
>> +++ b/include/drm/drm_mipi_dsi.h
>> @@ -127,8 +127,8 @@ struct mipi_dsi_device {
>>
>>   int mipi_dsi_attach(struct mipi_dsi_device *dsi);
>>   int mipi_dsi_detach(struct mipi_dsi_device *dsi);
>> -int mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int channel,
>> -   const void *data, size_t len);
>> +ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, unsigned int 
>> channel,
>> +   const void *data, size_t len);
>>   ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, unsigned int 
>> channel,
>>u8 cmd, void *data, size_t len);
>>
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>

[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

Hi Thierry,

Now I understand what you mean.

I'll implement common DSI helper functions.

Thank you.
Best regards YJ

On 07/21/2014 06:35 PM, Thierry Reding wrote:
> On Fri, Jul 18, 2014 at 10:49:35AM +0900, YoungJun Cho wrote:
>> Hi Thierry,
>>
>> Thank you a lot for kind comments.
>>
>> On 07/17/2014 07:36 PM, Thierry Reding wrote:
>>> On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
> [...]
>>>> diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
>>>> b/drivers/gpu/drm/panel/panel-s6e3fa0.c
> [...]
>>>> +static void s6e3fa0_set_maximum_return_packet_size(struct s6e3fa0 *ctx,
>>>> +  unsigned int size)
>>>> +{
>>>> +  struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
>>>> +  const struct mipi_dsi_host_ops *ops = dsi->host->ops;
>>>> +
>>>> +  if (ops && ops->transfer) {
>>>> +  unsigned char buf[] = {size, 0};
>>>> +  struct mipi_dsi_msg msg = {
>>>> +  .channel = dsi->channel,
>>>> +  .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
>>>> +  .tx_len = sizeof(buf),
>>>> +  .tx_buf = buf
>>>> +  };
>>>> +
>>>> +  ops->transfer(dsi->host, &msg);
>>>> +  }
>>>> +}
>>>
>>> The Set Maximum Return Packet Size command is a standard command, so
>>> please turn that into a generic function exposed by the DSI core.
>>>
>>
>> For this and below standard DCS commands, you want to use generic functions,
>> but I have no idea for that.
>> Could you explain more detail?
>
> The goal should be to make these standard DCS commands available to all
> DSI peripherals, so the implementation should look something like this:
>
> static int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device 
> *dsi,
>  u16 size)
> {
>   struct mipi_dsi_msg msg;
>
>   if (!dsi->ops || !dsi->ops->transfer)
>   return -ENOSYS;
>
>   memset(&msg, 0, sizeof(msg));
>   msg.channel = dsi->channel;
>   msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE;
>   msg.tx_len = sizeof(size);
>   msg.tx_buf = &size;
>
>   return dsi->ops->transfer(dsi->host, &msg);
> }
>
> The above is somewhat special, since it isn't DCS. For DCS I'd suggest a
> common prefix, like so:
>
> enum mipi_dcs_tear_mode {
>   MIPI_DCS_TEAR_VBLANK,
>   MIPI_DCS_TEAR_BLANK,
> };
>
> static int mipi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
>   enum mipi_dcs_tear_mode mode)
> {
>   u8 data[2] = { MIPI_DSI_DCS_SET_TEAR_ON, mode };
>   struct mipi_dsi_msg msg;
>
>   if (!dsi->ops || !dsi->ops->transfer)
>   return -ENOSYS;
>
>   memset(&msg, 0, sizeof(msg));
>   msg.channel = dsi->channel;
>   msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
>   msg.tx_len = sizeof(data);
>   msg.tx_buf = data;
>
>   return dsi->ops->transfer(dsi->host, &msg);
> }
>
> Thierry
>

[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

Hi,

On 07/21/2014 08:18 PM, Andrzej Hajda wrote:
> On 07/21/2014 11:19 AM, Thierry Reding wrote:
>> On Mon, Jul 21, 2014 at 10:56:08AM +0200, Andrzej Hajda wrote:
>>> On 07/18/2014 03:49 AM, YoungJun Cho wrote:
>>>> Hi Thierry,
>>>>
>>>> Thank you a lot for kind comments.
>>>>
>>>> On 07/17/2014 07:36 PM, Thierry Reding wrote:
>>>>> On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
>>>>> [...]
>>>>>> diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
>>>>>> b/drivers/gpu/drm/panel/panel-s6e3fa0.c
>>>>> [...]
>>>>>> +/* Manufacturer Command Set */
>>>>>> +#define MCS_GLOBAL_PARAMETER0xb0
>>>>>> +#define MCS_AID 0xb2
>>>>>> +#define MCS_ELVSSOPT0xb6
>>>>>> +#define MCS_TEMPERATURE_SET 0xb8
>>>>>> +#define MCS_PENTILE_CTRL0xc0
>>>>>> +#define MCS_GAMMA_MODE  0xca
>>>>>> +#define MCS_VDDM0xd7
>>>>>> +#define MCS_ALS 0xe3
>>>>>> +#define MCS_ERR_FG  0xed
>>>>>> +#define MCS_KEY_LEV10xf0
>>>>>> +#define MCS_GAMMA_UPDATE0xf7
>>>>>> +#define MCS_KEY_LEV20xfc
>>>>>> +#define MCS_RE  0xfe
>>>>>> +#define MCS_TOUT2_HSYNC 0xff
>>>>>> +
>>>>>> +/* Content Adaptive Brightness Control */
>>>>>> +#define DCS_WRITE_CABC  0x55
>>>>> Is this not a manufacturer specific command? I couldn't find it in the
>>>>> DSI or DCS specifications, but it sounds like something standard (also
>>>>> indicated by the DCS_ prefix). Can you point out the specification for
>>>>> this?
>>>>>
>>>> Andrzej commented before and decided it as DCS one because if the value
>>>> is less than 0xb0, it is DCS one and the others are MCS one.
>>>> But still I'm not sure it is correct.
>>> I would not say 'decided'. I have just stated that according to DCS
>>> specification
>>> it should be DCS command (below 0xb0), but it is not present in mipi dcs
>>> specs.
>>> On the other side many panels have it [1]:
>>>
>>> [1]:
>>> https://www.google.com/search?q=%22Write+Content+Adaptive+Brightness+Control%22
>>
>> Yeah, my search yielded similar results. I wonder if this is perhaps
>> part of a draft future specification. I'll try to ask around some more
>> if anybody knows what the status of this is.
>>
>>>>>> +static void s6e3fa0_read_mtp_id(struct s6e3fa0 *ctx)
>>>>>> +{
>>>>>> +unsigned char id[MTP_ID_LEN];
>>>>>> +int ret;
>>>>>> +
>>>>>> +s6e3fa0_set_maximum_return_packet_size(ctx, MTP_ID_LEN);
>>>>>> +ret = s6e3fa0_dcs_read(ctx, MIPI_DCS_GET_DISPLAY_ID, id, 
>>>>>> MTP_ID_LEN);
>>>>> This also looks like a standard DCS command. I can't find it in either
>>>>> v1.01 nor v1.02 of the specification, though. Do you know where it's
>>>>> specified?
>>>>>
>>>> Yes, I also can't find it in DCS specification and there is no special
>>>> description in panel datasheet.
>>>> But as it is declared in "include/video/mipi_display.h", so I think it
>>>> is a standard one.
>>>
>>> On page 9 of the "Introduction of MIPI by Renesas" [2] there is info
>>> it is a part of "Nokia I/F command list", I guess it is kind of alpha
>>> version of MIPI DCS.
>>>
>>> [2]: http://wenku.baidu.com/view/658fab68af1ffc4ffe47acbe.html
>>
>> That link is the only one which contains "Nokia I/F command list" on the
>> internet (that is, according to Google). But since this is already part
>> of the mipi_display.h header file we may as well use it.
>>
>> I wonder if perhaps the READ_DDB_START and READ_DDB_CONTINUE commands
>> could be used as a replacement for this display ID.
>>

There is a simple description for "Read DDB Start(A1H)" like below.
- This command returns supplier identification and display module model 
/ revision information.
- NOTE: This information is not the same what Read IDs(04H) command is 
returning.

For reference, Read IDs(04H) description is

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

Hi,

On 07/22/2014 10:23 AM, Inki Dae wrote:
> On 2014? 07? 21? 23:01, Andrzej Hajda wrote:
>> On 07/17/2014 11:01 AM, YoungJun Cho wrote:
>>> To support LCD I80 interface, the DSI host should register
>>> TE interrupt handler from the TE GPIO of attached panel.
>>> So the panel generates a tearing effect synchronization signal
>>> then the DSI host calls the CRTC device manager to trigger
>>> to transfer video image.
>>>
>>
>> This whole patch seems to be a hack.
>>
>> I think it is not a good idea to parse property of one device by another
>> device's driver.
>>
>> Especially here TE GPIO belongs to the panel. The panel driver should
>> know how to configure it and how to use it or not. The panel driver will
>> generate TE signal based on this GPIO, DSI/BTA mechanism or any other
>> mechanism provided by the panel.
>> TE signal should be delivered to the display controller. The only role
>> of DSIM here is that it is between the panel and the display controller
>> so it should be used to route this signal to DC.

It looks like DSIM transfers only TE signal to FIMD, but there is one 
thing important role, DSIM transfers TE signal only it is activated.
Without this thing, a broken screen would be showed at booting time.

>>
>> According to specs TE signal should/can be generated by DBI and DSI
>> command mode panels, so its handling should be more generic, not Exynos
>> specific.
>>
>
> Right. However, it seems that there are no much users using command mode
> panel so we would need more times to discuss the generic way. I think we
> can have this feature in specific to Exynos drm - it doesn't affect
> other SoC -.  Actually, I know OMAP people handle this feature in a way

For your information, there is a dsicm_te_isr() in 
drivers/video/fbdev/omap2/displays-new.
It seems like that panel -> dsi -> display controller.

Thank you.
Best regards YJ

> specific to OMAP SoC. If other users need more generic way to this
> feature then we could have a discussion about the generic way at that time.
>
> That is why Mr. Cho implemented TE feature like this. Do you have more
> good idea? I wish the idea would be specific so that Mr. Cho can
> implement it.
>
> P.s. Thierry already opposed the use of mipi_dsi_host_ops, I agree with
> him. And also it seems not good to use crtc and encoder/connector
> because these frameworks are common to all architecture including x86 so
> other architectures wouldn't need TE feature.
>
> Thanks,
> Inki Dae
>
>> Regards
>> Andrzej
>>
>>> Signed-off-by: YoungJun Cho 
>>> Acked-by: Inki Dae 
>>> Acked-by: Kyungmin Park 
>>> ---
>>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 
>>> -
>>>   1 file changed, 93 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> index 58bfb2a..4997bfe 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>> @@ -16,7 +16,9 @@
>>>   #include 
>>>
>>>   #include 
>>> +#include 
>>>   #include 
>>> +#include 
>>>   #include 
>>>   #include 
>>>   #include 
>>> @@ -24,6 +26,7 @@
>>>   #include 
>>>   #include 
>>>
>>> +#include "exynos_drm_crtc.h"
>>>   #include "exynos_drm_drv.h"
>>>
>>>   /* returns true iff both arguments logically differs */
>>> @@ -247,6 +250,7 @@ struct exynos_dsi {
>>> struct clk *bus_clk;
>>> struct regulator_bulk_data supplies[2];
>>> int irq;
>>> +   int te_gpio;
>>>
>>> u32 pll_clk_rate;
>>> u32 burst_clk_rate;
>>> @@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void 
>>> *dev_id)
>>> return IRQ_HANDLED;
>>>   }
>>>
>>> +static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
>>> +{
>>> +   struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
>>> +   struct drm_encoder *encoder = dsi->encoder;
>>> +
>>> +   if (dsi->state & DSIM_STATE_ENABLED)
>>> +   exynos_drm_crtc_te_handler(encoder->crtc);
>>> +
>>> +   return IRQ_HANDLED;
>>> +}
>>> +
>>> +static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
>>> +{
>>> +   enable_irq(dsi->irq);
>>> +
>>&

[PATCH v6 09/14] ARM: dts: s6e3fa0: add DT bindings

[YoungJun Cho]

Hi Thierry,

On 07/17/2014 07:38 PM, Thierry Reding wrote:
> On Thu, Jul 17, 2014 at 06:01:24PM +0900, YoungJun Cho wrote:
>> This patch adds DT bindings for s6e3fa0 panel.
>> The bindings describes panel resources and display timings.
>
> The commit message here should preferably say which platform this is
> used on.

Although only exynos drm could use this panel now, I think this panel 
could be used by any platform.
Do you have any good idea for that?

>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   .../devicetree/bindings/panel/samsung,s6e3fa0.txt  | 46 
>> ++
>>   1 file changed, 46 insertions(+)
>>   create mode 100644 
>> Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
>>
>> diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
>> b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
>> new file mode 100644
>> index 000..2cd32f5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
>> @@ -0,0 +1,46 @@
>> +Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
>> +
>> +Required properties:
>> +  - compatible: "samsung,s6e3fa0"
>> +  - reg: the virtual channel number of a DSI peripheral
>> +  - vdd3-supply: core voltage supply
>> +  - vci-supply: voltage supply for analog circuits
>> +  - reset-gpios: a GPIO spec for the reset pin
>> +  - det-gpios: a GPIO spec for the OLED detection pin
>> +  - te-gpios: a GPIO spec for the TE pin
>> +  - display-timings: timings for the connected panel as described by [1]
>
> display-timings should be optional. The panel driver should provide a
> default mode. And only if you really need to override the default mode
> you should provide the option of getting an alternative set of values
> from DT.

Could you explain why this display-timings should be optional?
Most of DTs regard display-timings as required property.

Thank you.
Best regards YJ

>
> Thierry
>

[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

Hi Thierry,

Thank you a lot for kind comments.

On 07/17/2014 07:36 PM, Thierry Reding wrote:
> On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
> [...]
>> diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
>> b/drivers/gpu/drm/panel/panel-s6e3fa0.c
> [...]
>> +/* Manufacturer Command Set */
>> +#define MCS_GLOBAL_PARAMETER0xb0
>> +#define MCS_AID 0xb2
>> +#define MCS_ELVSSOPT0xb6
>> +#define MCS_TEMPERATURE_SET 0xb8
>> +#define MCS_PENTILE_CTRL0xc0
>> +#define MCS_GAMMA_MODE  0xca
>> +#define MCS_VDDM0xd7
>> +#define MCS_ALS 0xe3
>> +#define MCS_ERR_FG  0xed
>> +#define MCS_KEY_LEV10xf0
>> +#define MCS_GAMMA_UPDATE0xf7
>> +#define MCS_KEY_LEV20xfc
>> +#define MCS_RE  0xfe
>> +#define MCS_TOUT2_HSYNC 0xff
>> +
>> +/* Content Adaptive Brightness Control */
>> +#define DCS_WRITE_CABC  0x55
>
> Is this not a manufacturer specific command? I couldn't find it in the
> DSI or DCS specifications, but it sounds like something standard (also
> indicated by the DCS_ prefix). Can you point out the specification for
> this?
>

Andrzej commented before and decided it as DCS one because if the value 
is less than 0xb0, it is DCS one and the others are MCS one.
But still I'm not sure it is correct.

>> +#define MTP_ID_LEN  3
>> +#define GAMMA_LEVEL_NUM 30
>> +
>> +#define DEFAULT_VDDM_VAL0x15
>> +
>> +struct s6e3fa0 {
>> +struct device   *dev;
>> +struct drm_panelpanel;
>> +
>> +struct regulator_bulk_data  supplies[2];
>> +struct gpio_desc*reset_gpio;
>> +struct videomodevm;
>> +
>> +unsigned intpower_on_delay;
>> +unsigned intreset_delay;
>> +unsigned intinit_delay;
>> +unsigned intwidth_mm;
>> +unsigned intheight_mm;
>> +
>> +unsigned char   id;
>> +unsigned char   vddm;
>> +unsigned intbrightness;
>> +};
>
> Please don't use this kind of artificial padding. A simple space will
> do.
>
>> +
>> +#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
>
> Please turn this into a function so we can get proper type checking.
>
>> +
>> +/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
>> +static const unsigned char s6e3fa0_vddm_lut[][2] = {
>> +{0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
>> +{0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
>> +{0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
>> +{0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
>> +{0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
>> +{0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
>> +{0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
>> +{0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
>> +{0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
>> +{0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
>> +{0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
>> +{0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
>> +{0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
>> +{0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
>> +{0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
>> +{0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
>> +{0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
>> +{0x55, 0x49}, {0x56, 0x4a}, {0x57, 0x4b}, {0x58, 0x4c}, {0x59, 0x4d},
>> +{0x5a, 0x4e}, {0x5b, 0x4f}, {0x5c, 0x50}, {0x5d, 0x51}, {0x5e, 0x52},
>> +{0x5f, 0x53}, {0x60, 0x54}, {0x61, 0x55}, {0x62, 0x56}, {0x63, 0x57},
>> +{0x64, 0x58}, {0x65, 0x59}, {0x66, 0x5a}, {0x67, 0x5b}, {0x68, 0x5c},
>> +{0x69, 0x5d}, {0x6a, 0x5e}, {0x6b, 0x5f}, {0x6c, 0x60}, {0x6d, 0x61},
>> +{0x6e, 0x62}, {0x6f, 0x63}, {0x70, 0x64}, {0x71, 0x65}, {0x72, 0x66},
>> +{0x73, 0x67}, {0x74, 0x68}, {0x75, 0x69}, {0x76, 0x6a}, {

[PATCH v6 14/14] ARM: dts: exynos5420: add dsi node

[YoungJun Cho]

This patch adds common part of dsi node.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 0b9d15d..3a7862b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -523,6 +523,20 @@
#phy-cells = <1>;
};

+   dsi at 1450 {
+   compatible = "samsung,exynos5410-mipi-dsi";
+   reg = <0x1450 0x1>;
+   interrupts = <0 82 0>;
+   samsung,power-domain = <&disp_pd>;
+   phys = <&mipi_phy 1>;
+   phy-names = "dsim";
+   clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
+   clock-names = "bus_clk", "pll_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
fimd: fimd at 1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.9.0

[PATCH v6 13/14] ARM: dts: exynos5420: add mipi-phy node

[YoungJun Cho]

This patch adds mipi-phy node for MIPI DSI device.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..0b9d15d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -517,6 +517,12 @@
phy-names = "dp";
};

+   mipi_phy: video-phy at 10040714 {
+   compatible = "samsung,s5pv210-mipi-video-phy";
+   reg = <0x10040714 12>;
+   #phy-cells = <1>;
+   };
+
fimd: fimd at 1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.9.0

[PATCH v6 12/14] ARM: dts: exynos5: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..fdead12 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -87,6 +87,7 @@
reg = <0x1440 0x4>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <18 4>, <18 5>, <18 6>;
+   samsung,sysreg = <&sysreg_system_controller>;
status = "disabled";
};

-- 
1.9.0

[PATCH v6 11/14] ARM: dts: exynos4: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos4.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index fbaf426..3793881 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -608,6 +608,7 @@
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
+   samsung,sysreg = <&sys_reg>;
status = "disabled";
};
 };
-- 
1.9.0

[PATCH v6 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/panel/Kconfig |   7 +
 drivers/gpu/drm/panel/Makefile|   1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c | 541 ++
 3 files changed, 549 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS

+config DRM_PANEL_S6E3FA0
+   tristate "S6E3FA0 DSI command mode panel"
+   depends on DRM && DRM_PANEL
+   depends on OF
+   select DRM_MIPI_DSI
+   select VIDEOMODE_HELPERS
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
 obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..811ec92
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,541 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER   0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT   0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL   0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM   0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1   0xf0
+#define MCS_GAMMA_UPDATE   0xf7
+#define MCS_KEY_LEV2   0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL   0x15
+
+struct s6e3fa0 {
+   struct device   *dev;
+   struct drm_panelpanel;
+
+   struct regulator_bulk_data  supplies[2];
+   struct gpio_desc*reset_gpio;
+   struct videomodevm;
+
+   unsigned intpower_on_delay;
+   unsigned intreset_delay;
+   unsigned intinit_delay;
+   unsigned intwidth_mm;
+   unsigned intheight_mm;
+
+   unsigned char   id;
+   unsigned char   vddm;
+   unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+   {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+   {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+   {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+   {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+   {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+   {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+   {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+   {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+   {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+   {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+   {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+   {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+   {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+   {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+   {0x46, 0x06}, {0x47, 0x05}, {0x48, 0x04}, {0x49, 0x03}, {0x4a, 0x02},
+   {0x4b, 0x01}, {0x4c, 0x40}, {0x4d, 0x41}, {0x4e, 0x42}, {0x4f, 0x43},
+   {0x50, 0x44}, {0x51, 0x45}, {0x52, 0x46}, {0x53, 0x47}, {0x54, 0x48},
+   {

[PATCH v6 09/14] ARM: dts: s6e3fa0: add DT bindings

[YoungJun Cho]

This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  | 46 ++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt

diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+  - compatible: "samsung,s6e3fa0"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - det-gpios: a GPIO spec for the OLED detection pin
+  - te-gpios: a GPIO spec for the TE pin
+  - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   panel at 0 {
+   compatible = "samsung,s6e3fa0";
+   reg = <0>;
+   vdd3-supply = <&vcclcd_reg>;
+   vci-supply = <&vlcd_reg>;
+   reset-gpios = <&gpy7 4 0>;
+   det-gpios = <&gpg0 6 0>;
+   te-gpios = <&gpd1 7 0>;
+
+   display-timings {
+   timings0 {
+   clock-frequency = <0>;
+   hactive = <1080>;
+   vactive = <1920>;
+   hfront-porch = <2>;
+   hback-porch = <2>;
+   hsync-len = <1>;
+   vfront-porch = <1>;
+   vback-porch = <4>;
+   vsync-len = <1>;
+   };
+   };
+   };
-- 
1.9.0

[PATCH v6 08/14] drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs

[YoungJun Cho]

The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.

In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 +++-
 1 file changed, 135 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 4997bfe..93ad4a2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,9 +58,12 @@

 /* FIFO memory AC characteristic register */
 #define DSIM_PLLCTRL_REG   0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
 #define DSIM_PHYACCHR_REG  0x54/* D-PHY AC characteristic register */
 #define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG   0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c

 /* DSIM_STATUS */
 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -203,6 +207,24 @@
 #define DSIM_PLL_M(x)  ((x) << 4)
 #define DSIM_PLL_S(x)  ((x) << 1)

+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x)  (((x) & 0x1ff) << 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x)  ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x)  ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x)   ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x)  ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
 #define DSI_MAX_BUS_WIDTH  4
 #define DSI_NUM_VIRTUAL_CHANNELS   4
 #define DSI_TX_FIFO_SIZE   2048
@@ -236,6 +258,12 @@ struct exynos_dsi_transfer {
 #define DSIM_STATE_INITIALIZED BIT(1)
 #define DSIM_STATE_CMD_LPM BIT(2)

+struct exynos_dsi_driver_data {
+   unsigned int plltmr_reg;
+
+   unsigned int has_freqband:1;
+};
+
 struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -266,11 +294,39 @@ struct exynos_dsi {

spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+   struct exynos_dsi_driver_data *driver_data;
 };

 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)

+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+   .plltmr_reg = 0x50,
+   .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+   .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+   { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+   { .compatible = "samsung,exynos5410-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+   { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+   struct platform_device *pdev)
+{
+   const struct of_device_id *of_id =
+   of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+   return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
 {
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -344,14 +400,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct 
exynos_dsi *dsi,
 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
 {
-   static const unsigned long freq_bands[] = {
-   100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
-   270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
-   510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
-   770 * MHZ, 870 * MHZ, 950 * MHZ,
-   };
+   struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
-   int timeout, band;
+   int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -372,18 +423,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi 
*dsi,
"failed to find PLL PMS 

[PATCH v6 07/14] ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings

[YoungJun Cho]

This patch adds relevant to exynos5410 compatible
for exynos5410 / 5420 / 5440 SoCs support.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 Documentation/devicetree/bindings/video/exynos_dsim.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt 
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 33b5730..31036c6 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -1,7 +1,9 @@
 Exynos MIPI DSI Master

 Required properties:
-  - compatible: "samsung,exynos4210-mipi-dsi"
+  - compatible: value should be one of the following
+   "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
+   "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs 
*/
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
   - clocks: list of clock specifiers, must contain an entry for each required
-- 
1.9.0

[PATCH v6 06/14] drm/exynos: fimd: support LCD I80 interface

[YoungJun Cho]

To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
  to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
  flip request, and implements TE handler to call trigger function.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/Kconfig   |   1 +
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
 include/video/samsung_fimd.h |   3 +-
 3 files changed, 235 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool "Exynos DRM FIMD"
depends on DRM_EXYNOS && !FB_S3C
select FB_MODE_HELPERS
+   select MFD_SYSCON
help
  Choose this option if you want to use Exynos FIMD for DRM.

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..28a3168 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include 
 #include 
@@ -61,6 +63,24 @@
 /* color key value register for hardware window 1 ~ 4. */
 #define WKEYCON1_BASE(x)   ((WKEYCON1 + 0x140) + ((x - 1) * 8))

+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 << 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0  (0x2 << 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) << 16)
+#define LCD_WR_SETUP(x)((x) << 12)
+#define LCD_WR_ACTIVE(x)   ((x) << 8)
+#define LCD_WR_HOLD(x) ((x) << 4)
+#define I80IFEN_ENABLE (1 << 0)
+
 /* FIMD has totally five hardware windows. */
 #define WINDOWS_NR 5

@@ -68,10 +88,14 @@

 struct fimd_driver_data {
unsigned int timing_base;
+   unsigned int lcdblk_offset;
+   unsigned int lcdblk_vt_shift;
+   unsigned int lcdblk_bypass_shift;

unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+   unsigned int has_vidoutcon:1;
 };

 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {

 static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+   .lcdblk_offset = 0x210,
+   .lcdblk_vt_shift = 10,
+   .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
 };

 static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+   .lcdblk_offset = 0x214,
+   .lcdblk_vt_shift = 24,
+   .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+   .has_vidoutcon = 1,
 };

 struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk  *bus_clk;
struct clk  *lcd_clk;
void __iomem*regs;
+   struct regmap   *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long   irq_flags;
+   u32 vidcon0;
u32 vidcon1;
+   u32 vidout_con;
+   u32 i80ifcon;
+   booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t   wait_vsync_queue;
atomic_twait_vsync_event;
+   atomic_twin_updated;
+   atomic_ttriggering;

struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
u32 clkdiv;

+   if (ct

[PATCH v6 05/14] drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the DSI host should register
TE interrupt handler from the TE GPIO of attached panel.
So the panel generates a tearing effect synchronization signal
then the DSI host calls the CRTC device manager to trigger
to transfer video image.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 95 -
 1 file changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 58bfb2a..4997bfe 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -16,7 +16,9 @@
 #include 

 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -24,6 +26,7 @@
 #include 
 #include 

+#include "exynos_drm_crtc.h"
 #include "exynos_drm_drv.h"

 /* returns true iff both arguments logically differs */
@@ -247,6 +250,7 @@ struct exynos_dsi {
struct clk *bus_clk;
struct regulator_bulk_data supplies[2];
int irq;
+   int te_gpio;

u32 pll_clk_rate;
u32 burst_clk_rate;
@@ -954,17 +958,89 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
return IRQ_HANDLED;
 }

+static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
+{
+   struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
+   struct drm_encoder *encoder = dsi->encoder;
+
+   if (dsi->state & DSIM_STATE_ENABLED)
+   exynos_drm_crtc_te_handler(encoder->crtc);
+
+   return IRQ_HANDLED;
+}
+
+static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
+{
+   enable_irq(dsi->irq);
+
+   if (gpio_is_valid(dsi->te_gpio))
+   enable_irq(gpio_to_irq(dsi->te_gpio));
+}
+
+static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
+{
+   if (gpio_is_valid(dsi->te_gpio))
+   disable_irq(gpio_to_irq(dsi->te_gpio));
+
+   disable_irq(dsi->irq);
+}
+
 static int exynos_dsi_init(struct exynos_dsi *dsi)
 {
exynos_dsi_enable_clock(dsi);
exynos_dsi_reset(dsi);
-   enable_irq(dsi->irq);
+   exynos_dsi_enable_irq(dsi);
exynos_dsi_wait_for_reset(dsi);
exynos_dsi_init_link(dsi);

return 0;
 }

+static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
+{
+   int ret;
+
+   dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
+   if (!gpio_is_valid(dsi->te_gpio)) {
+   dev_err(dsi->dev, "no te-gpios specified\n");
+   ret = dsi->te_gpio;
+   goto out;
+   }
+
+   ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
+   if (ret) {
+   dev_err(dsi->dev, "gpio request failed with %d\n", ret);
+   goto out;
+   }
+
+   /*
+* This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel
+* calls drm_panel_init() first then calls mipi_dsi_attach() in probe().
+* It means that te_gpio is invalid when exynos_dsi_enable_irq() is
+* called by drm_panel_init() before panel is attached.
+*/
+   ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio),
+   exynos_dsi_te_irq_handler, NULL,
+   IRQF_TRIGGER_RISING, "TE", dsi);
+   if (ret) {
+   dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
+   gpio_free(dsi->te_gpio);
+   goto out;
+   }
+
+out:
+   return ret;
+}
+
+static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
+{
+   if (gpio_is_valid(dsi->te_gpio)) {
+   free_irq(gpio_to_irq(dsi->te_gpio), dsi);
+   gpio_free(dsi->te_gpio);
+   dsi->te_gpio = -ENOENT;
+   }
+}
+
 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
  struct mipi_dsi_device *device)
 {
@@ -978,6 +1054,16 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host 
*host,
if (dsi->connector.dev)
drm_helper_hpd_irq_event(dsi->connector.dev);

+   /*
+* If attached panel device is for command mode one, dsi should
+* register TE interrupt handler.
+*/
+   if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
+   int ret = exynos_dsi_register_te_irq(dsi);
+   if (ret)
+   return ret;
+   }
+
return 0;
 }

@@ -986,6 +1072,8 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host 
*host,
 {
struct exynos_dsi *dsi = host_to_dsi(host);

+   exynos_dsi_unregister_te_irq(dsi);
+
dsi->panel_node = NULL;

if (dsi->connector.dev)
@@ -1099,7 +1187,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi)

 

[PATCH v6 04/14] drm/exynos: add TE handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it to the display controller.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 
 drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 +++
 drivers/gpu/drm/exynos/exynos_drm_drv.h  | 3 +++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..b68e58f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,11 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device 
*drm_dev,

return -EPERM;
 }
+
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+   struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager;
+
+   if (manager->ops->te_handler)
+   manager->ops->te_handler(manager);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..690dcdd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc, 
int zpos);
 int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);

+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 02f3b3d..13be498 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -186,6 +186,8 @@ struct exynos_drm_display {
  * @win_commit: apply hardware specific overlay data to registers.
  * @win_enable: enable hardware specific overlay.
  * @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
  */
 struct exynos_drm_manager;
 struct exynos_drm_manager_ops {
@@ -204,6 +206,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+   void (*te_handler)(struct exynos_drm_manager *mgr);
 };

 /*
-- 
1.9.0

[PATCH v6 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties

[YoungJun Cho]

In case of using MIPI DSI based I80 interface panel,
the relevant registers should be set.
So this patch adds relevant DT bindings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/video/samsung-fimd.txt | 28 ++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt 
b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b..59ff61e 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -44,6 +44,34 @@ Optional Properties:
 - display-timings: timing settings for FIMD, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
+- samsung,sysreg: handle to syscon used to control the system registers
+- i80-if-timings: timing configuration for lcd i80 interface support.
+  - cs-setup: clock cycles for the active period of address signal is enabled
+  until chip select is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-setup: clock cycles for the active period of CS signal is enabled until
+  write signal is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-active: clock cycles for the active period of CS is enabled.
+   If not specified, the default value(1) will be used.
+  - wr-hold: clock cycles for the active period of CS is disabled until write
+ signal is disabled.
+ If not specified, the default value(0) will be used.
+
+  The parameters are defined as:
+
+VCLK(internal)  __|??|_|??|_|??|_|??|_|??
+  :::::
+Address Output  --:|:::
+Chip Select ???|::|??
+   | wr-setup+1 || wr-hold+1  |
+   |<-->||<-->|
+Write Enable||???
+| wr-active+1|
+|<-->|
+Video Data  --

 The device node can contain 'port' child nodes according to the bindings 
defined
 in [2]. The following are properties specific to those nodes:
-- 
1.9.0

[PATCH v6 02/14] drm/exynos: use wait_event_timeout() for safety usage

[YoungJun Cho]

There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc->pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int 
mode)

if (mode > DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
-   wait_event(exynos_crtc->pending_flip_queue,
-   atomic_read(&exynos_crtc->pending_flip) == 0);
+   if (!wait_event_timeout(exynos_crtc->pending_flip_queue,
+   !atomic_read(&exynos_crtc->pending_flip),
+   HZ/20))
+   atomic_set(&exynos_crtc->pending_flip, 0);
drm_vblank_off(crtc->dev, exynos_crtc->pipe);
}

@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(&dev->event_lock);
drm_vblank_put(dev, exynos_crtc->pipe);
list_del(&event->base.link);
+   atomic_set(&exynos_crtc->pending_flip, 0);
spin_unlock_irq(&dev->event_lock);

goto out;
-- 
1.9.0

[PATCH v6 01/14] drm/exynos: dsi: move the EoT packets configuration point

[YoungJun Cho]

This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 2df3592..58bfb2a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -468,13 +468,20 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
/* DSI configuration */
reg = 0;

+   /*
+* The first bit of mode_flags specifies display configuration.
+* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+* mode, otherwise it will support command mode.
+*/
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;

+   /*
+* The user manual describes that following bits are ignored in
+* command mode.
+*/
if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
-   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
-   reg |= DSIM_EOT_DISABLE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +498,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}

+   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+   reg |= DSIM_EOT_DISABLE;
+
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
-- 
1.9.0

[PATCH v6 00/14] drm/exynos: support LCD I80 interface display

[YoungJun Cho]

Hi,

This series adds LCD I80 interface display support for Exynos DRM driver.
The FIMD(display controller) specification describes it as "LCD I80 interface"
and the DSI specification describes it as "Command mode interface".

This is based on exynos-drm-next branch.

The previous patches,
RFC: http://www.spinics.net/lists/dri-devel/msg58898.html
V1: http://www.spinics.net/lists/dri-devel/msg59291.html
V2: http://www.spinics.net/lists/dri-devel/msg59867.html
V3: http://www.spinics.net/lists/dri-devel/msg60708.html
V4: http://www.spinics.net/lists/dri-devel/msg60943.html
V5: http://www.spinics.net/lists/dri-devel/msg62956.html

Changelog v2:
- Fixes typo and removes unnecessary error log. (commented by Andrzej Hazda)
- Adds missed pendlig_flip flag clear points. (commented by Daniel Kurtz)

Changelog v3:
- Removes generic command mode and command mode display timing interface.
- Moves I80 interface timings from panel DT to the FIMD(display controller) DT.

Changelog v4:
- Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because
  it was already updated by linux-samsung-soc. (commented by Vivek Gautam)

Changelog v5:
- Fixes FIMD vidcon0 register relevant code.
- Fixes panel gamma table, disable sequence.
- Slitely updates for code cleanup.

Changelog v6:
- Removes pass TE host ops in dsi and exynos dsi uses TE irq handler instead,
  and it is related with the TE GPIO of panel. (commented by Thierry Reding)

Patches 1 and 2 fix trivial bugs.

Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface.
The MIPI DSI command mode based panel generates Tearing Effect synchronization
signal between MCU and FB to display video image, and FIMD should trigger to
transfer video image at this signal.
So the panel generates it and the dsi should receive the TE IRQ and call TE
handler chains to notify it to the FIMD.

Patches 7 and 8 implement to use Exynos5410 / 5420 / 5440 SoC DSI driver
which is different from previous Exynos4 SoCs for some registers control.

Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED
5.7" LCD drm panel driver.

The ohters add DT property nodes to support MIPI DSI command mode.

I welcome any comments.

Thank you.
Best regards YJ

YoungJun Cho (14):
  drm/exynos: dsi: move the EoT packets configuration point
  drm/exynos: use wait_event_timeout() for safety usage
  ARM: dts: samsung-fimd: add LCD I80 interface specific properties
  drm/exynos: add TE handler to support LCD I80 interface
  drm/exynos: dsi: add TE interrupt handler to support LCD I80 interface
  drm/exynos: fimd: support LCD I80 interface
  ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings
  drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
  ARM: dts: s6e3fa0: add DT bindings
  drm/panel: add S6E3FA0 driver
  ARM: dts: exynos4: add system register property
  ARM: dts: exynos5: add system register property
  ARM: dts: exynos5420: add mipi-phy node
  ARM: dts: exynos5420: add dsi node

 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |  46 ++
 .../devicetree/bindings/video/exynos_dsim.txt  |   4 +-
 .../devicetree/bindings/video/samsung-fimd.txt |  28 ++
 arch/arm/boot/dts/exynos4.dtsi |   1 +
 arch/arm/boot/dts/exynos5.dtsi |   1 +
 arch/arm/boot/dts/exynos5420.dtsi  |  20 +
 drivers/gpu/drm/exynos/Kconfig |   1 +
 drivers/gpu/drm/exynos/exynos_drm_crtc.c   |  15 +-
 drivers/gpu/drm/exynos/exynos_drm_crtc.h   |   7 +
 drivers/gpu/drm/exynos/exynos_drm_drv.h|   3 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c| 266 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c   | 276 +--
 drivers/gpu/drm/panel/Kconfig  |   7 +
 drivers/gpu/drm/panel/Makefile |   1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c  | 541 +
 include/video/samsung_fimd.h   |   3 +-
 16 files changed, 1146 insertions(+), 74 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

-- 
1.9.0

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

[YoungJun Cho]

Hi Thierry,

On 07/16/2014 04:54 PM, Thierry Reding wrote:
> On Wed, Jul 16, 2014 at 11:23:09AM +0900, YoungJun Cho wrote:
>> Hi Inki,
>>
>> On 07/15/2014 11:34 AM, Inki Dae wrote:
>>> On 2014? 07? 14? 20:03, Thierry Reding wrote:
>>>> On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
>>>>> On 07/14/2014 06:41 PM, Thierry Reding wrote:
>>>> [...]
>>>>>> That said, I've been doing some research and it seems like we have a
>>>>>> somewhat similar feature on Tegra. What happens there is that there are
>>>>>> three GPIO pins that can be repurposed for TE signalling. But as opposed
>>>>>> to using them as interrupts the display controller can be configured to
>>>>>> use them, upon which it will automatically handle the TE signal by
>>>>>> sending the next frame.
>>>>>
>>>>> Could you explain more detail how the Tegra display controller could be
>>>>> configured with this GPIO pins?
>>>>> I have no idea except that the display controller registers this GPIO as 
>>>>> an
>>>>> IRQ.
>>>>
>>>> On Tegra the display controller has a special register that can be
>>>> programmed to use one of the three GPIOs as TE signal. Then the display
>>>> controller can be configured in one-shot (non-continuous) mode, which
>>>> means that software needs to explicitly set a trigger bit to tell the
>>>> display controller to send a new frame. If TE signalling is enabled,
>>>> then the display controller will not immediately send a new frame when
>>>> triggered but wait for signalling of this GPIO.
>>>>
>>>>>> So we have at least two very different implementations of this on two
>>>>>> different SoCs. Further the specification explicitly recommends using
>>>>>> the BTA sequence and DSI protocol to wait for TE. So I still think that
>>>>>> controllers that provide an additional, non-spec compliant method to
>>>>>> signal TE should handle it separately rather than within DSI. Otherwise
>>>>>> we essentially need to make the DSI "core" aware of all these quirks,
>>>>>> and I'd rather avoid that.
>>>>>
>>>>> You mean, the DSI specification guides to use BTA, so it's better to use
>>>>> display controller rather than DSIM, right?
>>>>
>>>> What I'm saying is that there's nothing about a side-band TE wire in the
>>>> DSI spec. In fact the spec explicitly says that this mechanism of an
>>>> external TE wire from older protocols (DBI) was replaced by the BTA
>>>> sequence over the protocol.
>>>>
>>>> Now, my understanding is that using the BTA sequence over the DSI
>>>> protocol would introduce some latency and that forces some panel vendors
>>>> to still provide a side-band TE wire even in DSI compliant panels. But
>>>> since this is not part of the specification there is no standard way to
>>>> do this (as evidenced by Tegra and Exynos). Therefore putting such
>>>> functionality into the core DSI code is bad.
>>>>
>>>> But that doesn't mean that you have to put this functionality into the
>>>> display controller driver on Exynos. What I'm saying is that it should
>>>> be handled by the SoC driver rather than the core. Where exactly
>>>> probably depends on the particular case.
>>>>
>>>>>>> As Inki commented before, I'll try to use remote-endpoint property of 
>>>>>>> DSI
>>>>>>> device node in exynos DSIM driver and call FIMD notifier.
>>>>>>
>>>>>> Sounds like it matches what I said above. I'm not a huge fan of
>>>>>> notifiers, but if it works for you I suppose that's fine. The
>>>>>> alternative would be to directly call a FIMD function, which is
>>>>>> somewhat more explicit than a notifier.
>>>>>
>>>>> Yes, I also like explicit call, so I want to use dsi_host_ops and calls it
>>>>> in panel. But there is an objection to use dis_host_ops, we think notifier
>>>>> in exynos dsim for fimd(display controller).
>>>>
>>>> There are other ways to explicitly call into the display controller. You
>>>> could for example get access to the CRTC that DSIM is currently
>>>&g

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

[YoungJun Cho]

Hi Inki,

On 07/15/2014 11:34 AM, Inki Dae wrote:
> On 2014? 07? 14? 20:03, Thierry Reding wrote:
>> On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
>>> On 07/14/2014 06:41 PM, Thierry Reding wrote:
>> [...]
>>>> That said, I've been doing some research and it seems like we have a
>>>> somewhat similar feature on Tegra. What happens there is that there are
>>>> three GPIO pins that can be repurposed for TE signalling. But as opposed
>>>> to using them as interrupts the display controller can be configured to
>>>> use them, upon which it will automatically handle the TE signal by
>>>> sending the next frame.
>>>
>>> Could you explain more detail how the Tegra display controller could be
>>> configured with this GPIO pins?
>>> I have no idea except that the display controller registers this GPIO as an
>>> IRQ.
>>
>> On Tegra the display controller has a special register that can be
>> programmed to use one of the three GPIOs as TE signal. Then the display
>> controller can be configured in one-shot (non-continuous) mode, which
>> means that software needs to explicitly set a trigger bit to tell the
>> display controller to send a new frame. If TE signalling is enabled,
>> then the display controller will not immediately send a new frame when
>> triggered but wait for signalling of this GPIO.
>>
>>>> So we have at least two very different implementations of this on two
>>>> different SoCs. Further the specification explicitly recommends using
>>>> the BTA sequence and DSI protocol to wait for TE. So I still think that
>>>> controllers that provide an additional, non-spec compliant method to
>>>> signal TE should handle it separately rather than within DSI. Otherwise
>>>> we essentially need to make the DSI "core" aware of all these quirks,
>>>> and I'd rather avoid that.
>>>
>>> You mean, the DSI specification guides to use BTA, so it's better to use
>>> display controller rather than DSIM, right?
>>
>> What I'm saying is that there's nothing about a side-band TE wire in the
>> DSI spec. In fact the spec explicitly says that this mechanism of an
>> external TE wire from older protocols (DBI) was replaced by the BTA
>> sequence over the protocol.
>>
>> Now, my understanding is that using the BTA sequence over the DSI
>> protocol would introduce some latency and that forces some panel vendors
>> to still provide a side-band TE wire even in DSI compliant panels. But
>> since this is not part of the specification there is no standard way to
>> do this (as evidenced by Tegra and Exynos). Therefore putting such
>> functionality into the core DSI code is bad.
>>
>> But that doesn't mean that you have to put this functionality into the
>> display controller driver on Exynos. What I'm saying is that it should
>> be handled by the SoC driver rather than the core. Where exactly
>> probably depends on the particular case.
>>
>>>>> As Inki commented before, I'll try to use remote-endpoint property of DSI
>>>>> device node in exynos DSIM driver and call FIMD notifier.
>>>>
>>>> Sounds like it matches what I said above. I'm not a huge fan of
>>>> notifiers, but if it works for you I suppose that's fine. The
>>>> alternative would be to directly call a FIMD function, which is
>>>> somewhat more explicit than a notifier.
>>>
>>> Yes, I also like explicit call, so I want to use dsi_host_ops and calls it
>>> in panel. But there is an objection to use dis_host_ops, we think notifier
>>> in exynos dsim for fimd(display controller).
>>
>> There are other ways to explicitly call into the display controller. You
>> could for example get access to the CRTC that DSIM is currently
>> connected to (via exynos_dsi.encoder->crtc) and then cast that to a
>> struct exynos_drm_crtc and call a function to trigger a new frame to be
>> sent (for example exynos_drm_crtc_send_frame()). This assumes that you
>> can safely cast struct drm_crtc * to struct exynos_drm_crtc *, but that
>> shouldn't be a problem.
>>
>> With the above, you could make the DSIM handle the TE signal interrupts
>> and trigger the DC using the new exynos_drm_crtc_send_frame() function.
>>
>
> It seems better than the use of notifier. Actually, original patch used
> this way except TE event.
> Mr. Cho, let's use remote-endpoint property and this way instead of
> notifier.
>

The struct exynos_dsi has panel_node, which is valid by 
exynos_dsi_host_attach() is called from panel, we could use it instead 
of getting new remote-endpoint node.

So after called exynos_dsi_host_attach(), the dsi driver could know that 
the panel supports mipi command mode or video mode,
and if the panel is for mipi command mode one, dsi driver gets panel te 
gpio and registers its irq.

I'll try.

Thank you.
Best regards YJ

> Thanks,
> Inki Dae
>
>> Thierry
>>
>
>

[PATCH RFA] drm: add of_graph endpoint helper to find possible CRTCs

[YoungJun Cho]

Hi Russell,

On 07/11/2014 03:01 AM, Russell King wrote:
> Add a helper to allow encoders to find their possible CRTCs from the
> OF graph without having to re-implement this functionality.  We add a
> device_node to drm_crtc which corresponds with the port node in the
> DT description of the CRTC device.
>
> We can then scan the DRM device list for CRTCs to find their index,
> matching the appropriate CRTC using the port device_node, thus building
> up the possible CRTC mask.
>
> Signed-off-by: Russell King 
> ---
>
> RFA = request for acks
>
> - Updated commentry in the drm_of_find_possible_crtcs() comment block to
> point at the description of the of_graph bindings.
> - Not updated for drm kerneldoc as I'm unable to build the documentation.
>
>   drivers/gpu/drm/Makefile |  1 +
>   drivers/gpu/drm/drm_of.c | 67 
> 
>   include/drm/drm_crtc.h   |  2 ++
>   include/drm/drm_of.h | 18 +
>   4 files changed, 88 insertions(+)
>   create mode 100644 drivers/gpu/drm/drm_of.c
>   create mode 100644 include/drm/drm_of.h
>
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index dd2ba4269740..533d011eab3e 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -20,6 +20,7 @@ drm-$(CONFIG_COMPAT) += drm_ioc32.o
>   drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o
>   drm-$(CONFIG_PCI) += ati_pcigart.o
>   drm-$(CONFIG_DRM_PANEL) += drm_panel.o
> +drm-$(CONFIG_OF) += drm_of.o
>
>   drm-usb-y   := drm_usb.o
>
> diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c
> new file mode 100644
> index ..16150a00c237
> --- /dev/null
> +++ b/drivers/gpu/drm/drm_of.c
> @@ -0,0 +1,67 @@
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/**
> + * drm_crtc_port_mask - find the mask of a registered CRTC by port OF node
> + * @dev: DRM device
> + * @port: port OF node
> + *
> + * Given a port OF node, return the possible mask of the corresponding
> + * CRTC within a device's list of CRTCs.  Returns zero if not found.
> + */
> +static uint32_t drm_crtc_port_mask(struct drm_device *dev,
> +struct device_node *port)
> +{
> + unsigned int index = 0;
> + struct drm_crtc *tmp;
> +
> + list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
> + if (tmp->port == port)
> + return 1 << index;
> +
> + index++;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * drm_of_find_possible_crtcs - find the possible CRTCs for an encoder port
> + * @dev: DRM device
> + * @port: encoder port to scan for endpoints
> + *
> + * Scan all endpoints attached to a port, locate their attached CRTCs,
> + * and generate the DRM mask of CRTCs which may be attached to this
> + * encoder.
> + *
> + * See Documentation/devicetree/bindings/graph.txt for the bindings.
> + */
> +uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
> + struct device_node *port)
> +{
> + struct device_node *remote_port, *ep = NULL;
> + uint32_t possible_crtcs = 0;
> +
> + do {
> + ep = of_graph_get_next_endpoint(port, ep);
> + if (!ep)
> + break;
> +
> + remote_port = of_graph_get_remote_port(ep);
> + if (!remote_port) {
> + of_node_put(ep);
> + return 0;
> + }
> +
> + possible_crtcs |= drm_crtc_port_mask(dev, remote_port);
> +
> + of_node_put(remote_port);

In my humble opinion, this requires of_node_put(ep),
because of_graph_get_next_endpoint() doesn't decrement it.

+   of_node_put(ep);

Thank you.
Best regards YJ

> + } while (1);
> +
> + return possible_crtcs;
> +}
> +EXPORT_SYMBOL(drm_of_find_possible_crtcs);
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 251b75e6bf7a..6a94909f1ca9 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -41,6 +41,7 @@ struct drm_framebuffer;
>   struct drm_object_properties;
>   struct drm_file;
>   struct drm_clip_rect;
> +struct device_node;
>
>   #define DRM_MODE_OBJECT_CRTC 0x
>   #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
> @@ -314,6 +315,7 @@ struct drm_crtc_funcs {
>*/
>   struct drm_crtc {
>   struct drm_device *dev;
> + struct device_node *port;
>   struct list_head head;
>
>   /**
> diff --git a/include/drm/drm_of.h b/include/drm/drm_of.h
> new file mode 100644
> index ..2441f7112074
> --- /dev/null
> +++ b/include/drm/drm_of.h
> @@ -0,0 +1,18 @@
> +#ifndef __DRM_OF_H__
> +#define __DRM_OF_H__
> +
> +struct drm_device;
> +struct device_node;
> +
> +#ifdef CONFIG_OF
> +extern uint32_t drm_of_find_possible_crtcs(struct drm_device *dev,
> +struct device_node *port);
> +#else
> +static inline uint32_t drm_of_find_possible_crtcs(struct drm_device *dev

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

[YoungJun Cho]

Hi Thierry,

On 07/14/2014 06:41 PM, Thierry Reding wrote:
> On Mon, Jul 14, 2014 at 06:22:39PM +0900, YoungJun Cho wrote:
>> Hi Thierry,
>>
>> Thank you for comment.
>>
>> On 07/10/2014 04:38 PM, Thierry Reding wrote:
>>> On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
>>>> On 07/10/2014 12:22 AM, Thierry Reding wrote:
>>>>> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
>>>>>> To support LCD I80 interface, the DSI host calls this function
>>>>>> to notify the panel tearing effect synchronization signal to
>>>>>> the CRTC device manager to trigger to transfer video image.
>>>>>>
>>>>>> Signed-off-by: YoungJun Cho 
>>>>>> Acked-by: Inki Dae 
>>>>>> Acked-by: Kyungmin Park 
>>>>>> ---
>>>>>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
>>>>>>   include/drm/drm_mipi_dsi.h  |  7 +++
>>>>>>   2 files changed, 18 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>>>>>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>>>> index dad543a..76e34ca 100644
>>>>>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>>>> @@ -24,6 +24,7 @@
>>>>>>   #include 
>>>>>>   #include 
>>>>>>
>>>>>> +#include "exynos_drm_crtc.h"
>>>>>>   #include "exynos_drm_drv.h"
>>>>>>
>>>>>>   /* returns true iff both arguments logically differs */
>>>>>> @@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct 
>>>>>> mipi_dsi_host *host,
>>>>>>  return (ret < 0) ? ret : xfer.rx_done;
>>>>>>   }
>>>>>>
>>>>>> +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
>>>>>> +{
>>>>>> +struct exynos_dsi *dsi = host_to_dsi(host);
>>>>>> +struct drm_encoder *encoder = dsi->encoder;
>>>>>> +
>>>>>> +if (dsi->state & DSIM_STATE_ENABLED)
>>>>>> +exynos_drm_crtc_te_handler(encoder->crtc);
>>>>>> +}
>>>>>> +
>>>>>>   static const struct mipi_dsi_host_ops exynos_dsi_ops = {
>>>>>>  .attach = exynos_dsi_host_attach,
>>>>>>  .detach = exynos_dsi_host_detach,
>>>>>>  .transfer = exynos_dsi_host_transfer,
>>>>>> +.pass_te = exynos_dsi_host_pass_te,
>>>>>>   };
>>>>>>
>>>>>>   static int exynos_dsi_poweron(struct exynos_dsi *dsi)
>>>>>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>>>>>> index 944f33f..3f21bea 100644
>>>>>> --- a/include/drm/drm_mipi_dsi.h
>>>>>> +++ b/include/drm/drm_mipi_dsi.h
>>>>>> @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
>>>>>>* @detach: detach DSI device from DSI host
>>>>>>* @transfer: send and/or receive DSI packet, return number of 
>>>>>> received bytes,
>>>>>>*   or error
>>>>>> + * @pass_te: call the crtc te_handler() callback from DSI host.
>>>>>> + *   The panel generates tearing effect synchronization signal 
>>>>>> between
>>>>>> + *   MCU and FB to display video images. And the display 
>>>>>> controller
>>>>>> + *   should trigger to transfer video image at this signal. So 
>>>>>> the panel
>>>>>> + *   receives the TE IRQ, then calls this function to notify it 
>>>>>> to the
>>>>>> + *   display controller.
>>>>>>*/
>>>>>>   struct mipi_dsi_host_ops {
>>>>>>  int (*attach)(struct mipi_dsi_host *host,
>>>>>> @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
>>>>>>struct mipi_dsi_device *dsi);
>>>>>>  ssize_t (*transfer)(struct mipi_dsi_host *host,
>>>>>>  struct mipi_dsi_msg *msg);
>>>>>> +void (*pass_te)(struct mipi_ds

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

[YoungJun Cho]

Hi Thierry,

Thank you for comment.

On 07/10/2014 04:38 PM, Thierry Reding wrote:
> On Thu, Jul 10, 2014 at 10:06:07AM +0900, YoungJun Cho wrote:
>> On 07/10/2014 12:22 AM, Thierry Reding wrote:
>>> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
>>>> To support LCD I80 interface, the DSI host calls this function
>>>> to notify the panel tearing effect synchronization signal to
>>>> the CRTC device manager to trigger to transfer video image.
>>>>
>>>> Signed-off-by: YoungJun Cho 
>>>> Acked-by: Inki Dae 
>>>> Acked-by: Kyungmin Park 
>>>> ---
>>>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
>>>>   include/drm/drm_mipi_dsi.h  |  7 +++
>>>>   2 files changed, 18 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>>>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>> index dad543a..76e34ca 100644
>>>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>>>> @@ -24,6 +24,7 @@
>>>>   #include 
>>>>   #include 
>>>>
>>>> +#include "exynos_drm_crtc.h"
>>>>   #include "exynos_drm_drv.h"
>>>>
>>>>   /* returns true iff both arguments logically differs */
>>>> @@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct 
>>>> mipi_dsi_host *host,
>>>>return (ret < 0) ? ret : xfer.rx_done;
>>>>   }
>>>>
>>>> +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
>>>> +{
>>>> +  struct exynos_dsi *dsi = host_to_dsi(host);
>>>> +  struct drm_encoder *encoder = dsi->encoder;
>>>> +
>>>> +  if (dsi->state & DSIM_STATE_ENABLED)
>>>> +  exynos_drm_crtc_te_handler(encoder->crtc);
>>>> +}
>>>> +
>>>>   static const struct mipi_dsi_host_ops exynos_dsi_ops = {
>>>>.attach = exynos_dsi_host_attach,
>>>>.detach = exynos_dsi_host_detach,
>>>>.transfer = exynos_dsi_host_transfer,
>>>> +  .pass_te = exynos_dsi_host_pass_te,
>>>>   };
>>>>
>>>>   static int exynos_dsi_poweron(struct exynos_dsi *dsi)
>>>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>>>> index 944f33f..3f21bea 100644
>>>> --- a/include/drm/drm_mipi_dsi.h
>>>> +++ b/include/drm/drm_mipi_dsi.h
>>>> @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
>>>>* @detach: detach DSI device from DSI host
>>>>* @transfer: send and/or receive DSI packet, return number of received 
>>>> bytes,
>>>>* or error
>>>> + * @pass_te: call the crtc te_handler() callback from DSI host.
>>>> + * The panel generates tearing effect synchronization signal 
>>>> between
>>>> + * MCU and FB to display video images. And the display 
>>>> controller
>>>> + * should trigger to transfer video image at this signal. So 
>>>> the panel
>>>> + * receives the TE IRQ, then calls this function to notify it 
>>>> to the
>>>> + * display controller.
>>>>*/
>>>>   struct mipi_dsi_host_ops {
>>>>int (*attach)(struct mipi_dsi_host *host,
>>>> @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
>>>>  struct mipi_dsi_device *dsi);
>>>>ssize_t (*transfer)(struct mipi_dsi_host *host,
>>>>struct mipi_dsi_msg *msg);
>>>> +  void (*pass_te)(struct mipi_dsi_host *host);
>>>
>>> I've objected to this particular change before and that objection still
>>> stands. I don't see how this is related to DSI. It seems like an
>>> implementation detail of this particular setup and I think it should be
>>> handled differently (within the Exynos DSI controller implementation
>>> possibly).
>>>
>>
>> Okay, I understand what you mean.
>> As you know, this function is called by panel TE interrupt handler, so it
>> could be accessed by panel.
>> Do you have any good idea for panel to access exynos_drm_dsi directly
>> without mipi_dis_host_ops?
>
> I've gone through the DSI specification again and the only mention of
> the tearing effect is in section 8.12 "TE Signaling in DSI". That s

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

[YoungJun Cho]

On 07/10/2014 12:22 AM, Thierry Reding wrote:
> On Tue, Jul 08, 2014 at 09:39:38AM +0900, YoungJun Cho wrote:
>> To support LCD I80 interface, the DSI host calls this function
>> to notify the panel tearing effect synchronization signal to
>> the CRTC device manager to trigger to transfer video image.
>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
>>   include/drm/drm_mipi_dsi.h  |  7 +++
>>   2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> index dad543a..76e34ca 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> @@ -24,6 +24,7 @@
>>   #include 
>>   #include 
>>
>> +#include "exynos_drm_crtc.h"
>>   #include "exynos_drm_drv.h"
>>
>>   /* returns true iff both arguments logically differs */
>> @@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct 
>> mipi_dsi_host *host,
>>  return (ret < 0) ? ret : xfer.rx_done;
>>   }
>>
>> +static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
>> +{
>> +struct exynos_dsi *dsi = host_to_dsi(host);
>> +struct drm_encoder *encoder = dsi->encoder;
>> +
>> +if (dsi->state & DSIM_STATE_ENABLED)
>> +exynos_drm_crtc_te_handler(encoder->crtc);
>> +}
>> +
>>   static const struct mipi_dsi_host_ops exynos_dsi_ops = {
>>  .attach = exynos_dsi_host_attach,
>>  .detach = exynos_dsi_host_detach,
>>  .transfer = exynos_dsi_host_transfer,
>> +.pass_te = exynos_dsi_host_pass_te,
>>   };
>>
>>   static int exynos_dsi_poweron(struct exynos_dsi *dsi)
>> diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
>> index 944f33f..3f21bea 100644
>> --- a/include/drm/drm_mipi_dsi.h
>> +++ b/include/drm/drm_mipi_dsi.h
>> @@ -49,6 +49,12 @@ struct mipi_dsi_msg {
>>* @detach: detach DSI device from DSI host
>>* @transfer: send and/or receive DSI packet, return number of received 
>> bytes,
>>*   or error
>> + * @pass_te: call the crtc te_handler() callback from DSI host.
>> + *   The panel generates tearing effect synchronization signal between
>> + *   MCU and FB to display video images. And the display controller
>> + *   should trigger to transfer video image at this signal. So the panel
>> + *   receives the TE IRQ, then calls this function to notify it to the
>> + *   display controller.
>>*/
>>   struct mipi_dsi_host_ops {
>>  int (*attach)(struct mipi_dsi_host *host,
>> @@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
>>struct mipi_dsi_device *dsi);
>>  ssize_t (*transfer)(struct mipi_dsi_host *host,
>>  struct mipi_dsi_msg *msg);
>> +void (*pass_te)(struct mipi_dsi_host *host);
>
> I've objected to this particular change before and that objection still
> stands. I don't see how this is related to DSI. It seems like an
> implementation detail of this particular setup and I think it should be
> handled differently (within the Exynos DSI controller implementation
> possibly).
>

Okay, I understand what you mean.
As you know, this function is called by panel TE interrupt handler, so 
it could be accessed by panel.
Do you have any good idea for panel to access exynos_drm_dsi directly 
without mipi_dis_host_ops?

Thank you.
Best regards YJ

> Laurent also asked you to split this up into two patches, one for the
> core part, the other for the Exynos driver parts, yet this patch
> contains both changes.
>
> Thierry
>

[PATCH v5 06/14] drm/exynos: fimd: support LCD I80 interface

[YoungJun Cho]

To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
  to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
  flip request, and implements TE handler to call trigger function.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/Kconfig   |   1 +
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
 include/video/samsung_fimd.h |   3 +-
 3 files changed, 235 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool "Exynos DRM FIMD"
depends on DRM_EXYNOS && !FB_S3C
select FB_MODE_HELPERS
+   select MFD_SYSCON
help
  Choose this option if you want to use Exynos FIMD for DRM.

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..28a3168 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include 
 #include 
@@ -61,6 +63,24 @@
 /* color key value register for hardware window 1 ~ 4. */
 #define WKEYCON1_BASE(x)   ((WKEYCON1 + 0x140) + ((x - 1) * 8))

+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 << 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0  (0x2 << 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) << 16)
+#define LCD_WR_SETUP(x)((x) << 12)
+#define LCD_WR_ACTIVE(x)   ((x) << 8)
+#define LCD_WR_HOLD(x) ((x) << 4)
+#define I80IFEN_ENABLE (1 << 0)
+
 /* FIMD has totally five hardware windows. */
 #define WINDOWS_NR 5

@@ -68,10 +88,14 @@

 struct fimd_driver_data {
unsigned int timing_base;
+   unsigned int lcdblk_offset;
+   unsigned int lcdblk_vt_shift;
+   unsigned int lcdblk_bypass_shift;

unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+   unsigned int has_vidoutcon:1;
 };

 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {

 static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+   .lcdblk_offset = 0x210,
+   .lcdblk_vt_shift = 10,
+   .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
 };

 static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+   .lcdblk_offset = 0x214,
+   .lcdblk_vt_shift = 24,
+   .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+   .has_vidoutcon = 1,
 };

 struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk  *bus_clk;
struct clk  *lcd_clk;
void __iomem*regs;
+   struct regmap   *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long   irq_flags;
+   u32 vidcon0;
u32 vidcon1;
+   u32 vidout_con;
+   u32 i80ifcon;
+   booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t   wait_vsync_queue;
atomic_twait_vsync_event;
+   atomic_twin_updated;
+   atomic_ttriggering;

struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
u32 clkdiv;

+   if (ct

[PATCH v5 14/14] ARM: dts: exynos5420: add dsi node

[YoungJun Cho]

This patch adds common part of dsi node.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 0b9d15d..3a7862b 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -523,6 +523,20 @@
#phy-cells = <1>;
};

+   dsi at 1450 {
+   compatible = "samsung,exynos5410-mipi-dsi";
+   reg = <0x1450 0x1>;
+   interrupts = <0 82 0>;
+   samsung,power-domain = <&disp_pd>;
+   phys = <&mipi_phy 1>;
+   phy-names = "dsim";
+   clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
+   clock-names = "bus_clk", "pll_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
fimd: fimd at 1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.9.0

[PATCH v5 13/14] ARM: dts: exynos5420: add mipi-phy node

[YoungJun Cho]

This patch adds mipi-phy node for MIPI DSI device.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..0b9d15d 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -517,6 +517,12 @@
phy-names = "dp";
};

+   mipi_phy: video-phy at 10040714 {
+   compatible = "samsung,s5pv210-mipi-video-phy";
+   reg = <0x10040714 12>;
+   #phy-cells = <1>;
+   };
+
fimd: fimd at 1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.9.0

[PATCH v5 12/14] ARM: dts: exynos5: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..fdead12 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -87,6 +87,7 @@
reg = <0x1440 0x4>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <18 4>, <18 5>, <18 6>;
+   samsung,sysreg = <&sysreg_system_controller>;
status = "disabled";
};

-- 
1.9.0

[PATCH v5 11/14] ARM: dts: exynos4: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos4.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index b8ece4b..92ee786 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -608,6 +608,7 @@
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
+   samsung,sysreg = <&sys_reg>;
status = "disabled";
};
 };
-- 
1.9.0

[PATCH v5 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/panel/Kconfig |   7 +
 drivers/gpu/drm/panel/Makefile|   1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c | 569 ++
 3 files changed, 577 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS

+config DRM_PANEL_S6E3FA0
+   tristate "S6E3FA0 DSI command mode panel"
+   depends on DRM && DRM_PANEL
+   depends on OF
+   select DRM_MIPI_DSI
+   select VIDEOMODE_HELPERS
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
 obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..66058a7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,569 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER   0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT   0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL   0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM   0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1   0xf0
+#define MCS_GAMMA_UPDATE   0xf7
+#define MCS_KEY_LEV2   0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL   0x15
+
+struct s6e3fa0 {
+   struct device   *dev;
+   struct drm_panelpanel;
+
+   struct regulator_bulk_data  supplies[2];
+   struct gpio_desc*reset_gpio;
+   struct gpio_desc*det_gpio;
+   struct gpio_desc*te_gpio;
+   struct videomodevm;
+
+   unsigned intpower_on_delay;
+   unsigned intreset_delay;
+   unsigned intinit_delay;
+   unsigned intwidth_mm;
+   unsigned intheight_mm;
+
+   unsigned char   id;
+   unsigned char   vddm;
+   unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+   {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+   {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+   {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+   {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+   {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+   {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+   {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+   {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+   {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+   {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+   {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+   {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+   {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+   {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+   {0x46, 0x06}, {0x47, 

[PATCH v5 09/14] ARM: dts: s6e3fa0: add DT bindings

[YoungJun Cho]

This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  | 46 ++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt

diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+  - compatible: "samsung,s6e3fa0"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - det-gpios: a GPIO spec for the OLED detection pin
+  - te-gpios: a GPIO spec for the TE pin
+  - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   panel at 0 {
+   compatible = "samsung,s6e3fa0";
+   reg = <0>;
+   vdd3-supply = <&vcclcd_reg>;
+   vci-supply = <&vlcd_reg>;
+   reset-gpios = <&gpy7 4 0>;
+   det-gpios = <&gpg0 6 0>;
+   te-gpios = <&gpd1 7 0>;
+
+   display-timings {
+   timings0 {
+   clock-frequency = <0>;
+   hactive = <1080>;
+   vactive = <1920>;
+   hfront-porch = <2>;
+   hback-porch = <2>;
+   hsync-len = <1>;
+   vfront-porch = <1>;
+   vback-porch = <4>;
+   vsync-len = <1>;
+   };
+   };
+   };
-- 
1.9.0

[PATCH v5 08/14] drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs

[YoungJun Cho]

The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.

In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 157 +++-
 1 file changed, 135 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 76e34ca..162f74d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@

 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -55,9 +56,12 @@

 /* FIFO memory AC characteristic register */
 #define DSIM_PLLCTRL_REG   0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
 #define DSIM_PHYACCHR_REG  0x54/* D-PHY AC characteristic register */
 #define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG   0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c

 /* DSIM_STATUS */
 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -201,6 +205,24 @@
 #define DSIM_PLL_M(x)  ((x) << 4)
 #define DSIM_PLL_S(x)  ((x) << 1)

+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x)  (((x) & 0x1ff) << 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x)  ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x)  ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x)   ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x)  ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
 #define DSI_MAX_BUS_WIDTH  4
 #define DSI_NUM_VIRTUAL_CHANNELS   4
 #define DSI_TX_FIFO_SIZE   2048
@@ -234,6 +256,12 @@ struct exynos_dsi_transfer {
 #define DSIM_STATE_INITIALIZED BIT(1)
 #define DSIM_STATE_CMD_LPM BIT(2)

+struct exynos_dsi_driver_data {
+   unsigned int plltmr_reg;
+
+   unsigned int has_freqband:1;
+};
+
 struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -263,11 +291,39 @@ struct exynos_dsi {

spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+   struct exynos_dsi_driver_data *driver_data;
 };

 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)

+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+   .plltmr_reg = 0x50,
+   .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+   .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+   { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+   { .compatible = "samsung,exynos5410-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+   { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+   struct platform_device *pdev)
+{
+   const struct of_device_id *of_id =
+   of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+   return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
 {
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -341,14 +397,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct 
exynos_dsi *dsi,
 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
 {
-   static const unsigned long freq_bands[] = {
-   100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
-   270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
-   510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
-   770 * MHZ, 870 * MHZ, 950 * MHZ,
-   };
+   struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
-   int timeout, band;
+   int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -369,18 +420,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi 
*dsi,
"failed to find PLL PMS for reque

[PATCH v5 07/14] ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings

[YoungJun Cho]

This patch adds relevant to exynos5410 compatible
for exynos5410 / 5420 / 5440 SoCs support.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 Documentation/devicetree/bindings/video/exynos_dsim.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt 
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 33b5730..31036c6 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -1,7 +1,9 @@
 Exynos MIPI DSI Master

 Required properties:
-  - compatible: "samsung,exynos4210-mipi-dsi"
+  - compatible: value should be one of the following
+   "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
+   "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs 
*/
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
   - clocks: list of clock specifiers, must contain an entry for each required
-- 
1.9.0

[PATCH v5 06/14] drm/exynos: fimd: support LCD I80 interface

[YoungJun Cho]

To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one
  to generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
  flip request, and implements TE handler to call trigger function.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/Kconfig   |   1 +
 drivers/gpu/drm/exynos/exynos_drm_fimd.c | 276 ++-
 include/video/samsung_fimd.h |   3 +-
 3 files changed, 235 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool "Exynos DRM FIMD"
depends on DRM_EXYNOS && !FB_S3C
select FB_MODE_HELPERS
+   select MFD_SYSCON
help
  Choose this option if you want to use Exynos FIMD for DRM.

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 33161ad..207872d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include 
 #include 
@@ -61,6 +63,24 @@
 /* color key value register for hardware window 1 ~ 4. */
 #define WKEYCON1_BASE(x)   ((WKEYCON1 + 0x140) + ((x - 1) * 8))

+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 << 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0  (0x2 << 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) << 16)
+#define LCD_WR_SETUP(x)((x) << 12)
+#define LCD_WR_ACTIVE(x)   ((x) << 8)
+#define LCD_WR_HOLD(x) ((x) << 4)
+#define I80IFEN_ENABLE (1 << 0)
+
 /* FIMD has totally five hardware windows. */
 #define WINDOWS_NR 5

@@ -68,10 +88,14 @@

 struct fimd_driver_data {
unsigned int timing_base;
+   unsigned int lcdblk_offset;
+   unsigned int lcdblk_vt_shift;
+   unsigned int lcdblk_bypass_shift;

unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+   unsigned int has_vidoutcon:1;
 };

 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {

 static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+   .lcdblk_offset = 0x210,
+   .lcdblk_vt_shift = 10,
+   .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
 };

 static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+   .lcdblk_offset = 0x214,
+   .lcdblk_vt_shift = 24,
+   .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+   .has_vidoutcon = 1,
 };

 struct fimd_win_data {
@@ -112,15 +143,22 @@ struct fimd_context {
struct clk  *bus_clk;
struct clk  *lcd_clk;
void __iomem*regs;
+   struct regmap   *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long   irq_flags;
+   u32 vidcon0;
u32 vidcon1;
+   u32 vidout_con;
+   u32 i80ifcon;
+   booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t   wait_vsync_queue;
atomic_twait_vsync_event;
+   atomic_twin_updated;
+   atomic_ttriggering;

struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +281,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
u32 clkdiv;

+   if (ct

[PATCH v5 05/14] drm/exynos: dsi: add pass TE host ops to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++
 include/drm/drm_mipi_dsi.h  |  7 +++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index dad543a..76e34ca 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
 #include 
 #include 

+#include "exynos_drm_crtc.h"
 #include "exynos_drm_drv.h"

 /* returns true iff both arguments logically differs */
@@ -1041,10 +1042,20 @@ static ssize_t exynos_dsi_host_transfer(struct 
mipi_dsi_host *host,
return (ret < 0) ? ret : xfer.rx_done;
 }

+static void exynos_dsi_host_pass_te(struct mipi_dsi_host *host)
+{
+   struct exynos_dsi *dsi = host_to_dsi(host);
+   struct drm_encoder *encoder = dsi->encoder;
+
+   if (dsi->state & DSIM_STATE_ENABLED)
+   exynos_drm_crtc_te_handler(encoder->crtc);
+}
+
 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+   .pass_te = exynos_dsi_host_pass_te,
 };

 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 944f33f..3f21bea 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,12 @@ struct mipi_dsi_msg {
  * @detach: detach DSI device from DSI host
  * @transfer: send and/or receive DSI packet, return number of received bytes,
  *   or error
+ * @pass_te: call the crtc te_handler() callback from DSI host.
+ *  The panel generates tearing effect synchronization signal between
+ *  MCU and FB to display video images. And the display controller
+ *  should trigger to transfer video image at this signal. So the panel
+ *  receives the TE IRQ, then calls this function to notify it to the
+ *  display controller.
  */
 struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +63,7 @@ struct mipi_dsi_host_ops {
  struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+   void (*pass_te)(struct mipi_dsi_host *host);
 };

 /**
-- 
1.9.0

[PATCH v5 04/14] drm/exynos: add TE handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it to the display controller.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 8 
 drivers/gpu/drm/exynos/exynos_drm_crtc.h | 7 +++
 drivers/gpu/drm/exynos/exynos_drm_drv.h  | 3 +++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..b68e58f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,11 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device 
*drm_dev,

return -EPERM;
 }
+
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+   struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager;
+
+   if (manager->ops->te_handler)
+   manager->ops->te_handler(manager);
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..690dcdd 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc, 
int zpos);
 int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);

+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+void exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 06cde45..d4e0726 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -188,6 +188,8 @@ struct exynos_drm_display {
  * @win_commit: apply hardware specific overlay data to registers.
  * @win_enable: enable hardware specific overlay.
  * @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
  */
 struct exynos_drm_manager;
 struct exynos_drm_manager_ops {
@@ -206,6 +208,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+   void (*te_handler)(struct exynos_drm_manager *mgr);
 };

 /*
-- 
1.9.0

[PATCH v5 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties

[YoungJun Cho]

In case of using MIPI DSI based I80 interface panel,
the relevant registers should be set.
So this patch adds relevant DT bindings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/video/samsung-fimd.txt | 28 ++
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt 
b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b..59ff61e 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -44,6 +44,34 @@ Optional Properties:
 - display-timings: timing settings for FIMD, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
+- samsung,sysreg: handle to syscon used to control the system registers
+- i80-if-timings: timing configuration for lcd i80 interface support.
+  - cs-setup: clock cycles for the active period of address signal is enabled
+  until chip select is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-setup: clock cycles for the active period of CS signal is enabled until
+  write signal is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-active: clock cycles for the active period of CS is enabled.
+   If not specified, the default value(1) will be used.
+  - wr-hold: clock cycles for the active period of CS is disabled until write
+ signal is disabled.
+ If not specified, the default value(0) will be used.
+
+  The parameters are defined as:
+
+VCLK(internal)  __|??|_|??|_|??|_|??|_|??
+  :::::
+Address Output  --:|:::
+Chip Select ???|::|??
+   | wr-setup+1 || wr-hold+1  |
+   |<-->||<-->|
+Write Enable||???
+| wr-active+1|
+|<-->|
+Video Data  --

 The device node can contain 'port' child nodes according to the bindings 
defined
 in [2]. The following are properties specific to those nodes:
-- 
1.9.0

[PATCH v5 02/14] drm/exynos: use wait_event_timeout() for safety usage

[YoungJun Cho]

There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc->pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int 
mode)

if (mode > DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
-   wait_event(exynos_crtc->pending_flip_queue,
-   atomic_read(&exynos_crtc->pending_flip) == 0);
+   if (!wait_event_timeout(exynos_crtc->pending_flip_queue,
+   !atomic_read(&exynos_crtc->pending_flip),
+   HZ/20))
+   atomic_set(&exynos_crtc->pending_flip, 0);
drm_vblank_off(crtc->dev, exynos_crtc->pipe);
}

@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(&dev->event_lock);
drm_vblank_put(dev, exynos_crtc->pipe);
list_del(&event->base.link);
+   atomic_set(&exynos_crtc->pending_flip, 0);
spin_unlock_irq(&dev->event_lock);

goto out;
-- 
1.9.0

[PATCH v5 01/14] drm/exynos: dsi: move the EoT packets configuration point

[YoungJun Cho]

This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6302aa6..dad543a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -468,13 +468,19 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
/* DSI configuration */
reg = 0;

+   /* The first bit of mode_flags specifies display configuration.
+* If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
+* mode, otherwise it will support command mode.
+*/
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
reg |= DSIM_VIDEO_MODE;

+   /*
+* The user manual describes that following bits are ignored in
+* command mode.
+*/
if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
-   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
-   reg |= DSIM_EOT_DISABLE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +497,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}

+   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+   reg |= DSIM_EOT_DISABLE;
+
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
-- 
1.9.0

[PATCH v5 00/14] drm/exynos: support LCD I80 interface display

[YoungJun Cho]

Hi,

This series adds LCD I80 interface display support for Exynos DRM driver.
The FIMD(display controller) specification describes it as "LCD I80 interface"
and the DSI specification describes it as "Command mode interface".

This is based on exynos-drm-next branch.

The previous patches,
RFC: http://www.spinics.net/lists/dri-devel/msg58898.html
V1: http://www.spinics.net/lists/dri-devel/msg59291.html
V2: http://www.spinics.net/lists/dri-devel/msg59867.html
V3: http://www.spinics.net/lists/dri-devel/msg60708.html
V4: http://www.spinics.net/lists/dri-devel/msg60943.html

Changelog v2:
- Fixes typo and removes unnecessary error log (commented by Andrzej Hazda)
- Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz)

Changelog v3:
- Removes generic command mode and command mode display timing interface.
- Moves I80 interface timings from panel DT to the FIMD(display controller) DT.

Changelog v4:
- Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because
  it was already updated by linux-samsung-soc (commented by Vivek Gautam)

Changelog v5:
- Fixes FIMD vidcon0 register relevant code
- Fixes panel gamma table, disable sequence
- Slitely updates for code cleanup

Patches 1 and 2 fix trivial bugs.

Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface.
The MIPI DSI command mode based panel generates Tearing Effect synchronization
signal between MCU and FB to display video image, and FIMD should trigger to
transfer video image at this signal.
So the panel should receive the TE IRQ and call TE handler chains to notify
it to the FIMD.

Patches 7 and 8 implement to use Exynos5410 / 5420 / 5440 SoC DSI driver
which is different from previous Exynos4 SoCs for some registers control.

Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED
5.7" LCD drm panel driver.

The ohters add DT property nodes to support MIPI DSI command mode.

I welcome any comments.

Thank you.
Best regards YJ

YoungJun Cho (14):
  drm/exynos: dsi: move the EoT packets configuration point
  drm/exynos: use wait_event_timeout() for safety usage
  ARM: dts: samsung-fimd: add LCD I80 interface specific properties
  drm/exynos: add TE handler to support LCD I80 interface
  drm/exynos: dsi: add pass TE host ops to support LCD I80 interface
  drm/exynos: fimd: support LCD I80 interface
  ARM: dts: exynos_dsim: add exynos5410 compatible to DT bindings
  drm/exynos: dsi: add driver data to support Exynos5410/5420/5440 SoCs
  ARM: dts: s6e3fa0: add DT bindings
  drm/panel: add S6E3FA0 driver
  ARM: dts: exynos4: add system register property
  ARM: dts: exynos5: add system register property
  ARM: dts: exynos5420: add mipi-phy node
  ARM: dts: exynos5420: add dsi node

 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |  46 ++
 .../devicetree/bindings/video/exynos_dsim.txt  |   4 +-
 .../devicetree/bindings/video/samsung-fimd.txt |  28 +
 arch/arm/boot/dts/exynos4.dtsi |   1 +
 arch/arm/boot/dts/exynos5.dtsi |   1 +
 arch/arm/boot/dts/exynos5420.dtsi  |  20 +
 drivers/gpu/drm/exynos/Kconfig |   1 +
 drivers/gpu/drm/exynos/exynos_drm_crtc.c   |  15 +-
 drivers/gpu/drm/exynos/exynos_drm_crtc.h   |   7 +
 drivers/gpu/drm/exynos/exynos_drm_drv.h|   3 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c| 181 ++-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c   | 276 --
 drivers/gpu/drm/panel/Kconfig  |   7 +
 drivers/gpu/drm/panel/Makefile |   1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c  | 569 +
 include/drm/drm_mipi_dsi.h |   7 +
 include/video/samsung_fimd.h   |   3 +-
 17 files changed, 1098 insertions(+), 72 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

-- 
1.9.0

[PATCH 0/3] drm/exynos: add framework to control DISP1BLK setting

[YoungJun Cho]

Hi Ajay,

I'm sorry for say that the patchset for exynos drm supporting I80 i/f
includes yours.

The patchset is still in reviewing and I'm preparing v5.

Please check this:
http://www.spinics.net/lists/dri-devel/msg60943.html

Thank you.
Best regards YJ

On Jun 25, 2014 11:19 PM, "Ajay Kumar"  wrote:
>
> This series is based on exynos-drm-next branch of Inki Dae's tree at:
> git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
>
> Exynos SOC have a DISP1BLK register where we can select
> the path for FIMD output. We can redirect the video data
> directly to DP/MIPI interface, or we can pass it via
> image enhancement chips.
>
> Since we don't use any image enhancement chips in exynos-drm,
> we need to set FIMD BYPASS in DISP1BLK.
>
> This patchset is tested for basic display + DPMS + S2R on snow and
peach_pit.
>
> Ajay Kumar (3):
>   [PATCH 1/3] drm/exynos: Control DISP1BLK system register in FIMD
>   [PATCH 2/3] ARM: dts: exynos5420: Add sysreg phandle to FIMD node
>   [PATCH 3/3] ARM: dts: exynos5250: Add sysreg phandle to FIMD node
>
>  .../devicetree/bindings/video/samsung-fimd.txt |2 ++
>  arch/arm/boot/dts/exynos5250.dtsi  |1 +
>  arch/arm/boot/dts/exynos5420.dtsi  |1 +
>  drivers/gpu/drm/exynos/exynos_drm_fimd.c   |   19
+++
>  include/video/samsung_fimd.h   |5 +
>  5 files changed, 28 insertions(+)
>
> --
> 1.7.9.5
>
> --
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[PATCH v4 14/14] ARM: dts: exynos5420: add dsi node

[YoungJun Cho]

This patch adds common part of dsi node.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index 6fde5fd..43b6852 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -478,6 +478,20 @@
#phy-cells = <1>;
};

+   dsi at 1450 {
+   compatible = "samsung,exynos5420-mipi-dsi";
+   reg = <0x1450 0x1>;
+   interrupts = <0 82 0>;
+   samsung,power-domain = <&disp_pd>;
+   phys = <&mipi_phy 1>;
+   phy-names = "dsim";
+   clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
+   clock-names = "bus_clk", "pll_clk";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
fimd at 1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.7.9.5

[PATCH v4 13/14] ARM: dts: exynos5420: add mipi-phy node

[YoungJun Cho]

This patch adds mipi-phy node for MIPI DSI device.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5420.dtsi |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi 
b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66..6fde5fd 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -472,6 +472,12 @@
phy-names = "dp";
};

+   mipi_phy: video-phy at 10040714 {
+   compatible = "samsung,s5pv210-mipi-video-phy";
+   reg = <0x10040714 12>;
+   #phy-cells = <1>;
+   };
+
fimd at 1440 {
samsung,power-domain = <&disp_pd>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
-- 
1.7.9.5

[PATCH v4 12/14] ARM: dts: exynos5: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos5.dtsi |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..fdead12 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -87,6 +87,7 @@
reg = <0x1440 0x4>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <18 4>, <18 5>, <18 6>;
+   samsung,sysreg = <&sysreg_system_controller>;
status = "disabled";
};

-- 
1.7.9.5

[PATCH v4 11/14] ARM: dts: exynos4: add system register property

[YoungJun Cho]

This patch adds sysreg property to fimd device node
which is required to use I80 interface.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 arch/arm/boot/dts/exynos4.dtsi |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 2f8bcd0..abfcbe2 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -534,6 +534,7 @@
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
+   samsung,sysreg = <&sys_reg>;
status = "disabled";
};
 };
-- 
1.7.9.5

[PATCH v4 10/14] drm/panel: add S6E3FA0 driver

[YoungJun Cho]

This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/panel/Kconfig |7 +
 drivers/gpu/drm/panel/Makefile|1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c |  568 +
 3 files changed, 576 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 4ec874d..be1392e 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -30,4 +30,11 @@ config DRM_PANEL_S6E8AA0
select DRM_MIPI_DSI
select VIDEOMODE_HELPERS

+config DRM_PANEL_S6E3FA0
+   tristate "S6E3FA0 DSI command mode panel"
+   depends on DRM && DRM_PANEL
+   depends on OF
+   select DRM_MIPI_DSI
+   select VIDEOMODE_HELPERS
+
 endmenu
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 8b92921..85c6738 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_LD9040) += panel-ld9040.o
 obj-$(CONFIG_DRM_PANEL_S6E8AA0) += panel-s6e8aa0.o
+obj-$(CONFIG_DRM_PANEL_S6E3FA0) += panel-s6e3fa0.o
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c 
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
new file mode 100644
index 000..5373ba7
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-s6e3fa0.c
@@ -0,0 +1,568 @@
+/*
+ * MIPI DSI command mode based s6e3fa0 AMOLED LCD 5.7 inch drm panel driver.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd
+ *
+ * YoungJun Cho 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+/* Manufacturer Command Set */
+#define MCS_GLOBAL_PARAMETER   0xb0
+#define MCS_AID0xb2
+#define MCS_ELVSSOPT   0xb6
+#define MCS_TEMPERATURE_SET0xb8
+#define MCS_PENTILE_CTRL   0xc0
+#define MCS_GAMMA_MODE 0xca
+#define MCS_VDDM   0xd7
+#define MCS_ALS0xe3
+#define MCS_ERR_FG 0xed
+#define MCS_KEY_LEV1   0xf0
+#define MCS_PANEL_UPDATE   0xf7
+#define MCS_KEY_LEV2   0xfc
+#define MCS_RE 0xfe
+#define MCS_TOUT2_HSYNC0xff
+
+/* Content Adaptive Brightness Control */
+#define DCS_WRITE_CABC 0x55
+
+#define MTP_ID_LEN 3
+#define GAMMA_LEVEL_NUM30
+
+#define DEFAULT_VDDM_VAL   0x15
+
+struct s6e3fa0 {
+   struct device   *dev;
+   struct drm_panelpanel;
+
+   struct regulator_bulk_data  supplies[2];
+   struct gpio_desc*reset_gpio;
+   struct gpio_desc*det_gpio;
+   struct gpio_desc*te_gpio;
+   struct videomodevm;
+
+   unsigned intpower_on_delay;
+   unsigned intreset_delay;
+   unsigned intinit_delay;
+   unsigned intwidth_mm;
+   unsigned intheight_mm;
+
+   unsigned char   id;
+   unsigned char   vddm;
+   unsigned intbrightness;
+};
+
+#define panel_to_s6e3fa0(p) container_of(p, struct s6e3fa0, panel)
+
+/* VDD Memory Lookup Table contains pairs of {ReadValue, WriteValue} */
+static const unsigned char s6e3fa0_vddm_lut[][2] = {
+   {0x00, 0x0d}, {0x01, 0x0d}, {0x02, 0x0e}, {0x03, 0x0f}, {0x04, 0x10},
+   {0x05, 0x11}, {0x06, 0x12}, {0x07, 0x13}, {0x08, 0x14}, {0x09, 0x15},
+   {0x0a, 0x16}, {0x0b, 0x17}, {0x0c, 0x18}, {0x0d, 0x19}, {0x0e, 0x1a},
+   {0x0f, 0x1b}, {0x10, 0x1c}, {0x11, 0x1d}, {0x12, 0x1e}, {0x13, 0x1f},
+   {0x14, 0x20}, {0x15, 0x21}, {0x16, 0x22}, {0x17, 0x23}, {0x18, 0x24},
+   {0x19, 0x25}, {0x1a, 0x26}, {0x1b, 0x27}, {0x1c, 0x28}, {0x1d, 0x29},
+   {0x1e, 0x2a}, {0x1f, 0x2b}, {0x20, 0x2c}, {0x21, 0x2d}, {0x22, 0x2e},
+   {0x23, 0x2f}, {0x24, 0x30}, {0x25, 0x31}, {0x26, 0x32}, {0x27, 0x33},
+   {0x28, 0x34}, {0x29, 0x35}, {0x2a, 0x36}, {0x2b, 0x37}, {0x2c, 0x38},
+   {0x2d, 0x39}, {0x2e, 0x3a}, {0x2f, 0x3b}, {0x30, 0x3c}, {0x31, 0x3d},
+   {0x32, 0x3e}, {0x33, 0x3f}, {0x34, 0x3f}, {0x35, 0x3f}, {0x36, 0x3f},
+   {0x37, 0x3f}, {0x38, 0x3f}, {0x39, 0x3f}, {0x3a, 0x3f}, {0x3b, 0x3f},
+   {0x3c, 0x3f}, {0x3d, 0x3f}, {0x3e, 0x3f}, {0x3f, 0x3f}, {0x40, 0x0c},
+   {0x41, 0x0b}, {0x42, 0x0a}, {0x43, 0x09}, {0x44, 0x08}, {0x45, 0x07},
+   {0x46, 0x06}, {0x47, 

[PATCH v4 09/14] ARM: dts: s6e3fa0: add DT bindings

[YoungJun Cho]

This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |   46 
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt

diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt 
b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
new file mode 100644
index 000..2cd32f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
@@ -0,0 +1,46 @@
+Samsung S6E3FA0 AMOLED LCD 5.7 inch panel
+
+Required properties:
+  - compatible: "samsung,s6e3fa0"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - det-gpios: a GPIO spec for the OLED detection pin
+  - te-gpios: a GPIO spec for the TE pin
+  - display-timings: timings for the connected panel as described by [1]
+
+Optional properties:
+
+The device node can contain one 'port' child node with one child 'endpoint'
+node, according to the bindings defined in [2]. This node should describe
+panel's video bus.
+
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   panel at 0 {
+   compatible = "samsung,s6e3fa0";
+   reg = <0>;
+   vdd3-supply = <&vcclcd_reg>;
+   vci-supply = <&vlcd_reg>;
+   reset-gpios = <&gpy7 4 0>;
+   det-gpios = <&gpg0 6 0>;
+   te-gpios = <&gpd1 7 0>;
+
+   display-timings {
+   timings0 {
+   clock-frequency = <0>;
+   hactive = <1080>;
+   vactive = <1920>;
+   hfront-porch = <2>;
+   hback-porch = <2>;
+   hsync-len = <1>;
+   vfront-porch = <1>;
+   vback-porch = <4>;
+   vsync-len = <1>;
+   };
+   };
+   };
-- 
1.7.9.5

[PATCH v4 08/14] drm/exynos: dsi: add driver data to support Exynos5420

[YoungJun Cho]

The offset of register DSIM_PLLTMR_REG in Exynos5420 is
different from the one in Exynos4 SoC.

In case of Exynos5420 SoC, there is no frequency band bit
in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this patch adds driver data to distinguish it.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c |  157 ++-
 1 file changed, 135 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index db760d8..c348392 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -17,6 +17,7 @@

 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -55,9 +56,12 @@

 /* FIFO memory AC characteristic register */
 #define DSIM_PLLCTRL_REG   0x4c/* PLL control register */
-#define DSIM_PLLTMR_REG0x50/* PLL timer register */
 #define DSIM_PHYACCHR_REG  0x54/* D-PHY AC characteristic register */
 #define DSIM_PHYACCHR1_REG 0x58/* D-PHY AC characteristic register1 */
+#define DSIM_PHYCTRL_REG   0x5c
+#define DSIM_PHYTIMING_REG 0x64
+#define DSIM_PHYTIMING1_REG0x68
+#define DSIM_PHYTIMING2_REG0x6c

 /* DSIM_STATUS */
 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
@@ -201,6 +205,24 @@
 #define DSIM_PLL_M(x)  ((x) << 4)
 #define DSIM_PLL_S(x)  ((x) << 1)

+/* DSIM_PHYCTRL */
+#define DSIM_PHYCTRL_ULPS_EXIT(x)  (((x) & 0x1ff) << 0)
+
+/* DSIM_PHYTIMING */
+#define DSIM_PHYTIMING_LPX(x)  ((x) << 8)
+#define DSIM_PHYTIMING_HS_EXIT(x)  ((x) << 0)
+
+/* DSIM_PHYTIMING1 */
+#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
+#define DSIM_PHYTIMING1_CLK_ZERO(x)((x) << 16)
+#define DSIM_PHYTIMING1_CLK_POST(x)((x) << 8)
+#define DSIM_PHYTIMING1_CLK_TRAIL(x)   ((x) << 0)
+
+/* DSIM_PHYTIMING2 */
+#define DSIM_PHYTIMING2_HS_PREPARE(x)  ((x) << 16)
+#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
+#define DSIM_PHYTIMING2_HS_TRAIL(x)((x) << 0)
+
 #define DSI_MAX_BUS_WIDTH  4
 #define DSI_NUM_VIRTUAL_CHANNELS   4
 #define DSI_TX_FIFO_SIZE   2048
@@ -234,6 +256,12 @@ struct exynos_dsi_transfer {
 #define DSIM_STATE_INITIALIZED BIT(1)
 #define DSIM_STATE_CMD_LPM BIT(2)

+struct exynos_dsi_driver_data {
+   unsigned int plltmr_reg;
+
+   unsigned int has_freqband:1;
+};
+
 struct exynos_dsi {
struct mipi_dsi_host dsi_host;
struct drm_connector connector;
@@ -263,11 +291,39 @@ struct exynos_dsi {

spinlock_t transfer_lock; /* protects transfer_list */
struct list_head transfer_list;
+
+   struct exynos_dsi_driver_data *driver_data;
 };

 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)

+static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
+   .plltmr_reg = 0x50,
+   .has_freqband = 1,
+};
+
+static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
+   .plltmr_reg = 0x58,
+};
+
+static struct of_device_id exynos_dsi_of_match[] = {
+   { .compatible = "samsung,exynos4210-mipi-dsi",
+ .data = &exynos4_dsi_driver_data },
+   { .compatible = "samsung,exynos5420-mipi-dsi",
+ .data = &exynos5_dsi_driver_data },
+   { }
+};
+
+static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
+   struct platform_device *pdev)
+{
+   const struct of_device_id *of_id =
+   of_match_device(exynos_dsi_of_match, &pdev->dev);
+
+   return (struct exynos_dsi_driver_data *)of_id->data;
+}
+
 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
 {
if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
@@ -341,14 +397,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct 
exynos_dsi *dsi,
 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
unsigned long freq)
 {
-   static const unsigned long freq_bands[] = {
-   100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
-   270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
-   510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
-   770 * MHZ, 870 * MHZ, 950 * MHZ,
-   };
+   struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
unsigned long fin, fout;
-   int timeout, band;
+   int timeout;
u8 p, s;
u16 m;
u32 reg;
@@ -369,18 +420,30 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi 
*dsi,
"failed to find PLL PMS for requested frequency\n");
  

[PATCH v4 07/14] ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings

[YoungJun Cho]

This patch adds relevant to exynos5420 compatible
for exynos5420 SoC support.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/video/exynos_dsim.txt  |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt 
b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 33b5730..29bf3b2 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -1,7 +1,9 @@
 Exynos MIPI DSI Master

 Required properties:
-  - compatible: "samsung,exynos4210-mipi-dsi"
+  - compatible: value should be one of the following
+   "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
+   "samsung,exynos5420-mipi-dsi" /* for Exynos5420 SoCs */
   - reg: physical base address and length of the registers set for the device
   - interrupts: should contain DSI interrupt
   - clocks: list of clock specifiers, must contain an entry for each required
-- 
1.7.9.5

[PATCH v4 06/14] drm/exynos: fimd: support LCD I80 interface

[YoungJun Cho]

To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster than the original one to
  generate frame done IRQ prior to the next TE signal.
- Implements trigger feature that transfers image data if there is page
  flip request, and implements TE handler to call trigger function.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/Kconfig   |1 +
 drivers/gpu/drm/exynos/exynos_drm_fimd.c |  287 +-
 include/video/samsung_fimd.h |3 +-
 3 files changed, 247 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 178d2a9..9ba1aae 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -28,6 +28,7 @@ config DRM_EXYNOS_FIMD
bool "Exynos DRM FIMD"
depends on DRM_EXYNOS && !FB_S3C
select FB_MODE_HELPERS
+   select MFD_SYSCON
help
  Choose this option if you want to use Exynos FIMD for DRM.

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c 
b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index bb45ab2..589017c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -20,6 +20,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 #include 
 #include 
@@ -61,6 +63,24 @@
 /* color key value register for hardware window 1 ~ 4. */
 #define WKEYCON1_BASE(x)   ((WKEYCON1 + 0x140) + ((x - 1) * 8))

+/* I80 / RGB trigger control register */
+#define TRIGCON0x1A4
+#define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
+#define SWTRGCMD_I80_RGB_ENABLE(1 << 1)
+
+/* display mode change control register except exynos4 */
+#define VIDOUT_CON 0x000
+#define VIDOUT_CON_F_I80_LDI0  (0x2 << 8)
+
+/* I80 interface control for main LDI register */
+#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
+#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
+#define LCD_CS_SETUP(x)((x) << 16)
+#define LCD_WR_SETUP(x)((x) << 12)
+#define LCD_WR_ACTIVE(x)   ((x) << 8)
+#define LCD_WR_HOLD(x) ((x) << 4)
+#define I80IFEN_ENABLE (1 << 0)
+
 /* FIMD has totally five hardware windows. */
 #define WINDOWS_NR 5

@@ -68,10 +88,14 @@

 struct fimd_driver_data {
unsigned int timing_base;
+   unsigned int lcdblk_off;
+   unsigned int lcdblk_vt_shift;
+   unsigned int lcdblk_bypass_shift;

unsigned int has_shadowcon:1;
unsigned int has_clksel:1;
unsigned int has_limited_fmt:1;
+   unsigned int has_vidoutcon:1;
 };

 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
@@ -82,12 +106,19 @@ static struct fimd_driver_data s3c64xx_fimd_driver_data = {

 static struct fimd_driver_data exynos4_fimd_driver_data = {
.timing_base = 0x0,
+   .lcdblk_off = 0x210,
+   .lcdblk_vt_shift = 10,
+   .lcdblk_bypass_shift = 1,
.has_shadowcon = 1,
 };

 static struct fimd_driver_data exynos5_fimd_driver_data = {
.timing_base = 0x2,
+   .lcdblk_off = 0x214,
+   .lcdblk_vt_shift = 24,
+   .lcdblk_bypass_shift = 15,
.has_shadowcon = 1,
+   .has_vidoutcon = 1,
 };

 struct fimd_win_data {
@@ -112,15 +143,23 @@ struct fimd_context {
struct clk  *bus_clk;
struct clk  *lcd_clk;
void __iomem*regs;
+   struct regmap   *sysreg;
struct drm_display_mode mode;
struct fimd_win_datawin_data[WINDOWS_NR];
unsigned intdefault_win;
unsigned long   irq_flags;
+   u32 vidcon0;
u32 vidcon1;
+   u32 vidout_con;
+   u32 i80ifcon;
+   booli80_if;
boolsuspended;
int pipe;
wait_queue_head_t   wait_vsync_queue;
atomic_twait_vsync_event;
+   atomic_twin_updated;
+   atomic_ttriggering;
+   spinlock_t  win_updated_lock;

struct exynos_drm_panel_info panel;
struct fimd_driver_data *driver_data;
@@ -243,6 +282,14 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
unsigned long ideal_clk = mode->htota

[PATCH v4 05/14] drm/exynos: dsi: add TE handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the DSI host calls this handler
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c |   13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index df2d23d..db760d8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -24,6 +24,7 @@
 #include 
 #include 

+#include "exynos_drm_crtc.h"
 #include "exynos_drm_drv.h"

 /* returns true iff both arguments logically differs */
@@ -1033,10 +1034,22 @@ static ssize_t exynos_dsi_host_transfer(struct 
mipi_dsi_host *host,
return (ret < 0) ? ret : xfer.rx_done;
 }

+static int exynos_dsi_host_te_handler(struct mipi_dsi_host *host)
+{
+   struct exynos_dsi *dsi = host_to_dsi(host);
+   struct drm_encoder *encoder = dsi->encoder;
+
+   if (!(dsi->state & DSIM_STATE_ENABLED))
+   return -EPERM;
+
+   return exynos_drm_crtc_te_handler(encoder->crtc);
+}
+
 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
.attach = exynos_dsi_host_attach,
.detach = exynos_dsi_host_detach,
.transfer = exynos_dsi_host_transfer,
+   .te_handler = exynos_dsi_host_te_handler,
 };

 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
-- 
1.7.9.5

[PATCH v4 04/14] drm/exynos: add TE handler to support LCD I80 interface

[YoungJun Cho]

To support LCD I80 interface, the panel should generates
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls this handler
chains to notify it to the display controller.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c |   11 +++
 drivers/gpu/drm/exynos/exynos_drm_crtc.h |7 +++
 drivers/gpu/drm/exynos/exynos_drm_drv.h  |3 +++
 include/drm/drm_mipi_dsi.h   |8 
 4 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 3bf091d..504e023 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -511,3 +511,14 @@ int exynos_drm_crtc_get_pipe_from_type(struct drm_device 
*drm_dev,

return -EPERM;
 }
+
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc)
+{
+   struct exynos_drm_manager *manager = to_exynos_crtc(crtc)->manager;
+   int ret = 0;
+
+   if (manager->ops->te_handler)
+   ret = manager->ops->te_handler(manager);
+
+   return ret;
+}
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
index 9f74b10..875d93d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h
@@ -36,4 +36,11 @@ void exynos_drm_crtc_plane_disable(struct drm_crtc *crtc, 
int zpos);
 int exynos_drm_crtc_get_pipe_from_type(struct drm_device *drm_dev,
unsigned int out_type);

+/*
+ * This function calls the crtc device(manager)'s te_handler() callback
+ * to trigger to transfer video image at the tearing effect synchronization
+ * signal.
+ */
+int exynos_drm_crtc_te_handler(struct drm_crtc *crtc);
+
 #endif
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h 
b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 36535f3..ab3a88d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -188,6 +188,8 @@ struct exynos_drm_display {
  * @win_commit: apply hardware specific overlay data to registers.
  * @win_enable: enable hardware specific overlay.
  * @win_disable: disable hardware specific overlay.
+ * @te_handler: trigger to transfer video image at the tearing effect
+ * synchronization signal if there is a page flip request.
  */
 struct exynos_drm_manager;
 struct exynos_drm_manager_ops {
@@ -206,6 +208,7 @@ struct exynos_drm_manager_ops {
void (*win_commit)(struct exynos_drm_manager *mgr, int zpos);
void (*win_enable)(struct exynos_drm_manager *mgr, int zpos);
void (*win_disable)(struct exynos_drm_manager *mgr, int zpos);
+   int (*te_handler)(struct exynos_drm_manager *mgr);
 };

 /*
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 7209df1..f6d4c85 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/include/drm/drm_mipi_dsi.h
@@ -49,6 +49,13 @@ struct mipi_dsi_msg {
  * @detach: detach DSI device from DSI host
  * @transfer: send and/or receive DSI packet, return number of received bytes,
  *   or error
+ * @te_handler: call the crtc te_handler() callback from DSI host.
+ * The panel generates tearing effect synchronization signal
+ * between MCU and FB to display video images.
+ * And the display controller should trigger to transfer video
+ * image at this signal.
+ * So the panel receives the TE IRQ, then calls this handler
+ * to notify it to the display controller.
  */
 struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -57,6 +64,7 @@ struct mipi_dsi_host_ops {
  struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
+   int (*te_handler)(struct mipi_dsi_host *host);
 };

 /**
-- 
1.7.9.5

[PATCH v4 03/14] ARM: dts: samsung-fimd: add LCD I80 interface specific properties

[YoungJun Cho]

In case of using MIPI DSI based I80 interface panel,
the relevant registers should be set.
So this patch adds relevant DT bindings.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
---
 .../devicetree/bindings/video/samsung-fimd.txt |   28 
 1 file changed, 28 insertions(+)

diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt 
b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b..59ff61e 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -44,6 +44,34 @@ Optional Properties:
 - display-timings: timing settings for FIMD, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
+- samsung,sysreg: handle to syscon used to control the system registers
+- i80-if-timings: timing configuration for lcd i80 interface support.
+  - cs-setup: clock cycles for the active period of address signal is enabled
+  until chip select is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-setup: clock cycles for the active period of CS signal is enabled until
+  write signal is enabled.
+  If not specified, the default value(0) will be used.
+  - wr-active: clock cycles for the active period of CS is enabled.
+   If not specified, the default value(1) will be used.
+  - wr-hold: clock cycles for the active period of CS is disabled until write
+ signal is disabled.
+ If not specified, the default value(0) will be used.
+
+  The parameters are defined as:
+
+VCLK(internal)  __|??|_|??|_|??|_|??|_|??
+  :::::
+Address Output  --:|:::
+Chip Select ???|::|??
+   | wr-setup+1 || wr-hold+1  |
+   |<-->||<-->|
+Write Enable||???
+| wr-active+1|
+|<-->|
+Video Data  --

 The device node can contain 'port' child nodes according to the bindings 
defined
 in [2]. The following are properties specific to those nodes:
-- 
1.7.9.5

[PATCH v4 02/14] drm/exynos: use wait_event_timeout() for safety usage

[YoungJun Cho]

There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc->pending_flip in exynos_drm_crtc_page_flip()
when exynos_drm_crtc_mode_set_commit() is failed.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_crtc.c |7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 95c9435..3bf091d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -69,8 +69,10 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int 
mode)

if (mode > DRM_MODE_DPMS_ON) {
/* wait for the completion of page flip. */
-   wait_event(exynos_crtc->pending_flip_queue,
-   atomic_read(&exynos_crtc->pending_flip) == 0);
+   if (!wait_event_timeout(exynos_crtc->pending_flip_queue,
+   !atomic_read(&exynos_crtc->pending_flip),
+   HZ/20))
+   atomic_set(&exynos_crtc->pending_flip, 0);
drm_vblank_off(crtc->dev, exynos_crtc->pipe);
}

@@ -259,6 +261,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
spin_lock_irq(&dev->event_lock);
drm_vblank_put(dev, exynos_crtc->pipe);
list_del(&event->base.link);
+   atomic_set(&exynos_crtc->pending_flip, 0);
spin_unlock_irq(&dev->event_lock);

goto out;
-- 
1.7.9.5

[PATCH v4 01/14] drm/exynos: dsi: move the EoT packets configuration point

[YoungJun Cho]

This configuration could be used in MIPI DSI command mode also.

Signed-off-by: YoungJun Cho 
Acked-by: Inki Dae 
Acked-by: Kyungmin Park 
Reviewed-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos_drm_dsi.c |5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
index 6302aa6..df2d23d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
@@ -473,8 +473,6 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)

if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
reg |= DSIM_MFLUSH_VS;
-   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
-   reg |= DSIM_EOT_DISABLE;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
reg |= DSIM_SYNC_INFORM;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
@@ -491,6 +489,9 @@ static int exynos_dsi_init_link(struct exynos_dsi *dsi)
reg |= DSIM_HSA_MODE;
}

+   if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+   reg |= DSIM_EOT_DISABLE;
+
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
-- 
1.7.9.5

[PATCH v4 00/14] drm/exynos: support LCD I80 interface display

[YoungJun Cho]

Hi,

This series adds LCD I80 interface display support for Exynos DRM driver.
The FIMD(display controller) specification describes it as "LCD I80 interface"
and the DSI specification describes it as "Command mode interface".

This is based on exynos-drm-next branch.

The previous patches,
RFC: http://www.spinics.net/lists/dri-devel/msg58898.html
V1: http://www.spinics.net/lists/dri-devel/msg59291.html
V2: http://www.spinics.net/lists/dri-devel/msg59867.html
V3: http://www.spinics.net/lists/dri-devel/msg60708.html

Changelog v2:
- Fixes typo and removes unnecessary error log (commented by Andrzej Hazda)
- Adds missed pendlig_flip flag clear points (commented by Daniel Kurtz)

Changelog v3:
- Removes generic command mode and command mode display timing interface.
- Moves I80 interface timings from panel DT to the FIMD(display controller) DT.

Changelog v4:
- Removes exynos5 sysreg(syscon) DT bindings and node from dtsi because
  it was already updated by linux-samsung-soc (commented by Vivek Gautam)

Patches 1 and 2 fix trivial bugs.

Patches 3, 4, 5 and 6 implement FIMD(display controller) I80 interface.
The MIPI DSI command mode based panel generates Tearing Effect synchronization
signal between MCU and FB to display video image, and FIMD should trigger to
transfer video image at this signal.
So the panel should receive the TE IRQ and call TE handler chains to notify
it to the FIMD.

Patches 7 and 8 implement to use Exynos5420 SoC DSI driver which is different
from previous Exynos4 SoCs for some registers control.

Patches 9 and 10 introduce MIPI DSI command mode based Samsung S6E3FA0 AMOLED
5.7" LCD drm panel driver.

The ohters add DT property nodes to support MIPI DSI command mode.

I welcome any comments.

Thank you.
Best regards YJ

YoungJun Cho (14):
  drm/exynos: dsi: move the EoT packets configuration point
  drm/exynos: use wait_event_timeout() for safety usage
  ARM: dts: samsung-fimd: add LCD I80 interface specific properties
  drm/exynos: add TE handler to support LCD I80 interface
  drm/exynos: dsi: add TE handler to support LCD I80 interface
  drm/exynos: fimd: support LCD I80 interface
  ARM: dts: exynos_dsim: add exynos5420 compatible to DT bindings
  drm/exynos: dsi: add driver data to support Exynos5420
  ARM: dts: s6e3fa0: add DT bindings
  drm/panel: add S6E3FA0 driver
  ARM: dts: exynos4: add system register property
  ARM: dts: exynos5: add system register property
  ARM: dts: exynos5420: add mipi-phy node
  ARM: dts: exynos5420: add dsi node

 .../devicetree/bindings/panel/samsung,s6e3fa0.txt  |   46 ++
 .../devicetree/bindings/video/exynos_dsim.txt  |4 +-
 .../devicetree/bindings/video/samsung-fimd.txt |   28 +
 arch/arm/boot/dts/exynos4.dtsi |1 +
 arch/arm/boot/dts/exynos5.dtsi |1 +
 arch/arm/boot/dts/exynos5420.dtsi  |   20 +
 drivers/gpu/drm/exynos/Kconfig |1 +
 drivers/gpu/drm/exynos/exynos_drm_crtc.c   |   18 +-
 drivers/gpu/drm/exynos/exynos_drm_crtc.h   |7 +
 drivers/gpu/drm/exynos/exynos_drm_drv.h|3 +
 drivers/gpu/drm/exynos/exynos_drm_dsi.c|  175 +-
 drivers/gpu/drm/exynos/exynos_drm_fimd.c   |  287 --
 drivers/gpu/drm/panel/Kconfig  |7 +
 drivers/gpu/drm/panel/Makefile |1 +
 drivers/gpu/drm/panel/panel-s6e3fa0.c  |  568 
 include/drm/drm_mipi_dsi.h |8 +
 include/video/samsung_fimd.h   |3 +-
 17 files changed, 1107 insertions(+), 71 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/panel/samsung,s6e3fa0.txt
 create mode 100644 drivers/gpu/drm/panel/panel-s6e3fa0.c

-- 
1.7.9.5

[PATCH v3 13/15] ARM: dts: exynos5: add system register support

[YoungJun Cho]

Hi Vivek,

On 06/04/2014 08:50 PM, Vivek Gautam wrote:
> On Mon, Jun 2, 2014 at 10:52 AM, YoungJun Cho  wrote:
>> This patch adds sysreg device node, and sysreg property
>> to fimd device node which is required to use I80 interface.
>
> Same here. The system register nodes have been added to exynos5250 and
> exynos5420 by the patch:
> dfbbdbf ARM: dts: Add sysreg sytem controller node to exynos5250 and 
> exynos5420
>
> May be, you may want to move those two nodes to this common file 
> (exynos5.dtsi).
>

Thank you for reporting.
I didn't check linux-samsung-soc.

The exynos5410, 5420 and 5422 use system register with base address
0x1005.
But exynos5260 and 5430 are different.
And I can't check exynos5250.

So with this condition, it is reasonable to remove these sysreg relevant
patches.

Thank you.
Best regards YJ

>>
>> Signed-off-by: YoungJun Cho 
>> Acked-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>   arch/arm/boot/dts/exynos5.dtsi |6 ++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
>> index 79d0608..95ee496 100644
>> --- a/arch/arm/boot/dts/exynos5.dtsi
>> +++ b/arch/arm/boot/dts/exynos5.dtsi
>> @@ -81,12 +81,18 @@
>>  status = "disabled";
>>  };
>>
>> +   sys_reg: syscon at 1005 {
>> +   compatible = "samsung,exynos5-sysreg", "syscon";
>> +   reg = <0x1005 0x500>;
>> +   };
>> +
>>  fimd at 1440 {
>>  compatible = "samsung,exynos5250-fimd";
>>  interrupt-parent = <&combiner>;
>>  reg = <0x1440 0x4>;
>>  interrupt-names = "fifo", "vsync", "lcd_sys";
>>  interrupts = <18 4>, <18 5>, <18 6>;
>> +   samsung,sysreg = <&sys_reg>;
>>  status = "disabled";
>>  };
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
>> in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>