[PATCH v3 0/3] Add bus format negotiation support for Cadence MHDP8546 driver
This patch series add bus format negotiation support for Cadence MHDP8546 bridge driver. The patch series has four patches in the below sequence: 1. drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function. Return all the input formats supported. 2. drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info Remove the bus format configuration using connector info structure. 3. drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format Get the pixel format and bpc based on negotiated output bus format. This patch series is dependent on tidss series [1] for the new connector model support. [1] https://patchwork.kernel.org/project/dri-devel/cover/20201201121830.29704-1-nikhil...@ti.com/ Version History: v3: - Modify the atomic_get_input_bus_fmts to return the MEDIA_BUS_FMT_RGB121212_1X36 as default format.along as tidss currently supports only this format. v2: - Remove the Add output bus format negotiation patch from the series, as we use ouput format as MEDIA_BUS_FMT_FIXED and that is the default value if atomic_get_output_bus_fmts function is not implemented. - Return NULL if output format is not MEDIA_BUS_FMT_FIXED. - Return the supported color formats based on the display info structure. Yuti Amonkar (3): drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format .../drm/bridge/cadence/cdns-mhdp8546-core.c | 171 ++ 1 file changed, 138 insertions(+), 33 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 3/3] drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format
Get the pixel format and bpc based on the output bus format
negotiated instead of hardcoding the values.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 82 +++
1 file changed, 64 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index d9f7eb8249e8..2ad5cad46599 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1530,24 +1530,8 @@ static int cdns_mhdp_get_modes(struct drm_connector
*connector)
drm_connector_update_edid_property(connector, edid);
num_modes = drm_add_edid_modes(connector, edid);
- kfree(edid);
- /*
-* HACK: Warn about unsupported display formats until we deal
-* with them correctly.
-*/
- if (connector->display_info.color_formats &&
- !(connector->display_info.color_formats &
- mhdp->display_fmt.color_format))
- dev_warn(mhdp->dev,
-"%s: No supported color_format found (0x%08x)\n",
- __func__, connector->display_info.color_formats);
-
- if (connector->display_info.bpc &&
- connector->display_info.bpc < mhdp->display_fmt.bpc)
- dev_warn(mhdp->dev, "%s: Display bpc only %d < %d\n",
-__func__, connector->display_info.bpc,
-mhdp->display_fmt.bpc);
+ kfree(edid);
return num_modes;
}
@@ -1706,6 +1690,66 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
return 0;
}
+static void cdns_mhdp_get_display_fmt(struct cdns_mhdp_device *mhdp,
+ struct drm_bridge_state *state)
+{
+ u32 bus_fmt, bpc, pxlfmt;
+
+ bus_fmt = state->output_bus_cfg.format;
+ switch (bus_fmt) {
+ case MEDIA_BUS_FMT_RGB161616_1X48:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 16;
+ break;
+ case MEDIA_BUS_FMT_YUV16_1X48:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 16;
+ break;
+ case MEDIA_BUS_FMT_RGB121212_1X36:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_UYVY12_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_YUV12_1X36:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 8;
+ break;
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 8;
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 8;
+ break;
+ default:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 8;
+ }
+
+ mhdp->display_fmt.color_format = pxlfmt;
+ mhdp->display_fmt.bpc = bpc;
+}
+
static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,
const struct drm_display_mode *mode)
{
@@ -2186,6 +2230,8 @@ static int cdns_mhdp_atomic_check(struct drm_bridge
*bridge,
struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
const struct drm_display_mode *mode = _state->adjusted_mode;
+ cdns_mhdp_get_display_fmt(mhdp, bridge_state);
+
mutex_lock(>link_mutex);
if (!cdns_mhdp_bandwidth_ok(mhdp, mode, mhdp->link.num_lanes,
@@ -2499,7 +2545,7 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
mhdp->link.rate = mhdp->host.link_rate;
mhdp->link.num_lanes = mhdp->host.lanes_cnt;
- /* The only currently supported format */
+ /* Initialize color format bpc and y_only to default values*/
mhdp->display_fmt.y_only = false;
mhdp->display_fmt.color_format = DRM_COLOR_FORMAT_RGB444;
mhdp->display_fmt.bpc = 8;
--
2.17.1
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[PATCH v3 1/3] drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function
Modify atomic_get_input_bus_format function to return input formats
supported instead of using hardcoded value.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 83 +--
1 file changed, 74 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index d0ed950f4f87..5ef6adb8bc82 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -2095,27 +2095,92 @@ cdns_mhdp_bridge_atomic_reset(struct drm_bridge *bridge)
return _mhdp_state->base;
}
+#define MAX_INPUT_FORMAT 11
+
static u32 *cdns_mhdp_get_input_bus_fmts(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state,
- u32 output_fmt,
- unsigned int *num_input_fmts)
-{
+struct drm_bridge_state *bridge_state,
+struct drm_crtc_state *crtc_state,
+struct drm_connector_state *conn_state,
+u32 output_fmt,
+unsigned int *num_input_fmts)
+{
+ struct drm_connector *conn = conn_state->connector;
+ struct drm_display_info *info = >display_info;
u32 *input_fmts;
u32 default_bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
+ unsigned int i = 0;
*num_input_fmts = 0;
if (output_fmt != MEDIA_BUS_FMT_FIXED)
return NULL;
- input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL);
+ input_fmts = kcalloc(MAX_INPUT_FORMAT,
+sizeof(*input_fmts), GFP_KERNEL);
if (!input_fmts)
return NULL;
- *num_input_fmts = 1;
- input_fmts[0] = default_bus_format;
+ input_fmts[i++] = default_bus_format;
+
+ if (info->color_formats & DRM_COLOR_FORMAT_RGB444) {
+ if (info->bpc == 16) {
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ }
+
+ if (info->bpc == 12) {
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ }
+
+ if (info->bpc == 10) {
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ }
+
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ }
+
+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
+ if (info->bpc == 16) {
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ }
+
+ if (info->bpc == 12) {
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ }
+
+ if (info->bpc == 10) {
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ }
+
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ }
+
+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
+ if (info->bpc == 12) {
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+ }
+
+ if (info->bpc == 10) {
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+ }
+
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+ }
+
+ *num_input_fmts = i;
+
return input_fmts;
}
--
2.17.1
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[PATCH v3 2/3] drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info
As we are using bus negotiations for selecting bus format
remove the setting of bus format using the connector info
structure.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 5ef6adb8bc82..d9f7eb8249e8 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1648,7 +1648,6 @@ static const struct drm_connector_funcs
cdns_mhdp_conn_funcs = {
static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp)
{
- u32 bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
struct drm_connector *conn = >connector;
struct drm_bridge *bridge = >bridge;
int ret;
@@ -1669,11 +1668,6 @@ static int cdns_mhdp_connector_init(struct
cdns_mhdp_device *mhdp)
drm_connector_helper_add(conn, _mhdp_conn_helper_funcs);
- ret = drm_display_info_set_bus_formats(>display_info,
- _format, 1);
- if (ret)
- return ret;
-
ret = drm_connector_attach_encoder(conn, bridge->encoder);
if (ret) {
dev_err(mhdp->dev, "Failed to attach connector to encoder\n");
--
2.17.1
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[PATCH v2 0/3] Add bus format negotiation support for Cadence MHDP8546 driver
This patch series add bus format negotiation support for Cadence MHDP8546 bridge driver. The patch series has four patches in the below sequence: 1. drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function. Return all the input formats supported. 2. drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info Remove the bus format configuration using connector info structure. 3. drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format Get the pixel format and bpc based on negotiated output bus format. This patch series is dependent on tidss series [1] for the new connector model support. [1] https://patchwork.kernel.org/project/dri-devel/cover/20201109170601.21557-1-nikhil...@ti.com/ Version History: v2: - Remove the Add output bus format negotiation patch from the series, as we use ouput format as MEDIA_BUS_FMT_FIXED and that is the default value if atomic_get_output_bus_fmts function is not implemented. - Return NULL if output format is not MEDIA_BUS_FMT_FIXED. - Return the supported color formats based on the display info structure. Yuti Amonkar (3): drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format .../drm/bridge/cadence/cdns-mhdp8546-core.c | 133 +- 1 file changed, 99 insertions(+), 34 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 3/3] drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format
Get the pixel format and bpc based on the output bus format
negotiated instead of hardcoding the values.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 82 +++
1 file changed, 64 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index d5e94bd74df1..e1f4bbd09816 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1512,24 +1512,8 @@ static int cdns_mhdp_get_modes(struct drm_connector
*connector)
drm_connector_update_edid_property(connector, edid);
num_modes = drm_add_edid_modes(connector, edid);
- kfree(edid);
- /*
-* HACK: Warn about unsupported display formats until we deal
-* with them correctly.
-*/
- if (connector->display_info.color_formats &&
- !(connector->display_info.color_formats &
- mhdp->display_fmt.color_format))
- dev_warn(mhdp->dev,
-"%s: No supported color_format found (0x%08x)\n",
- __func__, connector->display_info.color_formats);
-
- if (connector->display_info.bpc &&
- connector->display_info.bpc < mhdp->display_fmt.bpc)
- dev_warn(mhdp->dev, "%s: Display bpc only %d < %d\n",
-__func__, connector->display_info.bpc,
-mhdp->display_fmt.bpc);
+ kfree(edid);
return num_modes;
}
@@ -1689,6 +1673,66 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
return 0;
}
+static void cdns_mhdp_get_display_fmt(struct cdns_mhdp_device *mhdp,
+ struct drm_bridge_state *state)
+{
+ u32 bus_fmt, bpc, pxlfmt;
+
+ bus_fmt = state->output_bus_cfg.format;
+ switch (bus_fmt) {
+ case MEDIA_BUS_FMT_RGB161616_1X48:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 16;
+ break;
+ case MEDIA_BUS_FMT_YUV16_1X48:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 16;
+ break;
+ case MEDIA_BUS_FMT_RGB121212_1X36:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_UYVY12_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_YUV12_1X36:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 8;
+ break;
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 8;
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 8;
+ break;
+ default:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 8;
+ }
+
+ mhdp->display_fmt.color_format = pxlfmt;
+ mhdp->display_fmt.bpc = bpc;
+}
+
static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,
const struct drm_display_mode *mode)
{
@@ -2129,6 +2173,8 @@ static int cdns_mhdp_atomic_check(struct drm_bridge
*bridge,
struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
const struct drm_display_mode *mode = _state->adjusted_mode;
+ cdns_mhdp_get_display_fmt(mhdp, bridge_state);
+
mutex_lock(>link_mutex);
if (!cdns_mhdp_bandwidth_ok(mhdp, mode, mhdp->link.num_lanes,
@@ -2456,7 +2502,7 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
mhdp->link.rate = mhdp->host.link_rate;
mhdp->link.num_lanes = mhdp->host.lanes_cnt;
- /* The only currently supported format */
+ /* Initialize color format bpc and y_only to default values*/
mhdp->display_fmt.y_only = false;
mhdp->display_fmt.color_format = DRM_COLOR_FORMAT_RGB444;
mhdp->display_fmt.bpc = 8;
--
2.17.1
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[PATCH v2 2/3] drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info
As we are using bus negotiations for selecting bus format
remove the setting of bus format using the connector info
structure.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 7c80555ab4ab..d5e94bd74df1 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1630,7 +1630,6 @@ static const struct drm_connector_funcs
cdns_mhdp_conn_funcs = {
static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp)
{
- u32 bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
struct drm_connector *conn = >connector;
struct drm_bridge *bridge = >bridge;
int ret;
@@ -1651,11 +1650,6 @@ static int cdns_mhdp_connector_init(struct
cdns_mhdp_device *mhdp)
drm_connector_helper_add(conn, _mhdp_conn_helper_funcs);
- ret = drm_display_info_set_bus_formats(>display_info,
- _format, 1);
- if (ret)
- return ret;
-
ret = drm_connector_attach_encoder(conn, bridge->encoder);
if (ret) {
dev_err(mhdp->dev, "Failed to attach connector to encoder\n");
--
2.17.1
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[PATCH v2 1/3] drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function
Modify atomic_get_input_bus_format function to return input formats
supported instead of using hardcoded value.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 45 ++-
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 6beccd2a408e..7c80555ab4ab 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -2078,27 +2078,52 @@ cdns_mhdp_bridge_atomic_reset(struct drm_bridge *bridge)
return _mhdp_state->base;
}
+#define MAX_INPUT_FORMAT 11
+
static u32 *cdns_mhdp_get_input_bus_fmts(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state,
- u32 output_fmt,
- unsigned int *num_input_fmts)
-{
+struct drm_bridge_state *bridge_state,
+struct drm_crtc_state *crtc_state,
+struct drm_connector_state *conn_state,
+u32 output_fmt,
+unsigned int *num_input_fmts)
+{
+ struct drm_connector *conn = conn_state->connector;
+ struct drm_display_info *info = >display_info;
u32 *input_fmts;
- u32 default_bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
+ unsigned int i = 0;
*num_input_fmts = 0;
if (output_fmt != MEDIA_BUS_FMT_FIXED)
return NULL;
- input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL);
+ input_fmts = kcalloc(MAX_INPUT_FORMAT,
+sizeof(*input_fmts), GFP_KERNEL);
if (!input_fmts)
return NULL;
- *num_input_fmts = 1;
- input_fmts[0] = default_bus_format;
+ if (info->color_formats & DRM_COLOR_FORMAT_RGB444) {
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
+ }
+
+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) {
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
+ }
+
+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) {
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
+ }
+
+ *num_input_fmts = i;
+
return input_fmts;
}
--
2.17.1
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[PATCH v1 0/4] Add bus format negotiation support for Cadence MHDP8546 driver
This patch series add bus format negotiation support for Cadence MHDP8546 bridge driver. The patch series has four patches in the below sequence: 1. drm: bridge: cdns-mhdp8546: Add output bus format negotiation Add minimal output bus format negotiation support. 2. drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function. Get the input format based on output format supported. 3. drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info Remove the bus format configuration using connector info structure. 4. drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format Get the pixel format and bpc based on negotiated output bus format. This patch series is dependent on tidss series [1] for the new connector model support. [1] https://patchwork.kernel.org/project/dri-devel/cover/20201109170601.21557-1-nikhil...@ti.com/ Yuti Amonkar (4): drm: bridge: cdns-mhdp8546: Add output bus format negotiation drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format .../drm/bridge/cadence/cdns-mhdp8546-core.c | 216 +++--- 1 file changed, 182 insertions(+), 34 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 1/4] drm: bridge: cdns-mhdp8546: Add output bus format negotiation
This patch adds minimal output bus format negotiation support.
Currently we are adding support for only MEDIA_BUS_FMT_FIXED.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c| 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 6beccd2a408e..bdb0d95aa412 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -2102,6 +2102,23 @@ static u32 *cdns_mhdp_get_input_bus_fmts(struct
drm_bridge *bridge,
return input_fmts;
}
+static u32 *cdns_mhdp_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state
*conn_state,
+ unsigned int *num_output_fmts)
+{
+ u32 *output_fmts;
+
+ output_fmts = kzalloc(sizeof(*output_fmts), GFP_KERNEL);
+ if (!output_fmts)
+ return NULL;
+
+ *num_output_fmts = 1;
+ output_fmts[0] = MEDIA_BUS_FMT_FIXED;
+ return output_fmts;
+}
+
static int cdns_mhdp_atomic_check(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
struct drm_crtc_state *crtc_state,
@@ -2170,6 +2187,7 @@ static const struct drm_bridge_funcs
cdns_mhdp_bridge_funcs = {
.atomic_destroy_state = cdns_mhdp_bridge_atomic_destroy_state,
.atomic_reset = cdns_mhdp_bridge_atomic_reset,
.atomic_get_input_bus_fmts = cdns_mhdp_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts = cdns_mhdp_get_output_bus_fmts,
.detect = cdns_mhdp_bridge_detect,
.get_edid = cdns_mhdp_bridge_get_edid,
.hpd_enable = cdns_mhdp_bridge_hpd_enable,
--
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[PATCH v1 2/4] drm: bridge: cdns-mhdp8546: Modify atomic_get_input_bus_format bridge function
Modify atomic_get_input_bus_format function to return input formats
based on the output format instead of using hardcoded value.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 110 --
1 file changed, 100 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index bdb0d95aa412..623eadb8948f 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -2078,27 +2078,117 @@ cdns_mhdp_bridge_atomic_reset(struct drm_bridge
*bridge)
return _mhdp_state->base;
}
+static const u32 cdns_mhdp_bus_fmts[] = {
+ MEDIA_BUS_FMT_YUV16_1X48,
+ MEDIA_BUS_FMT_RGB161616_1X48,
+ MEDIA_BUS_FMT_UYVY12_1X24,
+ MEDIA_BUS_FMT_YUV12_1X36,
+ MEDIA_BUS_FMT_RGB121212_1X36,
+ MEDIA_BUS_FMT_UYVY10_1X20,
+ MEDIA_BUS_FMT_YUV10_1X30,
+ MEDIA_BUS_FMT_RGB101010_1X30,
+ MEDIA_BUS_FMT_UYVY8_1X16,
+ MEDIA_BUS_FMT_YUV8_1X24,
+ MEDIA_BUS_FMT_RGB888_1X24
+};
+
+static bool cdns_mhdp_format_supported(u32 output_fmt)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(cdns_mhdp_bus_fmts); i++) {
+ if (output_fmt == cdns_mhdp_bus_fmts[i])
+ return true;
+ }
+
+ return false;
+}
+
+#define MAX_INPUT_FORMAT 4
+
static u32 *cdns_mhdp_get_input_bus_fmts(struct drm_bridge *bridge,
- struct drm_bridge_state *bridge_state,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state,
- u32 output_fmt,
- unsigned int *num_input_fmts)
+struct drm_bridge_state *bridge_state,
+struct drm_crtc_state *crtc_state,
+struct drm_connector_state *conn_state,
+u32 output_fmt,
+unsigned int *num_input_fmts)
{
u32 *input_fmts;
- u32 default_bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
+ unsigned int i = 0;
*num_input_fmts = 0;
- if (output_fmt != MEDIA_BUS_FMT_FIXED)
+ if (!cdns_mhdp_format_supported(output_fmt) &&
+ output_fmt != MEDIA_BUS_FMT_FIXED)
return NULL;
- input_fmts = kzalloc(sizeof(*input_fmts), GFP_KERNEL);
+ input_fmts = kcalloc(MAX_INPUT_FORMAT,
+sizeof(*input_fmts), GFP_KERNEL);
if (!input_fmts)
return NULL;
- *num_input_fmts = 1;
- input_fmts[0] = default_bus_format;
+ switch (output_fmt) {
+ /* RGB */
+ case MEDIA_BUS_FMT_RGB161616_1X48:
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ break;
+ case MEDIA_BUS_FMT_RGB121212_1X36:
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ break;
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
+ break;
+
+ /* YUV444 */
+ case MEDIA_BUS_FMT_YUV16_1X48:
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ break;
+ case MEDIA_BUS_FMT_YUV12_1X36:
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
+ break;
+
+ /* YUV422 */
+ case MEDIA_BUS_FMT_UYVY12_1X24:
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
+ break;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+
[PATCH v1 4/4] drm: bridge: cdns-mhdp8546: Retrieve the pixel format and bpc based on bus format
Get the pixel format and bpc based on the output bus format
negotiated instead of hardcoding the values.
Signed-off-by: Yuti Amonkar
---
.../drm/bridge/cadence/cdns-mhdp8546-core.c | 82 +++
1 file changed, 64 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 6f900bceb50c..44d79b0bd6d2 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1512,24 +1512,8 @@ static int cdns_mhdp_get_modes(struct drm_connector
*connector)
drm_connector_update_edid_property(connector, edid);
num_modes = drm_add_edid_modes(connector, edid);
- kfree(edid);
- /*
-* HACK: Warn about unsupported display formats until we deal
-* with them correctly.
-*/
- if (connector->display_info.color_formats &&
- !(connector->display_info.color_formats &
- mhdp->display_fmt.color_format))
- dev_warn(mhdp->dev,
-"%s: No supported color_format found (0x%08x)\n",
- __func__, connector->display_info.color_formats);
-
- if (connector->display_info.bpc &&
- connector->display_info.bpc < mhdp->display_fmt.bpc)
- dev_warn(mhdp->dev, "%s: Display bpc only %d < %d\n",
-__func__, connector->display_info.bpc,
-mhdp->display_fmt.bpc);
+ kfree(edid);
return num_modes;
}
@@ -1689,6 +1673,66 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
return 0;
}
+static void cdns_mhdp_get_display_fmt(struct cdns_mhdp_device *mhdp,
+ struct drm_bridge_state *state)
+{
+ u32 bus_fmt, bpc, pxlfmt;
+
+ bus_fmt = state->output_bus_cfg.format;
+ switch (bus_fmt) {
+ case MEDIA_BUS_FMT_RGB161616_1X48:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 16;
+ break;
+ case MEDIA_BUS_FMT_YUV16_1X48:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 16;
+ break;
+ case MEDIA_BUS_FMT_RGB121212_1X36:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_UYVY12_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_YUV12_1X36:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 12;
+ break;
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 10;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 8;
+ break;
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB422;
+ bpc = 8;
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ pxlfmt = DRM_COLOR_FORMAT_YCRCB444;
+ bpc = 8;
+ break;
+ default:
+ pxlfmt = DRM_COLOR_FORMAT_RGB444;
+ bpc = 8;
+ }
+
+ mhdp->display_fmt.color_format = pxlfmt;
+ mhdp->display_fmt.bpc = bpc;
+}
+
static void cdns_mhdp_configure_video(struct cdns_mhdp_device *mhdp,
const struct drm_display_mode *mode)
{
@@ -2211,6 +2255,8 @@ static int cdns_mhdp_atomic_check(struct drm_bridge
*bridge,
struct cdns_mhdp_device *mhdp = bridge_to_mhdp(bridge);
const struct drm_display_mode *mode = _state->adjusted_mode;
+ cdns_mhdp_get_display_fmt(mhdp, bridge_state);
+
mutex_lock(>link_mutex);
if (!cdns_mhdp_bandwidth_ok(mhdp, mode, mhdp->link.num_lanes,
@@ -2539,7 +2585,7 @@ static int cdns_mhdp_probe(struct platform_device *pdev)
mhdp->link.rate = mhdp->host.link_rate;
mhdp->link.num_lanes = mhdp->host.lanes_cnt;
- /* The only currently supported format */
+ /* Initialize color format bpc and y_only to default values*/
mhdp->display_fmt.y_only = false;
mhdp->display_fmt.color_format = DRM_COLOR_FORMAT_RGB444;
mhdp->display_fmt.bpc = 8;
--
2.17.1
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[PATCH v1 3/4] drm: bridge: cdns-mhdp8546: Remove setting of bus format using connector info
As we are using bus negotiations for selecting bus format
remove the setting of bus format using the connector info
structure.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 623eadb8948f..6f900bceb50c 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1630,7 +1630,6 @@ static const struct drm_connector_funcs
cdns_mhdp_conn_funcs = {
static int cdns_mhdp_connector_init(struct cdns_mhdp_device *mhdp)
{
- u32 bus_format = MEDIA_BUS_FMT_RGB121212_1X36;
struct drm_connector *conn = >connector;
struct drm_bridge *bridge = >bridge;
int ret;
@@ -1651,11 +1650,6 @@ static int cdns_mhdp_connector_init(struct
cdns_mhdp_device *mhdp)
drm_connector_helper_add(conn, _mhdp_conn_helper_funcs);
- ret = drm_display_info_set_bus_formats(>display_info,
- _format, 1);
- if (ret)
- return ret;
-
ret = drm_connector_attach_encoder(conn, bridge->encoder);
if (ret) {
dev_err(mhdp->dev, "Failed to attach connector to encoder\n");
--
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[PATCH v6 3/3] drm: bridge: cdns-mhdp: add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
Signed-off-by: Jyri Sarha
Reviewed-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/Kconfig | 12
drivers/gpu/drm/bridge/Makefile | 4 ++
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 14 +
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 1 +
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 +
6 files changed, 165 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3bfabb76f2bb..ba945071bb0b 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -38,6 +38,18 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and output it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721e Display Port and sets up the
+ clock and data muxes.
+endif
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 2e2c5be7c714..fa575ad57b95 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -19,5 +19,9 @@ obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
cdns-mhdp-objs := cdns-mhdp-core.o
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ cdns-mhdp-objs += cdns-mhdp-j721e.o
+endif
+
obj-y += analogix/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
index cc642893baa8..8d07ffe2d791 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -36,8 +36,22 @@
#include "cdns-mhdp-core.h"
+#include "cdns-mhdp-j721e.h"
+
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+static const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
+ .init = cdns_mhdp_j721e_init,
+ .exit = cdns_mhdp_j721e_fini,
+ .enable = cdns_mhdp_j721e_enable,
+ .disable = cdns_mhdp_j721e_disable,
+};
+#endif
+
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+ { .compatible = "ti,j721e-mhdp8546", .data = _ti_j721e_ops },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
index f8df54917816..0878a6e3fd31 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
@@ -335,6 +335,7 @@ struct mhdp_platform_ops {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index ..a87faf55c065
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1_SEL_DPI3BIT(5)
+#define DPTX_SRC_VIF_1_SEL_DPI10
+#define DPTX_SRC_VIF_0_SEL_DPI2BIT(4)
+#define DPTX_SRC_VIF_0_SEL_DPI00
+#define DPTX_SRC_VIF_3_EN BIT(3)
+#define DPTX_SRC_VIF_2_EN BIT(2)
+#define DPTX_SRC_VIF_1_EN BIT(1)
+#define DPTX_SRC_VIF_0_EN BIT(0)
+
+
[PATCH v6 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM driver for Cadence Display Port. The Cadence Display Port is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface Display Port) Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. This driver implements Single Stream Transport (SST) support. Adds Texas Instruments SoC J721e specific wrapper and adds the device tree bindings in YAML format. The patch series has three patches which applies the changes in the below sequence 1. 001-dt-bindings-drm-bridge-Document-Cadence-MHDP-bridge-bindings Documents the bindings in yaml format. 2. 002-drm-bridge-Add-support-for-Cadence-MHDP-bridge This patch adds new DRM driver for Cadence MHDP Display Port. The patch implements supports for single stream transport mode. 3. 003-drm-mhdp-add-j721e-wrapper Add Texas Instruments (TI) j721e wrapper for mhdp. The wrapper configures mhdp clocks and muxes as required by SoC. Version History: v6: - Added minor fixes in YAML file. - Added Reviewed-by: Laurent Pinchart to the YAML patch. - Removed all the FIXME comments which are invalid in drm driver. - Reduced the mailbox timeout from 5s to 2s. - Added Reviewed-by: Tomi Valkeinen to the 003-drm-mhdp-add-j721e-wrapper patch. - Added Signed-off all the module authors. - Fixed the compiler error Reported-by: kbuild test robot . v5: - Added Signed-off-by: Jyri Sarha tag to the code patches. v4: - Added SPDX dual license tag to YAML bindings. - Corrected indentation of the child node properties. - Removed the maxItems in the conditional statement. - Add Reviewed-by: Rob Herring tag to the Document Cadence MHDP bridge bindings patch. - Renamed the DRM driver executable name from mhdp8546 to cdns-mhdp in Makefile. - Renamed the DRM driver and header file from cdns-mhdp to cdns-mhdp-core. v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate based on update in PHY series [2]. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. This patch series is dependent on PHY DisplayPort configuration patch [1] [1] https://lkml.org/lkml/2020/1/6/279 [2] https://lkml.org/lkml/2020/2/6/15 Yuti Amonkar (3): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm: bridge: cdns-mhdp: add j721e wrapper .../bindings/display/bridge/cdns,mhdp.yaml| 127 + drivers/gpu/drm/bridge/Kconfig| 23 + drivers/gpu/drm/bridge/Makefile |6 + drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2210 + drivers/gpu/drm/bridge/cdns-mhdp-core.h | 381 +++ drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 + 7 files changed, 2881 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../bindings/display/bridge/cdns,mhdp.yaml| 127 ++
1 file changed, 127 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index ..cdf5760d4ec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers up to PHY mapped area
(AUX_CONFIG_P).
+ The AUX and PMA registers are not part of this range, they are
instead
+ included in the associated PHY.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+description:
+ phandle to the DisplayPort PHY.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt.
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ Input port representing the DP bridge input.
+
+ port@1:
+type: object
+description:
+ Output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+ };
+ };
+};
+};
+...
--
2.20.1
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and output it encoded in DP
format. Currently, it supports only SST mode.
Signed-off-by: Yuti Amonkar
Signed-off-by: Jyri Sarha
Signed-off-by: Quentin Schulz
Signed-off-by: Swapnil Jakhade
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |2 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2196 +++
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 380
4 files changed, 2589 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 20a439199cb8..3bfabb76f2bb 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and output it encoded
+ in DP format.
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index b0d5c3af0b5a..2e2c5be7c714 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
+cdns-mhdp-objs := cdns-mhdp-core.o
obj-y += analogix/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
new file mode 100644
index ..cc642893baa8
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -0,0 +1,2196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp-core.h"
+
+static const struct of_device_id mhdp_ids[] = {
+ { .compatible = "cdns,mhdp8546", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mhdp_ids);
+
+static inline u32 get_unaligned_be24(const void *p)
+{
+ const u8 *_p = p;
+
+ return _p[0] << 16 | _p[1] << 8 | _p[2];
+}
+
+static inline void put_unaligned_be24(u32 val, void *p)
+{
+ u8 *_p = p;
+
+ _p[0] = val >> 16;
+ _p[1] = val >> 8;
+ _p[2] = val;
+}
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int val, ret;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+val, !val, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox
[PATCH v5 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and output it encoded in DP
format. Currently, it supports only SST mode.
Signed-off-by: Yuti Amonkar
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |3 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2206 +++
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 380
4 files changed, 2600 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 8397bf72d2f3..c66f2ef04f71 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and output it encoded
+ in DP format.
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1eb5376c5d68..71019088d257 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -15,6 +15,9 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
obj-y += analogix/
obj-y += synopsys/
+
+cdns-mhdp-objs := cdns-mhdp-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
new file mode 100644
index ..51ed9cdee161
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -0,0 +1,2206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp-core.h"
+
+static const struct of_device_id mhdp_ids[] = {
+ { .compatible = "cdns,mhdp8546", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mhdp_ids);
+
+static inline u32 get_unaligned_be24(const void *p)
+{
+ const u8 *_p = p;
+
+ return _p[0] << 16 | _p[1] << 8 | _p[2];
+}
+
+static inline void put_unaligned_be24(u32 val, void *p)
+{
+ u8 *_p = p;
+
+ _p[0] = val >> 16;
+ _p[1] = val >> 8;
+ _p[2] = val;
+}
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int val, ret;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+val, !val, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2)
[PATCH v5 3/3] drm: bridge: cdns-mhdp: add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/bridge/Kconfig | 12
drivers/gpu/drm/bridge/Makefile | 3 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 14 +
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 1 +
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 +
6 files changed, 164 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index c66f2ef04f71..32e3bc5edae8 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -38,6 +38,18 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and output it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721e Display Port and sets up the
+ clock and data muxes.
+endif
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 71019088d257..7e6c64f9021f 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -21,3 +21,6 @@ obj-y += analogix/
obj-y += synopsys/
cdns-mhdp-objs := cdns-mhdp-core.o
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ cdns-mhdp-objs += cdns-mhdp-j721e.o
+endif
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
index 51ed9cdee161..8483b6b1023b 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -36,8 +36,22 @@
#include "cdns-mhdp-core.h"
+#include "cdns-mhdp-j721e.h"
+
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+static const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
+ .init = cdns_mhdp_j721e_init,
+ .exit = cdns_mhdp_j721e_fini,
+ .enable = cdns_mhdp_j721e_enable,
+ .disable = cdns_mhdp_j721e_disable,
+};
+#endif
+
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+ { .compatible = "ti,j721e-mhdp8546", .data = _ti_j721e_ops },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
index 2f3b67987832..67a99eab5db3 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
@@ -335,6 +335,7 @@ struct mhdp_platform_ops {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index ..a87faf55c065
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1_SEL_DPI3BIT(5)
+#define DPTX_SRC_VIF_1_SEL_DPI10
+#define DPTX_SRC_VIF_0_SEL_DPI2BIT(4)
+#define DPTX_SRC_VIF_0_SEL_DPI00
+#define DPTX_SRC_VIF_3_EN BIT(3)
+#define DPTX_SRC_VIF_2_EN BIT(2)
+#define DPTX_SRC_VIF_1_EN BIT(1)
+#define DPTX_SRC_VIF_0_EN BIT(0)
+
+/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
+
+int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
[PATCH v5 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM driver for Cadence Display Port. The Cadence Display Port is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface Display Port) Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. This driver implements Single Stream Transport (SST) support. Adds Texas Instruments SoC J721e specific wrapper and adds the device tree bindings in YAML format. The patch series has three patches which applies the changes in the below sequence 1. 001-dt-bindings-drm-bridge-Document-Cadence-MHDP-bridge-bindings Documents the bindings in yaml format. 2. 002-drm-bridge-Add-support-for-Cadence-MHDP-bridge This patch adds new DRM driver for Cadence MHDP Display Port. The patch implements supports for single stream transport mode. 3. 003-drm-mhdp-add-j721e-wrapper Add Texas Instruments (TI) j721e wrapper for mhdp. The wrapper configures mhdp clocks and muxes as required by SoC. Version History: v5: - Added Signed-off-by: Jyri Sarha tag to the code patches. v4: - Added SPDX dual license tag to YAML bindings. - Corrected indentation of the child node properties. - Removed the maxItems in the conditional statement. - Add Reviewed-by: Rob Herring tag to the Document Cadence MHDP bridge bindings patch. - Renamed the DRM driver executable name from mhdp8546 to cdns-mhdp in Makefile. - Renamed the DRM driver and header file from cdns-mhdp to cdns-mhdp-core. v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate based on update in PHY series [2]. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. This patch series is dependent on PHY DisplayPort configuration patch [1] [1] https://lkml.org/lkml/2020/1/6/279 [2] https://lkml.org/lkml/2020/2/6/15 Yuti Amonkar (3): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings. drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm: bridge: cdns-mhdp: add j721e wrapper .../bindings/display/bridge/cdns,mhdp.yaml| 125 + drivers/gpu/drm/bridge/Kconfig| 23 + drivers/gpu/drm/bridge/Makefile |6 + drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2220 + drivers/gpu/drm/bridge/cdns-mhdp-core.h | 381 +++ drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 + 7 files changed, 2889 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings.
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,mhdp.yaml| 125 ++
1 file changed, 125 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index ..e7f84ed1d2da
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers upto PHY mapped
area(AUX_CONFIG_P).
+ The AUX and PMA registers are mapped to associated phy driver.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, it's used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+description: Phandle to the DisplyPort phy.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ input port representing the DP bridge input
+
+ port@1:
+type: object
+description:
+ output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+ };
+ };
+};
+};
+...
--
2.20.1
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[PATCH v4 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and output it encoded in DP
format. Currently, it supports only SST mode.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile |3 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2206 +++
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 380
4 files changed, 2600 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 8397bf72d2f3..c66f2ef04f71 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -27,6 +27,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and output it encoded
+ in DP format.
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 1eb5376c5d68..71019088d257 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -15,6 +15,9 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += cdns-mhdp.o
obj-y += analogix/
obj-y += synopsys/
+
+cdns-mhdp-objs := cdns-mhdp-core.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
new file mode 100644
index ..51ed9cdee161
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -0,0 +1,2206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp-core.h"
+
+static const struct of_device_id mhdp_ids[] = {
+ { .compatible = "cdns,mhdp8546", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mhdp_ids);
+
+static inline u32 get_unaligned_be24(const void *p)
+{
+ const u8 *_p = p;
+
+ return _p[0] << 16 | _p[1] << 8 | _p[2];
+}
+
+static inline void put_unaligned_be24(u32 val, void *p)
+{
+ u8 *_p = p;
+
+ _p[0] = val >> 16;
+ _p[1] = val >> 8;
+ _p[2] = val;
+}
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int val, ret;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+val, !val, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ re
[PATCH v4 3/3] drm: bridge: cdns-mhdp: add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 12
drivers/gpu/drm/bridge/Makefile | 3 +
drivers/gpu/drm/bridge/cdns-mhdp-core.c | 14 +
drivers/gpu/drm/bridge/cdns-mhdp-core.h | 1 +
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 +
6 files changed, 164 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index c66f2ef04f71..32e3bc5edae8 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -38,6 +38,18 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and output it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721e Display Port and sets up the
+ clock and data muxes.
+endif
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 71019088d257..7e6c64f9021f 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -21,3 +21,6 @@ obj-y += analogix/
obj-y += synopsys/
cdns-mhdp-objs := cdns-mhdp-core.o
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ cdns-mhdp-objs += cdns-mhdp-j721e.o
+endif
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
index 51ed9cdee161..8483b6b1023b 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.c
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.c
@@ -36,8 +36,22 @@
#include "cdns-mhdp-core.h"
+#include "cdns-mhdp-j721e.h"
+
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+static const struct mhdp_platform_ops mhdp_ti_j721e_ops = {
+ .init = cdns_mhdp_j721e_init,
+ .exit = cdns_mhdp_j721e_fini,
+ .enable = cdns_mhdp_j721e_enable,
+ .disable = cdns_mhdp_j721e_disable,
+};
+#endif
+
static const struct of_device_id mhdp_ids[] = {
{ .compatible = "cdns,mhdp8546", },
+#ifdef CONFIG_DRM_CDNS_MHDP_J721E
+ { .compatible = "ti,j721e-mhdp8546", .data = _ti_j721e_ops },
+#endif
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mhdp_ids);
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
index 2f3b67987832..67a99eab5db3 100644
--- a/drivers/gpu/drm/bridge/cdns-mhdp-core.h
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-core.h
@@ -335,6 +335,7 @@ struct mhdp_platform_ops {
struct cdns_mhdp_device {
void __iomem *regs;
+ void __iomem *j721e_regs;
struct device *dev;
struct clk *clk;
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index ..a87faf55c065
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1_SEL_DPI3BIT(5)
+#define DPTX_SRC_VIF_1_SEL_DPI10
+#define DPTX_SRC_VIF_0_SEL_DPI2BIT(4)
+#define DPTX_SRC_VIF_0_SEL_DPI00
+#define DPTX_SRC_VIF_3_EN BIT(3)
+#define DPTX_SRC_VIF_2_EN BIT(2)
+#define DPTX_SRC_VIF_1_EN BIT(1)
+#define DPTX_SRC_VIF_0_EN BIT(0)
+
+/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
+
+int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
+{
+ struct platform
[PATCH v4 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings.
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Reviewed-by: Rob Herring
---
.../bindings/display/bridge/cdns,mhdp.yaml| 125 ++
1 file changed, 125 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index ..e7f84ed1d2da
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers upto PHY mapped
area(AUX_CONFIG_P).
+ The AUX and PMA registers are mapped to associated phy driver.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, it's used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+description: Phandle to the DisplyPort phy.
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt
+
+properties:
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ port@0:
+type: object
+description:
+ input port representing the DP bridge input
+
+ port@1:
+type: object
+description:
+ output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+reg-names:
+ minItems: 2
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+ };
+ };
+};
+};
+...
--
2.20.1
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[PATCH v4 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM driver for Cadence Display Port. The Cadence Display Port is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface Display Port) Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. This driver implements Single Stream Transport (SST) support. Adds Texas Instruments SoC J721e specific wrapper and adds the device tree bindings in YAML format. The patch series has three patches which applies the changes in the below sequence 1. 001-dt-bindings-drm-bridge-Document-Cadence-MHDP-bridge-bindings Documents the bindings in yaml format. 2. 002-drm-bridge-Add-support-for-Cadence-MHDP-bridge This patch adds new DRM driver for Cadence MHDP Display Port. The patch implements supports for single stream transport mode. 3. 003-drm-bridge-cdns-mhdp-add-j721e-wrapper Add Texas Instruments (TI) j721e wrapper for mhdp. The wrapper configures mhdp clocks and muxes as required by SoC. Version History: v4: - Added SPDX dual license tag to YAML bindings. - Corrected indentation of the child node properties. - Removed the maxItems in the conditional statement. - Removed phy-names property from the bindings. - Add Reviewed-by: Rob Herring tag to the "Document Cadence MHDP bridge bindings" patch. - Renamed the DRM driver executable name from mhdp8546 to cdns-mhdp in Makefile. - Renamed the DRM driver and header file from cdns-mhdp to cdns-mhdp-core. v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate based on update in PHY series [2]. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. This patch series is dependent on PHY DisplayPort configuration patch [1] [1] https://lkml.org/lkml/2020/1/6/279 [2] https://lkml.org/lkml/2020/2/6/15 Yuti Amonkar (3): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings. drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm: bridge: cdns-mhdp: add j721e wrapper .../bindings/display/bridge/cdns,mhdp.yaml| 125 + drivers/gpu/drm/bridge/Kconfig| 23 + drivers/gpu/drm/bridge/Makefile |6 + drivers/gpu/drm/bridge/cdns-mhdp-core.c | 2220 + drivers/gpu/drm/bridge/cdns-mhdp-core.h | 381 +++ drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 + 7 files changed, 2889 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-core.h create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards.It integrates uCPU running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and output it encoded in DP
format. Currently, it supports only SST mode.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile|3 +
drivers/gpu/drm/bridge/cdns-mhdp.c | 2202
drivers/gpu/drm/bridge/cdns-mhdp.h | 380 +++
4 files changed, 2596 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3436297..616c05f 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -37,6 +37,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and output it encoded
+ in DP format.
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4934fcf..c1a0da7 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -16,4 +16,7 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += mhdp8546.o
obj-y += synopsys/
+
+mhdp8546-objs := cdns-mhdp.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp.c
b/drivers/gpu/drm/bridge/cdns-mhdp.c
new file mode 100644
index 000..0bc7fba
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp.c
@@ -0,0 +1,2202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp.h"
+
+static const struct of_device_id mhdp_ids[] = {
+ { .compatible = "cdns,mhdp8546", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mhdp_ids);
+
+static inline u32 get_unaligned_be24(const void *p)
+{
+ const u8 *_p = p;
+
+ return _p[0] << 16 | _p[1] << 8 | _p[2];
+}
+
+static inline void put_unaligned_be24(u32 val, void *p)
+{
+ u8 *_p = p;
+
+ _p[0] = val >> 16;
+ _p[1] = val >> 8;
+ _p[2] = val;
+}
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int val, ret;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+val, !val, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ req_size != mbox_size) {
+ /*
+* If the message in ma
[PATCH v3 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM driver for Cadence Display Port. The Cadence Display Port is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface Display Port) Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards. This driver implements Single Stream Transport (SST) support. Adds Texas Instruments SoC J721e specific wrapper and adds the device tree bindings in YAML format. The patch series has three patches which applies the changes in the below sequence 1. 001-dt-bindings-drm-bridge-Document-Cadence-MHDP-bridge-bindings-in-yaml-format Documents the bindings in yaml format. 2. 002-drm-bridge-Add-support-for-Cadence-MHDP-bridge This patch adds new DRM driver for Cadence MHDP Display Port. The patch imple ments supports for single stream transport mode. 3. 003-drm-mhdp-add-j721e-wrapper Add Texas Instruments (TI) j721e wrapper for mhdp. The wrapper configures mhdp clocks and muxes as required by SoC. Version History: v3: - Added if / then clause to validate that the reg length is proper based on the value of the compatible property. - Updated phy property description in YAML to a generic one. - Renamed num_lanes and max_bit_rate property strings to cdns,num-lanes and cdns,max-bit-rate based on update in PHY series [2]. v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. This patch series is dependent on PHY DisplayPort configuration patch [1] [1] https://lkml.org/lkml/2020/1/6/279 [2] https://lkml.org/lkml/2020/1/22/631 Yuti Amonkar (3): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm/mhdp: add j721e wrapper .../bindings/display/bridge/cdns,mhdp.yaml | 131 ++ drivers/gpu/drm/bridge/Kconfig | 23 + drivers/gpu/drm/bridge/Makefile|6 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 + drivers/gpu/drm/bridge/cdns-mhdp.c | 2214 drivers/gpu/drm/bridge/cdns-mhdp.h | 381 7 files changed, 2889 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.h -- 2.4.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 3/3] drm/mhdp: add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 12 +
drivers/gpu/drm/bridge/Makefile | 3 ++
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 ++
drivers/gpu/drm/bridge/cdns-mhdp.c | 14 +-
drivers/gpu/drm/bridge/cdns-mhdp.h | 1 +
6 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 616c05f..6c366eb 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,18 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and output it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper. This is a wrapper
+ which adds support for J721E related platform ops. It
+ initializes the J721e Display Port and sets up the
+ clock and data muxes.
+endif
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c1a0da7..d358184 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -20,3 +20,6 @@ obj-$(CONFIG_DRM_CDNS_MHDP) += mhdp8546.o
obj-y += synopsys/
mhdp8546-objs := cdns-mhdp.o
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ mhdp8546-objs += cdns-mhdp-j721e.o
+endif
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index 000..a87faf5
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1_SEL_DPI3BIT(5)
+#define DPTX_SRC_VIF_1_SEL_DPI10
+#define DPTX_SRC_VIF_0_SEL_DPI2BIT(4)
+#define DPTX_SRC_VIF_0_SEL_DPI00
+#define DPTX_SRC_VIF_3_EN BIT(3)
+#define DPTX_SRC_VIF_2_EN BIT(2)
+#define DPTX_SRC_VIF_1_EN BIT(1)
+#define DPTX_SRC_VIF_0_EN BIT(0)
+
+/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
+
+int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
+{
+ struct platform_device *pdev = to_platform_device(mhdp->dev);
+ struct resource *regs;
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ mhdp->j721e_regs = devm_ioremap_resource(>dev, regs);
+ if (IS_ERR(mhdp->j721e_regs))
+ return PTR_ERR(mhdp->j721e_regs);
+
+ return 0;
+}
+
+void cdns_mhdp_j721e_fini(struct cdns_mhdp_device *mhdp)
+{
+}
+
+void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
+{
+ /*
+* Eneble VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
+* to eDP DPI2. This is the only supported SST configuration on
+* J721E.
+*/
+ writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
+ mhdp->j721e_regs + DPTX_SRC_CFG);
+}
+
+void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
+{
+ /* Put everything to defaults */
+ writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
+}
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
new file mode 100644
index 000..bd53508
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://
[PATCH v3 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
---
.../bindings/display/bridge/cdns,mhdp.yaml | 131 +
1 file changed, 131 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index 000..696418a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,131 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers upto PHY mapped
area(AUX_CONFIG_P).
+ The AUX and PMA registers are mapped to associated phy driver.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, it's used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ phys:
+description: Phandle to the DisplyPort phy.
+
+ phy-names:
+const: dpphy
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt
+
+properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description:
+ input port representing the DP bridge input
+
+ port@1:
+ type: object
+ description:
+ output port representing the DP bridge output.
+
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+const: ti,j721e-mhdp8546
+then:
+ properties:
+reg:
+ minItems: 2
+ maxItems: 2
+reg-names:
+ minItems: 2
+ maxItems: 2
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - phys
+ - phy-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>;
+reg-names = "mhdptx";
+clocks = <_clock>;
+phys = <_phy>;
+phy-names = "dpphy";
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+remote-endpoint = <_dp_connector_input>;
+ };
+ };
+ };
+};
+...
--
2.4.5
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[PATCH v3] phy: Add DisplayPort configuration options
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.
Add the DisplayPort phy mode to the generic phy_mode enum.
Signed-off-by: Yuti Amonkar
---
Version History:
v3:
Add DisplayPort mode to the generic phy_mode enum.
v2:
Update DisplayPort spec version in the commit message.
This patch was a part of [1] series earlier but we think that it needs
to have a separate attention of the reviewers. Also as both [1] & [2] are
dependent on this patch, our sincere request to reviewers to have a
faster review of this patch.
[1]
https://lkml.org/lkml/2019/12/23/392
[2]
https://lkml.org/lkml/2019/12/23/394
include/linux/phy/phy-dp.h | 95 ++
include/linux/phy/phy.h| 7 +++-
2 files changed, 101 insertions(+), 1 deletion(-)
create mode 100644 include/linux/phy/phy-dp.h
diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
new file mode 100644
index 000..18cad23
--- /dev/null
+++ b/include/linux/phy/phy-dp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Cadence Design Systems Inc.
+ */
+
+#ifndef __PHY_DP_H_
+#define __PHY_DP_H_
+
+#include
+
+/**
+ * struct phy_configure_opts_dp - DisplayPort PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * DisplayPort phy.
+ */
+struct phy_configure_opts_dp {
+ /**
+* @link_rate:
+*
+* Link Rate, in Mb/s, of the main link.
+*
+* Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
+*/
+ unsigned int link_rate;
+
+ /**
+* @lanes:
+*
+* Number of active, consecutive, data lanes, starting from
+* lane 0, used for the transmissions on main link.
+*
+* Allowed values: 1, 2, 4
+*/
+ unsigned int lanes;
+
+ /**
+* @voltage:
+*
+* Voltage swing levels, as specified by DisplayPort specification,
+* to be used by particular lanes. One value per lane.
+* voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
+*
+* Maximum value: 3
+*/
+ unsigned int voltage[4];
+
+ /**
+* @pre:
+*
+* Pre-emphasis levels, as specified by DisplayPort specification, to be
+* used by particular lanes. One value per lane.
+*
+* Maximum value: 3
+*/
+ unsigned int pre[4];
+
+ /**
+* @ssc:
+*
+* Flag indicating, whether or not to enable spread-spectrum clocking.
+*
+*/
+ u8 ssc : 1;
+
+ /**
+* @set_rate:
+*
+* Flag indicating, whether or not reconfigure link rate and SSC to
+* requested values.
+*
+*/
+ u8 set_rate : 1;
+
+ /**
+* @set_lanes:
+*
+* Flag indicating, whether or not reconfigure lane count to
+* requested value.
+*
+*/
+ u8 set_lanes : 1;
+
+ /**
+* @set_voltages:
+*
+* Flag indicating, whether or not reconfigure voltage swing
+* and pre-emphasis to requested values. Only lanes specified
+* by "lanes" parameter will be affected.
+*
+*/
+ u8 set_voltages : 1;
+};
+
+#endif /* __PHY_DP_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 15032f14..962a469 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -16,6 +16,7 @@
#include
#include
+#include
#include
struct phy;
@@ -38,7 +39,8 @@ enum phy_mode {
PHY_MODE_PCIE,
PHY_MODE_ETHERNET,
PHY_MODE_MIPI_DPHY,
- PHY_MODE_SATA
+ PHY_MODE_SATA,
+ PHY_MODE_DP
};
/**
@@ -46,9 +48,12 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @dp:Configuration set applicable for phys supporting
+ * the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_dpdp;
};
/**
--
2.7.4
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[PATCH v2 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
---
.../bindings/display/bridge/cdns,mhdp.yaml | 109 +
1 file changed, 109 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index 000..aed6224
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,109 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+enum:
+ - cdns,mhdp8546
+ - ti,j721e-mhdp8546
+
+ clocks:
+maxItems: 1
+description:
+ DP bridge clock, it's used by the IP to know how to translate a number of
+ clock cycles into a time (which is used to comply with DP standard
timings
+ and delays).
+
+ reg:
+minItems: 1
+maxItems: 2
+items:
+ - description:
+ Register block of mhdptx apb registers upto PHY mapped
area(AUX_CONFIG_P).
+ The AUX and PMA registers are mapped to associated phy driver.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ reg-names:
+minItems: 1
+maxItems: 2
+items:
+ - const: mhdptx
+ - const: j721e-intg
+
+ phys:
+description: see the
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+
+ phy-names:
+const: dpphy
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devicetree/bindings/graph.txt
+properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+ port@0:
+ description:
+ input port representing the DP bridge input
+
+ port@1:
+ description:
+ output port representing the DP bridge output
+required:
+ - port@0
+ - port@1
+ - '#address-cells'
+ - '#size-cells'
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - phys
+ - phy-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>,
+ <0xf0 0xfc00 0x0 0x200>;
+clocks = <_clock>;
+phys = <_phy>;
+phy-names = "dpphy";
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+remote-endpoint = <_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+ remote-endpoint =
<_dp_connector_input>;
+ };
+ };
+ };
+};
+...
--
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[PATCH v2] phy: Add DisplayPort configuration options
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the DisplayPort
spec 1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.
Signed-off-by: Yuti Amonkar
---
This patch was a part of [1] series earlier but we think that it needs
to have a separate attention of the reviewers. Also as both [1] & [2] are
dependent on this patch, our sincere request to reviewers to have a
faster review of this patch.
[1]
https://lkml.org/lkml/2019/12/11/455
[2]
https://patchwork.kernel.org/cover/11271191/
include/linux/phy/phy-dp.h | 95 ++
include/linux/phy/phy.h| 4 ++
2 files changed, 99 insertions(+)
create mode 100644 include/linux/phy/phy-dp.h
diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
new file mode 100644
index 000..18cad23
--- /dev/null
+++ b/include/linux/phy/phy-dp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Cadence Design Systems Inc.
+ */
+
+#ifndef __PHY_DP_H_
+#define __PHY_DP_H_
+
+#include
+
+/**
+ * struct phy_configure_opts_dp - DisplayPort PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * DisplayPort phy.
+ */
+struct phy_configure_opts_dp {
+ /**
+* @link_rate:
+*
+* Link Rate, in Mb/s, of the main link.
+*
+* Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
+*/
+ unsigned int link_rate;
+
+ /**
+* @lanes:
+*
+* Number of active, consecutive, data lanes, starting from
+* lane 0, used for the transmissions on main link.
+*
+* Allowed values: 1, 2, 4
+*/
+ unsigned int lanes;
+
+ /**
+* @voltage:
+*
+* Voltage swing levels, as specified by DisplayPort specification,
+* to be used by particular lanes. One value per lane.
+* voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
+*
+* Maximum value: 3
+*/
+ unsigned int voltage[4];
+
+ /**
+* @pre:
+*
+* Pre-emphasis levels, as specified by DisplayPort specification, to be
+* used by particular lanes. One value per lane.
+*
+* Maximum value: 3
+*/
+ unsigned int pre[4];
+
+ /**
+* @ssc:
+*
+* Flag indicating, whether or not to enable spread-spectrum clocking.
+*
+*/
+ u8 ssc : 1;
+
+ /**
+* @set_rate:
+*
+* Flag indicating, whether or not reconfigure link rate and SSC to
+* requested values.
+*
+*/
+ u8 set_rate : 1;
+
+ /**
+* @set_lanes:
+*
+* Flag indicating, whether or not reconfigure lane count to
+* requested value.
+*
+*/
+ u8 set_lanes : 1;
+
+ /**
+* @set_voltages:
+*
+* Flag indicating, whether or not reconfigure voltage swing
+* and pre-emphasis to requested values. Only lanes specified
+* by "lanes" parameter will be affected.
+*
+*/
+ u8 set_voltages : 1;
+};
+
+#endif /* __PHY_DP_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 15032f14..ba0aab5 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -16,6 +16,7 @@
#include
#include
+#include
#include
struct phy;
@@ -46,9 +47,12 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @dp:Configuration set applicable for phys supporting
+ * the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_dpdp;
};
/**
--
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[PATCH v2 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM driver for Cadence Display Port. The Cadence Display Port is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface Display Port) Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards This driver implements Single Stream Transport (SST) support. Adds Texas Instruments SoC J721e specific wrapper and adds the device tree bindings in YAML format. The patch series has three patches which applies the changes in the below sequence 1. 001-dt-bindings-drm-bridge-Document-Cadence-MHDP-bridge-bindings-in-yaml-format Documents the bindings in yaml format. 2. 002-drm-bridge-Add-support-for-Cadence-MHDP-bridge This patch adds new DRM driver for Cadence MHDP Display Port. The patch implements supports for single stream transport mode. 3. 003-drm-mhdp-add-j721e-wrapper Add Texas Instruments (TI) j721e wrapper for mhdp. The wrapper configures mhdp clocks and muxes as required by SoC. Version History: v2: - Use enum in compatible property of YAML file. - Add reg-names property to YAML file - Add minItems and maxItems to reg property in YAML. - Remove cdns_mhdp_link_probe function to remove duplication of reading dpcd capabilities. This patch series is dependent on PHY DisplayPort configuration patch [1] [1] https://patchwork.kernel.org/patch/11307829/ Yuti Amonkar (3): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm/mhdp: add j721e wrapper .../bindings/display/bridge/cdns,mhdp.yaml | 109 + drivers/gpu/drm/bridge/Kconfig | 21 + drivers/gpu/drm/bridge/Makefile|6 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 + drivers/gpu/drm/bridge/cdns-mhdp.c | 2214 drivers/gpu/drm/bridge/cdns-mhdp.h | 381 7 files changed, 2865 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 3/3] drm/mhdp: add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 10
drivers/gpu/drm/bridge/Makefile | 3 ++
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 ++
drivers/gpu/drm/bridge/cdns-mhdp.c | 14 +-
drivers/gpu/drm/bridge/cdns-mhdp.h | 1 +
6 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 616c05f..4b6799b 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,16 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and output it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper.It sets up
+ the clock and data muxes.
+endif
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c1a0da7..d358184 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -20,3 +20,6 @@ obj-$(CONFIG_DRM_CDNS_MHDP) += mhdp8546.o
obj-y += synopsys/
mhdp8546-objs := cdns-mhdp.o
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ mhdp8546-objs += cdns-mhdp-j721e.o
+endif
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index 000..a87faf5
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1_SEL_DPI3BIT(5)
+#define DPTX_SRC_VIF_1_SEL_DPI10
+#define DPTX_SRC_VIF_0_SEL_DPI2BIT(4)
+#define DPTX_SRC_VIF_0_SEL_DPI00
+#define DPTX_SRC_VIF_3_EN BIT(3)
+#define DPTX_SRC_VIF_2_EN BIT(2)
+#define DPTX_SRC_VIF_1_EN BIT(1)
+#define DPTX_SRC_VIF_0_EN BIT(0)
+
+/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
+
+int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
+{
+ struct platform_device *pdev = to_platform_device(mhdp->dev);
+ struct resource *regs;
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ mhdp->j721e_regs = devm_ioremap_resource(>dev, regs);
+ if (IS_ERR(mhdp->j721e_regs))
+ return PTR_ERR(mhdp->j721e_regs);
+
+ return 0;
+}
+
+void cdns_mhdp_j721e_fini(struct cdns_mhdp_device *mhdp)
+{
+}
+
+void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
+{
+ /*
+* Eneble VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
+* to eDP DPI2. This is the only supported SST configuration on
+* J721E.
+*/
+ writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
+ mhdp->j721e_regs + DPTX_SRC_CFG);
+}
+
+void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
+{
+ /* Put everything to defaults */
+ writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
+}
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
new file mode 100644
index 000..bd53508
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include "cdns-mhdp.h"
+
+struct cdns_mhdp_j721e_wrap;
+
+#ifdef CONFIG_DRM_CDNS_M
[PATCH v2 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards.It integrates uCPU running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and output it encoded in DP
format. Currently, it supports only SST mode.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile|3 +
drivers/gpu/drm/bridge/cdns-mhdp.c | 2202
drivers/gpu/drm/bridge/cdns-mhdp.h | 380 +++
4 files changed, 2596 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3436297..616c05f 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -37,6 +37,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and output it encoded
+ in DP format.
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4934fcf..c1a0da7 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -16,4 +16,7 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += mhdp8546.o
obj-y += synopsys/
+
+mhdp8546-objs := cdns-mhdp.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp.c
b/drivers/gpu/drm/bridge/cdns-mhdp.c
new file mode 100644
index 000..543ce80
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp.c
@@ -0,0 +1,2202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp.h"
+
+static const struct of_device_id mhdp_ids[] = {
+ { .compatible = "cdns,mhdp8546", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mhdp_ids);
+
+static inline u32 get_unaligned_be24(const void *p)
+{
+ const u8 *_p = p;
+
+ return _p[0] << 16 | _p[1] << 8 | _p[2];
+}
+
+static inline void put_unaligned_be24(u32 val, void *p)
+{
+ u8 *_p = p;
+
+ _p[0] = val >> 16;
+ _p[1] = val >> 8;
+ _p[2] = val;
+}
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int val, ret;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+val, !val, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ req_size != mbox_size) {
+ /*
+* If the message in ma
[PATCH v1] phy: Add DisplayPort configuration options
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.
The parameters added here are the ones defined in the DisplayPort
spec which include link rate, number of lanes, voltage swing
and pre-emphasis.
This patch was a part of [1] series earlier but we think that it needs
to have a separate attention of the reviewers. Also as both [1] & [2] are
dependent on this patch, our sincere request to reviewers to have a
faster review of this patch.
[1]
https://lkml.org/lkml/2019/12/11/455
[2]
https://patchwork.kernel.org/cover/11271191/
Signed-off-by: Yuti Amonkar
---
include/linux/phy/phy-dp.h | 95 ++
include/linux/phy/phy.h| 4 ++
2 files changed, 99 insertions(+)
create mode 100644 include/linux/phy/phy-dp.h
diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
new file mode 100644
index 000..18cad23
--- /dev/null
+++ b/include/linux/phy/phy-dp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Cadence Design Systems Inc.
+ */
+
+#ifndef __PHY_DP_H_
+#define __PHY_DP_H_
+
+#include
+
+/**
+ * struct phy_configure_opts_dp - DisplayPort PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * DisplayPort phy.
+ */
+struct phy_configure_opts_dp {
+ /**
+* @link_rate:
+*
+* Link Rate, in Mb/s, of the main link.
+*
+* Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
+*/
+ unsigned int link_rate;
+
+ /**
+* @lanes:
+*
+* Number of active, consecutive, data lanes, starting from
+* lane 0, used for the transmissions on main link.
+*
+* Allowed values: 1, 2, 4
+*/
+ unsigned int lanes;
+
+ /**
+* @voltage:
+*
+* Voltage swing levels, as specified by DisplayPort specification,
+* to be used by particular lanes. One value per lane.
+* voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
+*
+* Maximum value: 3
+*/
+ unsigned int voltage[4];
+
+ /**
+* @pre:
+*
+* Pre-emphasis levels, as specified by DisplayPort specification, to be
+* used by particular lanes. One value per lane.
+*
+* Maximum value: 3
+*/
+ unsigned int pre[4];
+
+ /**
+* @ssc:
+*
+* Flag indicating, whether or not to enable spread-spectrum clocking.
+*
+*/
+ u8 ssc : 1;
+
+ /**
+* @set_rate:
+*
+* Flag indicating, whether or not reconfigure link rate and SSC to
+* requested values.
+*
+*/
+ u8 set_rate : 1;
+
+ /**
+* @set_lanes:
+*
+* Flag indicating, whether or not reconfigure lane count to
+* requested value.
+*
+*/
+ u8 set_lanes : 1;
+
+ /**
+* @set_voltages:
+*
+* Flag indicating, whether or not reconfigure voltage swing
+* and pre-emphasis to requested values. Only lanes specified
+* by "lanes" parameter will be affected.
+*
+*/
+ u8 set_voltages : 1;
+};
+
+#endif /* __PHY_DP_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 15032f14..ba0aab5 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -16,6 +16,7 @@
#include
#include
+#include
#include
struct phy;
@@ -46,9 +47,12 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @dp:Configuration set applicable for phys supporting
+ * the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_dpdp;
};
/**
--
2.7.4
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[PATCH v1 05/15] phy: cadence-torrent: Add wrapper for PHY register access
From: Swapnil Jakhade
Add a wrapper function to write Torrent PHY registers to improve
code readability.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 142 --
1 file changed, 77 insertions(+), 65 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index eb61005..59c85d8 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -132,6 +132,14 @@ static const struct phy_ops cdns_torrent_phy_ops = {
.owner = THIS_MODULE,
};
+/* PHY mmr access functions */
+
+static void cdns_torrent_phy_write(struct cdns_torrent_phy *cdns_phy,
+ u32 offset, u32 val)
+{
+ writel(val, cdns_phy->sd_base + offset);
+}
+
static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
@@ -234,34 +242,35 @@ static
void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
{
/* refclock registers - assumes 25 MHz refclock */
- writel(0x0019, cdns_phy->sd_base + CMN_SSM_BIAS_TMR);
- writel(0x0032, cdns_phy->sd_base + CMN_PLLSM0_PLLPRE_TMR);
- writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM0_PLLLOCK_TMR);
- writel(0x0032, cdns_phy->sd_base + CMN_PLLSM1_PLLPRE_TMR);
- writel(0x00D1, cdns_phy->sd_base + CMN_PLLSM1_PLLLOCK_TMR);
- writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_INIT_TMR);
- writel(0x007D, cdns_phy->sd_base + CMN_BGCAL_ITER_TMR);
- writel(0x0019, cdns_phy->sd_base + CMN_IBCAL_INIT_TMR);
- writel(0x001E, cdns_phy->sd_base + CMN_TXPUCAL_INIT_TMR);
- writel(0x0006, cdns_phy->sd_base + CMN_TXPUCAL_ITER_TMR);
- writel(0x001E, cdns_phy->sd_base + CMN_TXPDCAL_INIT_TMR);
- writel(0x0006, cdns_phy->sd_base + CMN_TXPDCAL_ITER_TMR);
- writel(0x02EE, cdns_phy->sd_base + CMN_RXCAL_INIT_TMR);
- writel(0x0006, cdns_phy->sd_base + CMN_RXCAL_ITER_TMR);
- writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_INIT_TMR);
- writel(0x0002, cdns_phy->sd_base + CMN_SD_CAL_ITER_TMR);
- writel(0x000E, cdns_phy->sd_base + CMN_SD_CAL_REFTIM_START);
- writel(0x012B, cdns_phy->sd_base + CMN_SD_CAL_PLLCNT_START);
+ cdns_torrent_phy_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0019);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
+ cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_INIT_TMR, 0x007D);
+ cdns_torrent_phy_write(cdns_phy, CMN_BGCAL_ITER_TMR, 0x007D);
+ cdns_torrent_phy_write(cdns_phy, CMN_IBCAL_INIT_TMR, 0x0019);
+ cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x001E);
+ cdns_torrent_phy_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
+ cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x001E);
+ cdns_torrent_phy_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
+ cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x02EE);
+ cdns_torrent_phy_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
+ cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_INIT_TMR, 0x0002);
+ cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_ITER_TMR, 0x0002);
+ cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_REFTIM_START, 0x000E);
+ cdns_torrent_phy_write(cdns_phy, CMN_SD_CAL_PLLCNT_START, 0x012B);
+
/* PLL registers */
- writel(0x0409, cdns_phy->sd_base + CMN_PDIAG_PLL0_CP_PADJ_M0);
- writel(0x1001, cdns_phy->sd_base + CMN_PDIAG_PLL0_CP_IADJ_M0);
- writel(0x0F08, cdns_phy->sd_base + CMN_PDIAG_PLL0_FILT_PADJ_M0);
- writel(0x0004, cdns_phy->sd_base + CMN_PLL0_DSM_DIAG_M0);
- writel(0x00FA, cdns_phy->sd_base + CMN_PLL0_VCOCAL_INIT_TMR);
- writel(0x0004, cdns_phy->sd_base + CMN_PLL0_VCOCAL_ITER_TMR);
- writel(0x00FA, cdns_phy->sd_base + CMN_PLL1_VCOCAL_INIT_TMR);
- writel(0x0004, cdns_phy->sd_base + CMN_PLL1_VCOCAL_ITER_TMR);
- writel(0x0318, cdns_phy->sd_base + CMN_PLL0_VCOCAL_REFTIM_START);
+ cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0409);
+ cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x1001);
+ cdns_torrent_phy_write(cdns_phy, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLL0_DSM_DIAG_M0, 0x0004);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
+ cdns_torrent_phy_write(cdns_phy, CMN_PLL0_VCOCAL_REFTIM_START, 0x0318);
}
static
@@ -269,41 +278,41 @@ void
[PATCH v1 12/15] phy: cadence-torrent: Use regmap to read and write Torrent PHY registers
Use regmap for accessing Torrent PHY registers. Modify register offsets as defined in Torrent PHY user guide. Abstract address calculation using regmap APIs. Signed-off-by: Yuti Amonkar --- drivers/phy/cadence/phy-cadence-torrent.c | 1020 ++--- 1 file changed, 650 insertions(+), 370 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 006e786..75b8a81 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -19,6 +19,7 @@ #include #include #include +#include #define REF_CLK_19_2MHz1920 #define REF_CLK_25MHz 2500 @@ -28,7 +29,22 @@ #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ #define POLL_TIMEOUT_US5000 -#define LANE_MASK 0x7 + +#define TORRENT_COMMON_CDB_OFFSET 0x0 + +#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x4000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) + +#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ + ((0x8000 << (block_offset)) + \ + (((ln) << 9) << (reg_offset))) + +#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)\ + (0xC000 << (block_offset)) + +#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)\ + (0xE000 << (block_offset)) /* * register offsets from DPTX PHY register block base (i.e MHDP @@ -57,100 +73,114 @@ * register offsets from SD0801 PHY register block base (i.e MHDP * register base + 0x50) */ -#define CMN_SSM_BANDGAP_TMR0x00084 -#define CMN_SSM_BIAS_TMR 0x00088 -#define CMN_PLLSM0_PLLPRE_TMR 0x000a8 -#define CMN_PLLSM0_PLLLOCK_TMR 0x000b0 -#define CMN_PLLSM1_PLLPRE_TMR 0x000c8 -#define CMN_PLLSM1_PLLLOCK_TMR 0x000d0 -#define CMN_BGCAL_INIT_TMR 0x00190 -#define CMN_BGCAL_ITER_TMR 0x00194 -#define CMN_IBCAL_INIT_TMR 0x001d0 -#define CMN_PLL0_VCOCAL_TCTRL 0x00208 -#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210 -#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214 -#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218 -#define CMN_PLL0_VCOCAL_PLLCNT_START 0x00220 -#define CMN_PLL0_INTDIV_M0 0x00240 -#define CMN_PLL0_FRACDIVL_M0 0x00244 -#define CMN_PLL0_FRACDIVH_M0 0x00248 -#define CMN_PLL0_HIGH_THR_M0 0x0024c -#define CMN_PLL0_DSM_DIAG_M0 0x00250 -#define CMN_PLL0_SS_CTRL1_M0 0x00260 -#define CMN_PLL0_SS_CTRL2_M00x00264 -#define CMN_PLL0_SS_CTRL3_M00x00268 -#define CMN_PLL0_SS_CTRL4_M00x0026C -#define CMN_PLL0_LOCK_REFCNT_START 0x00270 -#define CMN_PLL0_LOCK_PLLCNT_START 0x00278 -#define CMN_PLL0_LOCK_PLLCNT_THR0x0027C -#define CMN_PLL1_VCOCAL_TCTRL 0x00308 -#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310 -#define CMN_PLL1_VCOCAL_ITER_TMR 0x00314 -#define CMN_PLL1_VCOCAL_REFTIM_START 0x00318 -#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00320 -#define CMN_PLL1_INTDIV_M0 0x00340 -#define CMN_PLL1_FRACDIVL_M0 0x00344 -#define CMN_PLL1_FRACDIVH_M0 0x00348 -#define CMN_PLL1_HIGH_THR_M0 0x0034c -#define CMN_PLL1_DSM_DIAG_M0 0x00350 -#define CMN_PLL1_SS_CTRL1_M0 0x00360 -#define CMN_PLL1_SS_CTRL2_M00x00364 -#define CMN_PLL1_SS_CTRL3_M00x00368 -#define CMN_PLL1_SS_CTRL4_M00x0036C -#define CMN_PLL1_LOCK_REFCNT_START 0x00370 -#define CMN_PLL1_LOCK_PLLCNT_START 0x00378 -#define CMN_PLL1_LOCK_PLLCNT_THR0x0037C -#define CMN_TXPUCAL_INIT_TMR 0x00410 -#define CMN_TXPUCAL_ITER_TMR 0x00414 -#define CMN_TXPDCAL_INIT_TMR 0x00430 -#define CMN_TXPDCAL_ITER_TMR 0x00434 -#define CMN_RXCAL_INIT_TMR 0x00450 -#define CMN_RXCAL_ITER_TMR 0x00454 -#define CMN_SD_CAL_INIT_TMR0x00490 -#define CMN_SD_CAL_ITER_TMR0x00494 -#define CMN_SD_CAL_REFTIM_START0x00498 -#define CMN_SD_CAL_PLLCNT_START0x004a0 -#define CMN_PDIAG_PLL0_CTRL_M0 0x00680 -#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x00684 -#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x00690 -#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x00694 -#define CMN_PDIAG_PLL0_FILT_PADJ_M00x00698 -#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x006d0 -#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x006d4 -#define CMN_PDIAG_PLL1_CTRL_M0 0x00700 -#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x00704 -#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x00710 -#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x00714 -#define CMN_PDIAG_PLL1_FILT_PADJ_M00x00718 - -#define TX_TXCC_CTRL
[PATCH v1 03/15] phy: cadence-dp: Rename to phy-cadence-torrent
Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent
to make it more generic for future use. Modifiy Makefile and Kconfig
accordingly. Also, change driver compatible from "cdns,dp-phy" to
"cdns,torrent-phy".
Signed-off-by: Yuti Amonkar
---
drivers/phy/cadence/Kconfig | 6 +++---
drivers/phy/cadence/Makefile| 2 +-
drivers/phy/cadence/{phy-cadence-dp.c => phy-cadence-torrent.c} | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
rename drivers/phy/cadence/{phy-cadence-dp.c => phy-cadence-torrent.c} (99%)
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index b2db916d..4595458 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -3,13 +3,13 @@
# Phy drivers for Cadence PHYs
#
-config PHY_CADENCE_DP
- tristate "Cadence MHDP DisplayPort PHY driver"
+config PHY_CADENCE_TORRENT
+ tristate "Cadence Torrent PHY driver"
depends on OF
depends on HAS_IOMEM
select GENERIC_PHY
help
- Support for Cadence MHDP DisplayPort PHY.
+ Support for Cadence Torrent PHY.
config PHY_CADENCE_DPHY
tristate "Cadence D-PHY Support"
diff --git a/drivers/phy/cadence/Makefile b/drivers/phy/cadence/Makefile
index 8f89560..6a7ffc6 100644
--- a/drivers/phy/cadence/Makefile
+++ b/drivers/phy/cadence/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_PHY_CADENCE_DP) += phy-cadence-dp.o
+obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
diff --git a/drivers/phy/cadence/phy-cadence-dp.c
b/drivers/phy/cadence/phy-cadence-torrent.c
similarity index 99%
rename from drivers/phy/cadence/phy-cadence-dp.c
rename to drivers/phy/cadence/phy-cadence-torrent.c
index bc10cb2..beb80f7 100644
--- a/drivers/phy/cadence/phy-cadence-dp.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -521,7 +521,7 @@ static int cdns_dp_phy_probe(struct platform_device *pdev)
static const struct of_device_id cdns_dp_phy_of_match[] = {
{
- .compatible = "cdns,dp-phy"
+ .compatible = "cdns,torrent-phy"
},
{}
};
--
2.7.4
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[PATCH v1 10/15] phy: cadence-torrent: Add PHY lane reset support
From: Swapnil Jakhade
Add reset support for PHY lane group.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index 6c3eaaa..ebc3b68 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#define REF_CLK_19_2MHz1920
#define REF_CLK_25MHz 2500
@@ -144,6 +145,7 @@ struct cdns_torrent_phy {
void __iomem *sd_base; /* SD0801 registers base */
u32 num_lanes; /* Number of lanes to use */
u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
+ struct reset_control *phy_rst;
struct device *dev;
struct clk *clk;
unsigned long ref_clk_rate;
@@ -182,9 +184,14 @@ static void cdns_dp_phy_write_field(struct
cdns_torrent_phy *cdns_phy,
unsigned char num_bits,
unsigned int val);
+static int cdns_torrent_phy_on(struct phy *phy);
+static int cdns_torrent_phy_off(struct phy *phy);
+
static const struct phy_ops cdns_torrent_phy_ops = {
.init = cdns_torrent_dp_init,
.exit = cdns_torrent_dp_exit,
+ .power_on = cdns_torrent_phy_on,
+ .power_off = cdns_torrent_phy_off,
.owner = THIS_MODULE,
};
@@ -317,6 +324,9 @@ static int cdns_torrent_dp_init(struct phy *phy)
/* take out of reset */
cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
+
+ cdns_torrent_phy_on(phy);
+
ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
if (ret)
return ret;
@@ -945,6 +955,21 @@ static void cdns_dp_phy_write_field(struct
cdns_torrent_phy *cdns_phy,
start_bit;
}
+static int cdns_torrent_phy_on(struct phy *phy)
+{
+ struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
+
+ /* Take the PHY lane group out of reset */
+ return reset_control_deassert(cdns_phy->phy_rst);
+}
+
+static int cdns_torrent_phy_off(struct phy *phy)
+{
+ struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
+
+ return reset_control_assert(cdns_phy->phy_rst);
+}
+
static int cdns_torrent_phy_probe(struct platform_device *pdev)
{
struct resource *regs;
@@ -976,6 +1001,8 @@ static int cdns_torrent_phy_probe(struct platform_device
*pdev)
if (IS_ERR(cdns_phy->sd_base))
return PTR_ERR(cdns_phy->sd_base);
+ cdns_phy->phy_rst = devm_reset_control_array_get_exclusive(dev);
+
err = device_property_read_u32(dev, "num_lanes",
_phy->num_lanes);
if (err)
--
2.7.4
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[PATCH v1 0/3] drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper.
This patch series adds new DRM driver for Cadence Display Port. The Cadence Display Port is also referred as MHDP (Mobile High Definition Link, High-Definition Multimedia Interface Display Port) Cadence Display Port complies with VESA DisplayPort (DP) and embedded Display Port (eDP) standards This driver implements Single Stream Transport (SST) support. Adds Texas Instruments SoC J721e specific wrapper and adds the device tree bindings in YAML format The patch series has three patches which applies the changes in the below sequence 1. 001-dt-bindings-drm-bridge-Document-Cadence-MHDP-bridge-bindings-in-yaml-format Documents the bindings in yaml format. 2. 002-drm-bridge-Add-support-for-Cadence-MHDP-bridge This patch adds new DRM driver for Cadence MHDP Display Port. The patch implements supports for single stream transport mode. 3. 003-drm-mhdp-add-j721e-wrapper Add Texas Instruments (TI) j721e wrapper for mhdp. The wrapper configures mhdp clocks and muxes as required by SoC. Yuti Amonkar (3): dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format drm: bridge: Add support for Cadence MHDP DPI/DP bridge drm/mhdp: add j721e wrapper .../bindings/display/bridge/cdns,mhdp.yaml | 101 + drivers/gpu/drm/bridge/Kconfig | 21 + drivers/gpu/drm/bridge/Makefile|6 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79 + drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 + drivers/gpu/drm/bridge/cdns-mhdp.c | 2243 drivers/gpu/drm/bridge/cdns-mhdp.h | 381 7 files changed, 2886 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.c create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 08/15] dt-bindings: phy: phy-cadence-torrent: Add clock bindings
Add Torrent PHY reference clock bindings. Signed-off-by: Yuti Amonkar --- .../devicetree/bindings/phy/phy-cadence-torrent.yaml | 12 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index d0037bc..6e1d71e5 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -16,6 +16,14 @@ properties: compatible: const: cdns,torrent-phy + clocks: +maxItems: 1 +description: + PHY reference clock. Must contain an entry in clock-names. + + clock-names: +const: "refclk" + reg: items: - description: Offset of the DPTX PHY configuration registers. @@ -36,6 +44,8 @@ properties: required: - compatible + - clocks + - clock-names - reg - "#phy-cells" @@ -48,5 +58,7 @@ examples: num_lanes = <4>; max_bit_rate = <8100>; #phy-cells = <0>; + clocks = <_clk>; + clock-names = "refclk"; }; ... -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 11/15] phy: cadence-torrent: Implement PHY configure APIs
From: Swapnil Jakhade
Add support for PHY configuration APIs. These will mainly reconfigure
link rate, number of lanes, voltage swing and pre-emphasis values.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 424 ++
1 file changed, 424 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index ebc3b68..006e786 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -37,6 +37,9 @@
#define PHY_AUX_CONFIG 0x00
#define PHY_AUX_CTRL 0x04
#define PHY_RESET 0x20
+#define PMA_TX_ELEC_IDLE_MASK 0xF0U
+#define PMA_TX_ELEC_IDLE_SHIFT 4
+#define PHY_L00_RESET_N_MASK 0x01U
#define PHY_PMA_XCVR_PLLCLK_EN 0x24
#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
@@ -120,6 +123,10 @@
#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x00714
#define CMN_PDIAG_PLL1_FILT_PADJ_M00x00718
+#define TX_TXCC_CTRL 0x10100
+#define TX_TXCC_CPOST_MULT_00 0x10130
+#define TX_TXCC_MGNFS_MULT_000 0x10140
+#define DRV_DIAG_TX_DRV0x10318
#define XCVR_DIAG_PLLDRC_CTRL 0x10394
#define XCVR_DIAG_HSCLK_SEL0x10398
#define XCVR_DIAG_HSCLK_DIV0x1039c
@@ -129,6 +136,8 @@
#define TX_PSC_A2 0x10408
#define TX_PSC_A3 0x1040c
#define TX_RCVDET_ST_TMR 0x1048c
+#define TX_DIAG_ACYA 0x1079c
+#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
#define RX_PSC_A0 0x2
#define RX_PSC_A1 0x20004
#define RX_PSC_A2 0x20008
@@ -140,6 +149,9 @@
#define PHY_PLL_CFG0x30038
+#define PHY_PMA_CMN_CTRL2 0x38004
+#define PHY_PMA_PLL_RAW_CTRL 0x3800c
+
struct cdns_torrent_phy {
void __iomem *base; /* DPTX registers base */
void __iomem *sd_base; /* SD0801 registers base */
@@ -184,12 +196,18 @@ static void cdns_dp_phy_write_field(struct
cdns_torrent_phy *cdns_phy,
unsigned char num_bits,
unsigned int val);
+static int cdns_torrent_dp_configure(struct phy *phy,
+union phy_configure_opts *opts);
+static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
+ u32 num_lanes,
+ enum phy_powerstate powerstate);
static int cdns_torrent_phy_on(struct phy *phy);
static int cdns_torrent_phy_off(struct phy *phy);
static const struct phy_ops cdns_torrent_phy_ops = {
.init = cdns_torrent_dp_init,
.exit = cdns_torrent_dp_exit,
+ .configure = cdns_torrent_dp_configure,
.power_on = cdns_torrent_phy_on,
.power_off = cdns_torrent_phy_off,
.owner = THIS_MODULE,
@@ -203,6 +221,16 @@ static void cdns_torrent_phy_write(struct cdns_torrent_phy
*cdns_phy,
writel(val, cdns_phy->sd_base + offset);
}
+static u32 cdns_torrent_phy_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
+{
+ return readl(cdns_phy->sd_base + offset);
+}
+
+#define cdns_torrent_phy_read_poll_timeout(cdns_phy, offset, val, cond, \
+ delay_us, timeout_us) \
+ readl_poll_timeout((cdns_phy)->sd_base + (offset), \
+ val, cond, delay_us, timeout_us)
+
/* DPTX mmr access functions */
static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
@@ -221,6 +249,237 @@ static u32 cdns_torrent_dp_read(struct cdns_torrent_phy
*cdns_phy, u32 offset)
readl_poll_timeout((cdns_phy)->base + (offset), \
val, cond, delay_us, timeout_us)
+/*
+ * Structure used to store values of PHY registers for voltage-related
+ * coefficients, for particular voltage swing and pre-emphasis level. Values
+ * are shared across all physical lanes.
+ */
+struct coefficients {
+ /* Value of DRV_DIAG_TX_DRV register to use */
+ u16 diag_tx_drv;
+ /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
+ u16 mgnfs_mult;
+ /* Value of TX_TXCC_CPOST_MULT_00 register to use */
+ u16 cpost_mult;
+};
+
+/*
+ * Array consists of values of voltage-related registers for sd0801 PHY. A
value
+ * of 0x is a placeholder for invalid combination, and will never be used.
+ */
+static const struct coefficients vltg_coeff[4][4] = {
+ /* voltage swing 0, pre-emphasis 0->3 */
+ { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
+.cpost_mult = 0x},
+ {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
+.cpost_mult = 0x0014},
+
[PATCH v1 09/15] phy: cadence-torrent: Add 19.2 MHz reference clock support
From: Swapnil Jakhade
Add configuration functions for 19.2 MHz refclock support.
Add register configurations for SSC support.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 456 --
1 file changed, 440 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index b180fba..6c3eaaa 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -6,6 +6,7 @@
*
*/
+#include
#include
#include
#include
@@ -18,7 +19,10 @@
#include
#include
-#define DEFAULT_NUM_LANES 2
+#define REF_CLK_19_2MHz1920
+#define REF_CLK_25MHz 2500
+
+#define DEFAULT_NUM_LANES 4
#define MAX_NUM_LANES 4
#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
@@ -58,6 +62,7 @@
#define CMN_BGCAL_INIT_TMR 0x00190
#define CMN_BGCAL_ITER_TMR 0x00194
#define CMN_IBCAL_INIT_TMR 0x001d0
+#define CMN_PLL0_VCOCAL_TCTRL 0x00208
#define CMN_PLL0_VCOCAL_INIT_TMR 0x00210
#define CMN_PLL0_VCOCAL_ITER_TMR 0x00214
#define CMN_PLL0_VCOCAL_REFTIM_START 0x00218
@@ -67,10 +72,30 @@
#define CMN_PLL0_FRACDIVH_M0 0x00248
#define CMN_PLL0_HIGH_THR_M0 0x0024c
#define CMN_PLL0_DSM_DIAG_M0 0x00250
+#define CMN_PLL0_SS_CTRL1_M0 0x00260
+#define CMN_PLL0_SS_CTRL2_M00x00264
+#define CMN_PLL0_SS_CTRL3_M00x00268
+#define CMN_PLL0_SS_CTRL4_M00x0026C
+#define CMN_PLL0_LOCK_REFCNT_START 0x00270
#define CMN_PLL0_LOCK_PLLCNT_START 0x00278
+#define CMN_PLL0_LOCK_PLLCNT_THR0x0027C
+#define CMN_PLL1_VCOCAL_TCTRL 0x00308
#define CMN_PLL1_VCOCAL_INIT_TMR 0x00310
#define CMN_PLL1_VCOCAL_ITER_TMR 0x00314
+#define CMN_PLL1_VCOCAL_REFTIM_START 0x00318
+#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00320
+#define CMN_PLL1_INTDIV_M0 0x00340
+#define CMN_PLL1_FRACDIVL_M0 0x00344
+#define CMN_PLL1_FRACDIVH_M0 0x00348
+#define CMN_PLL1_HIGH_THR_M0 0x0034c
#define CMN_PLL1_DSM_DIAG_M0 0x00350
+#define CMN_PLL1_SS_CTRL1_M0 0x00360
+#define CMN_PLL1_SS_CTRL2_M00x00364
+#define CMN_PLL1_SS_CTRL3_M00x00368
+#define CMN_PLL1_SS_CTRL4_M00x0036C
+#define CMN_PLL1_LOCK_REFCNT_START 0x00370
+#define CMN_PLL1_LOCK_PLLCNT_START 0x00378
+#define CMN_PLL1_LOCK_PLLCNT_THR0x0037C
#define CMN_TXPUCAL_INIT_TMR 0x00410
#define CMN_TXPUCAL_ITER_TMR 0x00414
#define CMN_TXPDCAL_INIT_TMR 0x00430
@@ -88,18 +113,30 @@
#define CMN_PDIAG_PLL0_FILT_PADJ_M00x00698
#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x006d0
#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x006d4
+#define CMN_PDIAG_PLL1_CTRL_M0 0x00700
#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x00704
+#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x00710
+#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x00714
+#define CMN_PDIAG_PLL1_FILT_PADJ_M00x00718
+
#define XCVR_DIAG_PLLDRC_CTRL 0x10394
#define XCVR_DIAG_HSCLK_SEL0x10398
#define XCVR_DIAG_HSCLK_DIV0x1039c
+#define XCVR_DIAG_BIDI_CTRL0x103a8
#define TX_PSC_A0 0x10400
#define TX_PSC_A1 0x10404
#define TX_PSC_A2 0x10408
#define TX_PSC_A3 0x1040c
+#define TX_RCVDET_ST_TMR 0x1048c
#define RX_PSC_A0 0x2
#define RX_PSC_A1 0x20004
#define RX_PSC_A2 0x20008
#define RX_PSC_A3 0x2000c
+#define RX_PSC_CAL 0x20018
+#define RX_REE_GCSM1_CTRL 0x20420
+#define RX_REE_GCSM2_CTRL 0x20440
+#define RX_REE_PERGCSM_CTRL0x20460
+
#define PHY_PLL_CFG0x30038
struct cdns_torrent_phy {
@@ -108,6 +145,8 @@ struct cdns_torrent_phy {
u32 num_lanes; /* Number of lanes to use */
u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
struct device *dev;
+ struct clk *clk;
+ unsigned long ref_clk_rate;
};
enum phy_powerstate {
@@ -118,17 +157,25 @@ enum phy_powerstate {
};
static int cdns_torrent_dp_init(struct phy *phy);
+static int cdns_torrent_dp_exit(struct phy *phy);
static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
static
int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy);
static
+void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
+static
+void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
+u32 rate, bool ssc);
+static
void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy
[PATCH v1 01/15] phy: Add DisplayPort configuration options
Add generic DP API for configuring DisplayPort PHYs. The parameters
that will be configured are link rate, number of lanes, voltage swing
and pre-emphasis.
Signed-off-by: Yuti Amonkar
---
include/linux/phy/phy-dp.h | 95 ++
include/linux/phy/phy.h| 4 ++
2 files changed, 99 insertions(+)
create mode 100644 include/linux/phy/phy-dp.h
diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
new file mode 100644
index 000..18cad23
--- /dev/null
+++ b/include/linux/phy/phy-dp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Cadence Design Systems Inc.
+ */
+
+#ifndef __PHY_DP_H_
+#define __PHY_DP_H_
+
+#include
+
+/**
+ * struct phy_configure_opts_dp - DisplayPort PHY configuration set
+ *
+ * This structure is used to represent the configuration state of a
+ * DisplayPort phy.
+ */
+struct phy_configure_opts_dp {
+ /**
+* @link_rate:
+*
+* Link Rate, in Mb/s, of the main link.
+*
+* Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
+*/
+ unsigned int link_rate;
+
+ /**
+* @lanes:
+*
+* Number of active, consecutive, data lanes, starting from
+* lane 0, used for the transmissions on main link.
+*
+* Allowed values: 1, 2, 4
+*/
+ unsigned int lanes;
+
+ /**
+* @voltage:
+*
+* Voltage swing levels, as specified by DisplayPort specification,
+* to be used by particular lanes. One value per lane.
+* voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
+*
+* Maximum value: 3
+*/
+ unsigned int voltage[4];
+
+ /**
+* @pre:
+*
+* Pre-emphasis levels, as specified by DisplayPort specification, to be
+* used by particular lanes. One value per lane.
+*
+* Maximum value: 3
+*/
+ unsigned int pre[4];
+
+ /**
+* @ssc:
+*
+* Flag indicating, whether or not to enable spread-spectrum clocking.
+*
+*/
+ u8 ssc : 1;
+
+ /**
+* @set_rate:
+*
+* Flag indicating, whether or not reconfigure link rate and SSC to
+* requested values.
+*
+*/
+ u8 set_rate : 1;
+
+ /**
+* @set_lanes:
+*
+* Flag indicating, whether or not reconfigure lane count to
+* requested value.
+*
+*/
+ u8 set_lanes : 1;
+
+ /**
+* @set_voltages:
+*
+* Flag indicating, whether or not reconfigure voltage swing
+* and pre-emphasis to requested values. Only lanes specified
+* by "lanes" parameter will be affected.
+*
+*/
+ u8 set_voltages : 1;
+};
+
+#endif /* __PHY_DP_H_ */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 15032f14..b981384 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -17,6 +17,7 @@
#include
#include
+#include
struct phy;
@@ -46,9 +47,12 @@ enum phy_mode {
*
* @mipi_dphy: Configuration set applicable for phys supporting
* the MIPI_DPHY phy mode.
+ * @dp:Configuration set applicable for phys supporting
+ * the DisplayPort protocol.
*/
union phy_configure_opts {
struct phy_configure_opts_mipi_dphy mipi_dphy;
+ struct phy_configure_opts_dpdp;
};
/**
--
2.7.4
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[PATCH v1 15/15] phy: cadence-torrent: Add platform dependent initialization structure
Add platform dependent initialization data for Torrent PHY used in TI's
J721E SoC.
Signed-off-by: Yuti Amonkar
---
drivers/phy/cadence/phy-cadence-torrent.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index a64ed4b..29e125b 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1792,11 +1792,20 @@ static const struct cdns_torrent_data cdns_map_torrent
= {
.reg_offset_shift = 0x2,
};
+static const struct cdns_torrent_data ti_j721e_map_torrent = {
+ .block_offset_shift = 0x0,
+ .reg_offset_shift = 0x1,
+};
+
static const struct of_device_id cdns_torrent_phy_of_match[] = {
{
.compatible = "cdns,torrent-phy",
.data = _map_torrent,
},
+ {
+ .compatible = "ti,j721e-serdes-10g",
+ .data = _j721e_map_torrent,
+ },
{}
};
MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
--
2.7.4
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[PATCH v1 07/15] phy: cadence-torrent: Refactor code for reusability
From: Swapnil Jakhade
Add a separate function to set different power state values.
Use uniform polling timeout value. Also check return values
of functions for proper error handling.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 230 ++
1 file changed, 137 insertions(+), 93 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index 5c7c185..b180fba 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -22,7 +22,7 @@
#define MAX_NUM_LANES 4
#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
-#define POLL_TIMEOUT_US2000
+#define POLL_TIMEOUT_US5000
#define LANE_MASK 0x7
/*
@@ -39,6 +39,7 @@
#define PHY_POWER_STATE_LN_1 0x0008
#define PHY_POWER_STATE_LN_2 0x0010
#define PHY_POWER_STATE_LN_3 0x0018
+#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
#define PHY_PMA_CMN_READY 0x34
#define PHY_PMA_XCVR_TX_VMARGIN0x38
@@ -109,10 +110,17 @@ struct cdns_torrent_phy {
struct device *dev;
};
+enum phy_powerstate {
+ POWERSTATE_A0 = 0,
+ /* Powerstate A1 is unused */
+ POWERSTATE_A2 = 2,
+ POWERSTATE_A3 = 3,
+};
+
static int cdns_torrent_dp_init(struct phy *phy);
-static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
+static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
static
-void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
+int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy);
static
void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
@@ -158,9 +166,46 @@ static u32 cdns_torrent_dp_read(struct cdns_torrent_phy
*cdns_phy, u32 offset)
readl_poll_timeout((cdns_phy)->base + (offset), \
val, cond, delay_us, timeout_us)
+/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
+static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
+ u32 num_lanes)
+{
+ u32 pwr_state = cdns_torrent_dp_read(cdns_phy,
+PHY_PMA_XCVR_POWER_STATE_REQ);
+ u32 pll_clk_en = cdns_torrent_dp_read(cdns_phy,
+ PHY_PMA_XCVR_PLLCLK_EN);
+
+ /* Lane 0 is always enabled. */
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_0);
+ pll_clk_en &= ~0x01U;
+
+ if (num_lanes > 1) {
+ /* lane 1 */
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_1);
+ pll_clk_en &= ~(0x01U << 1);
+ }
+
+ if (num_lanes > 2) {
+ /* lanes 2 and 3 */
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_2);
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_3);
+ pll_clk_en &= ~(0x01U << 2);
+ pll_clk_en &= ~(0x01U << 3);
+ }
+
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
+}
+
static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
+ int ret;
struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
@@ -173,40 +218,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
* Set lines power state to A0
* Set lines pll clk enable to 0
*/
-
- cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_0, 6, 0x);
-
- if (cdns_phy->num_lanes >= 2) {
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_1, 6, 0x);
-
- if (cdns_phy->num_lanes == 4) {
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_2, 6, 0);
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_3, 6, 0);
- }
- }
-
- cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
- 0, 1, 0x);
-
- if (cdns_phy->num_lanes >= 2) {
-
[PATCH v1 2/3] drm: bridge: Add support for Cadence MHDP DPI/DP bridge
This patch adds new DRM driver for Cadence MHDP DPTX IP used on J721e SoC.
MHDP DPTX IP is the component that complies with VESA DisplayPort (DP) and
embedded Display Port (eDP) standards.It integrates CPP (uCPU) running the
embedded Firmware(FW) interfaced over APB interface.
Basically, it takes a DPI stream as input and output it encoded in DP
format. Currently, it supports only SST mode.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 11 +
drivers/gpu/drm/bridge/Makefile|3 +
drivers/gpu/drm/bridge/cdns-mhdp.c | 2231
drivers/gpu/drm/bridge/cdns-mhdp.h | 380 ++
4 files changed, 2625 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 3436297..616c05f 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -37,6 +37,17 @@ config DRM_CDNS_DSI
Support Cadence DPI to DSI bridge. This is an internal
bridge and is meant to be directly embedded in a SoC.
+config DRM_CDNS_MHDP
+ tristate "Cadence DPI/DP bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ depends on OF
+ help
+ Support Cadence DPI to DP bridge. This is an internal
+ bridge and is meant to be directly embedded in a SoC.
+ It takes a DPI stream as input and output it encoded
+ in DP format.
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4934fcf..c1a0da7 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -16,4 +16,7 @@ obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
+obj-$(CONFIG_DRM_CDNS_MHDP) += mhdp8546.o
obj-y += synopsys/
+
+mhdp8546-objs := cdns-mhdp.o
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp.c
b/drivers/gpu/drm/bridge/cdns-mhdp.c
new file mode 100644
index 000..42468e1
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp.c
@@ -0,0 +1,2231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cadence MHDP DP bridge driver.
+ *
+ * Copyright: 2019 Cadence Design Systems, Inc.
+ *
+ * Author: Quentin Schulz
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+
+#include "cdns-mhdp.h"
+
+static const struct of_device_id mhdp_ids[] = {
+ { .compatible = "cdns,mhdp8546", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mhdp_ids);
+
+static inline u32 get_unaligned_be24(const void *p)
+{
+ const u8 *_p = p;
+
+ return _p[0] << 16 | _p[1] << 8 | _p[2];
+}
+
+static inline void put_unaligned_be24(u32 val, void *p)
+{
+ u8 *_p = p;
+
+ _p[0] = val >> 16;
+ _p[1] = val >> 8;
+ _p[2] = val;
+}
+
+static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+{
+ int val, ret;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_EMPTY,
+val, !val, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
+}
+
+static int cdns_dp_mailbox_write(struct cdns_mhdp_device *mhdp, u8 val)
+{
+ int ret, full;
+
+ WARN_ON(!mutex_is_locked(>mbox_mutex));
+
+ ret = readx_poll_timeout(readl, mhdp->regs + CDNS_MAILBOX_FULL,
+full, !full, MAILBOX_RETRY_US,
+MAILBOX_TIMEOUT_US);
+ if (ret < 0)
+ return ret;
+
+ writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
+
+ return 0;
+}
+
+static int cdns_mhdp_mailbox_validate_receive(struct cdns_mhdp_device *mhdp,
+ u8 module_id, u8 opcode,
+ u16 req_size)
+{
+ u32 mbox_size, i;
+ u8 header[4];
+ int ret;
+
+ /* read the header of the message */
+ for (i = 0; i < 4; i++) {
+ ret = cdns_mhdp_mailbox_read(mhdp);
+ if (ret < 0)
+ return ret;
+
+ header[i] = ret;
+ }
+
+ mbox_size = get_unaligned_be16(header + 2);
+
+ if (opcode != header[0] || module_id != header[1] ||
+ req_size != mbox_size) {
+ /*
+* If the message in ma
[PATCH v1 3/3] drm/mhdp: add j721e wrapper
Add j721e wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Yuti Amonkar
---
drivers/gpu/drm/bridge/Kconfig | 10
drivers/gpu/drm/bridge/Makefile | 3 ++
drivers/gpu/drm/bridge/cdns-mhdp-j721e.c | 79
drivers/gpu/drm/bridge/cdns-mhdp-j721e.h | 55 ++
drivers/gpu/drm/bridge/cdns-mhdp.c | 14 +-
drivers/gpu/drm/bridge/cdns-mhdp.h | 1 +
6 files changed, 161 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
create mode 100644 drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 616c05f..4b6799b 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -48,6 +48,16 @@ config DRM_CDNS_MHDP
It takes a DPI stream as input and output it encoded
in DP format.
+if DRM_CDNS_MHDP
+
+config DRM_CDNS_MHDP_J721E
+ bool "J721E Cadence DPI/DP wrapper support"
+ default y
+ help
+ Support J721E Cadence DPI/DP wrapper.It sets up
+ the clock and data muxes.
+endif
+
config DRM_DUMB_VGA_DAC
tristate "Dumb VGA DAC Bridge support"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c1a0da7..d358184 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -20,3 +20,6 @@ obj-$(CONFIG_DRM_CDNS_MHDP) += mhdp8546.o
obj-y += synopsys/
mhdp8546-objs := cdns-mhdp.o
+ifeq ($(CONFIG_DRM_CDNS_MHDP_J721E),y)
+ mhdp8546-objs += cdns-mhdp-j721e.o
+endif
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
new file mode 100644
index 000..a87faf5
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include
+
+#include "cdns-mhdp-j721e.h"
+
+#defineREVISION0x00
+#defineDPTX_IPCFG 0x04
+#defineECC_MEM_CFG 0x08
+#defineDPTX_DSC_CFG0x0c
+#defineDPTX_SRC_CFG0x10
+#defineDPTX_VIF_SECURE_MODE_CFG0x14
+#defineDPTX_VIF_CONN_STATUS0x18
+#definePHY_CLK_STATUS 0x1c
+
+#define DPTX_SRC_AIF_ENBIT(16)
+#define DPTX_SRC_VIF_3_IN30B BIT(11)
+#define DPTX_SRC_VIF_2_IN30B BIT(10)
+#define DPTX_SRC_VIF_1_IN30B BIT(9)
+#define DPTX_SRC_VIF_0_IN30B BIT(8)
+#define DPTX_SRC_VIF_3_SEL_DPI5BIT(7)
+#define DPTX_SRC_VIF_3_SEL_DPI30
+#define DPTX_SRC_VIF_2_SEL_DPI4BIT(6)
+#define DPTX_SRC_VIF_2_SEL_DPI20
+#define DPTX_SRC_VIF_1_SEL_DPI3BIT(5)
+#define DPTX_SRC_VIF_1_SEL_DPI10
+#define DPTX_SRC_VIF_0_SEL_DPI2BIT(4)
+#define DPTX_SRC_VIF_0_SEL_DPI00
+#define DPTX_SRC_VIF_3_EN BIT(3)
+#define DPTX_SRC_VIF_2_EN BIT(2)
+#define DPTX_SRC_VIF_1_EN BIT(1)
+#define DPTX_SRC_VIF_0_EN BIT(0)
+
+/* TODO turn DPTX_IPCFG fw_mem_clk_en at pm_runtime_suspend. */
+
+int cdns_mhdp_j721e_init(struct cdns_mhdp_device *mhdp)
+{
+ struct platform_device *pdev = to_platform_device(mhdp->dev);
+ struct resource *regs;
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ mhdp->j721e_regs = devm_ioremap_resource(>dev, regs);
+ if (IS_ERR(mhdp->j721e_regs))
+ return PTR_ERR(mhdp->j721e_regs);
+
+ return 0;
+}
+
+void cdns_mhdp_j721e_fini(struct cdns_mhdp_device *mhdp)
+{
+}
+
+void cdns_mhdp_j721e_enable(struct cdns_mhdp_device *mhdp)
+{
+ /*
+* Eneble VIF_0 and select DPI2 as its input. DSS0 DPI0 is connected
+* to eDP DPI2. This is the only supported SST configuration on
+* J721E.
+*/
+ writel(DPTX_SRC_VIF_0_EN | DPTX_SRC_VIF_0_SEL_DPI2,
+ mhdp->j721e_regs + DPTX_SRC_CFG);
+}
+
+void cdns_mhdp_j721e_disable(struct cdns_mhdp_device *mhdp)
+{
+ /* Put everything to defaults */
+ writel(0, mhdp->j721e_regs + DPTX_DSC_CFG);
+}
diff --git a/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
new file mode 100644
index 000..bd53508
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cdns-mhdp-j721e.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TI j721e Cadence MHDP DP wrapper
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Jyri Sarha
+#include "cdns-mhdp.h"
+
+struct cdns_mhdp_j721e_wrap;
+
+#ifdef CONFIG_DRM_CDNS_M
[PATCH v1 14/15] dt-bindings: phy: phy-cadence-torrent: Add platform dependent compatible string
Add a new compatible string used for TI SoCs using Torrent PHY. Signed-off-by: Yuti Amonkar --- Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index 6e1d71e5..d5fdfb6 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -14,7 +14,9 @@ maintainers: properties: compatible: -const: cdns,torrent-phy +anyOf: + - const: cdns,torrent-phy + - const: ti,j721e-serdes-10g clocks: maxItems: 1 -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 04/15] phy: cadence-torrent: Adopt Torrent nomenclature
From: Swapnil Jakhade
- Change private data struct cdns_dp_phy to cdns_torrent_phy
- Change module description and registration accordingly
- Generic torrent functions have prefix cdns_torrent_phy_*
- Functions specific to Torrent phy for DisplayPort are prefixed as
cdns_torrent_dp_*
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 111 --
1 file changed, 58 insertions(+), 53 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index beb80f7..eb61005 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Cadence MHDP DisplayPort SD0801 PHY driver.
+ * Cadence Torrent SD0801 PHY driver.
*
* Copyright 2018 Cadence Design Systems, Inc.
*
@@ -101,7 +101,7 @@
#define RX_PSC_A3 0x2000c
#define PHY_PLL_CFG0x30038
-struct cdns_dp_phy {
+struct cdns_torrent_phy {
void __iomem *base; /* DPTX registers base */
void __iomem *sd_base; /* SD0801 registers base */
u32 num_lanes; /* Number of lanes to use */
@@ -109,36 +109,39 @@ struct cdns_dp_phy {
struct device *dev;
};
-static int cdns_dp_phy_init(struct phy *phy);
-static void cdns_dp_phy_run(struct cdns_dp_phy *cdns_phy);
-static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy);
-static void cdns_dp_phy_pma_cfg(struct cdns_dp_phy *cdns_phy);
-static void cdns_dp_phy_pma_cmn_cfg_25mhz(struct cdns_dp_phy *cdns_phy);
-static void cdns_dp_phy_pma_lane_cfg(struct cdns_dp_phy *cdns_phy,
+static int cdns_torrent_dp_init(struct phy *phy);
+static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
+static
+void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
+static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy);
+static
+void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
+static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
unsigned int lane);
-static void cdns_dp_phy_pma_cmn_vco_cfg_25mhz(struct cdns_dp_phy *cdns_phy);
-static void cdns_dp_phy_pma_cmn_rate(struct cdns_dp_phy *cdns_phy);
-static void cdns_dp_phy_write_field(struct cdns_dp_phy *cdns_phy,
- unsigned int offset,
- unsigned char start_bit,
- unsigned char num_bits,
- unsigned int val);
-
-static const struct phy_ops cdns_dp_phy_ops = {
- .init = cdns_dp_phy_init,
+static
+void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
+static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy);
+static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
+ unsigned int offset,
+ unsigned char start_bit,
+ unsigned char num_bits,
+ unsigned int val);
+
+static const struct phy_ops cdns_torrent_phy_ops = {
+ .init = cdns_torrent_dp_init,
.owner = THIS_MODULE,
};
-static int cdns_dp_phy_init(struct phy *phy)
+static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
- struct cdns_dp_phy *cdns_phy = phy_get_drvdata(phy);
+ struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */
/* PHY PMA registers configuration function */
- cdns_dp_phy_pma_cfg(cdns_phy);
+ cdns_torrent_dp_pma_cfg(cdns_phy);
/*
* Set lines power state to A0
@@ -185,24 +188,25 @@ static int cdns_dp_phy_init(struct phy *phy)
*/
lane_bits = (1 << cdns_phy->num_lanes) - 1;
writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits),
- cdns_phy->base + PHY_RESET);
+ cdns_phy->base + PHY_RESET);
/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN);
/* PHY PMA registers configuration functions */
- cdns_dp_phy_pma_cmn_vco_cfg_25mhz(cdns_phy);
- cdns_dp_phy_pma_cmn_rate(cdns_phy);
+ cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy);
+ cdns_torrent_dp_pma_cmn_rate(cdns_phy);
/* take out of reset */
cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
- cdns_dp_phy_wait_pma_cmn_ready(cdns_phy);
- cdns_dp_phy_run(cdns_phy);
+ cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
+ cdns_torrent_dp_run(cdns_phy);
return 0;
}
-static void cdns_dp_phy_wait_pma_cmn_ready(struct cdns_dp_phy *cdns_phy)
+static
+void
[PATCH v1 02/15] dt-bindings:phy: Convert Cadence MHDP PHY bindings to YAML.
- Convert the MHDP PHY devicetree bindings to yaml schemas.
- Rename DP PHY to have generic Torrent PHY nomrnclature.
- Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy".
Signed-off-by: Yuti Amonkar
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 30 -
.../bindings/phy/phy-cadence-torrent.yaml | 52 ++
2 files changed, 52 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
deleted file mode 100644
index 7f49fd54e..000
--- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Cadence MHDP DisplayPort SD0801 PHY binding
-===
-
-This binding describes the Cadence SD0801 PHY hardware included with
-the Cadence MHDP DisplayPort controller.
-
-Required properties (controller (parent) node):
-- compatible : Should be "cdns,dp-phy"
-- reg : Defines the following sets of registers in the parent
- mhdp device:
- - Offset of the DPTX PHY configuration registers
- - Offset of the SD0801 PHY configuration registers
-- #phy-cells : from the generic PHY bindings, must be 0.
-
-Optional properties:
-- num_lanes: Number of DisplayPort lanes to use (1, 2 or 4)
-- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
- 2430, 2700, 3240, 4320, 5400 or 8100)
-
-Example:
- dp_phy: phy@f0fb030a00 {
- compatible = "cdns,dp-phy";
- reg = <0xf0 0xfb030a00 0x0 0x0040>,
- <0xf0 0xfb50 0x0 0x0010>;
- num_lanes = <4>;
- max_bit_rate = <8100>;
- #phy-cells = <0>;
- };
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
new file mode 100644
index 000..d0037bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -0,0 +1,52 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence Torrent SD0801 PHY binding for DisplayPort
+
+description:
+ This binding describes the Cadence SD0801 PHY hardware included with
+ the Cadence MHDP DisplayPort controller.
+
+maintainers:
+ - Kishon Vijay Abraham I
+
+properties:
+ compatible:
+const: cdns,torrent-phy
+
+ reg:
+items:
+ - description: Offset of the DPTX PHY configuration registers.
+ - description: Offset of the SD0801 PHY configuration registers.
+
+ "#phy-cells":
+const: 0
+
+ num_lanes:
+maxItems: 1
+description:
+ Number of DisplayPort lanes to use (1, 2 or 4)
+
+ max_bit_rate:
+maxItems: 1
+description:
+ Maximum DisplayPort link bit rate to use, in Mbps (2160, 2430, 2700,
3240, 4320, 5400 or 8100)
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+examples:
+ - |
+dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,torrent-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x0040>,
+<0xf0 0xfb50 0x0 0x0010>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+};
+...
--
2.7.4
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v1 06/15] phy: cadence-torrent: Add wrapper for DPTX register access
From: Swapnil Jakhade
Add wrapper functions to read, write DisplayPort specific PHY registers to
improve code readability.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 71 ++-
1 file changed, 50 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index 59c85d8..5c7c185 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -140,13 +140,31 @@ static void cdns_torrent_phy_write(struct
cdns_torrent_phy *cdns_phy,
writel(val, cdns_phy->sd_base + offset);
}
+/* DPTX mmr access functions */
+
+static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
+ u32 offset, u32 val)
+{
+ writel(val, cdns_phy->base + offset);
+}
+
+static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
+{
+ return readl(cdns_phy->base + offset);
+}
+
+#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \
+ delay_us, timeout_us) \
+ readl_poll_timeout((cdns_phy)->base + (offset), \
+ val, cond, delay_us, timeout_us)
+
static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
- writel(0x0003, cdns_phy->base + PHY_AUX_CTRL); /* enable AUX */
+ cdns_torrent_dp_write(cdns_phy, PHY_AUX_CTRL, 0x0003); /* enable AUX */
/* PHY PMA registers configuration function */
cdns_torrent_dp_pma_cfg(cdns_phy);
@@ -195,11 +213,11 @@ static int cdns_torrent_dp_init(struct phy *phy)
* used lanes
*/
lane_bits = (1 << cdns_phy->num_lanes) - 1;
- writel(((0xF & ~lane_bits) << 4) | (0xF & lane_bits),
- cdns_phy->base + PHY_RESET);
+ cdns_torrent_dp_write(cdns_phy, PHY_RESET,
+ ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
- writel(0x0001, cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
/* PHY PMA registers configuration functions */
cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy);
@@ -219,8 +237,8 @@ void cdns_torrent_dp_wait_pma_cmn_ready(struct
cdns_torrent_phy *cdns_phy)
unsigned int reg;
int ret;
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_CMN_READY, reg,
-reg & 1, 0, 500);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
+ reg, reg & 1, 0, 500);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for PMA common ready\n");
@@ -391,8 +409,10 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy
*cdns_phy)
* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
* master lane
*/
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_PLLCLK_EN_ACK,
-read_val, read_val & 1, 0, POLL_TIMEOUT_US);
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_PLLCLK_EN_ACK,
+ read_val, read_val & 1, 0,
+ POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link PLL clock enable ack\n");
@@ -417,28 +437,35 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy
*cdns_phy)
break;
}
- writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, write_val1);
+
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val,
+ (read_val & mask) == write_val1,
+ 0, POLL_TIMEOUT_US);
- ret = readl_poll_timeout(cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_ACK,
-read_val, (read_val & mask) == write_val1, 0,
-POLL_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_err(cdns_phy->dev,
"timeout waiting for link power state ack\n");
- writel(0, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
ndelay(100);
- writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ);
+
[PATCH v1 13/15] phy: cadence-torrent: Use regmap to read and write DPTX PHY registers
From: Swapnil Jakhade
Use regmap to read and write DPTX specific PHY registers.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 169 +-
1 file changed, 99 insertions(+), 70 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence-torrent.c
index 75b8a81..a64ed4b 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -46,11 +46,12 @@
#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)\
(0xE000 << (block_offset))
+#define TORRENT_DPTX_PHY_OFFSET0x0
+
/*
* register offsets from DPTX PHY register block base (i.e MHDP
* register base + 0x30a00)
*/
-#define PHY_AUX_CONFIG 0x00
#define PHY_AUX_CTRL 0x04
#define PHY_RESET 0x20
#define PMA_TX_ELEC_IDLE_MASK 0xF0U
@@ -66,8 +67,6 @@
#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
#define PHY_PMA_CMN_READY 0x34
-#define PHY_PMA_XCVR_TX_VMARGIN0x38
-#define PHY_PMA_XCVR_TX_DEEMPH 0x3c
/*
* register offsets from SD0801 PHY register block base (i.e MHDP
@@ -180,6 +179,9 @@ static const struct reg_field phy_pma_cmn_ctrl_2 =
static const struct reg_field phy_pma_pll_raw_ctrl =
REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
+static const struct reg_field phy_reset_ctrl =
+ REG_FIELD(PHY_RESET, 8, 8);
+
static const struct of_device_id cdns_torrent_phy_of_match[];
struct cdns_torrent_phy {
@@ -197,9 +199,11 @@ struct cdns_torrent_phy {
struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
+ struct regmap *regmap_dptx_phy_reg;
struct regmap_field *phy_pll_cfg;
struct regmap_field *phy_pma_cmn_ctrl_2;
struct regmap_field *phy_pma_pll_raw_ctrl;
+ struct regmap_field *phy_reset_ctrl;
};
enum phy_powerstate {
@@ -229,12 +233,6 @@ static void cdns_torrent_dp_pma_lane_cfg(struct
cdns_torrent_phy *cdns_phy,
unsigned int lane);
static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
u32 rate, u32 lanes);
-static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
- unsigned int offset,
- unsigned char start_bit,
- unsigned char num_bits,
- unsigned int val);
-
static int cdns_torrent_dp_configure(struct phy *phy,
union phy_configure_opts *opts);
static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
@@ -282,6 +280,27 @@ static int cdns_regmap_read(void *context, unsigned int
reg, unsigned int *val)
return 0;
}
+static int cdns_regmap_dptx_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct cdns_regmap_cdb_context *ctx = context;
+ u32 offset = reg;
+
+ writel(val, ctx->base + offset);
+
+ return 0;
+}
+
+static int cdns_regmap_dptx_read(void *context, unsigned int reg,
+unsigned int *val)
+{
+ struct cdns_regmap_cdb_context *ctx = context;
+ u32 offset = reg;
+
+ *val = readl(ctx->base + offset);
+ return 0;
+}
+
#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
{ \
.name = "torrent_tx_lane" n "_cdb", \
@@ -338,6 +357,14 @@ static struct regmap_config
cdns_torrent_phy_pma_cmn_cdb_config = {
.reg_read = cdns_regmap_read,
};
+static struct regmap_config cdns_torrent_dptx_phy_config = {
+ .name = "torrent_dptx_phy",
+ .reg_stride = 1,
+ .fast_io = true,
+ .reg_write = cdns_regmap_dptx_write,
+ .reg_read = cdns_regmap_dptx_read,
+};
+
/* PHY mmr access functions */
static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
@@ -355,21 +382,18 @@ static u32 cdns_torrent_phy_read(struct regmap *regmap,
u32 offset)
/* DPTX mmr access functions */
-static void cdns_torrent_dp_write(struct cdns_torrent_phy *cdns_phy,
- u32 offset, u32 val)
+static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
{
- writel(val, cdns_phy->base + offset);
+ regmap_write(regmap, offset, val);
}
-static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
+static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
{
- return readl(cdns_phy->base + offset);
-}
+ u32 val;
-#define cdns_torrent_dp_read_poll_timeout(cdns_phy, offset, val, cond, \
- delay_us,
[PATCH v1 1/3] dt-bindings: drm/bridge: Document Cadence MHDP bridge bindings in yaml format
Document the bindings used for the Cadence MHDP DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
---
.../bindings/display/bridge/cdns,mhdp.yaml | 101 +
1 file changed, 101 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
new file mode 100644
index 000..1739f2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml
@@ -0,0 +1,101 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Cadence MHDP bridge
+
+maintainers:
+ - Swapnil Jakhade
+ - Yuti Amonkar
+
+properties:
+ compatible:
+items:
+ - const: ti,j721e-mhdp8546
+ - const: cdns,mhdp8546
+
+ clocks:
+items:
+ descrption:
+DP bridge clock, it's used by the IP to know how to translate a number
of
+clock cycles into a time (which is used to comply with DP standard
timings
+and delays).
+
+ reg:
+items:
+ - description:
+ Register block of mhdptx abp registers upto PHY mapped
area(AUX_CONFIG_P).
+ The AUX and PMA registers are mapped to associated phy driver.
+ - description:
+ Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7
SoCs.
+
+ phys:
+description: see the
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+
+ phy-names:
+const: dpphy
+
+ interrupts:
+maxItems: 1
+
+ power-domains:
+maxItems: 1
+description: phandle to the associated power domain
+
+ ports:
+type: object
+description:
+ Ports as described in Documentation/devictree/bindings/graph.txt
+properties:
+ port@0:
+ description:
+ input port representing the DP bridge input
+
+ port@1:
+ description:
+ output port representing the DP bridge output
+required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - phys
+ - phy-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+mhdp: dp-bridge@f0fb00 {
+compatible = "ti,j721e-mhdp8546", "cdns,mhdp8546";
+reg = <0xf0 0xfb00 0x0 0x100>,
+ <0xf0 0xfc00 0x0 0x200>;
+clocks = <_clock>;
+phys = <_phy>;
+phy-names = "dpphy";
+
+ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp_bridge_input: endpoint {
+ remote-endpoint =
<_dpi_output>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_bridge_output: endpoint {
+ remote-endpoint =
<_dp_connector_input>;
+ };
+ };
+ };
+};
+...
--
2.7.4
___
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[PATCH v1 00/15] PHY: Update Cadence Torrent PHY driver with reconfiguration
This patch series applies to the Cadence SD0801 PHY driver. Cadence SD0801 PHY driver is Torrent PHY driver for Display Port.Torrent PHY is a multiprotocol PHY supporting PHY configurations including Display Port,USB and PCIe. This patch series first adds display port configuration then updates the driver to make it a generic Torrent driver and finally adds SoC platform dependent initialization. The patch series has 15 patches which applies the changes in the below sequence 1. 001-phy-cadance-dp-Add-DisplayPort-configuration-options This patch adds generic DisplayPort API for configuring PHY.The parameters configured are link rate, number of lanes, voltage swing and pre-emphasis. 2. 002-dt-bindings-phy-Convert-Cadence-MHDP-PHY-bindings-to-YAML This patch converts the MHDP PHY device tree bindings to yaml schemas 3. 003-phy-cadence-dp-Rename-to-phy-Cadence-Torrent Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent 4. 004-phy-cadence-torrent-Adopt-Torrent-nomenclature Update private data structures, module descriptions and functions prefix to Torrent 5. 005-phy-cadence-torrent-Add-wrapper-for-PHY-register-access Add a wrapper function to write Torrent PHY registers to improve code readability. 6. 006-phy-cadence-torrent-Add-wrapper-for-DPTX-register-access Add wrapper functions to read, write DisplayPort specific PHY registers to improve code readability. 7. 007-phy-cadence-torrent-Refactor-code-for-reusability Add separate function to set different power state values. Use of uniform polling timeout value. Check return values of functions for error handling. 8. 008-phy-cadence-torrent-Add clock bindings Add Torrent PHY reference clock bindings. 9. 009-phy-cadence-torrent-Add-19.2-MHz-reference-clock-support Add configuration functions for 19.2 MHz reference clock support.Add register configurations for SSC support. 10. 010-phy-cadence-torrent-Add-phy-lane-reset-support Add reset support for PHY lane group. 11. 011-phy-cadence-torrent-Implement-phy-configure-APIs Add PHY configuration APIs for link rate, number of lanes, voltage swing and pre-emphasis values. 12. 012-phy-cadence-torrent-Use-regmap Use regmap for accessing Torrent PHY registers. Update register offsets. Abstract address calculation using regmap APIs. 13. 013-phy: cadence-torrent-Use-regmap-to-read-and-write-DPTX-PHY-registers Use regmap to read and write DPTX specific PHY registers. 14. 014-dt-bindings-phy-phy-cadence-torrent-Add-platform-dependent-compatible-string Add a new compatible string used for TI SoCs using Torrent PHY. 15. 015-phy-cadence-torrent-Add-platform-dependent-initialization-structure Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Swapnil Jakhade (8): phy: cadence-torrent: Adopt Torrent nomenclature phy: cadence-torrent: Add wrapper for PHY register access phy: cadence-torrent: Add wrapper for DPTX register access phy: cadence-torrent: Refactor code for reusability phy: cadence-torrent: Add 19.2 MHz reference clock support phy: cadence-torrent: Add PHY lane reset support phy: cadence-torrent: Implement PHY configure APIs phy: cadence-torrent: Use regmap to read and write DPTX PHY registers Yuti Amonkar (7): phy: Add DisplayPort configuration options dt-bindings:phy: Convert Cadence MHDP PHY bindings to YAML. phy: cadence-dp: Rename to phy-cadence-torrent dt-bindings: phy: phy-cadence-torrent: Add clock bindings phy: cadence-torrent: Use regmap to read and write Torrent PHY registers dt-bindings: phy: phy-cadence-torrent: Add platform dependent compatible string phy: cadence-torrent: Add platform dependent initialization structure .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 - .../bindings/phy/phy-cadence-torrent.yaml | 66 + drivers/phy/cadence/Kconfig|6 +- drivers/phy/cadence/Makefile |2 +- drivers/phy/cadence/phy-cadence-dp.c | 541 -- drivers/phy/cadence/phy-cadence-torrent.c | 1824 include/linux/phy/phy-dp.h | 95 + include/linux/phy/phy.h|4 + 8 files changed, 1993 insertions(+), 575 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml delete mode 100644 drivers/phy/cadence/phy-cadence-dp.c create mode 100644 drivers/phy/cadence/phy-cadence-torrent.c create mode 100644 include/linux/phy/phy-dp.h -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
