[RFC v2 5/5] arm: dts: mt2701: Add display subsystem related nodes for MT2701
From: YT Shen
This patch adds the device nodes for the DISP function blocks for MT2701
Signed-off-by: YT Shen
---
arch/arm/boot/dts/mt2701.dtsi | 117 +
1 file changed, 117 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 363de0d..0beef2a 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -24,6 +24,13 @@
compatible = "mediatek,mt2701";
interrupt-parent = <&sysirq>;
+ aliases {
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ dpi0 = &dpi0;
+ dpi1 = &dpi1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -171,6 +178,14 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};
+ mipi_tx0: mipi-dphy at 1001 {
+ compatible = "mediatek,mt2701-mipi-tx";
+ reg = <0 0x1001 0 0x90>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ status = "disabled";
+ };
+
sysirq: interrupt-controller at 10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -255,6 +270,79 @@
status = "disabled";
};
+ ovl at 14007000 {
+ compatible = "mediatek,mt2701-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma at 14008000 {
+ compatible = "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ wdma at 14009000 {
+ compatible = "mediatek,mt2701-disp-wdma";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ bls at 1400a000 {
+ compatible = "mediatek,mt2701-disp-bls";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_BLS>;
+ };
+
+ color at 1400b000 {
+ compatible = "mediatek,mt2701-disp-color";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ };
+
+ dsi0: dsi at 1400c000 {
+ compatible = "mediatek,mt2701-dsi";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
+<&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dpi0: dpi at 1400d000 {
+ compatible = "mediatek,mt2701-dpi";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DPI_DIGL>,
+<&mmsys CLK_MM_DPI_ENGINE>;
+ clock-names = "clk_dpi_digl",
+ "clk_dpi_engine";
+ status = "disabled";
+ };
+
+ mutex: mutex at 1400e000 {
+ compatible = "mediatek,mt2701-disp-mutex";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
larb0: larb at 1401 {
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x1401 0 0x1000>;
@@ -265,6 +353,35 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};
+ rdma1: rdma at 14012000 {
+ compatible = "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ufoe at 14013000 {
+ compatible = "mediatek,mt2701-disp-ufoe";
+ reg = <0 0x14013000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+
+ dpi1: dpi at 14014000 {
+ compatible = "mediatek,mt2701-dpi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DPI1_DIGL>,
+
[RFC v2 4/5] drm/mediatek: add shadow register support
From: YT Shen
We need to acquire mutex before using the resources,
and need to release it after finished.
So we don't need to write registers in the blanking period.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 26 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp.h |2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c |2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h |1 +
5 files changed, 77 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 3095fc1..5f1eea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -315,6 +315,42 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
*mtk_crtc)
pm_runtime_put(drm->dev);
}
+static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
+{
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
+ struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ unsigned int i;
+
+ /*
+* TODO: instead of updating the registers here, we should prepare
+* working registers in atomic_commit and let the hardware command
+* queue update module registers on vblank.
+*/
+ if (state->pending_config) {
+ mtk_ddp_comp_config(ovl, state->pending_width,
+ state->pending_height,
+ state->pending_vrefresh);
+
+ state->pending_config = false;
+ }
+
+ if (mtk_crtc->pending_planes) {
+ for (i = 0; i < OVL_LAYER_NR; i++) {
+ struct drm_plane *plane = &mtk_crtc->planes[i].base;
+ struct mtk_plane_state *plane_state;
+
+ plane_state = to_mtk_plane_state(plane->state);
+
+ if (plane_state->pending.config) {
+ mtk_ddp_comp_layer_config(ovl, i, plane_state);
+ plane_state->pending.config = false;
+ }
+ }
+ mtk_crtc->pending_planes = false;
+ }
+}
+
static void mtk_drm_crtc_enable(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
@@ -391,6 +427,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_drm_private *priv = crtc->dev->dev_private;
unsigned int pending_planes = 0;
int i;
@@ -409,6 +446,12 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc
*crtc,
}
if (pending_planes)
mtk_crtc->pending_planes = true;
+
+ if (priv->data->shadow_register) {
+ mtk_disp_mutex_acquire(mtk_crtc->mutex);
+ mtk_crtc_ddp_config(crtc);
+ mtk_disp_mutex_release(mtk_crtc->mutex);
+ }
}
static const struct drm_crtc_funcs mtk_crtc_funcs = {
@@ -453,36 +496,10 @@ err_cleanup_crtc:
void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
- unsigned int i;
+ struct mtk_drm_private *priv = crtc->dev->dev_private;
- /*
-* TODO: instead of updating the registers here, we should prepare
-* working registers in atomic_commit and let the hardware command
-* queue update module registers on vblank.
-*/
- if (state->pending_config) {
- mtk_ddp_comp_config(ovl, state->pending_width,
- state->pending_height,
- state->pending_vrefresh);
-
- state->pending_config = false;
- }
-
- if (mtk_crtc->pending_planes) {
- for (i = 0; i < OVL_LAYER_NR; i++) {
- struct drm_plane *plane = &mtk_crtc->planes[i].base;
- struct mtk_plane_state *plane_state;
-
- plane_state = to_mtk_plane_state(plane->state);
-
- if (plane_state->pending.config) {
- mtk_ddp_comp_layer_config(ovl, i, plane_state);
- plane_state->pending.config = false;
- }
- }
- mtk_crtc->pending_planes = false;
- }
+ if (!priv->data->shadow_register)
+ mtk_crtc_ddp_config(crtc);
mtk_drm_finish_page_flip(mtk_crtc);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 529569d..f09a414 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_
[RFC v2 3/5] drm/mediatek: add *driver_data for different hardware settings
From: YT Shen
There are some hardware settings changed, between MT8173 & MT2701:
DISP_OVL address offset changed, color format definition changed.
DISP_RDMA fifo size changed.
DISP_COLOR offset changed.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 +++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 36
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 40 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 13 +++
4 files changed, 111 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8f62671f..8d2811d 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -40,8 +40,6 @@
#defineOVL_RDMA_MEM_GMC0x40402020
#define OVL_CON_BYTE_SWAP BIT(24)
-#define OVL_CON_CLRFMT_RGB565 (0 << 12)
-#define OVL_CON_CLRFMT_RGB888 (1 << 12)
#define OVL_CON_CLRFMT_RGBA(2 << 12)
#define OVL_CON_CLRFMT_ARGB(3 << 12)
#defineOVL_CON_AEN BIT(8)
@@ -136,18 +134,18 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp,
unsigned int idx)
writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
}
-static unsigned int ovl_fmt_convert(unsigned int fmt)
+static unsigned int ovl_fmt_convert(struct mtk_ddp_comp *comp, unsigned int
fmt)
{
switch (fmt) {
default:
case DRM_FORMAT_RGB565:
- return OVL_CON_CLRFMT_RGB565;
+ return comp->data->ovl.fmt_rgb565;
case DRM_FORMAT_BGR565:
- return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
+ return comp->data->ovl.fmt_rgb565 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGB888:
- return OVL_CON_CLRFMT_RGB888;
+ return comp->data->ovl.fmt_rgb888;
case DRM_FORMAT_BGR888:
- return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
+ return comp->data->ovl.fmt_rgb888 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGBX:
case DRM_FORMAT_RGBA:
return OVL_CON_CLRFMT_ARGB;
@@ -177,7 +175,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp,
unsigned int idx,
if (!pending->enable)
mtk_ovl_layer_off(comp, idx);
- con = ovl_fmt_convert(fmt);
+ con = ovl_fmt_convert(comp, fmt);
if (idx != 0)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
@@ -185,7 +183,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp,
unsigned int idx,
writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
- writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
+ writel_relaxed(addr, comp->regs + (comp->data->ovl.addr_offset + idx *
0x20));
if (pending->enable)
mtk_ovl_layer_on(comp, idx);
@@ -233,6 +231,32 @@ static const struct component_ops
mtk_disp_ovl_component_ops = {
.unbind = mtk_disp_ovl_unbind,
};
+static const struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = {
+ .ovl = {0x0040, 1 << 12, 0}
+};
+
+static const struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = {
+ .ovl = {0x0f40, 0, 1 << 12}
+};
+
+static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt2701-disp-ovl",
+ .data = &mt2701_ovl_driver_data},
+ { .compatible = "mediatek,mt8173-disp-ovl",
+ .data = &mt8173_ovl_driver_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
+
+static inline struct mtk_ddp_comp_driver_data *mtk_ovl_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(mtk_disp_ovl_driver_dt_match, &pdev->dev);
+
+ return (struct mtk_ddp_comp_driver_data *)of_id->data;
+}
+
static int mtk_disp_ovl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -269,6 +293,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
return ret;
}
+ priv->ddp_comp.data = mtk_ovl_get_driver_data(pdev);
+
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_ovl_component_ops);
@@ -285,11 +311,6 @@ static int mtk_disp_ovl_remove(struct platform_device
*pdev)
return 0;
}
-static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
- { .compatible = "mediatek,mt8173-disp-ovl", },
- {},
-};
-MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
struct platform_driver mtk_disp_ovl_driver = {
.probe = mtk_disp_ovl_probe,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 5fb80cb..a20a6cd 100644
--- a/drivers/gpu
[RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701
From: YT Shen
This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 63 +---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 70 ++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h |8 +++
5 files changed, 126 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index d6aafd4..529569d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -31,6 +31,10 @@
#define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
@@ -52,6 +56,13 @@
#define MUTEX_MOD_DISP_PWM1_MT8173 BIT(24)
#define MUTEX_MOD_DISP_OD_MT8173 BIT(25)
+#define MUTEX_MOD_DISP_OVL_MT2701 BIT(3)
+#define MUTEX_MOD_DISP_WDMA_MT2701 BIT(6)
+#define MUTEX_MOD_DISP_COLOR_MT2701BIT(7)
+#define MUTEX_MOD_DISP_BLS_MT2701 BIT(9)
+#define MUTEX_MOD_DISP_RDMA0_MT2701BIT(10)
+#define MUTEX_MOD_DISP_RDMA1_MT2701BIT(12)
+
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
#define MUTEX_SOF_DSI1 2
@@ -67,6 +78,10 @@
#define DPI0_SEL_IN_RDMA1 0x1
#define COLOR1_SEL_IN_OVL1 0x1
+#define OVL_MOUT_EN_RDMA 0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
+#define DSI_SEL_IN_BLS 0x0
+
struct mtk_disp_mutex {
int id;
bool claimed;
@@ -77,6 +92,16 @@ struct mtk_ddp {
struct clk *clk;
void __iomem*regs;
struct mtk_disp_mutex mutex[10];
+ const unsigned int *mutex_mod;
+};
+
+static const unsigned int mutex_mod_mt2701[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_BLS] = MUTEX_MOD_DISP_BLS_MT2701,
+ [DDP_COMPONENT_COLOR0] = MUTEX_MOD_DISP_COLOR_MT2701,
+ [DDP_COMPONENT_OVL0] = MUTEX_MOD_DISP_OVL_MT2701,
+ [DDP_COMPONENT_RDMA0] = MUTEX_MOD_DISP_RDMA0_MT2701,
+ [DDP_COMPONENT_RDMA1] = MUTEX_MOD_DISP_RDMA1_MT2701,
+ [DDP_COMPONENT_WDMA0] = MUTEX_MOD_DISP_WDMA_MT2701,
};
static const unsigned int mutex_mod_mt8173[DDP_COMPONENT_ID_MAX] = {
@@ -106,6 +131,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id
cur,
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+ *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
@@ -143,6 +171,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
value = COLOR1_SEL_IN_OVL1;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_BLS;
} else {
value = 0;
}
@@ -150,6 +181,15 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id
cur,
return value;
}
+static void mtk_ddp_mux_sel(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next)
+{
+ if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+ writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+ config_regs + DISP_REG_CONFIG_OUT_SEL);
+ }
+}
+
void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -162,6 +202,8 @@ void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
writel_relaxed(reg, config_regs + addr);
}
+ mtk_ddp_mux_sel(config_regs, cur, next);
+
value = mtk_ddp_sel_in(cur, next, &addr);
if (value) {
reg = readl_relaxed(config_regs + addr) | value;
@@ -247,7 +289,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
[RFC v2 1/5] drm/mediatek: rename macros, add chip suffix
From: YT Shen
Add MT8173 suffix for hardware related macros.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 62
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 17ba935..d6aafd4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -36,21 +36,21 @@
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
-#define MUTEX_MOD_DISP_OVL0BIT(11)
-#define MUTEX_MOD_DISP_OVL1BIT(12)
-#define MUTEX_MOD_DISP_RDMA0 BIT(13)
-#define MUTEX_MOD_DISP_RDMA1 BIT(14)
-#define MUTEX_MOD_DISP_RDMA2 BIT(15)
-#define MUTEX_MOD_DISP_WDMA0 BIT(16)
-#define MUTEX_MOD_DISP_WDMA1 BIT(17)
-#define MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MUTEX_MOD_DISP_AAL BIT(20)
-#define MUTEX_MOD_DISP_GAMMA BIT(21)
-#define MUTEX_MOD_DISP_UFOEBIT(22)
-#define MUTEX_MOD_DISP_PWM0BIT(23)
-#define MUTEX_MOD_DISP_PWM1BIT(24)
-#define MUTEX_MOD_DISP_OD BIT(25)
+#define MUTEX_MOD_DISP_OVL0_MT8173 BIT(11)
+#define MUTEX_MOD_DISP_OVL1_MT8173 BIT(12)
+#define MUTEX_MOD_DISP_RDMA0_MT8173BIT(13)
+#define MUTEX_MOD_DISP_RDMA1_MT8173BIT(14)
+#define MUTEX_MOD_DISP_RDMA2_MT8173BIT(15)
+#define MUTEX_MOD_DISP_WDMA0_MT8173BIT(16)
+#define MUTEX_MOD_DISP_WDMA1_MT8173BIT(17)
+#define MUTEX_MOD_DISP_COLOR0_MT8173 BIT(18)
+#define MUTEX_MOD_DISP_COLOR1_MT8173 BIT(19)
+#define MUTEX_MOD_DISP_AAL_MT8173 BIT(20)
+#define MUTEX_MOD_DISP_GAMMA_MT8173BIT(21)
+#define MUTEX_MOD_DISP_UFOE_MT8173 BIT(22)
+#define MUTEX_MOD_DISP_PWM0_MT8173 BIT(23)
+#define MUTEX_MOD_DISP_PWM1_MT8173 BIT(24)
+#define MUTEX_MOD_DISP_OD_MT8173 BIT(25)
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -79,22 +79,22 @@ struct mtk_ddp {
struct mtk_disp_mutex mutex[10];
};
-static const unsigned int mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = MUTEX_MOD_DISP_AAL,
- [DDP_COMPONENT_COLOR0] = MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_COLOR1] = MUTEX_MOD_DISP_COLOR1,
- [DDP_COMPONENT_GAMMA] = MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OD] = MUTEX_MOD_DISP_OD,
- [DDP_COMPONENT_OVL0] = MUTEX_MOD_DISP_OVL0,
- [DDP_COMPONENT_OVL1] = MUTEX_MOD_DISP_OVL1,
- [DDP_COMPONENT_PWM0] = MUTEX_MOD_DISP_PWM0,
- [DDP_COMPONENT_PWM1] = MUTEX_MOD_DISP_PWM1,
- [DDP_COMPONENT_RDMA0] = MUTEX_MOD_DISP_RDMA0,
- [DDP_COMPONENT_RDMA1] = MUTEX_MOD_DISP_RDMA1,
- [DDP_COMPONENT_RDMA2] = MUTEX_MOD_DISP_RDMA2,
- [DDP_COMPONENT_UFOE] = MUTEX_MOD_DISP_UFOE,
- [DDP_COMPONENT_WDMA0] = MUTEX_MOD_DISP_WDMA0,
- [DDP_COMPONENT_WDMA1] = MUTEX_MOD_DISP_WDMA1,
+static const unsigned int mutex_mod_mt8173[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL] = MUTEX_MOD_DISP_AAL_MT8173,
+ [DDP_COMPONENT_COLOR0] = MUTEX_MOD_DISP_COLOR0_MT8173,
+ [DDP_COMPONENT_COLOR1] = MUTEX_MOD_DISP_COLOR1_MT8173,
+ [DDP_COMPONENT_GAMMA] = MUTEX_MOD_DISP_GAMMA_MT8173,
+ [DDP_COMPONENT_OD] = MUTEX_MOD_DISP_OD_MT8173,
+ [DDP_COMPONENT_OVL0] = MUTEX_MOD_DISP_OVL0_MT8173,
+ [DDP_COMPONENT_OVL1] = MUTEX_MOD_DISP_OVL1_MT8173,
+ [DDP_COMPONENT_PWM0] = MUTEX_MOD_DISP_PWM0_MT8173,
+ [DDP_COMPONENT_PWM1] = MUTEX_MOD_DISP_PWM1_MT8173,
+ [DDP_COMPONENT_RDMA0] = MUTEX_MOD_DISP_RDMA0_MT8173,
+ [DDP_COMPONENT_RDMA1] = MUTEX_MOD_DISP_RDMA1_MT8173,
+ [DDP_COMPONENT_RDMA2] = MUTEX_MOD_DISP_RDMA2_MT8173,
+ [DDP_COMPONENT_UFOE] = MUTEX_MOD_DISP_UFOE_MT8173,
+ [DDP_COMPONENT_WDMA0] = MUTEX_MOD_DISP_WDMA0_MT8173,
+ [DDP_COMPONENT_WDMA1] = MUTEX_MOD_DISP_WDMA1_MT8173,
};
static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
--
1.7.9.5
[RFC v2 0/5] MT2701 DRM support
From: YT Shen
This is MT2701 DRM support RFC, based on MT8173 DRM patch v16.
Most codes are the same, except some register changed.
For example:
- DISP_OVL address offset changed, color format definition changed.
- DISP_RDMA fifo size changed.
- DISP_COLOR offset changed.
We add a new component DISP_BLS, and the connection settings are updated.
And we have shadow register support in MT2701.
Changes since v1:
- Removed BLS bindings and codes, which belong to pwm driver
- Moved mtk_disp_mutex_acquire() just before mtk_crtc_ddp_config()
- Split patch into smaller parts
- Added const keyword to constant structure
- Removed codes for special memory align
The RFC depends on MT2701 iommu/smi driver.
https://patchwork.kernel.org/patch/9043411/ ("dt-bindings: mediatek: add
descriptions for mediatek mt2701 iommu and smi"),
https://patchwork.kernel.org/patch/9043391/ ("iommu/mediatek: move the common
struct into header file"),
https://patchwork.kernel.org/patch/9043421/ ("memory/mediatek: add support for
mt2701"),
https://patchwork.kernel.org/patch/9043451/ ("iommu/mediatek: add support for
mtk iommu generation one HW"),
https://patchwork.kernel.org/patch/9043471/ ("ARM: dts: mt2701: add iommu/smi
dtsi node for mt2701"),
Thanks,
yt.shen
YT Shen (5):
drm/mediatek: rename macros, add chip suffix
drm/mediatke: add support for Mediatek SoC MT2701
drm/mediatek: add *driver_data for different hardware settings
drm/mediatek: add shadow register support
arm: dts: mt2701: Add display subsystem related nodes for MT2701
arch/arm/boot/dts/mt2701.dtsi | 117 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 ++---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 36 +--
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 75 -
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 151 ---
drivers/gpu/drm/mediatek/mtk_drm_ddp.h |2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 42 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 15 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 72 +++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h |9 ++
10 files changed, 462 insertions(+), 106 deletions(-)
--
1.7.9.5
[RFC 3/3] arm: dts: mt2701: Add display subsystem related nodes for MT2701
From: YT Shen
This patch adds the device nodes for the DISP function blocks for MT2701
Signed-off-by: YT Shen
---
arch/arm/boot/dts/mt2701.dtsi | 117 +
1 file changed, 117 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 363de0d..0beef2a 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -24,6 +24,13 @@
compatible = "mediatek,mt2701";
interrupt-parent = <&sysirq>;
+ aliases {
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ dpi0 = &dpi0;
+ dpi1 = &dpi1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -171,6 +178,14 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};
+ mipi_tx0: mipi-dphy at 1001 {
+ compatible = "mediatek,mt2701-mipi-tx";
+ reg = <0 0x1001 0 0x90>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ status = "disabled";
+ };
+
sysirq: interrupt-controller at 10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -255,6 +270,79 @@
status = "disabled";
};
+ ovl at 14007000 {
+ compatible = "mediatek,mt2701-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_OVL>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma at 14008000 {
+ compatible = "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ wdma at 14009000 {
+ compatible = "mediatek,mt2701-disp-wdma";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ bls at 1400a000 {
+ compatible = "mediatek,mt2701-disp-bls";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_BLS>;
+ };
+
+ color at 1400b000 {
+ compatible = "mediatek,mt2701-disp-color";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ };
+
+ dsi0: dsi at 1400c000 {
+ compatible = "mediatek,mt2701-dsi";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
+<&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dpi0: dpi at 1400d000 {
+ compatible = "mediatek,mt2701-dpi";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DPI_DIGL>,
+<&mmsys CLK_MM_DPI_ENGINE>;
+ clock-names = "clk_dpi_digl",
+ "clk_dpi_engine";
+ status = "disabled";
+ };
+
+ mutex: mutex at 1400e000 {
+ compatible = "mediatek,mt2701-disp-mutex";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
larb0: larb at 1401 {
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x1401 0 0x1000>;
@@ -265,6 +353,35 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};
+ rdma1: rdma at 14012000 {
+ compatible = "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ufoe at 14013000 {
+ compatible = "mediatek,mt2701-disp-ufoe";
+ reg = <0 0x14013000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+
+ dpi1: dpi at 14014000 {
+ compatible = "mediatek,mt2701-dpi";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = ;
+ clocks = <&mmsys CLK_MM_DPI1_DIGL>,
+
[RFC 2/3] drm/mediatek: add support for Mediatek SoC MT2701
From: YT Shen
This patch add support for the Mediatek MT2701 DISP subsystem.
There is only one OVL engine in MT2701, and we have shadow
register support here.
Signed-off-by: YT Shen
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 ++---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c| 36 +--
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 78 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 151 ---
drivers/gpu/drm/mediatek/mtk_drm_ddp.h |2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 63 +--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 15 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 72 +++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h |9 ++
drivers/gpu/drm/mediatek/mtk_drm_gem.c |4 +
10 files changed, 373 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8f62671f..e4a10bd6 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -40,8 +40,6 @@
#defineOVL_RDMA_MEM_GMC0x40402020
#define OVL_CON_BYTE_SWAP BIT(24)
-#define OVL_CON_CLRFMT_RGB565 (0 << 12)
-#define OVL_CON_CLRFMT_RGB888 (1 << 12)
#define OVL_CON_CLRFMT_RGBA(2 << 12)
#define OVL_CON_CLRFMT_ARGB(3 << 12)
#defineOVL_CON_AEN BIT(8)
@@ -136,18 +134,18 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp,
unsigned int idx)
writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
}
-static unsigned int ovl_fmt_convert(unsigned int fmt)
+static unsigned int ovl_fmt_convert(struct mtk_ddp_comp *comp, unsigned int
fmt)
{
switch (fmt) {
default:
case DRM_FORMAT_RGB565:
- return OVL_CON_CLRFMT_RGB565;
+ return comp->data->ovl.fmt_rgb565;
case DRM_FORMAT_BGR565:
- return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
+ return comp->data->ovl.fmt_rgb565 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGB888:
- return OVL_CON_CLRFMT_RGB888;
+ return comp->data->ovl.fmt_rgb888;
case DRM_FORMAT_BGR888:
- return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
+ return comp->data->ovl.fmt_rgb888 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGBX:
case DRM_FORMAT_RGBA:
return OVL_CON_CLRFMT_ARGB;
@@ -177,7 +175,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp,
unsigned int idx,
if (!pending->enable)
mtk_ovl_layer_off(comp, idx);
- con = ovl_fmt_convert(fmt);
+ con = ovl_fmt_convert(comp, fmt);
if (idx != 0)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
@@ -185,7 +183,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp,
unsigned int idx,
writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
- writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
+ writel_relaxed(addr, comp->regs + (comp->data->ovl.addr_offset + idx *
0x20));
if (pending->enable)
mtk_ovl_layer_on(comp, idx);
@@ -233,6 +231,32 @@ static const struct component_ops
mtk_disp_ovl_component_ops = {
.unbind = mtk_disp_ovl_unbind,
};
+static struct mtk_ddp_comp_driver_data mt2701_ovl_driver_data = {
+ .ovl = {0x0040, 1 << 12, 0}
+};
+
+static struct mtk_ddp_comp_driver_data mt8173_ovl_driver_data = {
+ .ovl = {0x0f40, 0, 1 << 12}
+};
+
+static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
+ { .compatible = "mediatek,mt2701-disp-ovl",
+ .data = &mt2701_ovl_driver_data},
+ { .compatible = "mediatek,mt8173-disp-ovl",
+ .data = &mt8173_ovl_driver_data},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
+
+static inline struct mtk_ddp_comp_driver_data *mtk_ovl_get_driver_data(
+ struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(mtk_disp_ovl_driver_dt_match, &pdev->dev);
+
+ return (struct mtk_ddp_comp_driver_data *)of_id->data;
+}
+
static int mtk_disp_ovl_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -269,6 +293,8 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
return ret;
}
+ priv->ddp_comp.data = mtk_ovl_get_driver_data(pdev);
+
platform_set_drvdata(pdev, priv);
ret = component_add(dev, &mtk_disp_ovl_component_ops);
@@ -285,11 +311,6 @@ static int mtk_disp_ovl_remove(struct platform_device
*pdev)
return 0;
}
-static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
- { .compatible = "mediatek,mt8173-disp-ovl", },
- {},
-};
-MODULE_DEVICE_TABL
[RFC 1/3] dt-bindings: drm/mediatek: Add display binding for Mediatek SoC MT2701
From: YT Shen Add device tree binding documentation for the display subsystem in Mediatek SoC MT2701 Signed-off-by: YT Shen --- .../bindings/display/mediatek/mediatek,disp.txt|1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index db6e77e..53b3cc3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,6 +40,7 @@ Required properties (all function blocks): "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt "mediatek,-disp-mutex" - display mutex "mediatek,-disp-od"- overdrive + "mediatek,-disp-bls" - backlight - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 1.7.9.5
[RFC 0/3] MT2701 DRM support
From: YT Shen
This is MT2701 DRM support RFC, based on MT8173 DRM patch v16.
Most codes are the same, except some register changed.
For example:
- DISP_OVL address offset changed, color format definition changed.
- DISP_RDMA fifo size changed.
- DISP_COLOR offset changed.
We add a new component DISP_BLS, and the connection settings are updated.
And we have shadow register support in MT2701.
The RFC depends on MT2701 iommu/smi driver.
https://patchwork.kernel.org/patch/9043411/ ("dt-bindings: mediatek: add
descriptions for mediatek mt2701 iommu and smi"),
https://patchwork.kernel.org/patch/9043391/ ("iommu/mediatek: move the common
struct into header file"),
https://patchwork.kernel.org/patch/9043421/ ("memory/mediatek: add support for
mt2701"),
https://patchwork.kernel.org/patch/9043451/ ("iommu/mediatek: add support for
mtk iommu generation one HW"),
https://patchwork.kernel.org/patch/9043471/ ("ARM: dts: mt2701: add iommu/smi
dtsi node for mt2701"),
Thanks,
yt.shen
YT Shen (3):
dt-bindings: drm/mediatek: Add display binding for Mediatek SoC MT2701
drm/mediatek: add support for Mediatek SoC MT2701
arm: dts: mt2701: Add display subsystem related nodes for MT2701
.../bindings/display/mediatek/mediatek,disp.txt|1 +
arch/arm/boot/dts/mt2701.dtsi | 117 +++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c| 49 +--
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 36 -
drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 78 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 151 +++-
drivers/gpu/drm/mediatek/mtk_drm_ddp.h |2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 63 +++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 15 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 72 --
drivers/gpu/drm/mediatek/mtk_drm_drv.h |9 ++
drivers/gpu/drm/mediatek/mtk_drm_gem.c |4 +
12 files changed, 491 insertions(+), 106 deletions(-)
--
1.7.9.5
