[Intel-gfx] [PATCH 6/8] drm/i915: Enable/Disable PSR
On Tue, 26 Feb 2013 14:48:33 +0200
Ville Syrj?l? wrote:
> On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote:
> > Adding Enable and Disable PSR functionalities. This includes setting the
> > PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
> > enabling PSR in the sink via DPCD register and finally enabling PSR on
> > the host.
> >
> > This patch is heavily based on initial PSR code by Sateesh Kavuri and
> > Kumar Shobhit but in a different implementation.
> >
> > Credits-by: Sateesh Kavuri
> > Credits-by: Shobhit Kumar
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 40 +
> > drivers/gpu/drm/i915/intel_dp.c | 183
> > +++
> > drivers/gpu/drm/i915/intel_drv.h | 3 +
> > 3 files changed, 226 insertions(+)
> >
>
> > +void intel_edp_write_vsc_psr(struct intel_dp* intel_dp,
> > +struct edp_vsc_psr *vsc_psr)
> > +{
> > + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct intel_crtc *intel_crtc =
> > to_intel_crtc(intel_dp_to_crtc(intel_dp));
> > + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
> > + u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(intel_crtc->cpu_transcoder);
> > + uint32_t *data = (uint32_t *)vsc_psr;
> > + unsigned int i;
> > + u32 val = I915_READ(ctl_reg);
> > +
> > + if (data_reg == 0)
> > + return;
> > +
> > + /* As per eDP spec, wait for vblank to send SDP VSC packet */
> > + intel_wait_for_vblank(dev, intel_crtc->pipe);
> > +
> > + mmiowb();
>
> I was curious about these mmiowb()s and apparently they were added to
> all infoframe writes "just in case". But AFAICS on x86 mmiowb() ends
> up as a compiler barrier, so this stuff seems to be a nop.
>
> And if these writes can get reordered somewhere, why not everything
> else too? I'm sure we have places where we write a bunch of registers,
> and the final write enables something which requires the earlier
> writes to have landed beforehand.
Yeah we shouldn't need mmiowb() anywhere in our driver (until our
on-chip topology gets really complicated anyway).
--
Jesse Barnes, Intel Open Source Technology Center
[Intel-gfx] [PATCH 6/8] drm/i915: Enable/Disable PSR
Hi
2013/2/26 Ville Syrj?l? :
> On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote:
>> Adding Enable and Disable PSR functionalities. This includes setting the
>> PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
>> enabling PSR in the sink via DPCD register and finally enabling PSR on
>> the host.
>>
>> This patch is heavily based on initial PSR code by Sateesh Kavuri and
>> Kumar Shobhit but in a different implementation.
>>
>> Credits-by: Sateesh Kavuri
>> Credits-by: Shobhit Kumar
>> Signed-off-by: Rodrigo Vivi
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 40 +
>> drivers/gpu/drm/i915/intel_dp.c | 183
>> +++
>> drivers/gpu/drm/i915/intel_drv.h | 3 +
>> 3 files changed, 226 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index b715ecd..1e31f23 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -844,6 +844,8 @@
>> #define SNB_CPU_FENCE_ENABLE (1<<29)
>> #define DPFC_CPU_FENCE_OFFSET0x100104
>>
>> +/* Framebuffer compression for Haswell */
>> +#define HSW_FBC_CONTROL 0x43208
>>
>> /*
>> * GPIO regs
>> @@ -1580,6 +1582,44 @@
>> #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
>> #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>>
>> +/* HSW eDP PSR registers */
>> +#define EDP_PSR_CTL 0x64800
>> +#define EDP_PSR_ENABLE (1<<31)
>> +#define EDP_PSR_LINK_DISABLE (0<<27)
>> +#define EDP_PSR_LINK_STANDBY (1<<27)
>> +#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
>> +#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES(0<<25)
>> +#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES(1<<25)
>> +#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES(2<<25)
>> +#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES(3<<25)
>> +#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
>> +#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
>> +#define EDP_PSR_TP1_TP2_SEL(0<<11)
>> +#define EDP_PSR_TP1_TP3_SEL(1<<11)
>> +#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
>> +#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
>> +#define EDP_PSR_TP2_TP3_TIME_2500us(2<<8)
>> +#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
>> +#define EDP_PSR_TP1_TIME_500us (0<<4)
>> +#define EDP_PSR_TP1_TIME_100us (1<<4)
>> +#define EDP_PSR_TP1_TIME_2500us(2<<4)
>> +#define EDP_PSR_TP1_TIME_0us (3<<4)
>> +#define EDP_PSR_IDLE_FRAME_SHIFT 0
>> +
>> +#define EDP_PSR_AUX_CTL 0x64810
>> +#define EDP_PSR_AUX_DATA10x64814
>> +#define EDP_PSR_AUX_DATA20x64818
>> +#define EDP_PSR_AUX_DATA30x6481c
>> +#define EDP_PSR_AUX_DATA40x64820
>> +#define EDP_PSR_AUX_DATA50x64824
>> +
>> +#define EDP_PSR_STATUS_CTL 0x64840
>> +#define EDP_PSR_STATUS_STATE_MASK (7<<29)
>> +
>> +#define EDP_PSR_DEBUG_CTL0x64860
>> +#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
>> +#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
>> +
>> /* VGA port control */
>> #define ADPA 0x61100
>> #define PCH_ADPA0xe1100
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>> b/drivers/gpu/drm/i915/intel_dp.c
>> index 5cfa9f4..a420f0d 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -83,6 +83,13 @@ static struct drm_device *intel_dp_to_dev(struct intel_dp
>> *intel_dp)
>> return intel_dig_port->base.base.dev;
>> }
>>
>> +static struct drm_crtc *intel_dp_to_crtc(struct intel_dp *intel_dp)
>> +{
>> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> +
>> + return intel_dig_port->base.base.crtc;
>> +}
>> +
>> static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
>> {
>> return enc_to_intel_dp(_attached_encoder(connector)->base);
>> @@ -1443,6 +1450,182 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
>> (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED));
>> }
>>
>> +static bool
>> +intel_edp_is_psr_enabled(struct intel_dp* intel_dp)
>> +{
>> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
>> +}
>> +
>> +static void
>> +intel_edp_psr_enable_src(struct intel_dp *intel_dp)
>> +{
>> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
>> + struct drm_i915_private *dev_priv = dev->dev_private;
>> + uint32_t max_sleep_time = 0x1f;
>> + uint32_t val = 0x0;
>> +
>> + if (dev_priv->vbt.psr_idle_frames)
>> + val |= dev_priv->vbt.psr_idle_frames <<
Re: [Intel-gfx] [PATCH 6/8] drm/i915: Enable/Disable PSR
Hi
2013/2/26 Ville Syrjälä ville.syrj...@linux.intel.com:
On Mon, Feb 25, 2013 at 07:55:20PM -0300, Rodrigo Vivi wrote:
Adding Enable and Disable PSR functionalities. This includes setting the
PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
enabling PSR in the sink via DPCD register and finally enabling PSR on
the host.
This patch is heavily based on initial PSR code by Sateesh Kavuri and
Kumar Shobhit but in a different implementation.
Credits-by: Sateesh Kavuri sateesh.kav...@intel.com
Credits-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Rodrigo Vivi rodrigo.v...@gmail.com
---
drivers/gpu/drm/i915/i915_reg.h | 40 +
drivers/gpu/drm/i915/intel_dp.c | 183
+++
drivers/gpu/drm/i915/intel_drv.h | 3 +
3 files changed, 226 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index b715ecd..1e31f23 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -844,6 +844,8 @@
#define SNB_CPU_FENCE_ENABLE (129)
#define DPFC_CPU_FENCE_OFFSET0x100104
+/* Framebuffer compression for Haswell */
+#define HSW_FBC_CONTROL 0x43208
/*
* GPIO regs
@@ -1580,6 +1582,44 @@
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+/* HSW eDP PSR registers */
+#define EDP_PSR_CTL 0x64800
+#define EDP_PSR_ENABLE (131)
+#define EDP_PSR_LINK_DISABLE (027)
+#define EDP_PSR_LINK_STANDBY (127)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (325)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES(025)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES(125)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES(225)
+#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES(325)
+#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
+#define EDP_PSR_SKIP_AUX_EXIT (112)
+#define EDP_PSR_TP1_TP2_SEL(011)
+#define EDP_PSR_TP1_TP3_SEL(111)
+#define EDP_PSR_TP2_TP3_TIME_500us (08)
+#define EDP_PSR_TP2_TP3_TIME_100us (18)
+#define EDP_PSR_TP2_TP3_TIME_2500us(28)
+#define EDP_PSR_TP2_TP3_TIME_0us (38)
+#define EDP_PSR_TP1_TIME_500us (04)
+#define EDP_PSR_TP1_TIME_100us (14)
+#define EDP_PSR_TP1_TIME_2500us(24)
+#define EDP_PSR_TP1_TIME_0us (34)
+#define EDP_PSR_IDLE_FRAME_SHIFT 0
+
+#define EDP_PSR_AUX_CTL 0x64810
+#define EDP_PSR_AUX_DATA10x64814
+#define EDP_PSR_AUX_DATA20x64818
+#define EDP_PSR_AUX_DATA30x6481c
+#define EDP_PSR_AUX_DATA40x64820
+#define EDP_PSR_AUX_DATA50x64824
+
+#define EDP_PSR_STATUS_CTL 0x64840
+#define EDP_PSR_STATUS_STATE_MASK (729)
+
+#define EDP_PSR_DEBUG_CTL0x64860
+#define EDP_PSR_DEBUG_MASK_MEMUP (126)
+#define EDP_PSR_DEBUG_MASK_HPD (125)
+
/* VGA port control */
#define ADPA 0x61100
#define PCH_ADPA0xe1100
diff --git a/drivers/gpu/drm/i915/intel_dp.c
b/drivers/gpu/drm/i915/intel_dp.c
index 5cfa9f4..a420f0d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -83,6 +83,13 @@ static struct drm_device *intel_dp_to_dev(struct intel_dp
*intel_dp)
return intel_dig_port-base.base.dev;
}
+static struct drm_crtc *intel_dp_to_crtc(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+
+ return intel_dig_port-base.base.crtc;
+}
+
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
return enc_to_intel_dp(intel_attached_encoder(connector)-base);
@@ -1443,6 +1450,182 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
(intel_dp-psr_dpcd[0] DP_PSR_IS_SUPPORTED));
}
+static bool
+intel_edp_is_psr_enabled(struct intel_dp* intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ return I915_READ(EDP_PSR_CTL) EDP_PSR_ENABLE;
+}
+
+static void
+intel_edp_psr_enable_src(struct intel_dp *intel_dp)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ uint32_t max_sleep_time = 0x1f;
+ uint32_t val = 0x0;
+
+ if (dev_priv-vbt.psr_idle_frames)
+ val |= dev_priv-vbt.psr_idle_frames EDP_PSR_IDLE_FRAME_SHIFT;
+ else
+ val |= 1 EDP_PSR_IDLE_FRAME_SHIFT;
+
+ if (intel_dp-psr_dpcd[1] DP_PSR_NO_TRAIN_ON_EXIT) {
+ val |= EDP_PSR_LINK_STANDBY;
There
