subject:"\[PATCH\] \[RFC\] drm\/i915\/dp\: DP PHY compliance for EHL\/JSL"

[PATCH] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL

2020-09-09 Thread Vidya Srinivas

Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.

v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL

Signed-off-by: Khaled Almahallawy 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 106 +++-
 drivers/gpu/drm/i915/i915_reg.h |  18 +-
 2 files changed, 92 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..0a535932ed18 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5404,26 +5404,37 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
+   i915_reg_t dp_tp_reg, dp_comp_reg;
+
+   if (IS_ELKHARTLAKE(dev_priv))
+   dp_tp_reg = DP_TP_CTL(dig_port->base.port);
+   else if (IS_TIGERLAKE(dev_priv))
+   dp_tp_reg = TGL_DP_TP_CTL(pipe);
+
+   if (IS_ELKHARTLAKE(dev_priv))
+   dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+   else if (IS_TIGERLAKE(dev_priv))
+   dp_comp_reg = DDI_DP_COMP_CTL(pipe);
 
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+   intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE |
   DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5443,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
 * current firmware of DPR-100 could not set it, so hardcoding
 * now for complaince test.
 */
-   DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 
0x0f83e0f8 0xf83e\n");
+   DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
-   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_de_write(dev_priv, 
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+  pattern_val);
+   else
+   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), 
pattern_val);
pattern_val = 0x0f83e0f8;
-   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_de_write(dev_priv, 
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+  pattern_val);
+   else
+   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), 
pattern_val);
pattern_val = 0xf83e;
-   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_de_write(dev_priv, 
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+  pattern_val);
+   else
+   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), 
pattern_val);
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE |
   DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,20

[PATCH] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL

2020-09-03 Thread Vidya Srinivas

Please Note: Comment from Ville could not be addressed
as his comments are with respect to base implementation
(design) which are already merged. We need JSL changes
for compliance. Hence pushing the required changes
on top of existing design. Apoligies for that.

v2: Rebased patch on top of Khaled's (yet to be merged):
https://patchwork.freedesktop.org/series/79779/
Fixed phy patterns for JSL/EHL
Add TPS4 support for JSL/EHL

Signed-off-by: Khaled Almahallawy 
Signed-off-by: Vidya Srinivas 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 81 +
 drivers/gpu/drm/i915/i915_reg.h | 18 ++--
 2 files changed, 78 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index a8a3ffcef5dc..1773f3d5d0f4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5405,25 +5405,32 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
enum pipe pipe = crtc->pipe;
u32 pattern_val, dp_tp_ctl;
 
+   i915_reg_t dp_comp_reg;
+
+   if (IS_ELKHARTLAKE(dev_priv))
+   dp_comp_reg = EHL_DDI_DP_COMP_CTL(dig_port->base.port);
+   else if (IS_TIGERLAKE(dev_priv))
+   dp_comp_reg = DDI_DP_COMP_CTL(pipe);
+
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+   intel_de_write(dev_priv, dp_comp_reg, 0x0);
break;
case DP_PHY_TEST_PATTERN_D10_2:
DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
break;
case DP_PHY_TEST_PATTERN_ERROR_COUNT:
DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE |
   DDI_DP_COMP_CTL_SCRAMBLED_0);
break;
case DP_PHY_TEST_PATTERN_PRBS7:
DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
break;
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
@@ -5432,14 +5439,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
 * current firmware of DPR-100 could not set it, so hardcoding
 * now for complaince test.
 */
-   DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 
0x0f83e0f8 0xf83e\n");
+   DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern \
+ 0x3e0f83e0 0x0f83e0f8 0xf83e\n");
pattern_val = 0x3e0f83e0;
-   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_de_write(dev_priv, 
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 0),
+  pattern_val);
+   else
+   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), 
pattern_val);
pattern_val = 0x0f83e0f8;
-   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_de_write(dev_priv, 
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 1),
+  pattern_val);
+   else
+   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), 
pattern_val);
pattern_val = 0xf83e;
-   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+   if (IS_ELKHARTLAKE(dev_priv))
+   intel_de_write(dev_priv, 
EHL_DDI_DP_COMP_PAT(dig_port->base.port, 2),
+  pattern_val);
+   else
+   intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), 
pattern_val);
+   intel_de_write(dev_priv, dp_comp_reg,
   DDI_DP_COMP_CTL_ENABLE |
   DDI_DP_COMP_CTL_CUSTOM80);
break;
@@ -5451,7 +5471,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
 */
DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
pattern_val = 0xFB;
-   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
+

[PATCH] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL

[PATCH] [RFC] drm/i915/dp: DP PHY compliance for EHL/JSL

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