On Fri, Nov 13, 2020 at 11:25 AM Bas Nieuwenhuizen
wrote:
>
> The DCC_MAX_COMPRESSED_BLOCK has to contain one of
> AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
> fit in 1 bit.
>
> Fix this cleanly while it is only in drm-next.
>
> Fixes: 8ba16d5993749c3f31fd2b49e16f0dc1e1770b9c
Fixes: 8ba16d599374 ("drm/fourcc: Add AMD DRM modifiers.")
Also missing your signed-off-by. With those things fixed:
Reviewed-by: Alex Deucher
> ---
>
> Found while reviewing Simon's drm_info PR:
> https://github.com/ascent12/drm_info/pull/63/commits/eaeae6ee78764a03d959cbc97c8b514f81a94c63
>
> include/uapi/drm/drm_fourcc.h | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index df56e71a7380..a878664ba41c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -1129,7 +1129,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
> #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
> #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
> -#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
> +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
>
> /*
> * DCC supports embedding some clear colors directly in the DCC surface.
> @@ -1140,7 +1140,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * If this bit is set that means the fastclear eliminate is not needed for
> these
> * embeddable colors.
> */
> -#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
> +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
> #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
>
> /*
> @@ -1153,15 +1153,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64
> modifier)
> * RB = only for TILE_VER_GFX9 & DCC
> * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
> */
> -#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
> +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
> #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
> -#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
> +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
> #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
> -#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
> +#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */
> #define AMD_FMT_MOD_PACKERS_MASK 0x7
> -#define AMD_FMT_MOD_RB_SHIFT 29
> +#define AMD_FMT_MOD_RB_SHIFT 30
> #define AMD_FMT_MOD_RB_MASK 0x7
> -#define AMD_FMT_MOD_PIPE_SHIFT 32
> +#define AMD_FMT_MOD_PIPE_SHIFT 33
> #define AMD_FMT_MOD_PIPE_MASK 0x7
>
> #define AMD_FMT_MOD_SET(field, value) \
> --
> 2.29.2
>
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