On Tue, Oct 04, 2022 at 05:25:34PM -0700, Radhakrishna Sripada wrote:
Meteorlake PCH reuses Alderlake ddc pin mapping. Extend
ADL-P pin mapping for Meteorlake.
Cc: Lucas De Marchi
Signed-off-by: Radhakrishna Sripada
This is actually the vbt -> display engine mapping.
Bspec 20124 - worth noting the absence of MTP in the VBT field, which
leads to the conclusion "should be the same pin mapping", if that holds
true in local tests.
with a reworded commit messages with some more details like above,
this is Reviewed-by: Lucas De Marchi
thanks
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 4c543e8205ca..c2987f2c2b2e 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2188,7 +2188,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
const u8 *ddc_pin_map;
int n_entries;
- if (IS_ALDERLAKE_P(i915)) {
+ if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
--
2.34.1
