Re: [Intel-gfx] [PATCH] drm/i915: Make wa list per-gt

2021-09-20 Thread Yokoyama, Caz 
On Fri, 2021-09-17 at 10:08 -0700, Matt Roper wrote:
> From: Venkata Sandeep Dhanalakota 
> 
> Support for multiple GT's within a single i915 device will be
> arriving
> soon.  Since each GT may have its own fusing and require different
> workarounds, we need to make the GT workaround functions and
> multicast
> steering setup per-gt.
> 
> Cc: Tvrtko Ursulin 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Venkata Sandeep Dhanalakota <
> venkata.s.dhanalak...@intel.com>
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c|   3 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h  |   2 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 143 +---
> --
>  drivers/gpu/drm/i915/gt/intel_workarounds.h   |   2 +-
>  .../gpu/drm/i915/gt/selftest_workarounds.c|   2 +-
>  drivers/gpu/drm/i915/i915_drv.c   |   2 -
>  drivers/gpu/drm/i915/i915_drv.h   |   2 -
>  drivers/gpu/drm/i915/i915_gem.c   |   2 -
>  8 files changed, 81 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 55e87aff51d2..449ff6e83543 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt)
>   if (err)
>   return err;
>  
> + intel_gt_init_workarounds(gt);
> +
>   /*
>* This is just a security blanket to placate dragons.
>* On some systems, we very sporadically observe that the first
> TLBs
> @@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
>   if (vm) /* FIXME being called twice on error paths :( */
>   i915_vm_put(vm);
>  
> + intel_wa_list_free(>wa_list);
>   intel_gt_pm_fini(gt);
>   intel_gt_fini_scratch(gt);
>   intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6fdcde64c180..ce127cae9e49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -72,6 +72,8 @@ struct intel_gt {
>  
>   struct intel_uc uc;
>  
> + struct i915_wa_list wa_list;
> +
>   struct intel_gt_timelines {
>   spinlock_t lock; /* protects active_list */
>   struct list_head active_list;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c314d4917b6b..1f0a54b383d9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
>  }
>  
>  static void
> -gen4_gt_workarounds_init(struct drm_i915_private *i915,
> +gen4_gt_workarounds_init(struct intel_gt *gt,
>struct i915_wa_list *wal)
>  {
>   /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
> @@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct
> drm_i915_private *i915,
>  }
>  
>  static void
> -g4x_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> +g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> *wal)
>  {
> - gen4_gt_workarounds_init(i915, wal);
> + gen4_gt_workarounds_init(gt, wal);
>  
>   /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
>   wa_masked_en(wal, CACHE_MODE_0,
> CM0_PIPELINED_RENDER_FLUSH_DISABLE);
>  }
>  
>  static void
> -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> +ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> *wal)
>  {
> - g4x_gt_workarounds_init(i915, wal);
> + g4x_gt_workarounds_init(gt, wal);
>  
>   wa_masked_en(wal, _3D_CHICKEN2,
> _3D_CHICKEN2_WM_READ_PIPELINED);
>  }
>  
>  static void
> -snb_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> +snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> *wal)
>  {
>  }
>  
>  static void
> -ivb_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> +ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> *wal)
>  {
>   /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb
> workaround. */
>   wa_masked_dis(wal,
> @@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>  }
>  
>  static void
> -vlv_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> +vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list
> *wal)
>  {
>   /* WaForceL3Serialization:vlv */
>   wa_write_clr(wal, GEN7_L3SQCREG4,
> L3SQ_URB_READ_CAM_MATCH_DISABLE);
> @@ -863,7 +863,7 @@ vlv_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
>  }
>  
>  static void
> -hsw_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> +hsw_gt_workarounds_init(struct intel_gt *gt, struct

Re: [Intel-gfx] [PATCH] drm/i915: Make wa list per-gt

2021-09-20 Thread Rodrigo Vivi 
On Fri, Sep 17, 2021 at 10:08:45AM -0700, Matt Roper wrote:
> From: Venkata Sandeep Dhanalakota 
> 
> Support for multiple GT's within a single i915 device will be arriving
> soon.  Since each GT may have its own fusing and require different
> workarounds, we need to make the GT workaround functions and multicast
> steering setup per-gt.
> 
> Cc: Tvrtko Ursulin 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Venkata Sandeep Dhanalakota 
> Signed-off-by: Matt Roper 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c|   3 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h  |   2 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 143 +-
>  drivers/gpu/drm/i915/gt/intel_workarounds.h   |   2 +-
>  .../gpu/drm/i915/gt/selftest_workarounds.c|   2 +-
>  drivers/gpu/drm/i915/i915_drv.c   |   2 -
>  drivers/gpu/drm/i915/i915_drv.h   |   2 -
>  drivers/gpu/drm/i915/i915_gem.c   |   2 -
>  8 files changed, 81 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 55e87aff51d2..449ff6e83543 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt)
>   if (err)
>   return err;
>  
> + intel_gt_init_workarounds(gt);
> +
>   /*
>* This is just a security blanket to placate dragons.
>* On some systems, we very sporadically observe that the first TLBs
> @@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
>   if (vm) /* FIXME being called twice on error paths :( */
>   i915_vm_put(vm);
>  
> + intel_wa_list_free(>wa_list);
>   intel_gt_pm_fini(gt);
>   intel_gt_fini_scratch(gt);
>   intel_gt_fini_buffer_pool(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6fdcde64c180..ce127cae9e49 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -72,6 +72,8 @@ struct intel_gt {
>  
>   struct intel_uc uc;
>  
> + struct i915_wa_list wa_list;
> +
>   struct intel_gt_timelines {
>   spinlock_t lock; /* protects active_list */
>   struct list_head active_list;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c314d4917b6b..1f0a54b383d9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
>  }
>  
>  static void
> -gen4_gt_workarounds_init(struct drm_i915_private *i915,
> +gen4_gt_workarounds_init(struct intel_gt *gt,
>struct i915_wa_list *wal)
>  {
>   /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
> @@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct drm_i915_private *i915,
>  }
>  
>  static void
> -g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
> +g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
> - gen4_gt_workarounds_init(i915, wal);
> + gen4_gt_workarounds_init(gt, wal);
>  
>   /* WaDisableRenderCachePipelinedFlush:g4x,ilk */
>   wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
>  }
>  
>  static void
> -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
> +ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
> - g4x_gt_workarounds_init(i915, wal);
> + g4x_gt_workarounds_init(gt, wal);
>  
>   wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
>  }
>  
>  static void
> -snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
> +snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
>  }
>  
>  static void
> -ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
> +ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
>   /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
>   wa_masked_dis(wal,
> @@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, 
> struct i915_wa_list *wal)
>  }
>  
>  static void
> -vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
> +vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {
>   /* WaForceL3Serialization:vlv */
>   wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
> @@ -863,7 +863,7 @@ vlv_gt_workarounds_init(struct drm_i915_private *i915, 
> struct i915_wa_list *wal)
>  }
>  
>  static void
> -hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
> *wal)
> +hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>  {

Re: [PATCH] drm/i915: Make wa list per-gt

2021-09-20 Thread Tvrtko Ursulin 



On 17/09/2021 18:08, Matt Roper wrote:

From: Venkata Sandeep Dhanalakota 

Support for multiple GT's within a single i915 device will be arriving
soon.  Since each GT may have its own fusing and require different
workarounds, we need to make the GT workaround functions and multicast
steering setup per-gt.

Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Venkata Sandeep Dhanalakota 
Signed-off-by: Matt Roper 
---
  drivers/gpu/drm/i915/gt/intel_gt.c|   3 +
  drivers/gpu/drm/i915/gt/intel_gt_types.h  |   2 +
  drivers/gpu/drm/i915/gt/intel_workarounds.c   | 143 +-
  drivers/gpu/drm/i915/gt/intel_workarounds.h   |   2 +-
  .../gpu/drm/i915/gt/selftest_workarounds.c|   2 +-
  drivers/gpu/drm/i915/i915_drv.c   |   2 -
  drivers/gpu/drm/i915/i915_drv.h   |   2 -
  drivers/gpu/drm/i915/i915_gem.c   |   2 -
  8 files changed, 81 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 55e87aff51d2..449ff6e83543 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
return err;
  
+	intel_gt_init_workarounds(gt);

+
/*
 * This is just a security blanket to placate dragons.
 * On some systems, we very sporadically observe that the first TLBs
@@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
  
+	intel_wa_list_free(>wa_list);

intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..ce127cae9e49 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -72,6 +72,8 @@ struct intel_gt {
  
  	struct intel_uc uc;
  
+	struct i915_wa_list wa_list;

+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c314d4917b6b..1f0a54b383d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
  }
  
  static void

-gen4_gt_workarounds_init(struct drm_i915_private *i915,
+gen4_gt_workarounds_init(struct intel_gt *gt,
 struct i915_wa_list *wal)
  {
/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
@@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct drm_i915_private *i915,
  }
  
  static void

-g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
-   gen4_gt_workarounds_init(i915, wal);
+   gen4_gt_workarounds_init(gt, wal);
  
  	/* WaDisableRenderCachePipelinedFlush:g4x,ilk */

wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
  }
  
  static void

-ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
-   g4x_gt_workarounds_init(i915, wal);
+   g4x_gt_workarounds_init(gt, wal);
  
  	wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);

  }
  
  static void

-snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
  }
  
  static void

-ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
wa_masked_dis(wal,
@@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
  }
  
  static void

-vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
/* WaForceL3Serialization:vlv */
wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
@@ -863,7 +863,7 @@ vlv_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
  }
  
  static void

-hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  {
/* L3 caching of data atomics doesn't work -- disable it. */
wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
@@ -878,15 +878,15 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, 
struct

[PATCH] drm/i915: Make wa list per-gt

2021-09-17 Thread Matt Roper 
From: Venkata Sandeep Dhanalakota 

Support for multiple GT's within a single i915 device will be arriving
soon.  Since each GT may have its own fusing and require different
workarounds, we need to make the GT workaround functions and multicast
steering setup per-gt.

Cc: Tvrtko Ursulin 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Venkata Sandeep Dhanalakota 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt.c|   3 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |   2 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 143 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.h   |   2 +-
 .../gpu/drm/i915/gt/selftest_workarounds.c|   2 +-
 drivers/gpu/drm/i915/i915_drv.c   |   2 -
 drivers/gpu/drm/i915/i915_drv.h   |   2 -
 drivers/gpu/drm/i915/i915_gem.c   |   2 -
 8 files changed, 81 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 55e87aff51d2..449ff6e83543 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -660,6 +660,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
return err;
 
+   intel_gt_init_workarounds(gt);
+
/*
 * This is just a security blanket to placate dragons.
 * On some systems, we very sporadically observe that the first TLBs
@@ -767,6 +769,7 @@ void intel_gt_driver_release(struct intel_gt *gt)
if (vm) /* FIXME being called twice on error paths :( */
i915_vm_put(vm);
 
+   intel_wa_list_free(>wa_list);
intel_gt_pm_fini(gt);
intel_gt_fini_scratch(gt);
intel_gt_fini_buffer_pool(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..ce127cae9e49 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -72,6 +72,8 @@ struct intel_gt {
 
struct intel_uc uc;
 
+   struct i915_wa_list wa_list;
+
struct intel_gt_timelines {
spinlock_t lock; /* protects active_list */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c314d4917b6b..1f0a54b383d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -804,7 +804,7 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
 }
 
 static void
-gen4_gt_workarounds_init(struct drm_i915_private *i915,
+gen4_gt_workarounds_init(struct intel_gt *gt,
 struct i915_wa_list *wal)
 {
/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
@@ -812,29 +812,29 @@ gen4_gt_workarounds_init(struct drm_i915_private *i915,
 }
 
 static void
-g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   gen4_gt_workarounds_init(i915, wal);
+   gen4_gt_workarounds_init(gt, wal);
 
/* WaDisableRenderCachePipelinedFlush:g4x,ilk */
wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
 }
 
 static void
-ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-   g4x_gt_workarounds_init(i915, wal);
+   g4x_gt_workarounds_init(gt, wal);
 
wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
 }
 
 static void
-snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
 }
 
 static void
-ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
wa_masked_dis(wal,
@@ -850,7 +850,7 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
 }
 
 static void
-vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
/* WaForceL3Serialization:vlv */
wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
@@ -863,7 +863,7 @@ vlv_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
 }
 
 static void
-hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list 
*wal)
+hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 {
/* L3 caching of data atomics doesn't work -- disable it. */
wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
@@ -878,15 +878,15 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, 
struct i915_wa_list *wal)
 }
 
 static void