Re: [PATCH] drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations

2019-06-07 Thread Neil Armstrong 
On 06/06/2019 18:30, Kevin Hilman wrote:
> Neil Armstrong  writes:
> 
>> The Amlogic G12A HDMI PLL needs some specific settings to lock with
>> different fractional values for the 5,4GHz mode.
>>
>> Handle the 1000/1001 variation fractional case here to avoid having
>> the PLL in an non lockable state.
>>
>> Fixes: 202b9808f8ed ("drm/meson: Add G12A Video Clock setup")
>> Signed-off-by: Neil Armstrong 
>> ---
>>  drivers/gpu/drm/meson/meson_vclk.c | 13 +++--
>>  1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/meson/meson_vclk.c 
>> b/drivers/gpu/drm/meson/meson_vclk.c
>> index 44250eff8a3f..83fc2fc82001 100644
>> --- a/drivers/gpu/drm/meson/meson_vclk.c
>> +++ b/drivers/gpu/drm/meson/meson_vclk.c
>> @@ -553,8 +553,17 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, 
>> unsigned int m,
>>  
>>  /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
>>  if (m >= 0xf7) {
>> -regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0xea68dc00);
>> -regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
>> +if (frac < 0x1) {
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
>> +0x6a685c00);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
>> +0x11551293);
>> +} else {
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
>> +0xea68dc00);
>> +regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
>> +0x65771290);
>> +}
>>  regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
>>  regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x5554);
>>  } else {
> 
> Reviewed-by: Kevin Hilman 

Applied to drm-misc-fixes

> 
> nit: this is continuing with more magic constants, and it would be nice
> to have them converted to #define'd bitfields.  But since that isn't a
> new problem in this patch, it's fine to cleanup later.

Yep, it's on our to priority.

Neil


> 
> Kevin
> 

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Re: [PATCH] drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations

2019-06-06 Thread Kevin Hilman 
Neil Armstrong  writes:

> The Amlogic G12A HDMI PLL needs some specific settings to lock with
> different fractional values for the 5,4GHz mode.
>
> Handle the 1000/1001 variation fractional case here to avoid having
> the PLL in an non lockable state.
>
> Fixes: 202b9808f8ed ("drm/meson: Add G12A Video Clock setup")
> Signed-off-by: Neil Armstrong 
> ---
>  drivers/gpu/drm/meson/meson_vclk.c | 13 +++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/meson/meson_vclk.c 
> b/drivers/gpu/drm/meson/meson_vclk.c
> index 44250eff8a3f..83fc2fc82001 100644
> --- a/drivers/gpu/drm/meson/meson_vclk.c
> +++ b/drivers/gpu/drm/meson/meson_vclk.c
> @@ -553,8 +553,17 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, 
> unsigned int m,
>  
>   /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
>   if (m >= 0xf7) {
> - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0xea68dc00);
> - regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
> + if (frac < 0x1) {
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
> + 0x6a685c00);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
> + 0x11551293);
> + } else {
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
> + 0xea68dc00);
> + regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
> + 0x65771290);
> + }
>   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
>   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x5554);
>   } else {

Reviewed-by: Kevin Hilman 

nit: this is continuing with more magic constants, and it would be nice
to have them converted to #define'd bitfields.  But since that isn't a
new problem in this patch, it's fine to cleanup later.

Kevin
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[PATCH] drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations

2019-06-05 Thread Neil Armstrong 
The Amlogic G12A HDMI PLL needs some specific settings to lock with
different fractional values for the 5,4GHz mode.

Handle the 1000/1001 variation fractional case here to avoid having
the PLL in an non lockable state.

Fixes: 202b9808f8ed ("drm/meson: Add G12A Video Clock setup")
Signed-off-by: Neil Armstrong 
---
 drivers/gpu/drm/meson/meson_vclk.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/meson/meson_vclk.c 
b/drivers/gpu/drm/meson/meson_vclk.c
index 44250eff8a3f..83fc2fc82001 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -553,8 +553,17 @@ void meson_hdmi_pll_set_params(struct meson_drm *priv, 
unsigned int m,
 
/* G12A HDMI PLL Needs specific parameters for 5.4GHz */
if (m >= 0xf7) {
-   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0xea68dc00);
-   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
+   if (frac < 0x1) {
+   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
+   0x6a685c00);
+   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
+   0x11551293);
+   } else {
+   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
+   0xea68dc00);
+   regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
+   0x65771290);
+   }
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x5554);
} else {
-- 
2.21.0

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