Re: [PATCH] drm/nouveau: tegra: Initialize mode configuration
On Wed, Nov 07, 2018 at 10:52:11AM -0500, Ilia Mirkin wrote: > On Wed, Nov 7, 2018 at 10:34 AM Thierry Reding > wrote: > > > > On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote: > > > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote: > > > > From: Thierry Reding > > > > > > > > Irrespective of whether or not the device has any usable outputs, the > > > > modesetting helpers will try to register all the resources such as CRTCs > > > > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to > > > > properly set up internal data structures. Since the Tegra GPU does not > > > > have a display engine, the Nouveau driver doesn't set this up for Tegra, > > > > which results in the following oops on driver probe: > > > > > > Remove DRIVER_MODESET ? > > > > Yeah, that works as well. Technically I suppose somebody could be > > instantiating the IP in an SoC and include a display engine, in which > > case we'd need the DRIVER_MODESET feature again, but I'm not aware of > > anyone doing that, so it may not be worth planning for that at this > > point. > > I thought DRIVER_MODESET was required even for rendernodes. Is that no > longer the case? Indeed. Removing the DRIVER_MODESET feature gets the driver to load properly, but trying to actually use Nouveau (e.g. kmscube) crashes in other places. Now that you mention it, I vaguely remember trying to do something similar a long time ago and I had to split up DRIVER_MODESET into more fine-grained features (basically DRIVER_MODESET and DRIVER_LEGACY, if I remember correctly) to avoid crashes. But this must have been three or four years ago and I can't recall the exact details. > Note that e.g. GF117 GPUs also don't have a display engine hooked up > in nouveau (or in hardware). That's interesting. I think there'd be some symmetric elegance to it if the PCI driver supported DRIVER_MODESET irrespective of the feature set of the card and if the platform driver did the same. In the end, this isn't really a driver-specific feature, but a device-specific feature. Or to put it another way: the driver inherently supports modesetting features, irrespective of a device's specific capabilities. Thierry signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/nouveau: tegra: Initialize mode configuration
On Wed, Nov 7, 2018 at 10:34 AM Thierry Reding wrote: > > On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote: > > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote: > > > From: Thierry Reding > > > > > > Irrespective of whether or not the device has any usable outputs, the > > > modesetting helpers will try to register all the resources such as CRTCs > > > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to > > > properly set up internal data structures. Since the Tegra GPU does not > > > have a display engine, the Nouveau driver doesn't set this up for Tegra, > > > which results in the following oops on driver probe: > > > > Remove DRIVER_MODESET ? > > Yeah, that works as well. Technically I suppose somebody could be > instantiating the IP in an SoC and include a display engine, in which > case we'd need the DRIVER_MODESET feature again, but I'm not aware of > anyone doing that, so it may not be worth planning for that at this > point. I thought DRIVER_MODESET was required even for rendernodes. Is that no longer the case? Note that e.g. GF117 GPUs also don't have a display engine hooked up in nouveau (or in hardware). -ilia ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/nouveau: tegra: Initialize mode configuration
On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote: > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote: > > From: Thierry Reding > > > > Irrespective of whether or not the device has any usable outputs, the > > modesetting helpers will try to register all the resources such as CRTCs > > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to > > properly set up internal data structures. Since the Tegra GPU does not > > have a display engine, the Nouveau driver doesn't set this up for Tegra, > > which results in the following oops on driver probe: > > Remove DRIVER_MODESET ? Yeah, that works as well. Technically I suppose somebody could be instantiating the IP in an SoC and include a display engine, in which case we'd need the DRIVER_MODESET feature again, but I'm not aware of anyone doing that, so it may not be worth planning for that at this point. Thierry signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/nouveau: tegra: Initialize mode configuration
On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote: > From: Thierry Reding > > Irrespective of whether or not the device has any usable outputs, the > modesetting helpers will try to register all the resources such as CRTCs > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to > properly set up internal data structures. Since the Tegra GPU does not > have a display engine, the Nouveau driver doesn't set this up for Tegra, > which results in the following oops on driver probe: Remove DRIVER_MODESET ? > > [ 18.776221] Unable to handle kernel NULL pointer dereference at > virtual address 006c > [ 18.785401] pgd = 16bb93b7 > [ 18.789331] [006c] *pgd=ad58c003, *pmd= > [ 18.800757] Internal error: Oops: 206 [#1] PREEMPT SMP ARM > [ 18.806233] Modules linked in: nouveau(+) ttm tegra_drm > [ 18.811457] CPU: 1 PID: 245 Comm: systemd-udevd Not tainted > 4.20.0-rc1 #36 > [ 18.818324] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) > [ 18.824596] PC is at drm_plane_register_all+0x18/0x50 > [ 18.824601] LR is at drm_modeset_register_all+0xc/0x70 > [ 18.824604] pc : []lr : []psr: a113 > [ 18.824607] sp : ed5dfc70 ip : ed742d40 fp : > [ 18.824610] r10: 0018 r9 : ed742d00 r8 : > [ 18.824613] r7 : bf26ac80 r6 : r5 : ed155650 r4 : > fffc > [ 18.824616] r3 : 0002f000 r2 : r1 : 2df3 r0 : > ed155400 > [ 18.824621] Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM > Segment user > [ 18.824624] Control: 30c5387d Table: aeb18840 DAC: > [ 18.824628] Process systemd-udevd (pid: 245, stack limit = > 0xc66954c3) > [ 18.824633] Stack: (0xed5dfc70 to 0xed5e) > [ 18.824636] fc60: ed155400 > ed155400 c068e45c > [ 18.824641] fc80: ed155400 c06751a4 0001 > 0001 > [ 18.905936] fca0: ed5dfcc0 c1204c88 ed155400 > bf268c5c bf1c5cd4 > [ 18.914108] fcc0: ed710c08 9543847b eea34810 > bf268c5c c06a3f64 > [ 18.923651] fce0: c131dd70 eea34810 c131dd74 > c06a2084 eea34810 bf268c5c > [ 18.932934] fd00: eea34844 c06a23e0 c1204c88 bf26a980 > c06a22d4 eefd093c c06a23e0 > [ 18.941096] fd20: eea34810 bf268c5c eea34844 c06a23e0 > c1204c88 bf26a980 > [ 18.949259] fd40: c06a24bc eea387b4 c1204c88 bf268c5c > c06a038c ee88335c > [ 18.957417] fd60: eea387b4 9543847b c1275a88 bf268c5c ed12b800 > c1275a88 c06a1528 > [ 18.965580] fd80: bf245be8 bf268ac8 e000 bf268c5c bf268ac8 > e000 bf292000 c06a30d8 > [ 18.973746] fda0: bf26ab80 bf268ac8 e000 bf292170 c12cf160 > c1204c88 e000 c0202dbc > [ 18.981913] fdc0: ed667700 006000c0 c02b2844 000c 600d0013 > bf26a980 0040 c03650f8 > [ 18.990079] fde0: a00d0013 2defd000 ee80 006000c0 006000c0 > c02b2844 000c c03666f4 > [ 18.998244] fe00: c0358254 a00d0013 bf26a980 9543847b bf26a980 > 0001 ed667700 0001 > [ 19.006404] fe20: ed1d9ee4 c02b2880 c1204c88 bf26a980 > ed5dff40 0001 ed1d9ec0 > [ 19.014569] fe40: 0001 c02b48c8 bf26a98c 7fff bf26a980 > c02b1a00 c02b1214 > [ 19.022735] fe60: bf26a9c8 bf26aa80 bf26ab5c bf26aab0 c0c0387c > c0e62374 c0db80fc c0db8108 > [ 19.030901] fe80: c0db8160 c1204c88 bf00 ed1296c0 06c18a20 > ed1296c0 c1204c88 > [ 19.039068] fea0: > 6e72656b 6c65 > [ 19.047228] fec0: > > [ 19.055393] fee0: > 9543847b 7fff c1204c88 > [ 19.063558] ff00: 000f b6c51c58 c0201204 ed5de000 > 017b bea73b0c c02b5188 > [ 19.071723] ff20: 7fff 0003 c0334b4c 0002 > f1bc1000 06c18a20 > [ 19.079890] ff40: f1d0c3aa f1d24e80 f1bc1000 06c18a20 f87d90c0 > f87d8e60 f70d7798 0016a000 > [ 19.088056] ff60: 0017e730 00050ba8 > 0039 003a 0022 > [ 19.096215] ff80: 0013 9543847b 00c0 > b6c51c58 000f > [ 19.104378] ffa0: 017b c02011d4 b6c51c58 000f > b6c51c58 00559220 > [ 19.112543] ffc0: b6c51c58 000f 017b > 00546958 bea73b0c > [ 19.120708] ffe0: bea73af8 bea73ae8 b6c44c14 b6b4b710 600d0010 > 000f > [ 19.128884] [] (drm_plane_register_all) from [] > (drm_modeset_register_all+0xc/0x70) > [ 19.138273] [] (drm
[PATCH] drm/nouveau: tegra: Initialize mode configuration
From: Thierry Reding Irrespective of whether or not the device has any usable outputs, the modesetting helpers will try to register all the resources such as CRTCs and planes. Unfortunately, the helpers rely on drm_mode_config_init() to properly set up internal data structures. Since the Tegra GPU does not have a display engine, the Nouveau driver doesn't set this up for Tegra, which results in the following oops on driver probe: [ 18.776221] Unable to handle kernel NULL pointer dereference at virtual address 006c [ 18.785401] pgd = 16bb93b7 [ 18.789331] [006c] *pgd=ad58c003, *pmd= [ 18.800757] Internal error: Oops: 206 [#1] PREEMPT SMP ARM [ 18.806233] Modules linked in: nouveau(+) ttm tegra_drm [ 18.811457] CPU: 1 PID: 245 Comm: systemd-udevd Not tainted 4.20.0-rc1 #36 [ 18.818324] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 18.824596] PC is at drm_plane_register_all+0x18/0x50 [ 18.824601] LR is at drm_modeset_register_all+0xc/0x70 [ 18.824604] pc : []lr : []psr: a113 [ 18.824607] sp : ed5dfc70 ip : ed742d40 fp : [ 18.824610] r10: 0018 r9 : ed742d00 r8 : [ 18.824613] r7 : bf26ac80 r6 : r5 : ed155650 r4 : fffc [ 18.824616] r3 : 0002f000 r2 : r1 : 2df3 r0 : ed155400 [ 18.824621] Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 18.824624] Control: 30c5387d Table: aeb18840 DAC: [ 18.824628] Process systemd-udevd (pid: 245, stack limit = 0xc66954c3) [ 18.824633] Stack: (0xed5dfc70 to 0xed5e) [ 18.824636] fc60: ed155400 ed155400 c068e45c [ 18.824641] fc80: ed155400 c06751a4 0001 0001 [ 18.905936] fca0: ed5dfcc0 c1204c88 ed155400 bf268c5c bf1c5cd4 [ 18.914108] fcc0: ed710c08 9543847b eea34810 bf268c5c c06a3f64 [ 18.923651] fce0: c131dd70 eea34810 c131dd74 c06a2084 eea34810 bf268c5c [ 18.932934] fd00: eea34844 c06a23e0 c1204c88 bf26a980 c06a22d4 eefd093c c06a23e0 [ 18.941096] fd20: eea34810 bf268c5c eea34844 c06a23e0 c1204c88 bf26a980 [ 18.949259] fd40: c06a24bc eea387b4 c1204c88 bf268c5c c06a038c ee88335c [ 18.957417] fd60: eea387b4 9543847b c1275a88 bf268c5c ed12b800 c1275a88 c06a1528 [ 18.965580] fd80: bf245be8 bf268ac8 e000 bf268c5c bf268ac8 e000 bf292000 c06a30d8 [ 18.973746] fda0: bf26ab80 bf268ac8 e000 bf292170 c12cf160 c1204c88 e000 c0202dbc [ 18.981913] fdc0: ed667700 006000c0 c02b2844 000c 600d0013 bf26a980 0040 c03650f8 [ 18.990079] fde0: a00d0013 2defd000 ee80 006000c0 006000c0 c02b2844 000c c03666f4 [ 18.998244] fe00: c0358254 a00d0013 bf26a980 9543847b bf26a980 0001 ed667700 0001 [ 19.006404] fe20: ed1d9ee4 c02b2880 c1204c88 bf26a980 ed5dff40 0001 ed1d9ec0 [ 19.014569] fe40: 0001 c02b48c8 bf26a98c 7fff bf26a980 c02b1a00 c02b1214 [ 19.022735] fe60: bf26a9c8 bf26aa80 bf26ab5c bf26aab0 c0c0387c c0e62374 c0db80fc c0db8108 [ 19.030901] fe80: c0db8160 c1204c88 bf00 ed1296c0 06c18a20 ed1296c0 c1204c88 [ 19.039068] fea0: 6e72656b 6c65 [ 19.047228] fec0: [ 19.055393] fee0: 9543847b 7fff c1204c88 [ 19.063558] ff00: 000f b6c51c58 c0201204 ed5de000 017b bea73b0c c02b5188 [ 19.071723] ff20: 7fff 0003 c0334b4c 0002 f1bc1000 06c18a20 [ 19.079890] ff40: f1d0c3aa f1d24e80 f1bc1000 06c18a20 f87d90c0 f87d8e60 f70d7798 0016a000 [ 19.088056] ff60: 0017e730 00050ba8 0039 003a 0022 [ 19.096215] ff80: 0013 9543847b 00c0 b6c51c58 000f [ 19.104378] ffa0: 017b c02011d4 b6c51c58 000f b6c51c58 00559220 [ 19.112543] ffc0: b6c51c58 000f 017b 00546958 bea73b0c [ 19.120708] ffe0: bea73af8 bea73ae8 b6c44c14 b6b4b710 600d0010 000f [ 19.128884] [] (drm_plane_register_all) from [] (drm_modeset_register_all+0xc/0x70) [ 19.138273] [] (drm_modeset_register_all) from [] (drm_dev_register+0x168/0x1c4) [ 19.147581] [] (drm_dev_register) from [] (nouveau_platform_probe+0x6c/0x88 [nouveau]) [ 19.157
