Re: [PATCH] dt-bindings: gpu: add bindings for the ARM Mali Bifrost GPU

2019-01-31 Thread Neil Armstrong
On 31/01/2019 14:29, Neil Armstrong wrote:
> Add the bindings for the Bifrost family of ARM Mali GPUs.
> 
> The Bifrost GPU architecture is similar to the Midgard family,
> but with a different Shader Core & Execution Engine structures.
> 
> Bindings are based on the Midgard family bindings, but the inner
> architectural changes makes it a separate family needing separate
> bindings.
> 
> The Bifrost GPUs are present in a number of recent SoCs, like the
> Amlogic G12A Family, and many other vendors.
> The Amlogic vendor specific compatible is added to handle the
> specific IP integration differences and dependencies.
> 
> Signed-off-by: Neil Armstrong 
> ---
>  .../bindings/gpu/arm,mali-bifrost.txt | 94 +++
>  1 file changed, 94 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt 
> b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
> new file mode 100644
> index ..a632f5136b08
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
> @@ -0,0 +1,94 @@
> +ARM Mali Bifrost GPU
> +
> +
> +Required properties:
> +
> +- compatible :
> +  * Must contain one of the following:
> ++ "arm,mali-g71"
> ++ "arm,mali-g51"
> ++ "arm,mali-g72"
> ++ "arm,mali-g76"

Wrong order and forgot the G31 and G52 cores.

Neil

> +  * which must be preceded by one of the following vendor specifics:
> ++ "amlogic,meson-g12a-mali"
> +
> +- reg : Physical base address of the device and length of the register area.
> +
> +- interrupts : Contains the three IRQ lines required by Mali Bifrost devices.
> +
> +- interrupt-names : Contains the names of IRQ resources in the order they 
> were
> +  provided in the interrupts property. Must contain: "job", "mmu", "gpu".
> +
> +
> +Optional properties:
> +
> +- clocks : Phandle to clock for the Mali Bifrost device.
> +
> +- mali-supply : Phandle to regulator for the Mali device. Refer to
> +  Documentation/devicetree/bindings/regulator/regulator.txt for details.
> +
> +- operating-points-v2 : Refer to 
> Documentation/devicetree/bindings/opp/opp.txt
> +  for details.
> +
> +- resets : Phandle of the GPU reset line.
> +
> +Vendor-specific bindings
> +
> +
> +The Mali GPU is integrated very differently from one SoC to
> +another. In order to accomodate those differences, you have the option
> +to specify one more vendor-specific compatible, among:
> +
> +- "amlogic,meson-g12a-mali"
> +  Required properties:
> +  - resets : Should contain phandles of :
> ++ GPU reset line
> ++ GPU APB glue reset line
> +
> +Example for a Mali-G71:
> +
> +gpu@ffa3 {
> + compatible = "amlogic,meson-g12a-mali", "arm,mali-g71";


It's a typo, it's a G31 on Amlogic G12A, anyway the example is still valid.

> + reg = <0xffe4 0x1>;
> + interrupts = ,
> +  ,
> +  ;
> + interrupt-names = "job", "mmu", "gpu";
> + clocks = < CLKID_MALI>;
> + mali-supply = <_gpu>;
> + operating-points-v2 = <_opp_table>;
> + resets = < RESET_DVALIN_CAPB3>, < RESET_DVALIN>;
> +};
> +
> +gpu_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> +
> + opp@53300 {
> + opp-hz = /bits/ 64 <53300>;
> + opp-microvolt = <125>;
> + };
> + opp@45000 {
> + opp-hz = /bits/ 64 <45000>;
> + opp-microvolt = <115>;
> + };
> + opp@4 {
> + opp-hz = /bits/ 64 <4>;
> + opp-microvolt = <1125000>;
> + };
> + opp@35000 {
> + opp-hz = /bits/ 64 <35000>;
> + opp-microvolt = <1075000>;
> + };
> + opp@26600 {
> + opp-hz = /bits/ 64 <26600>;
> + opp-microvolt = <1025000>;
> + };
> + opp@16000 {
> + opp-hz = /bits/ 64 <16000>;
> + opp-microvolt = <925000>;
> + };
> + opp@1 {
> + opp-hz = /bits/ 64 <1>;
> + opp-microvolt = <912500>;
> + };
> +};
> 

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[PATCH] dt-bindings: gpu: add bindings for the ARM Mali Bifrost GPU

2019-01-31 Thread Neil Armstrong
Add the bindings for the Bifrost family of ARM Mali GPUs.

The Bifrost GPU architecture is similar to the Midgard family,
but with a different Shader Core & Execution Engine structures.

Bindings are based on the Midgard family bindings, but the inner
architectural changes makes it a separate family needing separate
bindings.

The Bifrost GPUs are present in a number of recent SoCs, like the
Amlogic G12A Family, and many other vendors.
The Amlogic vendor specific compatible is added to handle the
specific IP integration differences and dependencies.

Signed-off-by: Neil Armstrong 
---
 .../bindings/gpu/arm,mali-bifrost.txt | 94 +++
 1 file changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt 
b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
new file mode 100644
index ..a632f5136b08
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
@@ -0,0 +1,94 @@
+ARM Mali Bifrost GPU
+
+
+Required properties:
+
+- compatible :
+  * Must contain one of the following:
++ "arm,mali-g71"
++ "arm,mali-g51"
++ "arm,mali-g72"
++ "arm,mali-g76"
+  * which must be preceded by one of the following vendor specifics:
++ "amlogic,meson-g12a-mali"
+
+- reg : Physical base address of the device and length of the register area.
+
+- interrupts : Contains the three IRQ lines required by Mali Bifrost devices.
+
+- interrupt-names : Contains the names of IRQ resources in the order they were
+  provided in the interrupts property. Must contain: "job", "mmu", "gpu".
+
+
+Optional properties:
+
+- clocks : Phandle to clock for the Mali Bifrost device.
+
+- mali-supply : Phandle to regulator for the Mali device. Refer to
+  Documentation/devicetree/bindings/regulator/regulator.txt for details.
+
+- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
+  for details.
+
+- resets : Phandle of the GPU reset line.
+
+Vendor-specific bindings
+
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+- "amlogic,meson-g12a-mali"
+  Required properties:
+  - resets : Should contain phandles of :
++ GPU reset line
++ GPU APB glue reset line
+
+Example for a Mali-G71:
+
+gpu@ffa3 {
+   compatible = "amlogic,meson-g12a-mali", "arm,mali-g71";
+   reg = <0xffe4 0x1>;
+   interrupts = ,
+,
+;
+   interrupt-names = "job", "mmu", "gpu";
+   clocks = < CLKID_MALI>;
+   mali-supply = <_gpu>;
+   operating-points-v2 = <_opp_table>;
+   resets = < RESET_DVALIN_CAPB3>, < RESET_DVALIN>;
+};
+
+gpu_opp_table: opp_table0 {
+   compatible = "operating-points-v2";
+
+   opp@53300 {
+   opp-hz = /bits/ 64 <53300>;
+   opp-microvolt = <125>;
+   };
+   opp@45000 {
+   opp-hz = /bits/ 64 <45000>;
+   opp-microvolt = <115>;
+   };
+   opp@4 {
+   opp-hz = /bits/ 64 <4>;
+   opp-microvolt = <1125000>;
+   };
+   opp@35000 {
+   opp-hz = /bits/ 64 <35000>;
+   opp-microvolt = <1075000>;
+   };
+   opp@26600 {
+   opp-hz = /bits/ 64 <26600>;
+   opp-microvolt = <1025000>;
+   };
+   opp@16000 {
+   opp-hz = /bits/ 64 <16000>;
+   opp-microvolt = <925000>;
+   };
+   opp@1 {
+   opp-hz = /bits/ 64 <1>;
+   opp-microvolt = <912500>;
+   };
+};
-- 
2.20.1

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