Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
On Thu, Nov 04, 2021 at 05:41:13PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 04, 2021 at 09:48:41AM +0100, Maxime Ripard wrote:
> > Hi Ville,
> >
> > On Wed, Nov 03, 2021 at 08:05:16PM +0200, Ville Syrjälä wrote:
> > > On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote:
> > > > On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> > > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > > @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> > > > > drm_connector *connector,
> > > > > u32 max_tmds_clock = hf_vsdb[5] * 5000;
> > > > > struct drm_scdc *scdc = >scdc;
> > > > >
> > > > > - if (max_tmds_clock > 34) {
> > > > > + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > > > > display->max_tmds_clock = max_tmds_clock;
> > > > > DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d
> > > > > kHz\n",
> > > > > display->max_tmds_clock);
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > > index d2e61f6c6e08..0666203d52b7 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > > @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct
> > > > > intel_encoder *encoder,
> > > > > if (scdc->scrambling.low_rates)
> > > > > pipe_config->hdmi_scrambling = true;
> > > > >
> > > > > - if (pipe_config->port_clock > 34) {
> > > > > + if (pipe_config->port_clock >
> > > > > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > > > > pipe_config->hdmi_scrambling = true;
> > > > > pipe_config->hdmi_high_tmds_clock_ratio = true;
> > > > > }
> > > >
> > > > All of that is HDMI 2.0 stuff. So this just makes it all super
> > > > confusing IMO. Nak.
> > >
> > > So reading throgh HDMI 1.4 again it does specify 340 MHz as some kind
> > > of upper limit for the physical cable. But nowhere else is that number
> > > really mentioned AFAICS. HDMI 2.0 does talk quite a bit about the 340
> > > Mcsc limit in various places.
> > >
> > > I wonder what people would think of a couple of helpers like:
> > > - drm_hdmi_{can,must}_use_scrambling()
> > > - drm_hdmi_is_high_tmds_clock_ratio()
> > > or something along those lines? At least with those the code would
> > > read decently and I wouldn't have to wonder what this HDMI 1.4 TMDS
> > > clock limit really is.
> >
> > Patch 2 introduces something along those lines.
> >
> > It doesn't cover everything though, we're using this define in vc4 to
> > limit the available modes in mode_valid on HDMI controllers not
> > 4k-capable
>
> I wouldn't want to use this kind of define for those kinds of checks
> anyway. If the hardware has specific limits in what kind of clocks it
> can generate (or what it was validated for) IMO you should spell
> those out explicitly instead of assuming they happen to match
> some standard defined max value.
AFAIK, in the vc4 case, this is the hardware limit.
And there's other cases where it still seems to make sense to have that
define:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_edid.c#n4978
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/radeon/radeon_encoders.c#n385
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c#n1174
etc..
Maxime
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Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
On Thu, Nov 04, 2021 at 09:48:41AM +0100, Maxime Ripard wrote:
> Hi Ville,
>
> On Wed, Nov 03, 2021 at 08:05:16PM +0200, Ville Syrjälä wrote:
> > On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> > > > --- a/drivers/gpu/drm/drm_edid.c
> > > > +++ b/drivers/gpu/drm/drm_edid.c
> > > > @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> > > > drm_connector *connector,
> > > > u32 max_tmds_clock = hf_vsdb[5] * 5000;
> > > > struct drm_scdc *scdc = >scdc;
> > > >
> > > > - if (max_tmds_clock > 34) {
> > > > + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > > > display->max_tmds_clock = max_tmds_clock;
> > > > DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d
> > > > kHz\n",
> > > > display->max_tmds_clock);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > index d2e61f6c6e08..0666203d52b7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > > @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct
> > > > intel_encoder *encoder,
> > > > if (scdc->scrambling.low_rates)
> > > > pipe_config->hdmi_scrambling = true;
> > > >
> > > > - if (pipe_config->port_clock > 34) {
> > > > + if (pipe_config->port_clock >
> > > > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > > > pipe_config->hdmi_scrambling = true;
> > > > pipe_config->hdmi_high_tmds_clock_ratio = true;
> > > > }
> > >
> > > All of that is HDMI 2.0 stuff. So this just makes it all super
> > > confusing IMO. Nak.
> >
> > So reading throgh HDMI 1.4 again it does specify 340 MHz as some kind
> > of upper limit for the physical cable. But nowhere else is that number
> > really mentioned AFAICS. HDMI 2.0 does talk quite a bit about the 340
> > Mcsc limit in various places.
> >
> > I wonder what people would think of a couple of helpers like:
> > - drm_hdmi_{can,must}_use_scrambling()
> > - drm_hdmi_is_high_tmds_clock_ratio()
> > or something along those lines? At least with those the code would
> > read decently and I wouldn't have to wonder what this HDMI 1.4 TMDS
> > clock limit really is.
>
> Patch 2 introduces something along those lines.
>
> It doesn't cover everything though, we're using this define in vc4 to
> limit the available modes in mode_valid on HDMI controllers not
> 4k-capable
I wouldn't want to use this kind of define for those kinds of checks
anyway. If the hardware has specific limits in what kind of clocks it
can generate (or what it was validated for) IMO you should spell
those out explicitly instead of assuming they happen to match
some standard defined max value.
--
Ville Syrjälä
Intel
Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
Hi Ville,
On Wed, Nov 03, 2021 at 08:05:16PM +0200, Ville Syrjälä wrote:
> On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> > > --- a/drivers/gpu/drm/drm_edid.c
> > > +++ b/drivers/gpu/drm/drm_edid.c
> > > @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> > > drm_connector *connector,
> > > u32 max_tmds_clock = hf_vsdb[5] * 5000;
> > > struct drm_scdc *scdc = >scdc;
> > >
> > > - if (max_tmds_clock > 34) {
> > > + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > > display->max_tmds_clock = max_tmds_clock;
> > > DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
> > > display->max_tmds_clock);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > index d2e61f6c6e08..0666203d52b7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > > @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct intel_encoder
> > > *encoder,
> > > if (scdc->scrambling.low_rates)
> > > pipe_config->hdmi_scrambling = true;
> > >
> > > - if (pipe_config->port_clock > 34) {
> > > + if (pipe_config->port_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > > pipe_config->hdmi_scrambling = true;
> > > pipe_config->hdmi_high_tmds_clock_ratio = true;
> > > }
> >
> > All of that is HDMI 2.0 stuff. So this just makes it all super
> > confusing IMO. Nak.
>
> So reading throgh HDMI 1.4 again it does specify 340 MHz as some kind
> of upper limit for the physical cable. But nowhere else is that number
> really mentioned AFAICS. HDMI 2.0 does talk quite a bit about the 340
> Mcsc limit in various places.
>
> I wonder what people would think of a couple of helpers like:
> - drm_hdmi_{can,must}_use_scrambling()
> - drm_hdmi_is_high_tmds_clock_ratio()
> or something along those lines? At least with those the code would
> read decently and I wouldn't have to wonder what this HDMI 1.4 TMDS
> clock limit really is.
Patch 2 introduces something along those lines.
It doesn't cover everything though, we're using this define in vc4 to
limit the available modes in mode_valid on HDMI controllers not
4k-capable
We could probably do better on the name, but I still believe a define
like this would be valuable.
Maxime
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Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
On Wed, Nov 03, 2021 at 01:02:11PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> > drm_connector *connector,
> > u32 max_tmds_clock = hf_vsdb[5] * 5000;
> > struct drm_scdc *scdc = >scdc;
> >
> > - if (max_tmds_clock > 34) {
> > + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > display->max_tmds_clock = max_tmds_clock;
> > DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
> > display->max_tmds_clock);
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index d2e61f6c6e08..0666203d52b7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct intel_encoder
> > *encoder,
> > if (scdc->scrambling.low_rates)
> > pipe_config->hdmi_scrambling = true;
> >
> > - if (pipe_config->port_clock > 34) {
> > + if (pipe_config->port_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> > pipe_config->hdmi_scrambling = true;
> > pipe_config->hdmi_high_tmds_clock_ratio = true;
> > }
>
> All of that is HDMI 2.0 stuff. So this just makes it all super
> confusing IMO. Nak.
So reading throgh HDMI 1.4 again it does specify 340 MHz as some kind
of upper limit for the physical cable. But nowhere else is that number
really mentioned AFAICS. HDMI 2.0 does talk quite a bit about the 340
Mcsc limit in various places.
I wonder what people would think of a couple of helpers like:
- drm_hdmi_{can,must}_use_scrambling()
- drm_hdmi_is_high_tmds_clock_ratio()
or something along those lines? At least with those the code would
read decently and I wouldn't have to wonder what this HDMI 1.4 TMDS
clock limit really is.
--
Ville Syrjälä
Intel
Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
On Tue, Nov 02, 2021 at 03:59:32PM +0100, Maxime Ripard wrote:
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> drm_connector *connector,
> u32 max_tmds_clock = hf_vsdb[5] * 5000;
> struct drm_scdc *scdc = >scdc;
>
> - if (max_tmds_clock > 34) {
> + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> display->max_tmds_clock = max_tmds_clock;
> DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
> display->max_tmds_clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index d2e61f6c6e08..0666203d52b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
> if (scdc->scrambling.low_rates)
> pipe_config->hdmi_scrambling = true;
>
> - if (pipe_config->port_clock > 34) {
> + if (pipe_config->port_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> pipe_config->hdmi_scrambling = true;
> pipe_config->hdmi_high_tmds_clock_ratio = true;
> }
All of that is HDMI 2.0 stuff. So this just makes it all super
confusing IMO. Nak.
--
Ville Syrjälä
Intel
Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
On 02/11/2021 15:59, Maxime Ripard wrote:
> A lot of drivers open-code the HDMI 1.4 maximum pixel rate in their
> driver to test whether the resolutions are supported or if the
> scrambling needs to be enabled.
>
> Let's create a common define for everyone to use it.
>
> Cc: Alex Deucher
> Cc: amd-...@lists.freedesktop.org
> Cc: Andrzej Hajda
> Cc: Benjamin Gaignard
> Cc: "Christian König"
> Cc: Emma Anholt
> Cc: intel-...@lists.freedesktop.org
> Cc: Jani Nikula
> Cc: Jernej Skrabec
> Cc: Jerome Brunet
> Cc: Jonas Karlman
> Cc: Jonathan Hunter
> Cc: Joonas Lahtinen
> Cc: Kevin Hilman
> Cc: Laurent Pinchart
> Cc: linux-amlo...@lists.infradead.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-te...@vger.kernel.org
> Cc: Martin Blumenstingl
> Cc: Neil Armstrong
> Cc: "Pan, Xinhui"
> Cc: Robert Foss
> Cc: Rodrigo Vivi
> Cc: Thierry Reding
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++--
> drivers/gpu/drm/drm_edid.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ++--
> drivers/gpu/drm/radeon/radeon_encoders.c | 2 +-
> drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c | 2 +-
> drivers/gpu/drm/tegra/sor.c| 8
> drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
> include/drm/drm_connector.h| 2 ++
> 9 files changed, 16 insertions(+), 14 deletions(-)
For meson & bridge/synopsys/dw-hdmi:
Acked-by: Neil Armstrong
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 62ae63565d3a..3a58db357be0 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -46,7 +46,7 @@
> /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
> #define SCDC_MIN_SOURCE_VERSION 0x1
>
> -#define HDMI14_MAX_TMDSCLK 34000
> +#define HDMI14_MAX_TMDSCLK (DRM_HDMI_14_MAX_TMDS_CLK_KHZ * 1000)
>
> enum hdmi_datamap {
> RGB444_8B = 0x01,
> @@ -1264,7 +1264,7 @@ static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
>* for low rates is not supported either
>*/
> if (!display->hdmi.scdc.scrambling.low_rates &&
> - display->max_tmds_clock <= 34)
> + display->max_tmds_clock <= DRM_HDMI_14_MAX_TMDS_CLK_KHZ)
> return false;
>
> return true;
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 7aa2a56a71c8..ec8fb2d098ae 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> drm_connector *connector,
> u32 max_tmds_clock = hf_vsdb[5] * 5000;
> struct drm_scdc *scdc = >scdc;
>
> - if (max_tmds_clock > 34) {
> + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> display->max_tmds_clock = max_tmds_clock;
> DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
> display->max_tmds_clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index d2e61f6c6e08..0666203d52b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
> if (scdc->scrambling.low_rates)
> pipe_config->hdmi_scrambling = true;
>
> - if (pipe_config->port_clock > 34) {
> + if (pipe_config->port_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> pipe_config->hdmi_scrambling = true;
> pipe_config->hdmi_high_tmds_clock_ratio = true;
> }
> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> index 0afbd1e70bfc..8078667aea0e 100644
> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> @@ -434,7 +434,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
> *data,
> readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
>
> DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name,
> - mode->clock > 34 ? 40 : 10);
> + mode->clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ ? 40 : 10);
>
> /* Enable clocks */
> regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0x, 0x100);
> @@ -457,7 +457,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
> *data,
> dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
>
> /* TMDS pattern setup */
> - if (mode->clock > 34 &&
> + if (mode->clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ &&
> dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_YUV8_1X24) {
> dw_hdmi->data->top_write(dw_hdmi,
Re: [PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
On Tue, Nov 2, 2021 at 10:59 AM Maxime Ripard wrote:
>
> A lot of drivers open-code the HDMI 1.4 maximum pixel rate in their
> driver to test whether the resolutions are supported or if the
> scrambling needs to be enabled.
>
> Let's create a common define for everyone to use it.
>
> Cc: Alex Deucher
> Cc: amd-...@lists.freedesktop.org
> Cc: Andrzej Hajda
> Cc: Benjamin Gaignard
> Cc: "Christian König"
> Cc: Emma Anholt
> Cc: intel-...@lists.freedesktop.org
> Cc: Jani Nikula
> Cc: Jernej Skrabec
> Cc: Jerome Brunet
> Cc: Jonas Karlman
> Cc: Jonathan Hunter
> Cc: Joonas Lahtinen
> Cc: Kevin Hilman
> Cc: Laurent Pinchart
> Cc: linux-amlo...@lists.infradead.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-te...@vger.kernel.org
> Cc: Martin Blumenstingl
> Cc: Neil Armstrong
> Cc: "Pan, Xinhui"
> Cc: Robert Foss
> Cc: Rodrigo Vivi
> Cc: Thierry Reding
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++--
> drivers/gpu/drm/drm_edid.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ++--
> drivers/gpu/drm/radeon/radeon_encoders.c | 2 +-
For radeon:
Acked-by: Alex Deucher
Note that there are several instances of this in amdgpu as well:
drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c:if
(pixel_clock > 34)
drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c:if
(pixel_clock > 34)
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:if
(mode->clock > 34)
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:if
(mode->clock > 34)
Alex
> drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c | 2 +-
> drivers/gpu/drm/tegra/sor.c| 8
> drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
> include/drm/drm_connector.h| 2 ++
> 9 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 62ae63565d3a..3a58db357be0 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -46,7 +46,7 @@
> /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
> #define SCDC_MIN_SOURCE_VERSION0x1
>
> -#define HDMI14_MAX_TMDSCLK 34000
> +#define HDMI14_MAX_TMDSCLK (DRM_HDMI_14_MAX_TMDS_CLK_KHZ * 1000)
>
> enum hdmi_datamap {
> RGB444_8B = 0x01,
> @@ -1264,7 +1264,7 @@ static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
> * for low rates is not supported either
> */
> if (!display->hdmi.scdc.scrambling.low_rates &&
> - display->max_tmds_clock <= 34)
> + display->max_tmds_clock <= DRM_HDMI_14_MAX_TMDS_CLK_KHZ)
> return false;
>
> return true;
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 7aa2a56a71c8..ec8fb2d098ae 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
> drm_connector *connector,
> u32 max_tmds_clock = hf_vsdb[5] * 5000;
> struct drm_scdc *scdc = >scdc;
>
> - if (max_tmds_clock > 34) {
> + if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> display->max_tmds_clock = max_tmds_clock;
> DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
> display->max_tmds_clock);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index d2e61f6c6e08..0666203d52b7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct intel_encoder
> *encoder,
> if (scdc->scrambling.low_rates)
> pipe_config->hdmi_scrambling = true;
>
> - if (pipe_config->port_clock > 34) {
> + if (pipe_config->port_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
> pipe_config->hdmi_scrambling = true;
> pipe_config->hdmi_high_tmds_clock_ratio = true;
> }
> diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> index 0afbd1e70bfc..8078667aea0e 100644
> --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
> +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
> @@ -434,7 +434,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
> *data,
> readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
>
> DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name,
> -mode->clock > 34 ? 40 : 10);
> +mode->clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ ? 40 :
> 10);
>
> /* Enable clocks */
> regmap_update_bits(priv->hhi,
[PATCH 01/13] drm/connector: Add define for HDMI 1.4 Maximum Pixel Rate
A lot of drivers open-code the HDMI 1.4 maximum pixel rate in their
driver to test whether the resolutions are supported or if the
scrambling needs to be enabled.
Let's create a common define for everyone to use it.
Cc: Alex Deucher
Cc: amd-...@lists.freedesktop.org
Cc: Andrzej Hajda
Cc: Benjamin Gaignard
Cc: "Christian König"
Cc: Emma Anholt
Cc: intel-...@lists.freedesktop.org
Cc: Jani Nikula
Cc: Jernej Skrabec
Cc: Jerome Brunet
Cc: Jonas Karlman
Cc: Jonathan Hunter
Cc: Joonas Lahtinen
Cc: Kevin Hilman
Cc: Laurent Pinchart
Cc: linux-amlo...@lists.infradead.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-te...@vger.kernel.org
Cc: Martin Blumenstingl
Cc: Neil Armstrong
Cc: "Pan, Xinhui"
Cc: Robert Foss
Cc: Rodrigo Vivi
Cc: Thierry Reding
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ++--
drivers/gpu/drm/drm_edid.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ++--
drivers/gpu/drm/radeon/radeon_encoders.c | 2 +-
drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c | 2 +-
drivers/gpu/drm/tegra/sor.c| 8
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
include/drm/drm_connector.h| 2 ++
9 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 62ae63565d3a..3a58db357be0 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -46,7 +46,7 @@
/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
#define SCDC_MIN_SOURCE_VERSION0x1
-#define HDMI14_MAX_TMDSCLK 34000
+#define HDMI14_MAX_TMDSCLK (DRM_HDMI_14_MAX_TMDS_CLK_KHZ * 1000)
enum hdmi_datamap {
RGB444_8B = 0x01,
@@ -1264,7 +1264,7 @@ static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
* for low rates is not supported either
*/
if (!display->hdmi.scdc.scrambling.low_rates &&
- display->max_tmds_clock <= 34)
+ display->max_tmds_clock <= DRM_HDMI_14_MAX_TMDS_CLK_KHZ)
return false;
return true;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 7aa2a56a71c8..ec8fb2d098ae 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -4966,7 +4966,7 @@ static void drm_parse_hdmi_forum_vsdb(struct
drm_connector *connector,
u32 max_tmds_clock = hf_vsdb[5] * 5000;
struct drm_scdc *scdc = >scdc;
- if (max_tmds_clock > 34) {
+ if (max_tmds_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
display->max_tmds_clock = max_tmds_clock;
DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
display->max_tmds_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index d2e61f6c6e08..0666203d52b7 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2226,7 +2226,7 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
if (scdc->scrambling.low_rates)
pipe_config->hdmi_scrambling = true;
- if (pipe_config->port_clock > 34) {
+ if (pipe_config->port_clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ) {
pipe_config->hdmi_scrambling = true;
pipe_config->hdmi_high_tmds_clock_ratio = true;
}
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c
b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index 0afbd1e70bfc..8078667aea0e 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -434,7 +434,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
*data,
readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name,
-mode->clock > 34 ? 40 : 10);
+mode->clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ ? 40 : 10);
/* Enable clocks */
regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0x, 0x100);
@@ -457,7 +457,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void
*data,
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
/* TMDS pattern setup */
- if (mode->clock > 34 &&
+ if (mode->clock > DRM_HDMI_14_MAX_TMDS_CLK_KHZ &&
dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_YUV8_1X24) {
dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
0);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 46549d5179ee..ddd8100e699f 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++
