[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Christian König 
From: Christian Koenig 

So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig 
---
 drivers/gpu/drm/radeon/evergreen.c  |   32 -
 drivers/gpu/drm/radeon/r100.c   |   10 +++---
 drivers/gpu/drm/radeon/r600.c   |   10 +++---
 drivers/gpu/drm/radeon/radeon.h |6 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c |   59 +++
 drivers/gpu/drm/radeon/rs600.c  |   10 +++---
 drivers/gpu/drm/radeon/si.c |   30 
 7 files changed, 76 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 8b64227..f2b6502 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2607,20 +2607,20 @@ int evergreen_irq_set(struct radeon_device *rdev)

if (rdev->family >= CHIP_CAYMAN) {
/* enable CP interrupts on all rings */
-   if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
}
} else {
-   if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
@@ -2628,32 +2628,32 @@ int evergreen_irq_set(struct radeon_device *rdev)
}

if (rdev->irq.crtc_vblank_int[0] ||
-   rdev->irq.pflip[0]) {
+   atomic_read(>irq.pflip[0])) {
DRM_DEBUG("evergreen_irq_set: vblank 0\n");
crtc1 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[1] ||
-   rdev->irq.pflip[1]) {
+   atomic_read(>irq.pflip[1])) {
DRM_DEBUG("evergreen_irq_set: vblank 1\n");
crtc2 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[2] ||
-   rdev->irq.pflip[2]) {
+   atomic_read(>irq.pflip[2])) {
DRM_DEBUG("evergreen_irq_set: vblank 2\n");
crtc3 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[3] ||
-   rdev->irq.pflip[3]) {
+   atomic_read(>irq.pflip[3])) {
DRM_DEBUG("evergreen_irq_set: vblank 3\n");
crtc4 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[4] ||
-   rdev->irq.pflip[4]) {
+   atomic_read(>irq.pflip[4])) {
DRM_DEBUG("evergreen_irq_set: vblank 4\n");
crtc5 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[5] ||
-   rdev->irq.pflip[5]) {
+   atomic_read(>irq.pflip[5])) {
DRM_DEBUG("evergreen_irq_set: vblank 5\n");
crtc6 |= VBLANK_INT_MASK;
}
@@ -2973,7 +2973,7 @@ restart_ih:
rdev->pm.vblank_sync = true;

wake_up(>irq.vblank_queue);
}
-   if (rdev->irq.pflip[0])
+   if (atomic_read(>irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 
0);
rdev->irq.stat_regs.evergreen.disp_int 
&= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
@@ -2999,7 +2999,7 @@ restart_ih:
rdev->pm.vblank_sync = true;

wake_up(>irq.vblank_queue);
}
-   if (rdev->irq.pflip[1])
+   if (atomic_read(>irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 
1);

rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Michel Dänzer 
On Fre, 2012-06-01 at 12:44 +0200, Christian K?nig wrote: 
> On 01.06.2012 08:30, Michel D?nzer wrote:
> > On Fre, 2012-06-01 at 08:19 +0200, Michel D?nzer wrote:
> >> I think this might introduce a race condition:
> >>
> >> Thread 0 Thread 1
> >>  
> >> atomic_inc_return() returns 1
> >> spin_lock_irqsave()
> >> atomic_dec_and_test()
> >> radeon_irq_set()
> >>
> >> =>  the interrupt won't be enabled.
> > Hrmm, I messed up the formatting there, let me try one more time:
> >
> > Thread 0Thread 1
> > 
> > atomic_inc_return() returns 1
> > spin_lock_irqsave()
> > atomic_dec_and_test()
> > radeon_irq_set()
> >
> >
> Nope that isn't a problem, cause what you really get in your example is:
> 
> Thread 0  Thread 1
>   
> atomic_inc_return() returns 1
> spin_lock_irqsave()
>   atomic_dec_and_test()
> radeon_irq_set()
> spin_unlock_irqrestore()
>   spin_lock_irqsave()
>   radeon_irq_set()
>   spin_unlock_irqrestore()
> 
> 
> So testing the atomic counters just determines if we need an update of 
> the irq registers or not, and since a significant change will always 
> trigger an update we can make sure that the irq regs are always set to 
> the last known state. We might call radeon_irq_set more often than 
> necessary, but that won't hurt us and is really unlikely.

Yeah, I also realized in the meantime that the race can't happen. I
blame it on lack of caffeine. :)


> Also I have found the real reason why using the atomic for preventing ih 
> recursion didn't worked as expected - it was just a stupid typo in my 
> patch.  But thanks for the comment anyway, it got me to look into the 
> right direction for the bug.

Glad to hear that!


-- 
Earthling Michel D?nzer   |   http://www.amd.com
Libre software enthusiast |  Debian, X and DRI developer

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Christian König 
On 01.06.2012 08:30, Michel D?nzer wrote:
> On Fre, 2012-06-01 at 08:19 +0200, Michel D?nzer wrote:
>> I think this might introduce a race condition:
>>
>> Thread 0 Thread 1
>>  
>> atomic_inc_return() returns 1
>> spin_lock_irqsave()
>> atomic_dec_and_test()
>> radeon_irq_set()
>>
>> =>  the interrupt won't be enabled.
> Hrmm, I messed up the formatting there, let me try one more time:
>
> Thread 0  Thread 1
>   
> atomic_inc_return() returns 1
> spin_lock_irqsave()
>   atomic_dec_and_test()
> radeon_irq_set()
>
>
Nope that isn't a problem, cause what you really get in your example is:

Thread 0Thread 1

atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()
spin_unlock_irqrestore()
spin_lock_irqsave()
radeon_irq_set()
spin_unlock_irqrestore()


So testing the atomic counters just determines if we need an update of 
the irq registers or not, and since a significant change will always 
trigger an update we can make sure that the irq regs are always set to 
the last known state. We might call radeon_irq_set more often than 
necessary, but that won't hurt us and is really unlikely.

Also I have found the real reason why using the atomic for preventing ih 
recursion didn't worked as expected - it was just a stupid typo in my 
patch.  But thanks for the comment anyway, it got me to look into the 
right direction for the bug.

Cheers,
Christian.

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Michel Dänzer 
On Fre, 2012-06-01 at 08:19 +0200, Michel D?nzer wrote: 
> 
> I think this might introduce a race condition:
> 
> Thread 0 Thread 1
>  
> atomic_inc_return() returns 1
> spin_lock_irqsave()
> atomic_dec_and_test()
> radeon_irq_set()
> 
> => the interrupt won't be enabled.

Hrmm, I messed up the formatting there, let me try one more time:

Thread 0Thread 1

atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()


-- 
Earthling Michel D?nzer   |   http://www.amd.com
Libre software enthusiast |  Debian, X and DRI developer

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Michel Dänzer 
On Don, 2012-05-31 at 22:16 +0200, Christian K?nig wrote: 
> 
> So we can skip the looking.

'locking'


> diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c 
> b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> index 73cd0fd..52f85ba 100644
> --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
> @@ -87,16 +87,7 @@ void radeon_driver_irq_preinstall_kms(struct drm_device 
> *dev)
>  
>  int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
>  {
> - struct radeon_device *rdev = dev->dev_private;
> - unsigned long irqflags;
> - unsigned i;
> -
>   dev->max_vblank_count = 0x001f;
> - spin_lock_irqsave(>irq.lock, irqflags);
> - for (i = 0; i < RADEON_NUM_RINGS; i++)
> - rdev->irq.sw_int[i] = true;
> - radeon_irq_set(rdev);
> - spin_unlock_irqrestore(>irq.lock, irqflags);
>   return 0;
>  }

Why does this function no longer need to enable SW interrupts? If it
really doesn't, that might be material for a separate patch.


> @@ -225,25 +216,28 @@ void radeon_irq_kms_sw_irq_get(struct radeon_device 
> *rdev, int ring)
>  {
>   unsigned long irqflags;
>  
> - spin_lock_irqsave(>irq.lock, irqflags);
> - if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount[ring] == 1)) {
> - rdev->irq.sw_int[ring] = true;
> + if (!rdev->ddev->irq_enabled)
> + return;
> +
> + if (atomic_inc_return(>irq.ring_int[ring]) == 1) {
> + spin_lock_irqsave(>irq.lock, irqflags);
>   radeon_irq_set(rdev);
> + spin_unlock_irqrestore(>irq.lock, irqflags);
>   }
> - spin_unlock_irqrestore(>irq.lock, irqflags);
>  }
>  
>  void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
>  {
>   unsigned long irqflags;
>  
> - spin_lock_irqsave(>irq.lock, irqflags);
> - BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount[ring] <= 0);
> - if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount[ring] == 0)) {
> - rdev->irq.sw_int[ring] = false;
> + if (!rdev->ddev->irq_enabled)
> + return;
> +
> + if (atomic_dec_and_test(>irq.ring_int[ring])) {
> + spin_lock_irqsave(>irq.lock, irqflags);
>   radeon_irq_set(rdev);
> + spin_unlock_irqrestore(>irq.lock, irqflags);
>   }
> - spin_unlock_irqrestore(>irq.lock, irqflags);
>  }
>  
>  void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)

I think this might introduce a race condition:

Thread 0 Thread 1
 
atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()

=> the interrupt won't be enabled.

Maybe this explains why you couldn't remove the spinlock in patch 6?


-- 
Earthling Michel D?nzer   |   http://www.amd.com
Libre software enthusiast |  Debian, X and DRI developer

Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Michel Dänzer 
On Don, 2012-05-31 at 22:16 +0200, Christian König wrote: 
 
 So we can skip the looking.

'locking'


 diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c 
 b/drivers/gpu/drm/radeon/radeon_irq_kms.c
 index 73cd0fd..52f85ba 100644
 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
 +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
 @@ -87,16 +87,7 @@ void radeon_driver_irq_preinstall_kms(struct drm_device 
 *dev)
  
  int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
  {
 - struct radeon_device *rdev = dev-dev_private;
 - unsigned long irqflags;
 - unsigned i;
 -
   dev-max_vblank_count = 0x001f;
 - spin_lock_irqsave(rdev-irq.lock, irqflags);
 - for (i = 0; i  RADEON_NUM_RINGS; i++)
 - rdev-irq.sw_int[i] = true;
 - radeon_irq_set(rdev);
 - spin_unlock_irqrestore(rdev-irq.lock, irqflags);
   return 0;
  }

Why does this function no longer need to enable SW interrupts? If it
really doesn't, that might be material for a separate patch.


 @@ -225,25 +216,28 @@ void radeon_irq_kms_sw_irq_get(struct radeon_device 
 *rdev, int ring)
  {
   unsigned long irqflags;
  
 - spin_lock_irqsave(rdev-irq.lock, irqflags);
 - if (rdev-ddev-irq_enabled  (++rdev-irq.sw_refcount[ring] == 1)) {
 - rdev-irq.sw_int[ring] = true;
 + if (!rdev-ddev-irq_enabled)
 + return;
 +
 + if (atomic_inc_return(rdev-irq.ring_int[ring]) == 1) {
 + spin_lock_irqsave(rdev-irq.lock, irqflags);
   radeon_irq_set(rdev);
 + spin_unlock_irqrestore(rdev-irq.lock, irqflags);
   }
 - spin_unlock_irqrestore(rdev-irq.lock, irqflags);
  }
  
  void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
  {
   unsigned long irqflags;
  
 - spin_lock_irqsave(rdev-irq.lock, irqflags);
 - BUG_ON(rdev-ddev-irq_enabled  rdev-irq.sw_refcount[ring] = 0);
 - if (rdev-ddev-irq_enabled  (--rdev-irq.sw_refcount[ring] == 0)) {
 - rdev-irq.sw_int[ring] = false;
 + if (!rdev-ddev-irq_enabled)
 + return;
 +
 + if (atomic_dec_and_test(rdev-irq.ring_int[ring])) {
 + spin_lock_irqsave(rdev-irq.lock, irqflags);
   radeon_irq_set(rdev);
 + spin_unlock_irqrestore(rdev-irq.lock, irqflags);
   }
 - spin_unlock_irqrestore(rdev-irq.lock, irqflags);
  }
  
  void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)

I think this might introduce a race condition:

Thread 0 Thread 1
 
atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()

= the interrupt won't be enabled.

Maybe this explains why you couldn't remove the spinlock in patch 6?


-- 
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Libre software enthusiast |  Debian, X and DRI developer
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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Michel Dänzer 
On Fre, 2012-06-01 at 08:19 +0200, Michel Dänzer wrote: 
 
 I think this might introduce a race condition:
 
 Thread 0 Thread 1
  
 atomic_inc_return() returns 1
 spin_lock_irqsave()
 atomic_dec_and_test()
 radeon_irq_set()
 
 = the interrupt won't be enabled.

Hrmm, I messed up the formatting there, let me try one more time:

Thread 0Thread 1

atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast |  Debian, X and DRI developer

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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Christian König 

On 01.06.2012 08:30, Michel Dänzer wrote:

On Fre, 2012-06-01 at 08:19 +0200, Michel Dänzer wrote:

I think this might introduce a race condition:

Thread 0 Thread 1
 
atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()

=  the interrupt won't be enabled.

Hrmm, I messed up the formatting there, let me try one more time:

Thread 0Thread 1

atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()



Nope that isn't a problem, cause what you really get in your example is:

Thread 0Thread 1

atomic_inc_return() returns 1
spin_lock_irqsave()
atomic_dec_and_test()
radeon_irq_set()
spin_unlock_irqrestore()
spin_lock_irqsave()
radeon_irq_set()
spin_unlock_irqrestore()


So testing the atomic counters just determines if we need an update of 
the irq registers or not, and since a significant change will always 
trigger an update we can make sure that the irq regs are always set to 
the last known state. We might call radeon_irq_set more often than 
necessary, but that won't hurt us and is really unlikely.


Also I have found the real reason why using the atomic for preventing ih 
recursion didn't worked as expected - it was just a stupid typo in my 
patch.  But thanks for the comment anyway, it got me to look into the 
right direction for the bug.


Cheers,
Christian.
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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Michel Dänzer 
On Fre, 2012-06-01 at 12:44 +0200, Christian König wrote: 
 On 01.06.2012 08:30, Michel Dänzer wrote:
  On Fre, 2012-06-01 at 08:19 +0200, Michel Dänzer wrote:
  I think this might introduce a race condition:
 
  Thread 0 Thread 1
   
  atomic_inc_return() returns 1
  spin_lock_irqsave()
  atomic_dec_and_test()
  radeon_irq_set()
 
  =  the interrupt won't be enabled.
  Hrmm, I messed up the formatting there, let me try one more time:
 
  Thread 0Thread 1
  
  atomic_inc_return() returns 1
  spin_lock_irqsave()
  atomic_dec_and_test()
  radeon_irq_set()
 
 
 Nope that isn't a problem, cause what you really get in your example is:
 
 Thread 0  Thread 1
   
 atomic_inc_return() returns 1
 spin_lock_irqsave()
   atomic_dec_and_test()
 radeon_irq_set()
 spin_unlock_irqrestore()
   spin_lock_irqsave()
   radeon_irq_set()
   spin_unlock_irqrestore()
 
 
 So testing the atomic counters just determines if we need an update of 
 the irq registers or not, and since a significant change will always 
 trigger an update we can make sure that the irq regs are always set to 
 the last known state. We might call radeon_irq_set more often than 
 necessary, but that won't hurt us and is really unlikely.

Yeah, I also realized in the meantime that the race can't happen. I
blame it on lack of caffeine. :)


 Also I have found the real reason why using the atomic for preventing ih 
 recursion didn't worked as expected - it was just a stupid typo in my 
 patch.  But thanks for the comment anyway, it got me to look into the 
 right direction for the bug.

Glad to hear that!


-- 
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Libre software enthusiast |  Debian, X and DRI developer
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[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-06-01 Thread Christian König 
From: Christian Koenig christian.koe...@amd.com

So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig christian.koe...@amd.com
---
 drivers/gpu/drm/radeon/evergreen.c  |   32 -
 drivers/gpu/drm/radeon/r100.c   |   10 +++---
 drivers/gpu/drm/radeon/r600.c   |   10 +++---
 drivers/gpu/drm/radeon/radeon.h |6 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c |   59 +++
 drivers/gpu/drm/radeon/rs600.c  |   10 +++---
 drivers/gpu/drm/radeon/si.c |   30 
 7 files changed, 76 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 8b64227..f2b6502 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2607,20 +2607,20 @@ int evergreen_irq_set(struct radeon_device *rdev)
 
if (rdev-family = CHIP_CAYMAN) {
/* enable CP interrupts on all rings */
-   if (rdev-irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int gfx\n);
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev-irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int cp1\n);
cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev-irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int cp2\n);
cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
}
} else {
-   if (rdev-irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int gfx\n);
cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
@@ -2628,32 +2628,32 @@ int evergreen_irq_set(struct radeon_device *rdev)
}
 
if (rdev-irq.crtc_vblank_int[0] ||
-   rdev-irq.pflip[0]) {
+   atomic_read(rdev-irq.pflip[0])) {
DRM_DEBUG(evergreen_irq_set: vblank 0\n);
crtc1 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[1] ||
-   rdev-irq.pflip[1]) {
+   atomic_read(rdev-irq.pflip[1])) {
DRM_DEBUG(evergreen_irq_set: vblank 1\n);
crtc2 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[2] ||
-   rdev-irq.pflip[2]) {
+   atomic_read(rdev-irq.pflip[2])) {
DRM_DEBUG(evergreen_irq_set: vblank 2\n);
crtc3 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[3] ||
-   rdev-irq.pflip[3]) {
+   atomic_read(rdev-irq.pflip[3])) {
DRM_DEBUG(evergreen_irq_set: vblank 3\n);
crtc4 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[4] ||
-   rdev-irq.pflip[4]) {
+   atomic_read(rdev-irq.pflip[4])) {
DRM_DEBUG(evergreen_irq_set: vblank 4\n);
crtc5 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[5] ||
-   rdev-irq.pflip[5]) {
+   atomic_read(rdev-irq.pflip[5])) {
DRM_DEBUG(evergreen_irq_set: vblank 5\n);
crtc6 |= VBLANK_INT_MASK;
}
@@ -2973,7 +2973,7 @@ restart_ih:
rdev-pm.vblank_sync = true;

wake_up(rdev-irq.vblank_queue);
}
-   if (rdev-irq.pflip[0])
+   if (atomic_read(rdev-irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 
0);
rdev-irq.stat_regs.evergreen.disp_int 
= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG(IH: D1 vblank\n);
@@ -2999,7 +2999,7 @@ restart_ih:
rdev-pm.vblank_sync = true;

wake_up(rdev-irq.vblank_queue);
}
-   if (rdev-irq.pflip[1])
+   if (atomic_read(rdev-irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 
1);

rdev-irq.stat_regs.evergreen.disp_int_cont = ~LB_D2_VBLANK_INTERRUPT;

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-31 Thread Christian König 
From: Christian Koenig 

So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig 
---
 drivers/gpu/drm/radeon/evergreen.c  |   32 -
 drivers/gpu/drm/radeon/r100.c   |   10 +++---
 drivers/gpu/drm/radeon/r600.c   |   10 +++---
 drivers/gpu/drm/radeon/radeon.h |6 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c |   59 +++
 drivers/gpu/drm/radeon/rs600.c  |   10 +++---
 drivers/gpu/drm/radeon/si.c |   30 
 7 files changed, 76 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 48ec1a0..3d3520a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2607,20 +2607,20 @@ int evergreen_irq_set(struct radeon_device *rdev)

if (rdev->family >= CHIP_CAYMAN) {
/* enable CP interrupts on all rings */
-   if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
}
} else {
-   if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(>irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
@@ -2628,32 +2628,32 @@ int evergreen_irq_set(struct radeon_device *rdev)
}

if (rdev->irq.crtc_vblank_int[0] ||
-   rdev->irq.pflip[0]) {
+   atomic_read(>irq.pflip[0])) {
DRM_DEBUG("evergreen_irq_set: vblank 0\n");
crtc1 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[1] ||
-   rdev->irq.pflip[1]) {
+   atomic_read(>irq.pflip[1])) {
DRM_DEBUG("evergreen_irq_set: vblank 1\n");
crtc2 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[2] ||
-   rdev->irq.pflip[2]) {
+   atomic_read(>irq.pflip[2])) {
DRM_DEBUG("evergreen_irq_set: vblank 2\n");
crtc3 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[3] ||
-   rdev->irq.pflip[3]) {
+   atomic_read(>irq.pflip[3])) {
DRM_DEBUG("evergreen_irq_set: vblank 3\n");
crtc4 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[4] ||
-   rdev->irq.pflip[4]) {
+   atomic_read(>irq.pflip[4])) {
DRM_DEBUG("evergreen_irq_set: vblank 4\n");
crtc5 |= VBLANK_INT_MASK;
}
if (rdev->irq.crtc_vblank_int[5] ||
-   rdev->irq.pflip[5]) {
+   atomic_read(>irq.pflip[5])) {
DRM_DEBUG("evergreen_irq_set: vblank 5\n");
crtc6 |= VBLANK_INT_MASK;
}
@@ -2974,7 +2974,7 @@ restart_ih:
rdev->pm.vblank_sync = true;

wake_up(>irq.vblank_queue);
}
-   if (rdev->irq.pflip[0])
+   if (atomic_read(>irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 
0);
rdev->irq.stat_regs.evergreen.disp_int 
&= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG("IH: D1 vblank\n");
@@ -3000,7 +3000,7 @@ restart_ih:
rdev->pm.vblank_sync = true;

wake_up(>irq.vblank_queue);
}
-   if (rdev->irq.pflip[1])
+   if (atomic_read(>irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 
1);

rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-31 Thread Christian König 
From: Christian Koenig christian.koe...@amd.com

So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig christian.koe...@amd.com
---
 drivers/gpu/drm/radeon/evergreen.c  |   32 -
 drivers/gpu/drm/radeon/r100.c   |   10 +++---
 drivers/gpu/drm/radeon/r600.c   |   10 +++---
 drivers/gpu/drm/radeon/radeon.h |6 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c |   59 +++
 drivers/gpu/drm/radeon/rs600.c  |   10 +++---
 drivers/gpu/drm/radeon/si.c |   30 
 7 files changed, 76 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 48ec1a0..3d3520a 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2607,20 +2607,20 @@ int evergreen_irq_set(struct radeon_device *rdev)
 
if (rdev-family = CHIP_CAYMAN) {
/* enable CP interrupts on all rings */
-   if (rdev-irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int gfx\n);
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev-irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int cp1\n);
cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev-irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int cp2\n);
cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
}
} else {
-   if (rdev-irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int gfx\n);
cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
@@ -2628,32 +2628,32 @@ int evergreen_irq_set(struct radeon_device *rdev)
}
 
if (rdev-irq.crtc_vblank_int[0] ||
-   rdev-irq.pflip[0]) {
+   atomic_read(rdev-irq.pflip[0])) {
DRM_DEBUG(evergreen_irq_set: vblank 0\n);
crtc1 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[1] ||
-   rdev-irq.pflip[1]) {
+   atomic_read(rdev-irq.pflip[1])) {
DRM_DEBUG(evergreen_irq_set: vblank 1\n);
crtc2 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[2] ||
-   rdev-irq.pflip[2]) {
+   atomic_read(rdev-irq.pflip[2])) {
DRM_DEBUG(evergreen_irq_set: vblank 2\n);
crtc3 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[3] ||
-   rdev-irq.pflip[3]) {
+   atomic_read(rdev-irq.pflip[3])) {
DRM_DEBUG(evergreen_irq_set: vblank 3\n);
crtc4 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[4] ||
-   rdev-irq.pflip[4]) {
+   atomic_read(rdev-irq.pflip[4])) {
DRM_DEBUG(evergreen_irq_set: vblank 4\n);
crtc5 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[5] ||
-   rdev-irq.pflip[5]) {
+   atomic_read(rdev-irq.pflip[5])) {
DRM_DEBUG(evergreen_irq_set: vblank 5\n);
crtc6 |= VBLANK_INT_MASK;
}
@@ -2974,7 +2974,7 @@ restart_ih:
rdev-pm.vblank_sync = true;

wake_up(rdev-irq.vblank_queue);
}
-   if (rdev-irq.pflip[0])
+   if (atomic_read(rdev-irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 
0);
rdev-irq.stat_regs.evergreen.disp_int 
= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG(IH: D1 vblank\n);
@@ -3000,7 +3000,7 @@ restart_ih:
rdev-pm.vblank_sync = true;

wake_up(rdev-irq.vblank_queue);
}
-   if (rdev-irq.pflip[1])
+   if (atomic_read(rdev-irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 
1);

rdev-irq.stat_regs.evergreen.disp_int_cont = ~LB_D2_VBLANK_INTERRUPT;

RE: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-25 Thread Koenig, Christian 
 -Original Message-
 From: Sylvain BERTRAND [mailto:sylw...@legeek.net]
 Sent: Thursday, May 24, 2012 1:59 PM
 To: Christian König
 Cc: j.gli...@gmail.com; Koenig, Christian; dri-devel@lists.freedesktop.org
 Subject: Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters
 with atomics
 
  +   atomic_tring_int[RADEON_NUM_RINGS];
  bool
   crtc_vblank_int[RADEON_MAX_CRTCS];
  -   boolpflip[RADEON_MAX_CRTCS];
  -   int
   pflip_refcount[RADEON_MAX_CRTCS];
  +   atomic_tpflip[RADEON_MAX_CRTCS];
 
 Hi,
 
 Does the linux API mandates atomic_t to be a 32bits word?

AFAIK it is, at least for the platforms we care about. But since this depends 
on the vertical refresh frequency even a 8bit counter should do fine.

On the other hand it was an accident that those patches hit the maillinglist in 
the first place, cause only the first four where supposed to be send out (my 
fault, sorry). This one isn't tested beside compiling, and I don't think it 
will work out of the box.

Cheers,
Christian.

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[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Sylvain BERTRAND 
> Does the linux API mandates atomic_t to be a 32bits word?

 AFAIK it is, at least for the platforms we care about.
 ...
>>>
>>> Then, the proper course of action would be to add to the linux API, sized
>>> atomic operation first, wouldn't it?
>>
>> No, atomic is fine for this, I think only sparc32 had 24-bit atomics,
>> and if you can get sparc32 + a radeon,
>> then you can keep both halves.
> 
> And even that is a lie now :-)
> 
> http://lwn.net/Articles/71732/

Ok then: atomic_t means exactly 32 bits!

-- 
Sylvain

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Sylvain BERTRAND 
>> Does the linux API mandates atomic_t to be a 32bits word?
> 
> AFAIK it is, at least for the platforms we care about.
> ...

Then, the proper course of action would be to add to the linux API, sized
atomic operation first, wouldn't it?

-- 
Sylvain

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Sylvain BERTRAND 
> + atomic_tring_int[RADEON_NUM_RINGS];
>   boolcrtc_vblank_int[RADEON_MAX_CRTCS];
> - boolpflip[RADEON_MAX_CRTCS];
> - int pflip_refcount[RADEON_MAX_CRTCS];
> + atomic_tpflip[RADEON_MAX_CRTCS];

Hi,

Does the linux API mandates atomic_t to be a 32bits word?

Regards,

-- 
Sylvain

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Dave Airlie 
On Thu, May 24, 2012 at 1:53 PM, Dave Airlie  wrote:
> On Thu, May 24, 2012 at 1:46 PM, Sylvain BERTRAND  
> wrote:
 Does the linux API mandates atomic_t to be a 32bits word?
>>>
>>> AFAIK it is, at least for the platforms we care about.
>>> ...
>>
>> Then, the proper course of action would be to add to the linux API, sized
>> atomic operation first, wouldn't it?
>>
>
> No, atomic is fine for this, I think only sparc32 had 24-bit atomics,
> and if you can get sparc32 + a radeon,
> then you can keep both halves.

And even that is a lie now :-)

http://lwn.net/Articles/71732/

Dave.

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Dave Airlie 
On Thu, May 24, 2012 at 1:46 PM, Sylvain BERTRAND  wrote:
>>> Does the linux API mandates atomic_t to be a 32bits word?
>>
>> AFAIK it is, at least for the platforms we care about.
>> ...
>
> Then, the proper course of action would be to add to the linux API, sized
> atomic operation first, wouldn't it?
>

No, atomic is fine for this, I think only sparc32 had 24-bit atomics,
and if you can get sparc32 + a radeon,
then you can keep both halves.

Dave.

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Koenig, Christian 
> -Original Message-
> From: Sylvain BERTRAND [mailto:sylware at legeek.net]
> Sent: Thursday, May 24, 2012 1:59 PM
> To: Christian K?nig
> Cc: j.glisse at gmail.com; Koenig, Christian; dri-devel at 
> lists.freedesktop.org
> Subject: Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters
> with atomics
> 
> > +   atomic_tring_int[RADEON_NUM_RINGS];
> > bool
>   crtc_vblank_int[RADEON_MAX_CRTCS];
> > -   boolpflip[RADEON_MAX_CRTCS];
> > -   int
>   pflip_refcount[RADEON_MAX_CRTCS];
> > +   atomic_tpflip[RADEON_MAX_CRTCS];
> 
> Hi,
> 
> Does the linux API mandates atomic_t to be a 32bits word?

AFAIK it is, at least for the platforms we care about. But since this depends 
on the vertical refresh frequency even a 8bit counter should do fine.

On the other hand it was an accident that those patches hit the maillinglist in 
the first place, cause only the first four where supposed to be send out (my 
fault, sorry). This one isn't tested beside compiling, and I don't think it 
will work out of the box.

Cheers,
Christian.

[PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Christian König 
From: Christian Koenig christian.koe...@amd.com

So we can skip the looking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig christian.koe...@amd.com
---
 drivers/gpu/drm/radeon/evergreen.c  |   32 -
 drivers/gpu/drm/radeon/r100.c   |   10 +++---
 drivers/gpu/drm/radeon/r600.c   |   10 +++---
 drivers/gpu/drm/radeon/radeon.h |6 ++--
 drivers/gpu/drm/radeon/radeon_irq_kms.c |   59 +++
 drivers/gpu/drm/radeon/rs600.c  |   10 +++---
 drivers/gpu/drm/radeon/si.c |   30 
 7 files changed, 76 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 9e9b3bb..ec6a8a2 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2615,20 +2615,20 @@ int evergreen_irq_set(struct radeon_device *rdev)
 
if (rdev-family = CHIP_CAYMAN) {
/* enable CP interrupts on all rings */
-   if (rdev-irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int gfx\n);
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev-irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int cp1\n);
cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
}
-   if (rdev-irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int cp2\n);
cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
}
} else {
-   if (rdev-irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+   if 
(atomic_read(rdev-irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG(evergreen_irq_set: sw int gfx\n);
cp_int_cntl |= RB_INT_ENABLE;
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
@@ -2636,32 +2636,32 @@ int evergreen_irq_set(struct radeon_device *rdev)
}
 
if (rdev-irq.crtc_vblank_int[0] ||
-   rdev-irq.pflip[0]) {
+   atomic_read(rdev-irq.pflip[0])) {
DRM_DEBUG(evergreen_irq_set: vblank 0\n);
crtc1 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[1] ||
-   rdev-irq.pflip[1]) {
+   atomic_read(rdev-irq.pflip[1])) {
DRM_DEBUG(evergreen_irq_set: vblank 1\n);
crtc2 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[2] ||
-   rdev-irq.pflip[2]) {
+   atomic_read(rdev-irq.pflip[2])) {
DRM_DEBUG(evergreen_irq_set: vblank 2\n);
crtc3 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[3] ||
-   rdev-irq.pflip[3]) {
+   atomic_read(rdev-irq.pflip[3])) {
DRM_DEBUG(evergreen_irq_set: vblank 3\n);
crtc4 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[4] ||
-   rdev-irq.pflip[4]) {
+   atomic_read(rdev-irq.pflip[4])) {
DRM_DEBUG(evergreen_irq_set: vblank 4\n);
crtc5 |= VBLANK_INT_MASK;
}
if (rdev-irq.crtc_vblank_int[5] ||
-   rdev-irq.pflip[5]) {
+   atomic_read(rdev-irq.pflip[5])) {
DRM_DEBUG(evergreen_irq_set: vblank 5\n);
crtc6 |= VBLANK_INT_MASK;
}
@@ -2984,7 +2984,7 @@ restart_ih:
rdev-pm.vblank_sync = true;

wake_up(rdev-irq.vblank_queue);
}
-   if (rdev-irq.pflip[0])
+   if (atomic_read(rdev-irq.pflip[0]))
radeon_crtc_handle_flip(rdev, 
0);
rdev-irq.stat_regs.evergreen.disp_int 
= ~LB_D1_VBLANK_INTERRUPT;
DRM_DEBUG(IH: D1 vblank\n);
@@ -3010,7 +3010,7 @@ restart_ih:
rdev-pm.vblank_sync = true;

wake_up(rdev-irq.vblank_queue);
}
-   if (rdev-irq.pflip[1])
+   if (atomic_read(rdev-irq.pflip[1]))
radeon_crtc_handle_flip(rdev, 
1);

rdev-irq.stat_regs.evergreen.disp_int_cont = ~LB_D2_VBLANK_INTERRUPT;

Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Sylvain BERTRAND 
 + atomic_tring_int[RADEON_NUM_RINGS];
   boolcrtc_vblank_int[RADEON_MAX_CRTCS];
 - boolpflip[RADEON_MAX_CRTCS];
 - int pflip_refcount[RADEON_MAX_CRTCS];
 + atomic_tpflip[RADEON_MAX_CRTCS];

Hi,

Does the linux API mandates atomic_t to be a 32bits word?

Regards,

-- 
Sylvain
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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Sylvain BERTRAND 
 Does the linux API mandates atomic_t to be a 32bits word?
 
 AFAIK it is, at least for the platforms we care about.
 ...

Then, the proper course of action would be to add to the linux API, sized
atomic operation first, wouldn't it?

-- 
Sylvain
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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Dave Airlie 
On Thu, May 24, 2012 at 1:46 PM, Sylvain BERTRAND sylw...@legeek.net wrote:
 Does the linux API mandates atomic_t to be a 32bits word?

 AFAIK it is, at least for the platforms we care about.
 ...

 Then, the proper course of action would be to add to the linux API, sized
 atomic operation first, wouldn't it?


No, atomic is fine for this, I think only sparc32 had 24-bit atomics,
and if you can get sparc32 + a radeon,
then you can keep both halves.

Dave.
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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Dave Airlie 
On Thu, May 24, 2012 at 1:53 PM, Dave Airlie airl...@gmail.com wrote:
 On Thu, May 24, 2012 at 1:46 PM, Sylvain BERTRAND sylw...@legeek.net wrote:
 Does the linux API mandates atomic_t to be a 32bits word?

 AFAIK it is, at least for the platforms we care about.
 ...

 Then, the proper course of action would be to add to the linux API, sized
 atomic operation first, wouldn't it?


 No, atomic is fine for this, I think only sparc32 had 24-bit atomics,
 and if you can get sparc32 + a radeon,
 then you can keep both halves.

And even that is a lie now :-)

http://lwn.net/Articles/71732/

Dave.
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Re: [PATCH 08/10] drm/radeon: replace pflip and sw_int counters with atomics

2012-05-24 Thread Sylvain BERTRAND 
 Does the linux API mandates atomic_t to be a 32bits word?

 AFAIK it is, at least for the platforms we care about.
 ...

 Then, the proper course of action would be to add to the linux API, sized
 atomic operation first, wouldn't it?

 No, atomic is fine for this, I think only sparc32 had 24-bit atomics,
 and if you can get sparc32 + a radeon,
 then you can keep both halves.
 
 And even that is a lie now :-)
 
 http://lwn.net/Articles/71732/

Ok then: atomic_t means exactly 32 bits!

-- 
Sylvain
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