[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

2013-11-12 Thread Anssi Hannula 
11.11.2013 17:55, Alex Deucher kirjoitti:
> On Fri, Nov 8, 2013 at 6:24 AM, Anssi Hannula  wrote:
>> 18.10.2013 23:41, Alex Deucher kirjoitti:
>>> Needed by the hda driver to properly set up synchronization
>>> on the audio side.
>>>
>>> Signed-off-by: Alex Deucher 
>>> ---
>>>  drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 
>>> 
>>>  drivers/gpu/drm/radeon/evergreend.h | 38 
>>> +
>>>  2 files changed, 75 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
>>> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>>> index 5fbe486..abdc893 100644
>>> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
>>> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> [...]
>>> + if (connector->latency_present[0])
>>> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
>>> + AUDIO_LIPSYNC(connector->audio_latency[0]);
>>> + else
>>> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
>>> + }
>>> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
>> [...]
>>> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
>>> +#   define VIDEO_LIPSYNC(x)   (((x) & 0xff) << 
>>> 0)
>>> +#   define AUDIO_LIPSYNC(x)   (((x) & 0xff) << 
>>> 8)
>>> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
>>> + * 0   = invalid
>>> + * x   = legal delay value
>>> + * 255 = sync not supported
>>> + */
>>
>> Hmm, AMD_HDA_verbs_v2.pdf says that:
>> 0  = unknown latency
>>
>> HDMI spec 1.4 says that:
>> 0  = not valid or unknown latency
>> 1..251 = valid delay value
>> 255= video not supported / audio not supported
>>
>> Are you sure you shouldn't use 0 instead for unknown (no latency_present)?
> 
> I'm not sure.  The comment in the code above is what the register spec
> says which seems to match the HDMI spec.  I can dig around a bit more
> internally.

OK, though don't waste too much time on that, ALSA has to handle 0 and
255 the same in any case (a patch has just been pushed to sound git to
handle 255). :)

-- 
Anssi Hannula

[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

2013-11-11 Thread Alex Deucher 
On Fri, Nov 8, 2013 at 6:24 AM, Anssi Hannula  wrote:
> 18.10.2013 23:41, Alex Deucher kirjoitti:
>> Needed by the hda driver to properly set up synchronization
>> on the audio side.
>>
>> Signed-off-by: Alex Deucher 
>> ---
>>  drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 
>> 
>>  drivers/gpu/drm/radeon/evergreend.h | 38 
>> +
>>  2 files changed, 75 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
>> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> index 5fbe486..abdc893 100644
>> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> [...]
>> + if (connector->latency_present[0])
>> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
>> + AUDIO_LIPSYNC(connector->audio_latency[0]);
>> + else
>> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
>> + }
>> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> [...]
>> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
>> +#   define VIDEO_LIPSYNC(x)   (((x) & 0xff) << 
>> 0)
>> +#   define AUDIO_LIPSYNC(x)   (((x) & 0xff) << 
>> 8)
>> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
>> + * 0   = invalid
>> + * x   = legal delay value
>> + * 255 = sync not supported
>> + */
>
> Hmm, AMD_HDA_verbs_v2.pdf says that:
> 0  = unknown latency
>
> HDMI spec 1.4 says that:
> 0  = not valid or unknown latency
> 1..251 = valid delay value
> 255= video not supported / audio not supported
>
> Are you sure you shouldn't use 0 instead for unknown (no latency_present)?

I'm not sure.  The comment in the code above is what the register spec
says which seems to match the HDMI spec.  I can dig around a bit more
internally.

Alex

[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

2013-11-08 Thread Anssi Hannula 
18.10.2013 23:41, Alex Deucher kirjoitti:
> Needed by the hda driver to properly set up synchronization
> on the audio side.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 
>  drivers/gpu/drm/radeon/evergreend.h | 38 
> +
>  2 files changed, 75 insertions(+)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
[...]
> + if (connector->latency_present[0])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> + AUDIO_LIPSYNC(connector->audio_latency[0]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + }
> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
[...]
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
> +#   define VIDEO_LIPSYNC(x)   (((x) & 0xff) << 0)
> +#   define AUDIO_LIPSYNC(x)   (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0   = invalid
> + * x   = legal delay value
> + * 255 = sync not supported
> + */

Hmm, AMD_HDA_verbs_v2.pdf says that:
0  = unknown latency

HDMI spec 1.4 says that:
0  = not valid or unknown latency
1..251 = valid delay value
255= video not supported / audio not supported

Are you sure you shouldn't use 0 instead for unknown (no latency_present)?

Not sure this matters much, though, since the only consumer here is ALSA
which we can write however we wish (and it is missing handling for 255
since it was missing from AMD_HDA_verbs_v2.pdf, but I'll add it in any
case since it is mentioned in HDMI specs).

[...]

-- 
Anssi Hannula

[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

2013-10-19 Thread Christian König 
Am 18.10.2013 22:41, schrieb Alex Deucher:
> Needed by the hda driver to properly set up synchronization
> on the audio side.
>
> Signed-off-by: Alex Deucher 

For both: Reviewed-by: Christian K?nig 

> ---
>   drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 
> 
>   drivers/gpu/drm/radeon/evergreend.h | 38 
> +
>   2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder 
> *encoder, uint32_t cloc
>   WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
>   }
>   
> +static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
> +struct drm_display_mode *mode)
> +{
> + struct radeon_device *rdev = encoder->dev->dev_private;
> + struct drm_connector *connector;
> + struct radeon_connector *radeon_connector = NULL;
> + u32 tmp = 0;
> +
> + list_for_each_entry(connector, 
> >dev->mode_config.connector_list, head) {
> + if (connector->encoder == encoder) {
> + radeon_connector = to_radeon_connector(connector);
> + break;
> + }
> + }
> +
> + if (!radeon_connector) {
> + DRM_ERROR("Couldn't find encoder's connector\n");
> + return;
> + }
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (connector->latency_present[1])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
> + AUDIO_LIPSYNC(connector->audio_latency[1]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + } else {
> + if (connector->latency_present[0])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> + AUDIO_LIPSYNC(connector->audio_latency[0]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + }
> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> +}
> +
>   static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
>   {
>   struct radeon_device *rdev = encoder->dev->dev_private;
> @@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, 
> struct drm_display_mode
>   dce6_afmt_write_sad_regs(encoder);
>   } else {
>   evergreen_hdmi_write_sad_regs(encoder);
> + dce4_afmt_write_latency_fields(encoder, mode);
>   }
>   
>   err = drm_hdmi_avi_infoframe_from_display_mode(, mode);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h 
> b/drivers/gpu/drm/radeon/evergreend.h
> index fa81893..11e002a 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -750,6 +750,44 @@
>* bit6 = 192 kHz
>*/
>   
> +#define AZ_CHANNEL_COUNT_CONTROL  0x5fe4
> +#   define HBR_CHANNEL_COUNT(x)   (((x) & 0x7) << 0)
> +#   define COMPRESSED_CHANNEL_COUNT(x)(((x) & 0x7) << 4)
> +/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
> + * 0   = use stream header
> + * 1-7 = channel count - 1
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
> +#   define VIDEO_LIPSYNC(x)   (((x) & 0xff) << 0)
> +#   define AUDIO_LIPSYNC(x)   (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0   = invalid
> + * x   = legal delay value
> + * 255 = sync not supported
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
> +#   define HBR_CAPABLE(1 << 0) /* 
> enabled by default */
> +
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
> +#   define DISPLAY0_TYPE(x)   (((x) & 0x3) << 0)
> +#   define DISPLAY_TYPE_NONE   0
> +#   define DISPLAY_TYPE_HDMI   1
> +#   define DISPLAY_TYPE_DP 2
> +#   define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
> +#   define DISPLAY1_TYPE(x)   (((x) & 0x3) << 8)
> +#   define DISPLAY1_ID(x) (((x) & 0x3f) << 
> 10)
> +#   define DISPLAY2_TYPE(x)   (((x) & 0x3) << 16)
> +#   define DISPLAY2_ID(x) (((x) & 0x3f) << 
> 18)
> +#   define DISPLAY3_TYPE(x)   (((x) & 0x3) << 24)
> +#   define DISPLAY3_ID(x) (((x) & 0x3f) << 
> 26)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
> +#   define DISPLAY4_TYPE(x)   (((x)

[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

2013-10-19 Thread Anssi Hannula 
18.10.2013 23:41, Alex Deucher kirjoitti:
> Needed by the hda driver to properly set up synchronization
> on the audio side.

For the record, the ALSA hda driver does not actually do anything with
these values yet (and my work-in-progress doesn't change that), except
show them in ELD information.

This might change in the future of course :)


> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 
>  drivers/gpu/drm/radeon/evergreend.h | 38 
> +
>  2 files changed, 75 insertions(+)
> 
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder 
> *encoder, uint32_t cloc
>   WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
>  }
>  
> +static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
> +struct drm_display_mode *mode)
> +{
> + struct radeon_device *rdev = encoder->dev->dev_private;
> + struct drm_connector *connector;
> + struct radeon_connector *radeon_connector = NULL;
> + u32 tmp = 0;
> +
> + list_for_each_entry(connector, 
> >dev->mode_config.connector_list, head) {
> + if (connector->encoder == encoder) {
> + radeon_connector = to_radeon_connector(connector);
> + break;
> + }
> + }
> +
> + if (!radeon_connector) {
> + DRM_ERROR("Couldn't find encoder's connector\n");
> + return;
> + }
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (connector->latency_present[1])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
> + AUDIO_LIPSYNC(connector->audio_latency[1]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + } else {
> + if (connector->latency_present[0])
> + tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> + AUDIO_LIPSYNC(connector->audio_latency[0]);
> + else
> + tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> + }
> + WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> +}
> +
>  static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
>  {
>   struct radeon_device *rdev = encoder->dev->dev_private;
> @@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, 
> struct drm_display_mode
>   dce6_afmt_write_sad_regs(encoder);
>   } else {
>   evergreen_hdmi_write_sad_regs(encoder);
> + dce4_afmt_write_latency_fields(encoder, mode);
>   }
>  
>   err = drm_hdmi_avi_infoframe_from_display_mode(, mode);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h 
> b/drivers/gpu/drm/radeon/evergreend.h
> index fa81893..11e002a 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -750,6 +750,44 @@
>   * bit6 = 192 kHz
>   */
>  
> +#define AZ_CHANNEL_COUNT_CONTROL  0x5fe4
> +#   define HBR_CHANNEL_COUNT(x)   (((x) & 0x7) << 0)
> +#   define COMPRESSED_CHANNEL_COUNT(x)(((x) & 0x7) << 4)
> +/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
> + * 0   = use stream header
> + * 1-7 = channel count - 1
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
> +#   define VIDEO_LIPSYNC(x)   (((x) & 0xff) << 0)
> +#   define AUDIO_LIPSYNC(x)   (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0   = invalid
> + * x   = legal delay value
> + * 255 = sync not supported
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
> +#   define HBR_CAPABLE(1 << 0) /* 
> enabled by default */
> +
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
> +#   define DISPLAY0_TYPE(x)   (((x) & 0x3) << 0)
> +#   define DISPLAY_TYPE_NONE   0
> +#   define DISPLAY_TYPE_HDMI   1
> +#   define DISPLAY_TYPE_DP 2
> +#   define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
> +#   define DISPLAY1_TYPE(x)   (((x) & 0x3) << 8)
> +#   define DISPLAY1_ID(x) (((x) & 0x3f) << 
> 10)
> +#   define DISPLAY2_TYPE(x)   (((x) & 0x3) << 16)
> +#   define DISPLAY2_ID(x) (((x) & 0x3f) << 
> 18)
> +#   define DISPLAY3_TYPE(x)   (((x) & 0x3) << 24)
> +#   define DISPLAY3_ID(x)

[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

2013-10-18 Thread Alex Deucher 
Needed by the hda driver to properly set up synchronization
on the audio side.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 
 drivers/gpu/drm/radeon/evergreend.h | 38 +
 2 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c 
b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 5fbe486..abdc893 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder 
*encoder, uint32_t cloc
WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
 }

+static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
+  struct drm_display_mode *mode)
+{
+   struct radeon_device *rdev = encoder->dev->dev_private;
+   struct drm_connector *connector;
+   struct radeon_connector *radeon_connector = NULL;
+   u32 tmp = 0;
+
+   list_for_each_entry(connector, 
>dev->mode_config.connector_list, head) {
+   if (connector->encoder == encoder) {
+   radeon_connector = to_radeon_connector(connector);
+   break;
+   }
+   }
+
+   if (!radeon_connector) {
+   DRM_ERROR("Couldn't find encoder's connector\n");
+   return;
+   }
+
+   if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+   if (connector->latency_present[1])
+   tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
+   AUDIO_LIPSYNC(connector->audio_latency[1]);
+   else
+   tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
+   } else {
+   if (connector->latency_present[0])
+   tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
+   AUDIO_LIPSYNC(connector->audio_latency[0]);
+   else
+   tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
+   }
+   WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
+}
+
 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
 {
struct radeon_device *rdev = encoder->dev->dev_private;
@@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, 
struct drm_display_mode
dce6_afmt_write_sad_regs(encoder);
} else {
evergreen_hdmi_write_sad_regs(encoder);
+   dce4_afmt_write_latency_fields(encoder, mode);
}

err = drm_hdmi_avi_infoframe_from_display_mode(, mode);
diff --git a/drivers/gpu/drm/radeon/evergreend.h 
b/drivers/gpu/drm/radeon/evergreend.h
index fa81893..11e002a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -750,6 +750,44 @@
  * bit6 = 192 kHz
  */

+#define AZ_CHANNEL_COUNT_CONTROL  0x5fe4
+#   define HBR_CHANNEL_COUNT(x)   (((x) & 0x7) << 0)
+#   define COMPRESSED_CHANNEL_COUNT(x)(((x) & 0x7) << 4)
+/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
+ * 0   = use stream header
+ * 1-7 = channel count - 1
+ */
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
+#   define VIDEO_LIPSYNC(x)   (((x) & 0xff) << 0)
+#   define AUDIO_LIPSYNC(x)   (((x) & 0xff) << 8)
+/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
+ * 0   = invalid
+ * x   = legal delay value
+ * 255 = sync not supported
+ */
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
+#   define HBR_CAPABLE(1 << 0) /* enabled 
by default */
+
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
+#   define DISPLAY0_TYPE(x)   (((x) & 0x3) << 0)
+#   define DISPLAY_TYPE_NONE   0
+#   define DISPLAY_TYPE_HDMI   1
+#   define DISPLAY_TYPE_DP 2
+#   define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
+#   define DISPLAY1_TYPE(x)   (((x) & 0x3) << 8)
+#   define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
+#   define DISPLAY2_TYPE(x)   (((x) & 0x3) << 16)
+#   define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
+#   define DISPLAY3_TYPE(x)   (((x) & 0x3) << 24)
+#   define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
+#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
+#   define DISPLAY4_TYPE(x)   (((x) & 0x3) << 0)
+#   define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
+#   define DISPLAY5_TYPE(x)   (((x) & 0x3) << 8)
+#   define DISPLAY5_ID(x) (((x) & 0x3f) << 10)