Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
On 21/05/2020 12:47, Bibby Hsieh wrote:
> On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
>> On 14/02/2020 11:06, Matthias Brugger wrote:
>>>
>>>
>>> On 14/02/2020 05:49, Bibby Hsieh wrote:
In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
Signed-off-by: Bibby Hsieh
Signed-off-by: Yongqiang Niu
---
>>>
>>> For the next time please provide some context on which patches this are
>>> based
>>> on. Bet below the '---' with a link.
>>>
>>> For this time, on which patch/series is this based? :)
>>
>> Bibby can you please help and rebase the patch against my for-next branch
>> [1].
>> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are
>> really
>> late, but we could try :)
>
> Hi, Matthias,
>
> NP, but this patch[1] is depends on another patch [2].
> Should I rebase them together into your for-next branch?
>
I see and [2] one depends on the scpsys driver.
Then maybe better wait until we have the scpsys driver accepted.
Regards,
Matthias
> [1] https://patchwork.kernel.org/patch/11385863/
> [2] https://patchwork.kernel.org/patch/11316277/
>
> Bibby
>
>>
>> Thanks!
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
>>>
>>> Thanks,
>>> Matthias
>>>
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include "mt8183-pinfunc.h"
/ {
@@ -664,6 +665,9 @@
reg = <0 0x1400 0 0x1000>;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
+ mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
+ < 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0
0x1000>;
};
ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_OVL0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x8000
0x1000>;
};
ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_OVL0_2L>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x9000
0x1000>;
};
ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_OVL1_2L>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xa000
0x1000>;
};
rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_RDMA0>;
mediatek,rdma_fifo_size = <5120>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xb000
0x1000>;
};
rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_RDMA1>;
mediatek,rdma_fifo_size = <2048>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xc000
0x1000>;
};
color0: color@1400e000 {
@@ -715,6 +724,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xe000
0x1000>;
};
ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xf000
0x1000>;
};
aal0: aal@1401 {
@@ -732,6 +743,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_AAL0>;
+
Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
On Thu, 2020-05-21 at 12:10 +0200, Matthias Brugger wrote:
> On 14/02/2020 11:06, Matthias Brugger wrote:
> >
> >
> > On 14/02/2020 05:49, Bibby Hsieh wrote:
> >> In order to use GCE function, we need add some information
> >> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
> >>
> >> Signed-off-by: Bibby Hsieh
> >> Signed-off-by: Yongqiang Niu
> >> ---
> >
> > For the next time please provide some context on which patches this are
> > based
> > on. Bet below the '---' with a link.
> >
> > For this time, on which patch/series is this based? :)
>
> Bibby can you please help and rebase the patch against my for-next branch [1].
> I'm then happy to queue it. Not sure if we can make it for v5.8 as we are
> really
> late, but we could try :)
Hi, Matthias,
NP, but this patch[1] is depends on another patch [2].
Should I rebase them together into your for-next branch?
[1] https://patchwork.kernel.org/patch/11385863/
[2] https://patchwork.kernel.org/patch/11316277/
Bibby
>
> Thanks!
> Matthias
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>
> >
> > Thanks,
> > Matthias
> >
> >> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16
> >> 1 file changed, 16 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> index be4428c92f35..8b522b039a37 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >> @@ -9,6 +9,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >> #include "mt8183-pinfunc.h"
> >>
> >> / {
> >> @@ -664,6 +665,9 @@
> >>reg = <0 0x1400 0 0x1000>;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>#clock-cells = <1>;
> >> + mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
> >> + < 1 CMDQ_THR_PRIO_HIGHEST>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0
> >> 0x1000>;
> >>};
> >>
> >>ovl0: ovl@14008000 {
> >> @@ -672,6 +676,7 @@
> >>interrupts = ;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_OVL0>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0x8000
> >> 0x1000>;
> >>};
> >>
> >>ovl_2l0: ovl@14009000 {
> >> @@ -680,6 +685,7 @@
> >>interrupts = ;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_OVL0_2L>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0x9000
> >> 0x1000>;
> >>};
> >>
> >>ovl_2l1: ovl@1400a000 {
> >> @@ -688,6 +694,7 @@
> >>interrupts = ;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_OVL1_2L>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0xa000
> >> 0x1000>;
> >>};
> >>
> >>rdma0: rdma@1400b000 {
> >> @@ -697,6 +704,7 @@
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_RDMA0>;
> >>mediatek,rdma_fifo_size = <5120>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0xb000
> >> 0x1000>;
> >>};
> >>
> >>rdma1: rdma@1400c000 {
> >> @@ -706,6 +714,7 @@
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_RDMA1>;
> >>mediatek,rdma_fifo_size = <2048>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0xc000
> >> 0x1000>;
> >>};
> >>
> >>color0: color@1400e000 {
> >> @@ -715,6 +724,7 @@
> >>interrupts = ;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_COLOR0>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0xe000
> >> 0x1000>;
> >>};
> >>
> >>ccorr0: ccorr@1400f000 {
> >> @@ -723,6 +733,7 @@
> >>interrupts = ;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_CCORR0>;
> >> + mediatek,gce-client-reg = < SUBSYS_1400 0xf000
> >> 0x1000>;
> >>};
> >>
> >>aal0: aal@1401 {
> >> @@ -732,6 +743,7 @@
> >>interrupts = ;
> >>power-domains = < MT8183_POWER_DOMAIN_DISP>;
> >>clocks = < CLK_MM_DISP_AAL0>;
> >> + mediatek,gce-client-reg = < SUBSYS_1401 0
> >> 0x1000>;
> >>};
> >>
> >>gamma0: gamma@14011000 {
> >> @@ -741,6 +753,7 @@
> >>interrupts = ;
>
Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
On 14/02/2020 11:06, Matthias Brugger wrote:
>
>
> On 14/02/2020 05:49, Bibby Hsieh wrote:
>> In order to use GCE function, we need add some information
>> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>>
>> Signed-off-by: Bibby Hsieh
>> Signed-off-by: Yongqiang Niu
>> ---
>
> For the next time please provide some context on which patches this are based
> on. Bet below the '---' with a link.
>
> For this time, on which patch/series is this based? :)
Bibby can you please help and rebase the patch against my for-next branch [1].
I'm then happy to queue it. Not sure if we can make it for v5.8 as we are really
late, but we could try :)
Thanks!
Matthias
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>
> Thanks,
> Matthias
>
>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index be4428c92f35..8b522b039a37 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -9,6 +9,7 @@
>> #include
>> #include
>> #include
>> +#include
>> #include "mt8183-pinfunc.h"
>>
>> / {
>> @@ -664,6 +665,9 @@
>> reg = <0 0x1400 0 0x1000>;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> #clock-cells = <1>;
>> +mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
>> + < 1 CMDQ_THR_PRIO_HIGHEST>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0
>> 0x1000>;
>> };
>>
>> ovl0: ovl@14008000 {
>> @@ -672,6 +676,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_OVL0>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0x8000
>> 0x1000>;
>> };
>>
>> ovl_2l0: ovl@14009000 {
>> @@ -680,6 +685,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_OVL0_2L>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0x9000
>> 0x1000>;
>> };
>>
>> ovl_2l1: ovl@1400a000 {
>> @@ -688,6 +694,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_OVL1_2L>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0xa000
>> 0x1000>;
>> };
>>
>> rdma0: rdma@1400b000 {
>> @@ -697,6 +704,7 @@
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_RDMA0>;
>> mediatek,rdma_fifo_size = <5120>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0xb000
>> 0x1000>;
>> };
>>
>> rdma1: rdma@1400c000 {
>> @@ -706,6 +714,7 @@
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_RDMA1>;
>> mediatek,rdma_fifo_size = <2048>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0xc000
>> 0x1000>;
>> };
>>
>> color0: color@1400e000 {
>> @@ -715,6 +724,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_COLOR0>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0xe000
>> 0x1000>;
>> };
>>
>> ccorr0: ccorr@1400f000 {
>> @@ -723,6 +733,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_CCORR0>;
>> +mediatek,gce-client-reg = < SUBSYS_1400 0xf000
>> 0x1000>;
>> };
>>
>> aal0: aal@1401 {
>> @@ -732,6 +743,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_AAL0>;
>> +mediatek,gce-client-reg = < SUBSYS_1401 0
>> 0x1000>;
>> };
>>
>> gamma0: gamma@14011000 {
>> @@ -741,6 +753,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = < CLK_MM_DISP_GAMMA0>;
>> +mediatek,gce-client-reg = < SUBSYS_1401 0x1000
>> 0x1000>;
>> };
>>
>> dither0: dither@14012000 {
>> @@ -749,6 +762,7 @@
>> interrupts = ;
>> power-domains = < MT8183_POWER_DOMAIN_DISP>;
>> clocks = <
Re: [PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
On 14/02/2020 05:49, Bibby Hsieh wrote:
> In order to use GCE function, we need add some information
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
> Signed-off-by: Bibby Hsieh
> Signed-off-by: Yongqiang Niu
> ---
For the next time please provide some context on which patches this are based
on. Bet below the '---' with a link.
For this time, on which patch/series is this based? :)
Thanks,
Matthias
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index be4428c92f35..8b522b039a37 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -664,6 +665,9 @@
> reg = <0 0x1400 0 0x1000>;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> #clock-cells = <1>;
> + mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
> + < 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0
> 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -672,6 +676,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_OVL0>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0x8000
> 0x1000>;
> };
>
> ovl_2l0: ovl@14009000 {
> @@ -680,6 +685,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_OVL0_2L>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0x9000
> 0x1000>;
> };
>
> ovl_2l1: ovl@1400a000 {
> @@ -688,6 +694,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_OVL1_2L>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xa000
> 0x1000>;
> };
>
> rdma0: rdma@1400b000 {
> @@ -697,6 +704,7 @@
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_RDMA0>;
> mediatek,rdma_fifo_size = <5120>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xb000
> 0x1000>;
> };
>
> rdma1: rdma@1400c000 {
> @@ -706,6 +714,7 @@
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_RDMA1>;
> mediatek,rdma_fifo_size = <2048>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xc000
> 0x1000>;
> };
>
> color0: color@1400e000 {
> @@ -715,6 +724,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xe000
> 0x1000>;
> };
>
> ccorr0: ccorr@1400f000 {
> @@ -723,6 +733,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xf000
> 0x1000>;
> };
>
> aal0: aal@1401 {
> @@ -732,6 +743,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = < SUBSYS_1401 0
> 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -741,6 +753,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = < SUBSYS_1401 0x1000
> 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -749,6 +762,7 @@
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = < SUBSYS_1401 0x2000
> 0x1000>;
> };
>
> mutex: mutex@14016000 {
> @@ -756,6 +770,8 @@
> reg = <0 0x14016000 0 0x1000>;
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> + mediatek,gce-events = ,
> +
[PATCH 1/3] arm64: dts: mt8183: Add gce setting in display node
In order to use GCE function, we need add some information
into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
Signed-off-by: Bibby Hsieh
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index be4428c92f35..8b522b039a37 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include "mt8183-pinfunc.h"
/ {
@@ -664,6 +665,9 @@
reg = <0 0x1400 0 0x1000>;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
+ mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
+< 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0
0x1000>;
};
ovl0: ovl@14008000 {
@@ -672,6 +676,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_OVL0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x8000
0x1000>;
};
ovl_2l0: ovl@14009000 {
@@ -680,6 +685,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_OVL0_2L>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x9000
0x1000>;
};
ovl_2l1: ovl@1400a000 {
@@ -688,6 +694,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_OVL1_2L>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xa000
0x1000>;
};
rdma0: rdma@1400b000 {
@@ -697,6 +704,7 @@
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_RDMA0>;
mediatek,rdma_fifo_size = <5120>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xb000
0x1000>;
};
rdma1: rdma@1400c000 {
@@ -706,6 +714,7 @@
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_RDMA1>;
mediatek,rdma_fifo_size = <2048>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xc000
0x1000>;
};
color0: color@1400e000 {
@@ -715,6 +724,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xe000
0x1000>;
};
ccorr0: ccorr@1400f000 {
@@ -723,6 +733,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0xf000
0x1000>;
};
aal0: aal@1401 {
@@ -732,6 +743,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = < SUBSYS_1401 0
0x1000>;
};
gamma0: gamma@14011000 {
@@ -741,6 +753,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = < SUBSYS_1401 0x1000
0x1000>;
};
dither0: dither@14012000 {
@@ -749,6 +762,7 @@
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
clocks = < CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = < SUBSYS_1401 0x2000
0x1000>;
};
mutex: mutex@14016000 {
@@ -756,6 +770,8 @@
reg = <0 0x14016000 0 0x1000>;
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-events = ,
+ ;
};
smi_common: smi@14019000 {
--
2.18.0
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