Re: [PATCH 1/3] drm/msm/dpu: fix DSC for DSI video mode
On Fri, 29 Mar 2024 at 04:47, Jun Nie wrote: > > Dmitry Baryshkov 于2024年3月28日周四 23:05写道： > > > > On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote: > > > > > > Fix DSC timing and control configurations in DPU for DSI video mode. > > > Only compression ratio 3:1 is handled and tested. > > > > > > This patch is modified from patchs of Jonathan Marek. > > > > > > Signed-off-by: Jun Nie > > > > This almost looks like a joke, except it isn't the 1st of April yet. > > The patch lacks proper Author / Sign-off tags from Jonathan. > > This is pretty close to copyright infringement. I'm sorry, but I'd > > have to ask you to abstain from sending patches w/o prior internal > > review. > > Thanks for pointing me the previous version. I am not aware of it actually. > The only version I knew is from internal repo. It is my fault. I see the > slides > says that Jonathan does not want to disturbed, so only his name is > mentioned in the commit message. > > What's the patch set status? I do not see it in mainline yet. If it is > in pipeline, > I can just forget the DPU side change. See https://patchwork.freedesktop.org/series/126430/ Jonathan posted the patches, but he didn't seem to be interested in following up the review feedback. > > Thanks! > Jun > > > > > > --- > > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > > > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- > > > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 + > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +++- > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + > > > drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + > > > drivers/gpu/drm/msm/dsi/dsi_host.c| 48 +++ > > > include/drm/display/drm_dsc.h | 4 ++ > > > > Ok. The feedback for the original patchset [1] was that it should be > > split logically. Instead you pile everything together into a single > > patch. This is a complete no-go. > > > > Also, this patchset lacks changelog in comparison to the previous > > patchseris. I don't think I'll continue the review of this patch. > > Please rework it properly and add corresponding changelog. > > > > [1] https://patchwork.freedesktop.org/patch/567518/?series=126430&rev=1 > > > > > 8 files changed, 56 insertions(+), 24 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > > > index 6a4b489d44e5..c1b9da06dde2 100644 > > > > -- > > With best wishes > > Dmitry -- With best wishes Dmitry
Re: [PATCH 1/3] drm/msm/dpu: fix DSC for DSI video mode
Dmitry Baryshkov 于2024年3月28日周四 23:05写道： > > On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote: > > > > Fix DSC timing and control configurations in DPU for DSI video mode. > > Only compression ratio 3:1 is handled and tested. > > > > This patch is modified from patchs of Jonathan Marek. > > > > Signed-off-by: Jun Nie > > This almost looks like a joke, except it isn't the 1st of April yet. > The patch lacks proper Author / Sign-off tags from Jonathan. > This is pretty close to copyright infringement. I'm sorry, but I'd > have to ask you to abstain from sending patches w/o prior internal > review. Thanks for pointing me the previous version. I am not aware of it actually. The only version I knew is from internal repo. It is my fault. I see the slides says that Jonathan does not want to disturbed, so only his name is mentioned in the commit message. What's the patch set status? I do not see it in mainline yet. If it is in pipeline, I can just forget the DPU side change. Thanks! Jun > > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- > > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 + > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +++- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + > > drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + > > drivers/gpu/drm/msm/dsi/dsi_host.c| 48 +++ > > include/drm/display/drm_dsc.h | 4 ++ > > Ok. The feedback for the original patchset [1] was that it should be > split logically. Instead you pile everything together into a single > patch. This is a complete no-go. > > Also, this patchset lacks changelog in comparison to the previous > patchseris. I don't think I'll continue the review of this patch. > Please rework it properly and add corresponding changelog. > > [1] https://patchwork.freedesktop.org/patch/567518/?series=126430&rev=1 > > > 8 files changed, 56 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > > index 6a4b489d44e5..c1b9da06dde2 100644 > > -- > With best wishes > Dmitry
Re: [PATCH 1/3] drm/msm/dpu: fix DSC for DSI video mode
On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote: > > Fix DSC timing and control configurations in DPU for DSI video mode. > Only compression ratio 3:1 is handled and tested. > > This patch is modified from patchs of Jonathan Marek. > > Signed-off-by: Jun Nie This almost looks like a joke, except it isn't the 1st of April yet. The patch lacks proper Author / Sign-off tags from Jonathan. This is pretty close to copyright infringement. I'm sorry, but I'd have to ask you to abstain from sending patches w/o prior internal review. > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- > .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + > drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + > drivers/gpu/drm/msm/dsi/dsi_host.c| 48 +++ > include/drm/display/drm_dsc.h | 4 ++ Ok. The feedback for the original patchset [1] was that it should be split logically. Instead you pile everything together into a single patch. This is a complete no-go. Also, this patchset lacks changelog in comparison to the previous patchseris. I don't think I'll continue the review of this patch. Please rework it properly and add corresponding changelog. [1] https://patchwork.freedesktop.org/patch/567518/?series=126430&rev=1 > 8 files changed, 56 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 6a4b489d44e5..c1b9da06dde2 100644 -- With best wishes Dmitry
[PATCH 1/3] drm/msm/dpu: fix DSC for DSI video mode
Fix DSC timing and control configurations in DPU for DSI video mode.
Only compression ratio 3:1 is handled and tested.
This patch is modified from patchs of Jonathan Marek.
Signed-off-by: Jun Nie
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 48 +++
include/drm/display/drm_dsc.h | 4 ++
8 files changed, 56 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6a4b489d44e5..c1b9da06dde2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2440,7 +2440,7 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct
drm_encoder *encoder)
return INTF_MODE_NONE;
}
-unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
+unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys
*phys_enc)
{
struct drm_encoder *encoder = phys_enc->parent;
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 993f26343331..5000fa22ad40 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -339,7 +339,7 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
* used for this encoder.
* @phys_enc: Pointer to physical encoder structure
*/
-unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys
*phys_enc);
/**
* dpu_encoder_helper_split_config - split display configuration helper
function
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d0f56c5c4cce..c0ff39450e66 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -102,6 +102,8 @@ static void drm_mode_to_intf_timing_params(
}
timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
+ if (dpu_encoder_helper_get_dsc(phys_enc))
+ timing->dsc_en = true;
/*
* for DP, divide the horizonal parameters by 2 when
@@ -114,6 +116,16 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width = timing->hsync_pulse_width >> 1;
}
+
+ /*
+* for DSI, if compression is enabled, then divide the horizonal active
+* timing parameters by compression ratio.
+*/
+ if (phys_enc->hw_intf->cap->type != INTF_DP && timing->dsc_en) {
+ /* TODO: handle non 3:1 compression ratio, such as 30bpp case */
+ timing->width = timing->width / 3;
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 6bba531d6dc4..e2f6fa542883 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -168,10 +168,18 @@ static void dpu_hw_intf_setup_timing_engine(struct
dpu_hw_intf *ctx,
* video timing. It is recommended to enable it for all cases, except
* if compression is enabled in 1 pixel per clock mode
*/
+ if (!p->dsc_en || p->wide_bus_en)
+ intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
+
if (p->wide_bus_en)
- intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN;
+ intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
+
+ if (p->dsc_en)
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
data_width = p->width;
+ if (p->wide_bus_en && !dp_intf)
+ data_width = p->width >> 1;
hsync_data_start_x = hsync_start_x;
hsync_data_end_x = hsync_start_x + data_width - 1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 0bd57a32144a..b452e3557d10 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params {
u32 hsync_skew;
bool wide_bus_en;
+ bool dsc_en;
};
struct dpu_hw_intf_prog_fetch {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 2a7d980e12c3..f0b3cdc020a1 100644
--- a/driv
