[PATCH 11/11] drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730
Signed-off-by: Christian K?nig
Signed-off-by: Alex Deucher
Reviewed-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c |3 +++
drivers/gpu/drm/radeon/evergreend.h |3 +++
drivers/gpu/drm/radeon/ni.c |3 +++
drivers/gpu/drm/radeon/nid.h|3 +++
drivers/gpu/drm/radeon/rv770.c |5 +
drivers/gpu/drm/radeon/rv770d.h |5 +
drivers/gpu/drm/radeon/si.c |3 +++
drivers/gpu/drm/radeon/sid.h|3 +++
8 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index a6e7186..c6d8017 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev->config.evergreen.max_backends == 1) &&
(rdev->flags & RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/evergreend.h
b/drivers/gpu/drm/radeon/evergreend.h
index 43e7d3f..eabf92a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1033,6 +1033,9 @@
/*
* UVD
*/
+#define UVD_UDEC_ADDR_CONFIG 0xef4c
+#define UVD_UDEC_DB_ADDR_CONFIG0xef50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
#define UVD_RBC_RB_RPTR0xf690
#define UVD_RBC_RB_WPTR0xf694
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ac944f5..9ed0571 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -624,6 +624,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev->config.cayman.max_backends_per_se == 1) &&
(rdev->flags & RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 3731f6c..358187a 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -491,6 +491,9 @@
#define UVD_SEMA_ADDR_LOW 0xEF00
#define UVD_SEMA_ADDR_HIGH 0xEF04
#define UVD_SEMA_CMD 0xEF08
+#define UVD_UDEC_ADDR_CONFIG 0xEF4C
+#define UVD_UDEC_DB_ADDR_CONFIG0xEF50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
#define UVD_RBC_RB_RPTR0xF690
#define UVD_RBC_RB_WPTR0xF694
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 5ccc865..b8f5f44 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0x));
WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0x));
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0x));
+ if (rdev->family == CHIP_RV730) {
+ WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0x));
+ WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0x));
+ WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0x));
+ }
WREG32(CGTS_SYS_TCC_DISABLE, 0);
WREG32(CGTS_TCC_DISABLE, 0);
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 162b177..6a52b20 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -136,6 +136,11 @@
#define DMA_TILING_CONFIG 0x3ec8
#define DMA_TILING_CONFIG2 0xd0b8
+/* RV730 only */
+#define UVD_UDEC_TILING_CONFIG 0xef40
+#define UVD_UDEC_DB_TILING_CONFIG 0xef44
+#define UVD_UDEC_DBW_TILING_CONFIG 0xef48
+
#defineGC_USER_SHADER_PIPE_CONFIG 0x8954
#defineINACTIVE_QD_PIPES(x)((x) <<
8)
#defineINACTIVE_QD_PIPES_MASK
0xFF00
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 472d9fb..34ffbcb 100644
---
[PATCH 11/11] drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730
Signed-off-by: Christian König christian.koe...@amd.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Jerome Glisse jgli...@redhat.com
---
drivers/gpu/drm/radeon/evergreen.c |3 +++
drivers/gpu/drm/radeon/evergreend.h |3 +++
drivers/gpu/drm/radeon/ni.c |3 +++
drivers/gpu/drm/radeon/nid.h|3 +++
drivers/gpu/drm/radeon/rv770.c |5 +
drivers/gpu/drm/radeon/rv770d.h |5 +
drivers/gpu/drm/radeon/si.c |3 +++
drivers/gpu/drm/radeon/sid.h|3 +++
8 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index a6e7186..c6d8017 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev-config.evergreen.max_backends == 1)
(rdev-flags RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/evergreend.h
b/drivers/gpu/drm/radeon/evergreend.h
index 43e7d3f..eabf92a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1033,6 +1033,9 @@
/*
* UVD
*/
+#define UVD_UDEC_ADDR_CONFIG 0xef4c
+#define UVD_UDEC_DB_ADDR_CONFIG0xef50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
#define UVD_RBC_RB_RPTR0xf690
#define UVD_RBC_RB_WPTR0xf694
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ac944f5..9ed0571 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -624,6 +624,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev-config.cayman.max_backends_per_se == 1)
(rdev-flags RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 3731f6c..358187a 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -491,6 +491,9 @@
#define UVD_SEMA_ADDR_LOW 0xEF00
#define UVD_SEMA_ADDR_HIGH 0xEF04
#define UVD_SEMA_CMD 0xEF08
+#define UVD_UDEC_ADDR_CONFIG 0xEF4C
+#define UVD_UDEC_DB_ADDR_CONFIG0xEF50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
#define UVD_RBC_RB_RPTR0xF690
#define UVD_RBC_RB_WPTR0xF694
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 5ccc865..b8f5f44 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32(HDP_TILING_CONFIG, (gb_tiling_config 0x));
WREG32(DMA_TILING_CONFIG, (gb_tiling_config 0x));
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config 0x));
+ if (rdev-family == CHIP_RV730) {
+ WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config 0x));
+ WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config 0x));
+ WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config 0x));
+ }
WREG32(CGTS_SYS_TCC_DISABLE, 0);
WREG32(CGTS_TCC_DISABLE, 0);
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 162b177..6a52b20 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -136,6 +136,11 @@
#define DMA_TILING_CONFIG 0x3ec8
#define DMA_TILING_CONFIG2 0xd0b8
+/* RV730 only */
+#define UVD_UDEC_TILING_CONFIG 0xef40
+#define UVD_UDEC_DB_TILING_CONFIG 0xef44
+#define UVD_UDEC_DBW_TILING_CONFIG 0xef48
+
#defineGC_USER_SHADER_PIPE_CONFIG 0x8954
#defineINACTIVE_QD_PIPES(x)((x)
8)
#defineINACTIVE_QD_PIPES_MASK
0xFF00
diff --git a/drivers/gpu/drm/radeon/si.c
[PATCH 11/11] drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730
Signed-off-by: Christian K?nig
Signed-off-by: Alex Deucher
Reviewed-by: Jerome Glisse
---
drivers/gpu/drm/radeon/evergreen.c |3 +++
drivers/gpu/drm/radeon/evergreend.h |3 +++
drivers/gpu/drm/radeon/ni.c |3 +++
drivers/gpu/drm/radeon/nid.h|3 +++
drivers/gpu/drm/radeon/rv770.c |5 +
drivers/gpu/drm/radeon/rv770d.h |5 +
drivers/gpu/drm/radeon/si.c |3 +++
drivers/gpu/drm/radeon/sid.h|3 +++
8 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index a6e7186..c6d8017 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev->config.evergreen.max_backends == 1) &&
(rdev->flags & RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/evergreend.h
b/drivers/gpu/drm/radeon/evergreend.h
index 43e7d3f..eabf92a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1033,6 +1033,9 @@
/*
* UVD
*/
+#define UVD_UDEC_ADDR_CONFIG 0xef4c
+#define UVD_UDEC_DB_ADDR_CONFIG0xef50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
#define UVD_RBC_RB_RPTR0xf690
#define UVD_RBC_RB_WPTR0xf694
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ac944f5..9ed0571 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -624,6 +624,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev->config.cayman.max_backends_per_se == 1) &&
(rdev->flags & RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 3731f6c..358187a 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -491,6 +491,9 @@
#define UVD_SEMA_ADDR_LOW 0xEF00
#define UVD_SEMA_ADDR_HIGH 0xEF04
#define UVD_SEMA_CMD 0xEF08
+#define UVD_UDEC_ADDR_CONFIG 0xEF4C
+#define UVD_UDEC_DB_ADDR_CONFIG0xEF50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
#define UVD_RBC_RB_RPTR0xF690
#define UVD_RBC_RB_WPTR0xF694
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 5ccc865..b8f5f44 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0x));
WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0x));
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0x));
+ if (rdev->family == CHIP_RV730) {
+ WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0x));
+ WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0x));
+ WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0x));
+ }
WREG32(CGTS_SYS_TCC_DISABLE, 0);
WREG32(CGTS_TCC_DISABLE, 0);
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 162b177..6a52b20 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -136,6 +136,11 @@
#define DMA_TILING_CONFIG 0x3ec8
#define DMA_TILING_CONFIG2 0xd0b8
+/* RV730 only */
+#define UVD_UDEC_TILING_CONFIG 0xef40
+#define UVD_UDEC_DB_TILING_CONFIG 0xef44
+#define UVD_UDEC_DBW_TILING_CONFIG 0xef48
+
#defineGC_USER_SHADER_PIPE_CONFIG 0x8954
#defineINACTIVE_QD_PIPES(x)((x) <<
8)
#defineINACTIVE_QD_PIPES_MASK
0xFF00
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 472d9fb..34ffbcb 100644
---
[PATCH 11/11] drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730
Signed-off-by: Christian König christian.koe...@amd.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Jerome Glisse jgli...@redhat.com
---
drivers/gpu/drm/radeon/evergreen.c |3 +++
drivers/gpu/drm/radeon/evergreend.h |3 +++
drivers/gpu/drm/radeon/ni.c |3 +++
drivers/gpu/drm/radeon/nid.h|3 +++
drivers/gpu/drm/radeon/rv770.c |5 +
drivers/gpu/drm/radeon/rv770d.h |5 +
drivers/gpu/drm/radeon/si.c |3 +++
drivers/gpu/drm/radeon/sid.h|3 +++
8 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index a6e7186..c6d8017 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev-config.evergreen.max_backends == 1)
(rdev-flags RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/evergreend.h
b/drivers/gpu/drm/radeon/evergreend.h
index 43e7d3f..eabf92a 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1033,6 +1033,9 @@
/*
* UVD
*/
+#define UVD_UDEC_ADDR_CONFIG 0xef4c
+#define UVD_UDEC_DB_ADDR_CONFIG0xef50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
#define UVD_RBC_RB_RPTR0xf690
#define UVD_RBC_RB_WPTR0xf694
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ac944f5..9ed0571 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -624,6 +624,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
if ((rdev-config.cayman.max_backends_per_se == 1)
(rdev-flags RADEON_IS_IGP)) {
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 3731f6c..358187a 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -491,6 +491,9 @@
#define UVD_SEMA_ADDR_LOW 0xEF00
#define UVD_SEMA_ADDR_HIGH 0xEF04
#define UVD_SEMA_CMD 0xEF08
+#define UVD_UDEC_ADDR_CONFIG 0xEF4C
+#define UVD_UDEC_DB_ADDR_CONFIG0xEF50
+#define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
#define UVD_RBC_RB_RPTR0xF690
#define UVD_RBC_RB_WPTR0xF694
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 5ccc865..b8f5f44 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32(HDP_TILING_CONFIG, (gb_tiling_config 0x));
WREG32(DMA_TILING_CONFIG, (gb_tiling_config 0x));
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config 0x));
+ if (rdev-family == CHIP_RV730) {
+ WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config 0x));
+ WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config 0x));
+ WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config 0x));
+ }
WREG32(CGTS_SYS_TCC_DISABLE, 0);
WREG32(CGTS_TCC_DISABLE, 0);
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 162b177..6a52b20 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -136,6 +136,11 @@
#define DMA_TILING_CONFIG 0x3ec8
#define DMA_TILING_CONFIG2 0xd0b8
+/* RV730 only */
+#define UVD_UDEC_TILING_CONFIG 0xef40
+#define UVD_UDEC_DB_TILING_CONFIG 0xef44
+#define UVD_UDEC_DBW_TILING_CONFIG 0xef48
+
#defineGC_USER_SHADER_PIPE_CONFIG 0x8954
#defineINACTIVE_QD_PIPES(x)((x)
8)
#defineINACTIVE_QD_PIPES_MASK
0xFF00
diff --git a/drivers/gpu/drm/radeon/si.c
