[PATCH 12/24] radeon/audio: consolidate update_acr() functions
Am 13.01.2015 um 18:46 schrieb Alex Deucher:
> From: Slava Grigorev
>
> Signed-off-by: Slava Grigorev
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/dce3_1_afmt.c| 38 +--
> drivers/gpu/drm/radeon/evergreen_hdmi.c | 46 ++---
> drivers/gpu/drm/radeon/r600_hdmi.c | 117
> +---
> drivers/gpu/drm/radeon/radeon_audio.c | 99 +++
> drivers/gpu/drm/radeon/radeon_audio.h | 3 +
> 5 files changed, 176 insertions(+), 127 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c
> b/drivers/gpu/drm/radeon/dce3_1_afmt.c
> index 0accc5e..678909f 100644
> --- a/drivers/gpu/drm/radeon/dce3_1_afmt.c
> +++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c
> @@ -167,6 +167,38 @@ void dce3_2_audio_set_dto(struct radeon_device *rdev,
> }
> }
>
> +void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
> +const struct radeon_hdmi_acr *acr)
> +{
> +struct drm_device *dev = encoder->dev;
> +struct radeon_device *rdev = dev->dev_private;
> +
> + WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
> +HDMI0_ACR_SOURCE | /* select SW CTS value */
> +HDMI0_ACR_AUTO_SEND);/* allow hw to sent ACR packets when
> required */
> +
> +WREG32_P(HDMI0_ACR_32_0 + offset,
> + HDMI0_ACR_CTS_32(acr->cts_32khz),
> + ~HDMI0_ACR_CTS_32_MASK);
> +WREG32_P(HDMI0_ACR_32_1 + offset,
> + HDMI0_ACR_N_32(acr->n_32khz),
> + ~HDMI0_ACR_N_32_MASK);
> +
> +WREG32_P(HDMI0_ACR_44_0 + offset,
> + HDMI0_ACR_CTS_44(acr->cts_44_1khz),
> + ~HDMI0_ACR_CTS_44_MASK);
> +WREG32_P(HDMI0_ACR_44_1 + offset,
> + HDMI0_ACR_N_44(acr->n_44_1khz),
> + ~HDMI0_ACR_N_44_MASK);
> +
> +WREG32_P(HDMI0_ACR_48_0 + offset,
> + HDMI0_ACR_CTS_48(acr->cts_48khz),
> + ~HDMI0_ACR_CTS_48_MASK);
> +WREG32_P(HDMI0_ACR_48_1 + offset,
> + HDMI0_ACR_N_48(acr->n_48khz),
> + ~HDMI0_ACR_N_48_MASK);
Looks like spaces were used for indentation instead of tabs.
Christian.
> +}
> +
> /*
>* update the info frames with the data from the current display mode
>*/
> @@ -220,10 +252,6 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder,
> struct drm_display_mode *m
> radeon_audio_write_sad_regs(encoder);
> }
>
> - WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
> -HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw
> CTS works on all families */
> -HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when
> required */
> -
> WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
> HDMI0_NULL_SEND | /* send null packets when required */
> HDMI0_GC_SEND | /* send general control packets */
> @@ -255,7 +283,7 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder,
> struct drm_display_mode *m
> }
>
> radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
> - r600_hdmi_update_ACR(encoder, mode->clock);
> + radeon_audio_update_acr(encoder, mode->clock);
>
> /* it's unknown what these bits do excatly, but it's indeed quite
> useful for debugging */
> WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FF);
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index f2896e5..c2abab4 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -64,26 +64,34 @@ void dce4_audio_enable(struct radeon_device *rdev,
> WREG32(AZ_HOT_PLUG_CONTROL, tmp);
> }
>
> -/*
> - * update the N and CTS parameters for a given pixel clock rate
> - */
> -static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t
> clock)
> +void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
> + const struct radeon_hdmi_acr *acr)
> {
> struct drm_device *dev = encoder->dev;
> struct radeon_device *rdev = dev->dev_private;
> - struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
> - struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
> - struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
> - uint32_t offset = dig->afmt->offset;
> + int bpc = 8;
> +
> + if (encoder->crtc) {
> + struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
> + bpc = radeon_crtc->bpc;
> + }
> +
> + if (bpc > 8)
> + WREG32(HDMI_ACR_PACKET_CONTROL + offset,
> +HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets
> when required */
> + else
> + WREG32(HDMI_ACR_PACKET_CONTROL + offset,
> +HDMI_ACR_SOURCE | /* select SW CTS value */
> +HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets
> when required */
>
> - WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
> - WREG32(HDMI_ACR_32_1 + offs
[PATCH 12/24] radeon/audio: consolidate update_acr() functions
From: Slava Grigorev
Signed-off-by: Slava Grigorev
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/dce3_1_afmt.c| 38 +--
drivers/gpu/drm/radeon/evergreen_hdmi.c | 46 ++---
drivers/gpu/drm/radeon/r600_hdmi.c | 117 +---
drivers/gpu/drm/radeon/radeon_audio.c | 99 +++
drivers/gpu/drm/radeon/radeon_audio.h | 3 +
5 files changed, 176 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/radeon/dce3_1_afmt.c
b/drivers/gpu/drm/radeon/dce3_1_afmt.c
index 0accc5e..678909f 100644
--- a/drivers/gpu/drm/radeon/dce3_1_afmt.c
+++ b/drivers/gpu/drm/radeon/dce3_1_afmt.c
@@ -167,6 +167,38 @@ void dce3_2_audio_set_dto(struct radeon_device *rdev,
}
}
+void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,
+const struct radeon_hdmi_acr *acr)
+{
+struct drm_device *dev = encoder->dev;
+struct radeon_device *rdev = dev->dev_private;
+
+ WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
+ HDMI0_ACR_SOURCE | /* select SW CTS value */
+ HDMI0_ACR_AUTO_SEND);/* allow hw to sent ACR packets when
required */
+
+WREG32_P(HDMI0_ACR_32_0 + offset,
+ HDMI0_ACR_CTS_32(acr->cts_32khz),
+ ~HDMI0_ACR_CTS_32_MASK);
+WREG32_P(HDMI0_ACR_32_1 + offset,
+ HDMI0_ACR_N_32(acr->n_32khz),
+ ~HDMI0_ACR_N_32_MASK);
+
+WREG32_P(HDMI0_ACR_44_0 + offset,
+ HDMI0_ACR_CTS_44(acr->cts_44_1khz),
+ ~HDMI0_ACR_CTS_44_MASK);
+WREG32_P(HDMI0_ACR_44_1 + offset,
+ HDMI0_ACR_N_44(acr->n_44_1khz),
+ ~HDMI0_ACR_N_44_MASK);
+
+WREG32_P(HDMI0_ACR_48_0 + offset,
+ HDMI0_ACR_CTS_48(acr->cts_48khz),
+ ~HDMI0_ACR_CTS_48_MASK);
+WREG32_P(HDMI0_ACR_48_1 + offset,
+ HDMI0_ACR_N_48(acr->n_48khz),
+ ~HDMI0_ACR_N_48_MASK);
+}
+
/*
* update the info frames with the data from the current display mode
*/
@@ -220,10 +252,6 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder,
struct drm_display_mode *m
radeon_audio_write_sad_regs(encoder);
}
- WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
- HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw
CTS works on all families */
- HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when
required */
-
WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
HDMI0_NULL_SEND | /* send null packets when required */
HDMI0_GC_SEND | /* send general control packets */
@@ -255,7 +283,7 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder,
struct drm_display_mode *m
}
radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
- r600_hdmi_update_ACR(encoder, mode->clock);
+ radeon_audio_update_acr(encoder, mode->clock);
/* it's unknown what these bits do excatly, but it's indeed quite
useful for debugging */
WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FF);
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c
b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index f2896e5..c2abab4 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -64,26 +64,34 @@ void dce4_audio_enable(struct radeon_device *rdev,
WREG32(AZ_HOT_PLUG_CONTROL, tmp);
}
-/*
- * update the N and CTS parameters for a given pixel clock rate
- */
-static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t
clock)
+void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
+ const struct radeon_hdmi_acr *acr)
{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
- struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
- struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
- struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
- uint32_t offset = dig->afmt->offset;
+ int bpc = 8;
+
+ if (encoder->crtc) {
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+ bpc = radeon_crtc->bpc;
+ }
+
+ if (bpc > 8)
+ WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+ HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets
when required */
+ else
+ WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+ HDMI_ACR_SOURCE | /* select SW CTS value */
+ HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets
when required */
- WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
- WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
+ WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));
+ WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);
- WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
- WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
+ WREG32(HDMI_ACR_44_0 + offset,
