[PATCH 14/20] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 191
1 file changed, 126 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index fd321b314f91..f4870c9b0db6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1696,6 +1696,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private
*i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC
limits\n",
+ intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state,
+struct link_config_limits *limits,
+int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by
source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+* For now enable DSC for max link rate, max lane count.
+* Optimize this later for the minimum possible link rate/lane count
+* with DSC enabled for the requested mode.
+*/
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+
pipe_config->port_clock,
+
pipe_config->lane_count,
+
adjusted_mode->crtc_clock,
+
adjusted_mode->crtc_hdisplay,
+
pipe_config->bigjoiner_pipes,
+
pipe_config->output_format,
+pipe_bpp,
+timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp,
output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state
*conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+
conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_db
Re: [PATCH 14/20] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
On Fri, Jul 28, 2023 at 09:41:44AM +0530, Ankit Nautiyal wrote:
> Refactor code to separate functions for eDP and DP for computing
> pipe_bpp/compressed bpp when DSC is involved.
>
> This will help to optimize the link configuration for DP later.
>
> v2: Fix checkpatch warning.
>
> Signed-off-by: Ankit Nautiyal
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 191
> 1 file changed, 126 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6228cfc44055..c87c3836966c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1699,6 +1699,115 @@ bool is_dsc_pipe_bpp_sufficient(struct
> drm_i915_private *i915, int pipe_bpp)
> return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
> }
>
> +static
> +int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + int forced_bpp;
> +
> + if (!intel_dp->force_dsc_bpc)
> + return 0;
> +
> + forced_bpp = intel_dp->force_dsc_bpc * 3;
> +
> + if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
> + drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
> intel_dp->force_dsc_bpc);
> + return forced_bpp;
> + }
> +
> + drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC
> limits\n",
> + intel_dp->force_dsc_bpc);
> +
> + return 0;
> +}
> +
> +static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state,
> + struct link_config_limits *limits,
> + int timeslots)
> +{
> + const struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u16 output_bpp, dsc_max_compressed_bpp = 0;
> + int forced_bpp, pipe_bpp;
> +
> + forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
> +
> + if (forced_bpp) {
> + pipe_bpp = forced_bpp;
> + } else {
> + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
> conn_state->max_requested_bpc);
> +
> + if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
> + drm_dbg_kms(&i915->drm,
> + "Computed BPC less than min supported by
> source for DSC\n");
> + return -EINVAL;
> + }
> + }
> + /*
> + * For now enable DSC for max link rate, max lane count.
> + * Optimize this later for the minimum possible link rate/lane count
> + * with DSC enabled for the requested mode.
> + */
> + pipe_config->port_clock = limits->max_rate;
> + pipe_config->lane_count = limits->max_lane_count;
> + dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
> +
> pipe_config->port_clock,
> +
> pipe_config->lane_count,
> +
> adjusted_mode->crtc_clock,
> +
> adjusted_mode->crtc_hdisplay,
> +
> pipe_config->bigjoiner_pipes,
> +
> pipe_config->output_format,
> + pipe_bpp,
> + timeslots);
> + if (!dsc_max_compressed_bpp) {
> + drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
> + return -EINVAL;
> + }
> +
> + output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
> +
> + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp,
> output_bpp);
> +
> + pipe_config->pipe_bpp = pipe_bpp;
> +
> + return 0;
> +}
> +
> +static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state
> *conn_state,
> + struct link_config_limits *limits)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + int pipe_bpp, forced_bpp;
> +
> + forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
> +
> + if (forced_bpp) {
> + pipe_bpp = forced_bpp;
> + } else {
> + /* For eDP use max bpp that can be supported with DSC. */
> + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
>
[PATCH 14/20] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp
Refactor code to separate functions for eDP and DP for computing
pipe_bpp/compressed bpp when DSC is involved.
This will help to optimize the link configuration for DP later.
v2: Fix checkpatch warning.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 191
1 file changed, 126 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 6228cfc44055..c87c3836966c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1699,6 +1699,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private
*i915, int pipe_bpp)
return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3;
}
+static
+int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int forced_bpp;
+
+ if (!intel_dp->force_dsc_bpc)
+ return 0;
+
+ forced_bpp = intel_dp->force_dsc_bpc * 3;
+
+ if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) {
+ drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n",
intel_dp->force_dsc_bpc);
+ return forced_bpp;
+ }
+
+ drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC
limits\n",
+ intel_dp->force_dsc_bpc);
+
+ return 0;
+}
+
+static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+struct intel_crtc_state *pipe_config,
+struct drm_connector_state *conn_state,
+struct link_config_limits *limits,
+int timeslots)
+{
+ const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 output_bpp, dsc_max_compressed_bpp = 0;
+ int forced_bpp, pipe_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
conn_state->max_requested_bpc);
+
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+ "Computed BPC less than min supported by
source for DSC\n");
+ return -EINVAL;
+ }
+ }
+ /*
+* For now enable DSC for max link rate, max lane count.
+* Optimize this later for the minimum possible link rate/lane count
+* with DSC enabled for the requested mode.
+*/
+ pipe_config->port_clock = limits->max_rate;
+ pipe_config->lane_count = limits->max_lane_count;
+ dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915,
+
pipe_config->port_clock,
+
pipe_config->lane_count,
+
adjusted_mode->crtc_clock,
+
adjusted_mode->crtc_hdisplay,
+
pipe_config->bigjoiner_pipes,
+
pipe_config->output_format,
+pipe_bpp,
+timeslots);
+ if (!dsc_max_compressed_bpp) {
+ drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n");
+ return -EINVAL;
+ }
+
+ output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
+
+ pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp,
output_bpp);
+
+ pipe_config->pipe_bpp = pipe_bpp;
+
+ return 0;
+}
+
+static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state
*conn_state,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int pipe_bpp, forced_bpp;
+
+ forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp);
+
+ if (forced_bpp) {
+ pipe_bpp = forced_bpp;
+ } else {
+ /* For eDP use max bpp that can be supported with DSC. */
+ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp,
+
conn_state->max_requested_bpc);
+ if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) {
+ drm_dbg_kms(&i915->drm,
+
