[PATCH 15/15] drm/exynos/fimc: fix source buffer registers
On 08/26/2014 03:35 PM, Andrzej Hajda wrote:
> On 08/26/2014 07:57 AM, Joonyoung Shim wrote:
>> Hi Andrzej,
>>
>> On 08/22/2014 04:52 PM, Andrzej Hajda wrote:
>>> FIMC in default mode of operation uses only one input buffer,
>>> but the driver used also second buffer, as a result only the
>>> first frame was processed correctly. The patch fixes it.
>> I can't understand well, then we don't need to distinguish buf_id in
>> fimc_src_set_addr()?
> Yes. FIMC in default operation mode uses only one input buffer pointer
> which should
> be updated when processing of the previous buffer has been finished.
>
> There exists also ping-pong mode which uses two buffer pointers, as I
> have spotted in
> specs. However I have not seen it was implemented neither in drm,
> neither in camera drivers.
> I will try to implement it later.
OK if operation is no problem, and i think it's better to add comments
about this.
>
> Regards
> Andrzej
>
>>
>>> Signed-off-by: Andrzej Hajda
>>> ---
>>> drivers/gpu/drm/exynos/exynos_drm_fimc.c | 16
>>> 1 file changed, 8 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>>> b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>>> index b20078e..e985253 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>>> @@ -720,24 +720,24 @@ static int fimc_src_set_addr(struct device *dev,
>>> case IPP_BUF_ENQUEUE:
>>> config = >config[EXYNOS_DRM_OPS_SRC];
>>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
>>> - EXYNOS_CIIYSA(buf_id));
>>> + EXYNOS_CIIYSA0);
>>>
>>> if (config->fmt == DRM_FORMAT_YVU420) {
>>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
>>> - EXYNOS_CIICBSA(buf_id));
>>> + EXYNOS_CIICBSA0);
>>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
>>> - EXYNOS_CIICRSA(buf_id));
>>> + EXYNOS_CIICRSA0);
>>> } else {
>>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
>>> - EXYNOS_CIICBSA(buf_id));
>>> + EXYNOS_CIICBSA0);
>>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
>>> - EXYNOS_CIICRSA(buf_id));
>>> + EXYNOS_CIICRSA0);
>>> }
>>> break;
>>> case IPP_BUF_DEQUEUE:
>>> - fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
>>> - fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
>>> - fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
>>> + fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
>>> + fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
>>> + fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
>>> break;
>>> default:
>>> /* bypass */
>>>
>>
>
>
[PATCH 15/15] drm/exynos/fimc: fix source buffer registers
Hi Andrzej,
On 08/22/2014 04:52 PM, Andrzej Hajda wrote:
> FIMC in default mode of operation uses only one input buffer,
> but the driver used also second buffer, as a result only the
> first frame was processed correctly. The patch fixes it.
I can't understand well, then we don't need to distinguish buf_id in
fimc_src_set_addr()?
>
> Signed-off-by: Andrzej Hajda
> ---
> drivers/gpu/drm/exynos/exynos_drm_fimc.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
> b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
> index b20078e..e985253 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
> @@ -720,24 +720,24 @@ static int fimc_src_set_addr(struct device *dev,
> case IPP_BUF_ENQUEUE:
> config = >config[EXYNOS_DRM_OPS_SRC];
> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
> - EXYNOS_CIIYSA(buf_id));
> + EXYNOS_CIIYSA0);
>
> if (config->fmt == DRM_FORMAT_YVU420) {
> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
> - EXYNOS_CIICBSA(buf_id));
> + EXYNOS_CIICBSA0);
> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
> - EXYNOS_CIICRSA(buf_id));
> + EXYNOS_CIICRSA0);
> } else {
> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
> - EXYNOS_CIICBSA(buf_id));
> + EXYNOS_CIICBSA0);
> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
> - EXYNOS_CIICRSA(buf_id));
> + EXYNOS_CIICRSA0);
> }
> break;
> case IPP_BUF_DEQUEUE:
> - fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
> - fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
> - fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
> + fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
> + fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
> + fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
> break;
> default:
> /* bypass */
>
[PATCH 15/15] drm/exynos/fimc: fix source buffer registers
On 08/26/2014 07:57 AM, Joonyoung Shim wrote:
> Hi Andrzej,
>
> On 08/22/2014 04:52 PM, Andrzej Hajda wrote:
>> FIMC in default mode of operation uses only one input buffer,
>> but the driver used also second buffer, as a result only the
>> first frame was processed correctly. The patch fixes it.
> I can't understand well, then we don't need to distinguish buf_id in
> fimc_src_set_addr()?
Yes. FIMC in default operation mode uses only one input buffer pointer
which should
be updated when processing of the previous buffer has been finished.
There exists also ping-pong mode which uses two buffer pointers, as I
have spotted in
specs. However I have not seen it was implemented neither in drm,
neither in camera drivers.
I will try to implement it later.
Regards
Andrzej
>
>> Signed-off-by: Andrzej Hajda
>> ---
>> drivers/gpu/drm/exynos/exynos_drm_fimc.c | 16
>> 1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>> b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>> index b20078e..e985253 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
>> @@ -720,24 +720,24 @@ static int fimc_src_set_addr(struct device *dev,
>> case IPP_BUF_ENQUEUE:
>> config = >config[EXYNOS_DRM_OPS_SRC];
>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
>> -EXYNOS_CIIYSA(buf_id));
>> +EXYNOS_CIIYSA0);
>>
>> if (config->fmt == DRM_FORMAT_YVU420) {
>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
>> -EXYNOS_CIICBSA(buf_id));
>> +EXYNOS_CIICBSA0);
>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
>> -EXYNOS_CIICRSA(buf_id));
>> +EXYNOS_CIICRSA0);
>> } else {
>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
>> -EXYNOS_CIICBSA(buf_id));
>> +EXYNOS_CIICBSA0);
>> fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
>> -EXYNOS_CIICRSA(buf_id));
>> +EXYNOS_CIICRSA0);
>> }
>> break;
>> case IPP_BUF_DEQUEUE:
>> -fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
>> -fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
>> -fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
>> +fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
>> +fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
>> +fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
>> break;
>> default:
>> /* bypass */
>>
>
[PATCH 15/15] drm/exynos/fimc: fix source buffer registers
FIMC in default mode of operation uses only one input buffer,
but the driver used also second buffer, as a result only the
first frame was processed correctly. The patch fixes it.
Signed-off-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index b20078e..e985253 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -720,24 +720,24 @@ static int fimc_src_set_addr(struct device *dev,
case IPP_BUF_ENQUEUE:
config = >config[EXYNOS_DRM_OPS_SRC];
fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
- EXYNOS_CIIYSA(buf_id));
+ EXYNOS_CIIYSA0);
if (config->fmt == DRM_FORMAT_YVU420) {
fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
- EXYNOS_CIICBSA(buf_id));
+ EXYNOS_CIICBSA0);
fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
- EXYNOS_CIICRSA(buf_id));
+ EXYNOS_CIICRSA0);
} else {
fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
- EXYNOS_CIICBSA(buf_id));
+ EXYNOS_CIICBSA0);
fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
- EXYNOS_CIICRSA(buf_id));
+ EXYNOS_CIICRSA0);
}
break;
case IPP_BUF_DEQUEUE:
- fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
- fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
- fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
+ fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
+ fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
+ fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
break;
default:
/* bypass */
--
1.9.1
