Re: [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2
On Wed, Jan 26, 2022 at 03:55:39PM +0100, Sascha Hauer wrote:
> The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
> The binding differs slightly from the existing VOP binding, so add a new
> binding file for it.
>
> Changes since v3:
> - drop redundant _vop suffix from clock names
>
> Signed-off-by: Sascha Hauer
> ---
> .../display/rockchip/rockchip-vop2.yaml | 146 ++
> 1 file changed, 146 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> new file mode 100644
> index ..572cfb307c20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> @@ -0,0 +1,146 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip SoC display controller (VOP2)
> +
> +description:
> + VOP2 (Video Output Processor v2) is the display controller for the Rockchip
> + series of SoCs which transfers the image data from a video memory
> + buffer to an external LCD interface.
> +
> +maintainers:
> + - Sandy Huang
> + - Heiko Stuebner
> +
> +properties:
> + compatible:
> +enum:
> + - rockchip,rk3566-vop
> + - rockchip,rk3568-vop
> +
> + reg:
> +minItems: 1
> +items:
> + - description:
> + Must contain one entry corresponding to the base address and length
> + of the register space.
> + - description:
> + Can optionally contain a second entry corresponding to
> + the CRTC gamma LUT address.
> +
> + interrupts:
> +maxItems: 1
> +description:
> + The VOP interrupt is shared by several interrupt sources, such as
> + frame start (VSYNC), line flag and other status interrupts.
> +
> + clocks:
> +items:
> + - description: Clock for ddr buffer transfer.
> + - description: Clock for the ahb bus to R/W the phy regs.
> + - description: Pixel clock for video port 0.
> + - description: Pixel clock for video port 1.
> + - description: Pixel clock for video port 2.
> +
> + clock-names:
> +items:
> + - const: aclk
> + - const: hclk
> + - const: dclk_vp0
> + - const: dclk_vp1
> + - const: dclk_vp2
> +
> + rockchip,grf:
> +$ref: /schemas/types.yaml#/definitions/phandle
> +description:
> + Phandle to GRF regs used for misc control
> +
> + ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +
> +properties:
> + port@0:
> +$ref: /schemas/graph.yaml#/properties/port
> +description:
> + Output endpoint of VP0
> +
> + port@1:
> +$ref: /schemas/graph.yaml#/properties/port
> +description:
> + Output endpoint of VP1
> +
> + port@2:
> +$ref: /schemas/graph.yaml#/properties/port
> +description:
> + Output endpoint of VP2
> +
> + assigned-clocks: true
> +
> + assigned-clock-rates: true
> +
> + assigned-clock-parents: true
You can drop these. They are implicitly allowed with 'clocks'.
> +
> + iommus:
> +maxItems: 1
> +
> + power-domains:
> +maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +#include
> +#include
> +#include
> +bus {
> +#address-cells = <2>;
> +#size-cells = <2>;
> +vop: vop@fe04 {
> +compatible = "rockchip,rk3568-vop";
> +reg = <0x0 0xfe04 0x0 0x3000>, <0x0 0xfe044000 0x0
> 0x1000>;
> +interrupts = ;
> +clocks = < ACLK_VOP>,
> + < HCLK_VOP>,
> + < DCLK_VOP0>,
> + < DCLK_VOP1>,
> + < DCLK_VOP2>;
> +clock-names = "aclk_vop",
> + "hclk_vop",
> + "dclk_vp0",
> + "dclk_vp1",
> + "dclk_vp2";
> +power-domains = < RK3568_PD_VO>;
> +iommus = <_mmu>;
> +vop_out: ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +vp0: port@0 {
> +reg = <0>;
> +#address-cells = <1>;
> +#size-cells = <0>;
> +};
> +vp1: port@1 {
> +reg = <1>;
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
Re: [PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2
On Wed, 26 Jan 2022 15:55:39 +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Changes since v3: > - drop redundant _vop suffix from clock names > > Signed-off-by: Sascha Hauer > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++ > 1 file changed, 146 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.example.dt.yaml: vop@fe04: clock-names:0: 'aclk' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.example.dt.yaml: vop@fe04: clock-names:1: 'hclk' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1584511 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
[PATCH 17/27] dt-bindings: display: rockchip: Add binding for VOP2
The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
The binding differs slightly from the existing VOP binding, so add a new
binding file for it.
Changes since v3:
- drop redundant _vop suffix from clock names
Signed-off-by: Sascha Hauer
---
.../display/rockchip/rockchip-vop2.yaml | 146 ++
1 file changed, 146 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
diff --git
a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
new file mode 100644
index ..572cfb307c20
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC display controller (VOP2)
+
+description:
+ VOP2 (Video Output Processor v2) is the display controller for the Rockchip
+ series of SoCs which transfers the image data from a video memory
+ buffer to an external LCD interface.
+
+maintainers:
+ - Sandy Huang
+ - Heiko Stuebner
+
+properties:
+ compatible:
+enum:
+ - rockchip,rk3566-vop
+ - rockchip,rk3568-vop
+
+ reg:
+minItems: 1
+items:
+ - description:
+ Must contain one entry corresponding to the base address and length
+ of the register space.
+ - description:
+ Can optionally contain a second entry corresponding to
+ the CRTC gamma LUT address.
+
+ interrupts:
+maxItems: 1
+description:
+ The VOP interrupt is shared by several interrupt sources, such as
+ frame start (VSYNC), line flag and other status interrupts.
+
+ clocks:
+items:
+ - description: Clock for ddr buffer transfer.
+ - description: Clock for the ahb bus to R/W the phy regs.
+ - description: Pixel clock for video port 0.
+ - description: Pixel clock for video port 1.
+ - description: Pixel clock for video port 2.
+
+ clock-names:
+items:
+ - const: aclk
+ - const: hclk
+ - const: dclk_vp0
+ - const: dclk_vp1
+ - const: dclk_vp2
+
+ rockchip,grf:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+ Phandle to GRF regs used for misc control
+
+ ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+ port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Output endpoint of VP0
+
+ port@1:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Output endpoint of VP1
+
+ port@2:
+$ref: /schemas/graph.yaml#/properties/port
+description:
+ Output endpoint of VP2
+
+ assigned-clocks: true
+
+ assigned-clock-rates: true
+
+ assigned-clock-parents: true
+
+ iommus:
+maxItems: 1
+
+ power-domains:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+bus {
+#address-cells = <2>;
+#size-cells = <2>;
+vop: vop@fe04 {
+compatible = "rockchip,rk3568-vop";
+reg = <0x0 0xfe04 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+interrupts = ;
+clocks = < ACLK_VOP>,
+ < HCLK_VOP>,
+ < DCLK_VOP0>,
+ < DCLK_VOP1>,
+ < DCLK_VOP2>;
+clock-names = "aclk_vop",
+ "hclk_vop",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2";
+power-domains = < RK3568_PD_VO>;
+iommus = <_mmu>;
+vop_out: ports {
+#address-cells = <1>;
+#size-cells = <0>;
+vp0: port@0 {
+reg = <0>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
+vp1: port@1 {
+reg = <1>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
+vp2: port@2 {
+reg = <2>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
+};
+};
+};
--
2.30.2
