[PATCH 2/2] radeon: add si tiling support v5

[Michel Dänzer]

On Mit, 2013-04-10 at 18:20 -0400, j.glisse at gmail.com wrote: 
> From: Jerome Glisse 
> 
> v2: Only writte tile index if flags for it is set
> v3: Remove useless allow2d scanout flags
> v4: Split radeon_drm.h update to its own patch
> v5: update against lastest next tree for radeon
> 
> Signed-off-by: Jerome Glisse 

Reviewed-by: Michel D?nzer 


-- 
Earthling Michel D?nzer   |   http://www.amd.com
Libre software enthusiast |  Debian, X and DRI developer

Re: [PATCH 2/2] radeon: add si tiling support v5

[Michel Dänzer]

On Mit, 2013-04-10 at 18:20 -0400, j.gli...@gmail.com wrote: 
 From: Jerome Glisse jgli...@redhat.com
 
 v2: Only writte tile index if flags for it is set
 v3: Remove useless allow2d scanout flags
 v4: Split radeon_drm.h update to its own patch
 v5: update against lastest next tree for radeon
 
 Signed-off-by: Jerome Glisse jgli...@redhat.com

Reviewed-by: Michel Dänzer michel.daen...@amd.com


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast |  Debian, X and DRI developer
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[PATCH 2/2] radeon: add si tiling support v5

[j.gli...@gmail.com]

From: Jerome Glisse 

v2: Only writte tile index if flags for it is set
v3: Remove useless allow2d scanout flags
v4: Split radeon_drm.h update to its own patch
v5: update against lastest next tree for radeon

Signed-off-by: Jerome Glisse 
---
 radeon/radeon_surface.c | 658 
 radeon/radeon_surface.h |  31 +++
 2 files changed, 644 insertions(+), 45 deletions(-)

diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 5935c23..288b5e2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -83,12 +83,14 @@ typedef int (*hw_best_surface_t)(struct 
radeon_surface_manager *surf_man,

 struct radeon_hw_info {
 /* apply to r6, eg */
-uint32_tgroup_bytes;
-uint32_tnum_banks;
-uint32_tnum_pipes;
+uint32_tgroup_bytes;
+uint32_tnum_banks;
+uint32_tnum_pipes;
 /* apply to eg */
-uint32_trow_size;
-unsignedallow_2d;
+uint32_trow_size;
+unsignedallow_2d;
+/* apply to si */
+uint32_ttile_mode_array[32];
 };

 struct radeon_surface_manager {
@@ -1000,12 +1002,403 @@ static int eg_surface_best(struct 
radeon_surface_manager *surf_man,
 /* ===
  * Southern Islands family
  */
+#define SI__GB_TILE_MODE__PIPE_CONFIG(x)(((x) >> 6) & 0x1f)
+#define SI__PIPE_CONFIG__ADDR_SURF_P2   0
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_8x16  4
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x168
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x169
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x1610
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
+#define SI__GB_TILE_MODE__TILE_SPLIT(x) (((x) >> 11) & 0x7)
+#define SI__TILE_SPLIT__64B 0
+#define SI__TILE_SPLIT__128B1
+#define SI__TILE_SPLIT__256B2
+#define SI__TILE_SPLIT__512B3
+#define SI__TILE_SPLIT__1024B   4
+#define SI__TILE_SPLIT__2048B   5
+#define SI__TILE_SPLIT__4096B   6
+#define SI__GB_TILE_MODE__BANK_WIDTH(x) (((x) >> 14) & 0x3)
+#define SI__BANK_WIDTH__1   0
+#define SI__BANK_WIDTH__2   1
+#define SI__BANK_WIDTH__4   2
+#define SI__BANK_WIDTH__8   3
+#define SI__GB_TILE_MODE__BANK_HEIGHT(x)(((x) >> 16) & 0x3)
+#define SI__BANK_HEIGHT__1  0
+#define SI__BANK_HEIGHT__2  1
+#define SI__BANK_HEIGHT__4  2
+#define SI__BANK_HEIGHT__8  3
+#define SI__GB_TILE_MODE__MACRO_TILE_ASPECT(x)  (((x) >> 18) & 0x3)
+#define SI__MACRO_TILE_ASPECT__10
+#define SI__MACRO_TILE_ASPECT__21
+#define SI__MACRO_TILE_ASPECT__42
+#define SI__MACRO_TILE_ASPECT__83
+#define SI__GB_TILE_MODE__NUM_BANKS(x)  (((x) >> 20) & 0x3)
+#define SI__NUM_BANKS__2_BANK   0
+#define SI__NUM_BANKS__4_BANK   1
+#define SI__NUM_BANKS__8_BANK   2
+#define SI__NUM_BANKS__16_BANK  3
+
+
+static void si_gb_tile_mode(uint32_t gb_tile_mode,
+unsigned *num_pipes,
+unsigned *num_banks,
+uint32_t *macro_tile_aspect,
+uint32_t *bank_w,
+uint32_t *bank_h,
+uint32_t *tile_split)
+{
+if (num_pipes) {
+switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
+case SI__PIPE_CONFIG__ADDR_SURF_P2:
+default:
+*num_pipes = 2;
+break;
+case SI__PIPE_CONFIG__ADDR_SURF_P4_8x16:
+case SI__PIPE_CONFIG__ADDR_SURF_P4_16x16:
+case SI__PIPE_CONFIG__ADDR_SURF_P4_16x32:
+case SI__PIPE_CONFIG__ADDR_SURF_P4_32x32:
+*num_pipes = 4;
+break;
+case SI__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
+case SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
+case 

[PATCH 2/2] radeon: add si tiling support v5

[j . glisse]

From: Jerome Glisse jgli...@redhat.com

v2: Only writte tile index if flags for it is set
v3: Remove useless allow2d scanout flags
v4: Split radeon_drm.h update to its own patch
v5: update against lastest next tree for radeon

Signed-off-by: Jerome Glisse jgli...@redhat.com
---
 radeon/radeon_surface.c | 658 
 radeon/radeon_surface.h |  31 +++
 2 files changed, 644 insertions(+), 45 deletions(-)

diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 5935c23..288b5e2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -83,12 +83,14 @@ typedef int (*hw_best_surface_t)(struct 
radeon_surface_manager *surf_man,
 
 struct radeon_hw_info {
 /* apply to r6, eg */
-uint32_tgroup_bytes;
-uint32_tnum_banks;
-uint32_tnum_pipes;
+uint32_tgroup_bytes;
+uint32_tnum_banks;
+uint32_tnum_pipes;
 /* apply to eg */
-uint32_trow_size;
-unsignedallow_2d;
+uint32_trow_size;
+unsignedallow_2d;
+/* apply to si */
+uint32_ttile_mode_array[32];
 };
 
 struct radeon_surface_manager {
@@ -1000,12 +1002,403 @@ static int eg_surface_best(struct 
radeon_surface_manager *surf_man,
 /* ===
  * Southern Islands family
  */
+#define SI__GB_TILE_MODE__PIPE_CONFIG(x)(((x)  6)  0x1f)
+#define SI__PIPE_CONFIG__ADDR_SURF_P2   0
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_8x16  4
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
+#define SI__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x168
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x169
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x1610
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
+#define SI__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
+#define SI__GB_TILE_MODE__TILE_SPLIT(x) (((x)  11)  0x7)
+#define SI__TILE_SPLIT__64B 0
+#define SI__TILE_SPLIT__128B1
+#define SI__TILE_SPLIT__256B2
+#define SI__TILE_SPLIT__512B3
+#define SI__TILE_SPLIT__1024B   4
+#define SI__TILE_SPLIT__2048B   5
+#define SI__TILE_SPLIT__4096B   6
+#define SI__GB_TILE_MODE__BANK_WIDTH(x) (((x)  14)  0x3)
+#define SI__BANK_WIDTH__1   0
+#define SI__BANK_WIDTH__2   1
+#define SI__BANK_WIDTH__4   2
+#define SI__BANK_WIDTH__8   3
+#define SI__GB_TILE_MODE__BANK_HEIGHT(x)(((x)  16)  0x3)
+#define SI__BANK_HEIGHT__1  0
+#define SI__BANK_HEIGHT__2  1
+#define SI__BANK_HEIGHT__4  2
+#define SI__BANK_HEIGHT__8  3
+#define SI__GB_TILE_MODE__MACRO_TILE_ASPECT(x)  (((x)  18)  0x3)
+#define SI__MACRO_TILE_ASPECT__10
+#define SI__MACRO_TILE_ASPECT__21
+#define SI__MACRO_TILE_ASPECT__42
+#define SI__MACRO_TILE_ASPECT__83
+#define SI__GB_TILE_MODE__NUM_BANKS(x)  (((x)  20)  0x3)
+#define SI__NUM_BANKS__2_BANK   0
+#define SI__NUM_BANKS__4_BANK   1
+#define SI__NUM_BANKS__8_BANK   2
+#define SI__NUM_BANKS__16_BANK  3
+
+
+static void si_gb_tile_mode(uint32_t gb_tile_mode,
+unsigned *num_pipes,
+unsigned *num_banks,
+uint32_t *macro_tile_aspect,
+uint32_t *bank_w,
+uint32_t *bank_h,
+uint32_t *tile_split)
+{
+if (num_pipes) {
+switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
+case SI__PIPE_CONFIG__ADDR_SURF_P2:
+default:
+*num_pipes = 2;
+break;
+case SI__PIPE_CONFIG__ADDR_SURF_P4_8x16:
+case SI__PIPE_CONFIG__ADDR_SURF_P4_16x16:
+case SI__PIPE_CONFIG__ADDR_SURF_P4_16x32:
+case SI__PIPE_CONFIG__ADDR_SURF_P4_32x32:
+*num_pipes = 4;
+break;
+case SI__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
+case SI__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
+case