[PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx

2014-11-07 Thread Ganesan, Aravind 


On 11/6/2014 2:11 PM, Rob Clark wrote:
> On Fri, Oct 31, 2014 at 11:08 AM, Ganesan, Aravind
>  wrote:
>> Register offsets have changed between a3xx and a4xx GPUs.
>> To be able access these registers in common code, we create
>> a lookup table, and set of read-write APIs to access the
>> register through the lookup table.
>>
>> Signed-off-by: Aravind Ganesan 
>> ---
>> Resend the patch-set with the same thread-id
>> Resend in patch-set format and with dri-devel at lists.freedesktop.org on
>> the CC.
>>  drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 103 +
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.c |  17 +++--
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130
>> 
>>  3 files changed, 244 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> index 6c4a91a..9713aef9 100644
>> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> @@ -2,6 +2,8 @@
>>   * Copyright (C) 2013 Red Hat
>>   * Author: Rob Clark 
>>   *
>> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
>> + *
>>   * This program is free software; you can redistribute it and/or modify it
>>   * under the terms of the GNU General Public License version 2 as
>> published by
>>   * the Free Software Foundation.
>> @@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
>> gpu_read(gpu, REG_A3XX_RBBM_STATUS));
>> adreno_dump(gpu);
>>  }
>> +/* Register offset defines for A3XX */
>> +static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, 
>> REG_AXXX_CP_ME_RAM_WADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, 
>> REG_AXXX_CP_ME_RAM_DATA),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
>> +   REG_A3XX_CP_PFP_UCODE_DATA),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
>> +   REG_A3XX_CP_PFP_UCODE_ADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, 
>> REG_A3XX_CP_WFI_PEND_CTR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, 
>> REG_AXXX_CP_RB_RPTR_ADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, 
>> REG_A3XX_CP_PROTECT_CTRL),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, 
>> REG_AXXX_CP_ME_RAM_RADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, 
>> REG_A3XX_CP_MERCIU_ADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, 
>> REG_A3XX_CP_MERCIU_DATA),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, 
>> REG_A3XX_CP_MERCIU_DATA2),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
>> +   REG_A3XX_CP_PROTECT_STATUS),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
>> +   REG_A3XX_RBBM_PERFCTR_CTL),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
>> +   REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
>> +   REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
>> +   REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, 
>> REG_A3XX_RBBM_INT_0_MASK),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
>> +   REG_A3XX_RBBM_INT_0_STATUS),
>> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
>> +

[PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx

2014-11-06 Thread Rob Clark 
On Fri, Oct 31, 2014 at 11:08 AM, Ganesan, Aravind
 wrote:
> Register offsets have changed between a3xx and a4xx GPUs.
> To be able access these registers in common code, we create
> a lookup table, and set of read-write APIs to access the
> register through the lookup table.
>
> Signed-off-by: Aravind Ganesan 
> ---
> Resend the patch-set with the same thread-id
> Resend in patch-set format and with dri-devel at lists.freedesktop.org on
> the CC.
>  drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 103 +
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c |  17 +++--
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130
> 
>  3 files changed, 244 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> index 6c4a91a..9713aef9 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -2,6 +2,8 @@
>   * Copyright (C) 2013 Red Hat
>   * Author: Rob Clark 
>   *
> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
> + *
>   * This program is free software; you can redistribute it and/or modify it
>   * under the terms of the GNU General Public License version 2 as
> published by
>   * the Free Software Foundation.
> @@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
> gpu_read(gpu, REG_A3XX_RBBM_STATUS));
> adreno_dump(gpu);
>  }
> +/* Register offset defines for A3XX */
> +static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, 
> REG_AXXX_CP_ME_RAM_WADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
> +   REG_A3XX_CP_PFP_UCODE_DATA),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
> +   REG_A3XX_CP_PFP_UCODE_ADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, 
> REG_A3XX_CP_WFI_PEND_CTR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, 
> REG_AXXX_CP_RB_RPTR_ADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, 
> REG_A3XX_CP_PROTECT_CTRL),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, 
> REG_AXXX_CP_ME_RAM_RADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, 
> REG_A3XX_CP_MERCIU_DATA2),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
> +   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
> +   REG_A3XX_CP_PROTECT_STATUS),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
> +   REG_A3XX_RBBM_PERFCTR_CTL),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
> +   REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
> +   REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
> +   REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, 
> REG_A3XX_RBBM_INT_0_MASK),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
> +   REG_A3XX_RBBM_INT_0_STATUS),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
> +   REG_A3XX_RBBM_AHB_ERROR_STATUS),
> +   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
> +   REG_ADRENO_DEFINE(

[PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx

2014-10-31 Thread Ganesan, Aravind 
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.

Signed-off-by: Aravind Ganesan 
---
Resend the patch-set with the same thread-id
Resend in patch-set format and with dri-devel at lists.freedesktop.org on
the CC.
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 103 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  17 +++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130

 3 files changed, 244 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 6c4a91a..9713aef9 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -2,6 +2,8 @@
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as
published by
  * the Free Software Foundation.
@@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
gpu_read(gpu, REG_A3XX_RBBM_STATUS));
adreno_dump(gpu);
 }
+/* Register offset defines for A3XX */
+static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
+   REG_A3XX_CP_PFP_UCODE_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
+   REG_A3XX_CP_PFP_UCODE_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
+   REG_A3XX_CP_PROTECT_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
+   REG_A3XX_RBBM_PERFCTR_CTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
+   REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
+   REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
+   REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
+   REG_A3XX_RBBM_INT_0_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
+   REG_A3XX_RBBM_AHB_ERROR_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,
+   REG_A3XX_RBBM_INT_CLEAR_CMD),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,
+   REG_A3

[PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx

2014-10-30 Thread Ganesan, Aravind 
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.

Signed-off-by: Aravind Ganesan 
---
Resend in patch-set format and with dri-devel at lists.freedesktop.org on
the CC.
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 103 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  17 +++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130

 3 files changed, 244 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 6c4a91a..9713aef9 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -2,6 +2,8 @@
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as
published by
  * the Free Software Foundation.
@@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
gpu_read(gpu, REG_A3XX_RBBM_STATUS));
adreno_dump(gpu);
 }
+/* Register offset defines for A3XX */
+static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
+   REG_A3XX_CP_PFP_UCODE_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
+   REG_A3XX_CP_PFP_UCODE_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
+   REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
+   REG_A3XX_CP_PROTECT_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
+   REG_A3XX_RBBM_PERFCTR_CTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
+   REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
+   REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
+   REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
+   REG_A3XX_RBBM_INT_0_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
+   REG_A3XX_RBBM_AHB_ERROR_STATUS),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,
+   REG_A3XX_RBBM_INT_CLEAR_CMD),
+   REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),
+   REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,
+   REG_A3XX_VPC_VPC_DEBUG_RAM_SEL),
+   REG_ADRENO