[PATCH 20/22] drm/i915: BDW: Load degamma correction values
Regards Shashank On 10/12/2015 11:43 PM, Rob Bradford wrote: > On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote: >> I915 color manager registers pipe degamma correction as palette >> correction before CTM, DRM property. >> >> This patch adds the no of coefficients(65) for degamma correction >> as "num_samples_before_ctm" parameter in device info structures, >> for BDW and higher platforms. > > Did you copy and paste this from the CHV version? The only constant you > add for degamma here is 512? Oops, side effects of too many code-refactoring without proper sleep :) will fix this. > > Rob > >> >> Signed-off-by: Shashank Sharma >> Signed-off-by: Kausal Malladi >> --- >> drivers/gpu/drm/i915/i915_drv.c| 7 +++ >> drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ >> 2 files changed, 10 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c >> b/drivers/gpu/drm/i915/i915_drv.c >> index 4fa046f..ebf4910 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -303,6 +303,7 @@ static const struct intel_device_info >> intel_broadwell_d_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .has_llc = 1, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> @@ -316,6 +317,7 @@ static const struct intel_device_info >> intel_broadwell_m_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .has_llc = 1, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> @@ -329,6 +331,7 @@ static const struct intel_device_info >> intel_broadwell_gt3d_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING >> | BSD2_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .has_llc = 1, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> @@ -342,6 +345,7 @@ static const struct intel_device_info >> intel_broadwell_gt3m_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING >> | BSD2_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .has_llc = 1, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> @@ -368,6 +372,7 @@ static const struct intel_device_info >> intel_skylake_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .has_llc = 1, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> @@ -382,6 +387,7 @@ static const struct intel_device_info >> intel_skylake_gt3_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING >> | BSD2_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .has_llc = 1, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> @@ -396,6 +402,7 @@ static const struct intel_device_info >> intel_broxton_info = { >> .need_gfx_hws = 1, .has_hotplug = 1, >> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, >> .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, >> +.num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, >> .num_pipes = 3, >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> diff --git a/drivers/gpu/drm/i915/intel_color_manager.h >> b/drivers/gpu/drm/i915/intel_color_manager.h >> index 6c7cb08..e0c486e 100644 >> --- a/drivers/gpu/drm/i915/intel_color_manager.h >> +++ b/drivers/gpu/drm/i915/intel_color_manager.h >> @@ -98,3 +98,6 @@ >> #define BDW_MAX_GAMMA ((1 << 24) - 1) >> #define BDW_INDEX_AUTO_INCREMENT (1 << 15) >> #define BDW_INDEX_SPLIT_MODE (1 << 31) >> + >> +/* Degamma on BDW */ >> +#define BDW_DEGAMMA_MAX_VALS 512
[PATCH 20/22] drm/i915: BDW: Load degamma correction values
On Sat, 2015-10-10 at 00:59 +0530, Shashank Sharma wrote: > I915 color manager registers pipe degamma correction as palette > correction before CTM, DRM property. > > This patch adds the no of coefficients(65) for degamma correction > as "num_samples_before_ctm" parameter in device info structures, > for BDW and higher platforms. Did you copy and paste this from the CHV version? The only constant you add for degamma here is 512? Rob > > Signed-off-by: Shashank Sharma > Signed-off-by: Kausal Malladi > --- > drivers/gpu/drm/i915/i915_drv.c| 7 +++ > drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > b/drivers/gpu/drm/i915/i915_drv.c > index 4fa046f..ebf4910 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -303,6 +303,7 @@ static const struct intel_device_info > intel_broadwell_d_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .has_llc = 1, > .has_ddi = 1, > .has_fpga_dbg = 1, > @@ -316,6 +317,7 @@ static const struct intel_device_info > intel_broadwell_m_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .has_llc = 1, > .has_ddi = 1, > .has_fpga_dbg = 1, > @@ -329,6 +331,7 @@ static const struct intel_device_info > intel_broadwell_gt3d_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING > | BSD2_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .has_llc = 1, > .has_ddi = 1, > .has_fpga_dbg = 1, > @@ -342,6 +345,7 @@ static const struct intel_device_info > intel_broadwell_gt3m_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING > | BSD2_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .has_llc = 1, > .has_ddi = 1, > .has_fpga_dbg = 1, > @@ -368,6 +372,7 @@ static const struct intel_device_info > intel_skylake_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .has_llc = 1, > .has_ddi = 1, > .has_fpga_dbg = 1, > @@ -382,6 +387,7 @@ static const struct intel_device_info > intel_skylake_gt3_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING > | BSD2_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .has_llc = 1, > .has_ddi = 1, > .has_fpga_dbg = 1, > @@ -396,6 +402,7 @@ static const struct intel_device_info > intel_broxton_info = { > .need_gfx_hws = 1, .has_hotplug = 1, > .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, > .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, > + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, > .num_pipes = 3, > .has_ddi = 1, > .has_fpga_dbg = 1, > diff --git a/drivers/gpu/drm/i915/intel_color_manager.h > b/drivers/gpu/drm/i915/intel_color_manager.h > index 6c7cb08..e0c486e 100644 > --- a/drivers/gpu/drm/i915/intel_color_manager.h > +++ b/drivers/gpu/drm/i915/intel_color_manager.h > @@ -98,3 +98,6 @@ > #define BDW_MAX_GAMMA ((1 << 24) - 1) > #define BDW_INDEX_AUTO_INCREMENT (1 << 15) > #define BDW_INDEX_SPLIT_MODE (1 << 31) > + > +/* Degamma on BDW */ > +#define BDW_DEGAMMA_MAX_VALS 512
[PATCH 20/22] drm/i915: BDW: Load degamma correction values
I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property. This patch adds the no of coefficients(65) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_drv.c| 7 +++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4fa046f..ebf4910 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -303,6 +303,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -316,6 +317,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -329,6 +331,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -342,6 +345,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -382,6 +387,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 6c7cb08..e0c486e 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -98,3 +98,6 @@ #define BDW_MAX_GAMMA ((1 << 24) - 1) #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31) + +/* Degamma on BDW */ +#define BDW_DEGAMMA_MAX_VALS 512 -- 1.9.1