Re: [PATCH 3/3] arm64: dts: qcom: sm8150: Wire up MDSS
On Mon, Dec 12, 2022 at 10:33:14AM +0100, Konrad Dybcio wrote:
> Add required nodes for MDSS and hook up provided clocks in DISPCC.
> This setup is almost identical to 8[23]50.
>
> Signed-off-by: Konrad Dybcio
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 271 ++-
> 1 file changed, 267 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index ff0439f4..c0c1e781eb43 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -9,6 +9,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -3579,14 +3580,276 @@ camnoc_virt: interconnect@ac0 {
> qcom,bcm-voters = <_bcm_voter>;
> };
>
> + mdss: mdss@ae0 {
As you're fixing up the dispcc patch, "display-subsystem@" seems nicer.
Regards,
Bjorn
> + compatible = "qcom,sm8150-mdss";
> + reg = <0 0x0ae0 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <_noc MASTER_MDP_PORT0 _virt
> SLAVE_EBI_CH0>,
> + <_noc MASTER_MDP_PORT1 _virt
> SLAVE_EBI_CH0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = < MDSS_GDSC>;
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>,
> + < GCC_DISP_SF_AXI_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <_smmu 0x800 0x420>;
> +
> + status = "disabled";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sm8150-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>,
> + < DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "iface", "bus", "core", "vsync";
> +
> + assigned-clocks = <
> DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <1920>;
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SM8150_MMCX>;
> +
> + interrupt-parent = <>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint =
> <_dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf2_out: endpoint {
> + remote-endpoint =
> <_dsi1_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-171428571 {
> + opp-hz = /bits/ 64 <171428571>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> + opp-3 {
> + opp-hz = /bits/ 64 <3>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-34500 {
> + opp-hz = /bits/ 64 <34500>;
> + required-opps =
> <_opp_svs_l1>;
> +
Re: [PATCH 3/3] arm64: dts: qcom: sm8150: Wire up MDSS
On 2022-12-12 10:33:14, Konrad Dybcio wrote: > Add required nodes for MDSS and hook up provided clocks in DISPCC. > This setup is almost identical to 8[23]50. > > Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten On Sony Xperia 5: Tested-by: Marijn Suijten Note that this device uses a command-mode panel which requires (since DPU 5.0.0) the TE functionality to be moved from the PP into the INTF block. I will send patches for this shortly, to enable proper vsyncing and presentation _without_ tearing. Note^2: We are also working to correct Display Stream Compression to work on the Sony Xperia 1 (bigger brother of Xperia 5 with a 4k display) and newer Sony devices on newer (sm8[234]50) SoCs! - Marijn
[PATCH 3/3] arm64: dts: qcom: sm8150: Wire up MDSS
Add required nodes for MDSS and hook up provided clocks in DISPCC.
This setup is almost identical to 8[23]50.
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 271 ++-
1 file changed, 267 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index ff0439f4..c0c1e781eb43 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -3579,14 +3580,276 @@ camnoc_virt: interconnect@ac0 {
qcom,bcm-voters = <_bcm_voter>;
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sm8150-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
+ <_noc MASTER_MDP_PORT1 _virt
SLAVE_EBI_CH0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = < MDSS_GDSC>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_smmu 0x800 0x420>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8150-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8150_MMCX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint =
<_dsi1_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-171428571 {
+ opp-hz = /bits/ 64 <171428571>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ required-opps =
<_opp_svs>;
+ };
+
+ opp-34500 {
+ opp-hz = /bits/ 64 <34500>;
+ required-opps =
<_opp_svs_l1>;
+ };
+
+ opp-46000 {
+ opp-hz = /bits/ 64 <46000>;
+ required-opps =
<_opp_nom>;
+
