Re: [PATCH 3/6] drm/ttm: Change the meaning of resource->start from pfn to bytes

2023-02-08 Thread Christian König
That finally starts to look sane. I'm going to make a few more 
adjustments and then send this out.


Christian.

Am 08.02.23 um 10:01 schrieb Somalapuram Amaranath:

Change resource->start from pfn to bytes to
allow allocating objects smaller than a page.
Change all DRM drivers using ttm_resource start and size pfn to bytes.
Change amdgpu_res_first() cur->start, cur->size from pfn to bytes.
Replacing ttm_resource resource->start field with cursor.start.
Change amdgpu_gtt_mgr_new() allocation from pfn to bytes.

Signed-off-by: Somalapuram Amaranath 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 13 +++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  4 +++-
  drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h  |  8 
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +++---
  .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c   |  6 +-
  drivers/gpu/drm/drm_gem_vram_helper.c   |  2 +-
  drivers/gpu/drm/nouveau/nouveau_bo.c| 13 ++---
  drivers/gpu/drm/nouveau/nouveau_bo0039.c|  4 ++--
  drivers/gpu/drm/nouveau/nouveau_mem.c   | 10 +-
  drivers/gpu/drm/nouveau/nouveau_ttm.c   |  2 +-
  drivers/gpu/drm/nouveau/nv17_fence.c|  2 +-
  drivers/gpu/drm/nouveau/nv50_fence.c|  2 +-
  drivers/gpu/drm/qxl/qxl_drv.h   |  2 +-
  drivers/gpu/drm/qxl/qxl_object.c|  2 +-
  drivers/gpu/drm/qxl/qxl_ttm.c   |  5 ++---
  drivers/gpu/drm/radeon/radeon_object.c  |  6 +++---
  drivers/gpu/drm/radeon/radeon_object.h  |  2 +-
  drivers/gpu/drm/radeon/radeon_ttm.c | 13 ++---
  drivers/gpu/drm/radeon/radeon_vm.c  |  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_bo.c  |  4 ++--
  drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c |  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c |  2 +-
  drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c  |  3 +--
  23 files changed, 63 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 44367f03316f..a1fbfc5984d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -116,7 +116,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
  struct ttm_resource **res)
  {
struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
-   uint32_t num_pages = PFN_UP(tbo->base.size);
struct ttm_range_mgr_node *node;
int r;
  
@@ -134,8 +133,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,

if (place->lpfn) {
spin_lock(&mgr->lock);
r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
-   num_pages, tbo->page_alignment,
-   0, place->fpfn, place->lpfn,
+   tbo->base.size,
+   tbo->page_alignment << 
PAGE_SHIFT, 0,
+   place->fpfn << PAGE_SHIFT,
+   place->lpfn << PAGE_SHIFT,
DRM_MM_INSERT_BEST);
spin_unlock(&mgr->lock);
if (unlikely(r))
@@ -144,7 +145,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
node->base.start = node->mm_nodes[0].start;
} else {
node->mm_nodes[0].start = 0;
-   node->mm_nodes[0].size = PFN_UP(node->base.size);
+   node->mm_nodes[0].size = node->base.size;
node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
  
@@ -285,8 +286,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
  
  	ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
  
-	start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;

-   size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
+   start = (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) 
<< PAGE_SHIFT;
+   size = adev->gmc.gart_size - start;
drm_mm_init(&mgr->mm, start, size);
spin_lock_init(&mgr->lock);
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

index d835ee2131d2..f5d5eee09cea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1488,9 +1488,11 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
  u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   struct amdgpu_res_cursor cursor;
uint64_t offset;
  
-	offset = (bo->tbo.resource->start << PAGE_SHIFT) +

+   amd

[PATCH 3/6] drm/ttm: Change the meaning of resource->start from pfn to bytes

2023-02-08 Thread Somalapuram Amaranath
Change resource->start from pfn to bytes to
allow allocating objects smaller than a page.
Change all DRM drivers using ttm_resource start and size pfn to bytes.
Change amdgpu_res_first() cur->start, cur->size from pfn to bytes.
Replacing ttm_resource resource->start field with cursor.start.
Change amdgpu_gtt_mgr_new() allocation from pfn to bytes.

Signed-off-by: Somalapuram Amaranath 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 13 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h  |  8 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 +++---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c   |  6 +-
 drivers/gpu/drm/drm_gem_vram_helper.c   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_bo.c| 13 ++---
 drivers/gpu/drm/nouveau/nouveau_bo0039.c|  4 ++--
 drivers/gpu/drm/nouveau/nouveau_mem.c   | 10 +-
 drivers/gpu/drm/nouveau/nouveau_ttm.c   |  2 +-
 drivers/gpu/drm/nouveau/nv17_fence.c|  2 +-
 drivers/gpu/drm/nouveau/nv50_fence.c|  2 +-
 drivers/gpu/drm/qxl/qxl_drv.h   |  2 +-
 drivers/gpu/drm/qxl/qxl_object.c|  2 +-
 drivers/gpu/drm/qxl/qxl_ttm.c   |  5 ++---
 drivers/gpu/drm/radeon/radeon_object.c  |  6 +++---
 drivers/gpu/drm/radeon/radeon_object.h  |  2 +-
 drivers/gpu/drm/radeon/radeon_ttm.c | 13 ++---
 drivers/gpu/drm/radeon/radeon_vm.c  |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c  |  4 ++--
 drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c  |  3 +--
 23 files changed, 63 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 44367f03316f..a1fbfc5984d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -116,7 +116,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
  struct ttm_resource **res)
 {
struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
-   uint32_t num_pages = PFN_UP(tbo->base.size);
struct ttm_range_mgr_node *node;
int r;
 
@@ -134,8 +133,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
if (place->lpfn) {
spin_lock(&mgr->lock);
r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
-   num_pages, tbo->page_alignment,
-   0, place->fpfn, place->lpfn,
+   tbo->base.size,
+   tbo->page_alignment << 
PAGE_SHIFT, 0,
+   place->fpfn << PAGE_SHIFT,
+   place->lpfn << PAGE_SHIFT,
DRM_MM_INSERT_BEST);
spin_unlock(&mgr->lock);
if (unlikely(r))
@@ -144,7 +145,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager 
*man,
node->base.start = node->mm_nodes[0].start;
} else {
node->mm_nodes[0].start = 0;
-   node->mm_nodes[0].size = PFN_UP(node->base.size);
+   node->mm_nodes[0].size = node->base.size;
node->base.start = AMDGPU_BO_INVALID_OFFSET;
}
 
@@ -285,8 +286,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, 
uint64_t gtt_size)
 
ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
 
-   start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
-   size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
+   start = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 
AMDGPU_GTT_NUM_TRANSFER_WINDOWS) << PAGE_SHIFT;
+   size = adev->gmc.gart_size - start;
drm_mm_init(&mgr->mm, start, size);
spin_lock_init(&mgr->lock);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d835ee2131d2..f5d5eee09cea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1488,9 +1488,11 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+   struct amdgpu_res_cursor cursor;
uint64_t offset;
 
-   offset = (bo->tbo.resource->start << PAGE_SHIFT) +
+   amdgpu_res_first(bo->tbo.resource, 0, bo->tbo.resource->size, &cursor);
+   offset = cursor.start +
 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);