Re: [PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning

[Akhil P Oommen]

On 12/13/2022 5:54 AM, Konrad Dybcio wrote:
> Add support for matching QFPROM fuse values to get the correct speed bin
> on A640 (SM8150) GPUs.
>
> Signed-off-by: Konrad Dybcio 
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 36c8fb699b56..2c1630f0c04c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1877,6 +1877,16 @@ static u32 a619_get_speed_bin(u32 fuse)
>   return UINT_MAX;
>  }
>  
> +static u32 a640_get_speed_bin(u32 fuse)
> +{
> + if (fuse == 0)
> + return 0;
> + else if (fuse == 1)
> + return 1;
> +
> + return UINT_MAX;
> +}
> +
>  static u32 adreno_7c3_get_speed_bin(u32 fuse)
>  {
>   if (fuse == 0)
> @@ -1902,6 +1912,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
> adreno_rev rev, u32 fuse)
>   if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
>   val = adreno_7c3_get_speed_bin(fuse);
>  
> + if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
> + val = a640_get_speed_bin(fuse);
> +
>   if (val == UINT_MAX) {
>   DRM_DEV_ERROR(dev,
>   "missing support for speed-bin: %u. Some OPPs may not 
> be supported by hardware\n",

Reviewed-by: Akhil P Oommen 


-Akhil.

[PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning

[Konrad Dybcio]

Add support for matching QFPROM fuse values to get the correct speed bin
on A640 (SM8150) GPUs.

Signed-off-by: Konrad Dybcio 
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 36c8fb699b56..2c1630f0c04c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1877,6 +1877,16 @@ static u32 a619_get_speed_bin(u32 fuse)
return UINT_MAX;
 }
 
+static u32 a640_get_speed_bin(u32 fuse)
+{
+   if (fuse == 0)
+   return 0;
+   else if (fuse == 1)
+   return 1;
+
+   return UINT_MAX;
+}
+
 static u32 adreno_7c3_get_speed_bin(u32 fuse)
 {
if (fuse == 0)
@@ -1902,6 +1912,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct 
adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
val = adreno_7c3_get_speed_bin(fuse);
 
+   if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+   val = a640_get_speed_bin(fuse);
+
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not 
be supported by hardware\n",
-- 
2.39.0