Re: [PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes
Hi,
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
wrote:
>
> Add display nodes and GCE info for MT8186 SoC. Also, add GCE
> (Global Command Engine) properties to the display nodes in order to
> enable the usage of the CMDQ (Command Queue), which is required for
> operating the display.
>
> Signed-off-by: Allen-KH Cheng
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++
> 1 file changed, 128 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index eab30ab01572..8670d37970ef 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -5,6 +5,7 @@
> */
> /dts-v1/;
> #include
> +#include
> #include
> #include
> #include
> @@ -632,6 +633,15 @@
> clocks = <>;
> };
>
> + gce: mailbox@1022c000 {
> + compatible = "mediatek,mt8186-gce";
> + reg = <0 0X1022c000 0 0x4000>;
> + interrupts = ;
> + #mbox-cells = <2>;
> + clocks = <_ao CLK_INFRA_AO_GCE>;
> + clock-names = "gce";
> + };
> +
> scp: scp@1050 {
> compatible = "mediatek,mt8186-scp";
> reg = <0 0x1050 0 0x4>,
> @@ -1197,6 +1207,20 @@
> reg = <0 0x1400 0 0x1000>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> + mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
> +< 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0
> 0x1000>;
> + };
> +
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8186-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = < CLK_MM_DISP_MUTEX0>;
> + interrupts = ;
> + mediatek,gce-client-reg = < SUBSYS_1401
> 0x1000 0x1000>;
> + mediatek,gce-events =
> ,
> +
> ;
> + power-domains = < MT8186_POWER_DOMAIN_DIS>;
> };
>
> smi_common: smi@14002000 {
> @@ -1230,6 +1254,49 @@
> power-domains = < MT8186_POWER_DOMAIN_DIS>;
> };
>
> + ovl0: ovl@14005000 {
If there's only one instance, you could drop the trailing zero. Same
for all the other nodes.
> + compatible = "mediatek,mt8186-disp-ovl",
> +"mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + clocks = < CLK_MM_DISP_OVL0>;
> + interrupts = ;
> + iommus = <_mm IOMMU_PORT_L0_OVL_RDMA0>;
> + mediatek,gce-client-reg = < SUBSYS_1400
> 0x5000 0x1000>;
> + power-domains = < MT8186_POWER_DOMAIN_DIS>;
> + };
> +
> + ovl0_2l: ovl@14006000 {
I think this should be "ovl_2l0" or "ovl_2l" instead?
> + compatible = "mediatek,mt8186-disp-ovl-2l",
> +"mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + power-domains = < MT8186_POWER_DOMAIN_DIS>;
> + clocks = < CLK_MM_DISP_OVL0_2L>;
> + interrupts = ;
> + iommus = <_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
> + mediatek,gce-client-reg = < SUBSYS_1400
> 0x6000 0x1000>;
> + };
Also, this patch is missing the aliases for ovl* and rdma*. Without them
the display driver doesn't properly detect the second pipeline, and only
one CRTC is generated.
ChenYu
[PATCH 9/9] arm64: dts: mediatek: mt8186: Add display nodes
Add display nodes and GCE info for MT8186 SoC. Also, add GCE
(Global Command Engine) properties to the display nodes in order to
enable the usage of the CMDQ (Command Queue), which is required for
operating the display.
Signed-off-by: Allen-KH Cheng
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++
1 file changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index eab30ab01572..8670d37970ef 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include
+#include
#include
#include
#include
@@ -632,6 +633,15 @@
clocks = <>;
};
+ gce: mailbox@1022c000 {
+ compatible = "mediatek,mt8186-gce";
+ reg = <0 0X1022c000 0 0x4000>;
+ interrupts = ;
+ #mbox-cells = <2>;
+ clocks = <_ao CLK_INFRA_AO_GCE>;
+ clock-names = "gce";
+ };
+
scp: scp@1050 {
compatible = "mediatek,mt8186-scp";
reg = <0 0x1050 0 0x4>,
@@ -1197,6 +1207,20 @@
reg = <0 0x1400 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
+< 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0
0x1000>;
+ };
+
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8186-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = < CLK_MM_DISP_MUTEX0>;
+ interrupts = ;
+ mediatek,gce-client-reg = < SUBSYS_1401 0x1000
0x1000>;
+ mediatek,gce-events =
,
+
;
+ power-domains = < MT8186_POWER_DOMAIN_DIS>;
};
smi_common: smi@14002000 {
@@ -1230,6 +1254,49 @@
power-domains = < MT8186_POWER_DOMAIN_DIS>;
};
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8186-disp-ovl",
+"mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = < CLK_MM_DISP_OVL0>;
+ interrupts = ;
+ iommus = <_mm IOMMU_PORT_L0_OVL_RDMA0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x5000
0x1000>;
+ power-domains = < MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ ovl0_2l: ovl@14006000 {
+ compatible = "mediatek,mt8186-disp-ovl-2l",
+"mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ power-domains = < MT8186_POWER_DOMAIN_DIS>;
+ clocks = < CLK_MM_DISP_OVL0_2L>;
+ interrupts = ;
+ iommus = <_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x6000
0x1000>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8186-disp-rdma",
+"mediatek,mt8183-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = < CLK_MM_DISP_RDMA0>;
+ interrupts = ;
+ iommus = <_mm IOMMU_PORT_L1_DISP_RDMA0>;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x7000
0x1000>;
+ power-domains = < MT8186_POWER_DOMAIN_DIS>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8186-disp-color",
+"mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ clocks = < CLK_MM_DISP_COLOR0>;
+ interrupts = ;
+ mediatek,gce-client-reg = < SUBSYS_1400 0x8000
0x1000>;
+ power-domains = < MT8186_POWER_DOMAIN_DIS>;
+ };
+
dpi0: dpi@1400a000 {
compatible = "mediatek,mt8186-dpi";
reg = <0 0x1400a000 0 0x1000>;
@@ -1247,6 +1314,56 @@
};
};
+ ccorr0: ccorr@1400b000 {
+ compatible = "mediatek,mt8186-disp-ccorr",
+"mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400b000 0 0x1000>;
+
